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dvs_pvt_comp_only_ml_method

dvs_pvt_comp_only_ml_method#

Overview#

The dvs_pvt_comp_only_ml_method application shows the usage of Dynamic Voltage Scalling using PVT Sensor using ML.
It is an improvement of the standard dvs_pvt_comp_only demo where only 3 frequency points are supported. Leveraging the ML, the PVTS can be enabled for every frequency.
User can use the driver to retrieve the correct PVTS delay depending on the core targeted and the desired frequency.
The model can predict the PVTS delay for the 4 cores (see struct pvts_core_t) at any frequency.
Before using the model to predict the PVTS delay, user must ensure that :

  • CPU/DSP clock is properly configured,

  • PVTS_ReadParametersFromOTP is called in order to retrieve the A and B parameters, used by the ML model.

Supported Boards#

MIMXRT700-EVK
Hardware requirements

  • Micro USB cable

  • MIMXRT700-EVK board

  • Personal Computer

Board settings

Make sure JP7(2-3) connected for 3.3V supply for VDDIO_2. JP55(1-2) disconnected to ommit the impact of MCU-LINK during DPD and FDPD mode.

Make sure the board is supplied by PMIC, Jumper setting - JP1(1-2), JP2(2-3), JP3(1-2), JP4(1-2).

NOTE,

  1. To rebuild the HiFi4’s binary, use the main_dsp.c provided in the project root folder to replace the file in dsp_examples/dsp_naturedsp/hifi4 and build dsp_naturedsp example to get the binaries for HiFi cores.

  2. To run the PVT only on CPU0, change the value of macro “DEMO_PVT_ON_CPU_DSP” in power_demo_config.h from “1” to “0”. When DEMO_PVT_ON_CPU_DSP = 0, the HIFI4 will not be booted.

Prepare the Demo

  1. Connect a micro USB cable between the PC host and the MCU-LINK on the board

  2. Open a serial terminal with the following settings:

    • 115200 baud rate

    • 8 data bits

    • No parity

    • One stop bit

    • No flow control

  3. Build cm33_core1 project first, then the cm33_core0 project.

  4. Download the core0 program to the target board.

  5. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.

Running the demo

The similar log below shows the output of the demo in the cm33_core0 terminal window:

PVT Application Demo

This application uses the PMIC for power supply.
SILICON_REV_ID = B0
Build Time: Nov 10 2025--16:51:05 
Core/NPU Frequency: 192 MHz
TensorArena Addr: 0x20200000 - 0x20240000
TensorArena Size: Total 0x40000 (262144 B); Used 0x9b0 (2480 B)
Model Addr: 0x280042c0 - 0x2805667c
Model Size: 0x523bc (336828 B)
Total Size Used: 339308 B (Model (336828 B) + TensorArena (2480 B))
PVTS delay CPU0 = 0x14
PVTS delay HIFI4 = 0x13
Core Clock: 192000000Hz 
Input any key to start

PVT Task: Current VDDCORE = 0.868750 V
......

The cm33_core1 terminal window shows the below log,

####################  Power Mode Demo - CPU1 ####################

    Build Time: Feb  4 2024--13:36:32 
    Core Clock: 32000000Hz 
Entering Deep sleep...
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