MIMX9322

MIMX9322#

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

base – eDMA peripheral base address.
config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)

Push content of TCD structure into hardware TCD register.

Parameters:

base – EDMA peripheral base address.
channel – EDMA channel number.
tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)

EDMA Channel initialization.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)

Set channel memory attribute.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
writeAttribute – Attributes associated with a write transaction.
readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)

Set channel sign extension.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)

Set channel swap size.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)

Set channel access type.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)

Set channel request source.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)

Gets the channel identification and attribute information on the system bus interface.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)

Set channel master ID replication.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – true is enable, false is disable.

static inline void EDMA_SetChannelSecurityLevel(EDMA_Type *base, uint32_t channel, edma_channel_security_level_t level)

Set channel security level.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)

Set channel security level.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number
config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
type – A channel link type, which can be one of the following:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Enables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Disables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
channel – edma channel number.
sourceOffset – source address offset will be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Parameters:

tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

Parameters:

tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)

Gets the eDMA channel error status flags.

Parameters:

base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)

Gets the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)

Clears the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.
base – eDMA peripheral base address.
channel – eDMA channel number.

Return values:

kStatus_Success –
kStatus_InvalidArgument –

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

handle – eDMA handle pointer.
tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.
tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

handle – eDMA handle pointer.
callback – eDMA callback function pointer.
userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

submit single transfer

edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit static link transfer,

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

submit dynamic link transfer

edma_tcd_t tcdpool[2];
EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit loop transfer

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

handle – eDMA handle pointer.
config – Pointer to eDMA transfer configuration structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

handle – eDMA handle pointer
transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail
transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

kStatus_Success – It means submit transfer request succeed
kStatus_EDMA_Busy – channel is in busy status
kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

handle – eDMA handle pointer.

void EDMA_TcdInit(EDMA_Type *base, edma_tcd_t *tcdRegs)

Initialize all fields to 0 for the TCD structure.

This function initialize all fields for this TCD structure to 0.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

FSL_EDMA_DRIVER_VERSION

eDMA driver version

Version 2.10.9.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull: TCD queue is full.

enumerator kStatus_EDMA_Busy: Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes: Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes: Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes: Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes: Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes: Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes: Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes: Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes: Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable: Disable modulo

enumerator kEDMA_Modulo2bytes: Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes: Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes: Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes: Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes: Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes: Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes: Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes: Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes: Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes: Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes: Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes: Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes: Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes: Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes: Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes: Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes: Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes: Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes: Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes: Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes: Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes: Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes: Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes: Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes: Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes: Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes: Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes: Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes: Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes: Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes: Circular buffer size is 2 G bytes.

enum _edma_bandwidth

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone: No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle: eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle: eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type

Channel link type.

Values:

enumerator kEDMA_LinkNone: No channel link

enumerator kEDMA_MinorLink: Channel link after each minor loop

enumerator kEDMA_MajorLink: Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag: DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag: eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag: eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag: Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag: Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag: Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag: NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag: Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag: Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag: Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag: Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag: Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag: Transfer cancelled

enumerator kEDMA_ValidFlag: No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable: Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable: Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable: Enable interrupt while major count to half value.

enum _edma_transfer_type

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory: Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory: Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral: Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral: Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer: No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable: No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer: No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable: No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer: No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable: No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer: No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable: No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer: write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable: write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer: write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable: write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer: write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable: write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer: write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable: write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled: Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap: Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap: Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap: Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap: Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap: Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap: Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel: Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId: DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess: Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess: Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser: user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged: Privileged protection level eDMA transfers.

enum _edma_channel_security_level

eDMA4 channel security level

Values:

enumerator kEDMA_ChannelSecurityLevelNonSecure: non secure level for eDMA transfers.

enumerator kEDMA_ChannelSecurityLevelSecure: secure level for eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t: eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t: eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t: Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t: Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t: eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t: eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t: eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t: eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t: eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t: eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t: eDMA4 channel protection level

typedef enum _edma_channel_security_level edma_channel_security_level_t: eDMA4 channel security level

typedef struct _edma_channel_config edma_channel_config_t: eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

typedef struct _edma_config edma_config_t: eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:: EDMA handle pointer, users shall not touch the values inside.
Param userData:: The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
Param transferDone:: If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
Param tcds:: How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t: eDMA transfer handle structure

FSL_EDMA_DRIVER_EDMA4: eDMA driver name

EDMA_ALLOCATE_TCD(name, number): Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel): Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption: If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility: If true: a channel can suspend other channel with low priority

uint8_t channelPriority: Channel priority

struct _edma_minor_offset_config

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset: Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset: Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset: Offset for a minor loop mapping.

struct _edma_channel_config

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig: channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute: channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute: channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize: channel swap size configuration

edma_channel_access_type_t channelAccessType: channel access type configuration

uint8_t channelDataSignExtensionBitPosition: channel data sign extension bit psition configuration

uint32_t channelRequestSource: hardware service request source for the channel

bool enableMasterIDReplication: enable master ID replication

edma_channel_security_level_t securityLevel: security level

edma_channel_protection_level_t protectionLevel: protection level

struct _edma_transfer_config

#include <fsl_edma.h>

edma4 channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error.

Public Members

uint32_t srcAddr: Source data address.

uint32_t destAddr: Destination data address.

edma_transfer_size_t srcTransferSize: Source data transfer size.

edma_transfer_size_t destTransferSize: Destination data transfer size.

int16_t srcOffset: Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset: Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes: bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts: minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask: channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo: source circular data queue range

int32_t srcMajorLoopOffset: source major loop offset

edma_modulo_t dstAddrModulo: destination circular data queue range

int32_t dstMajorLoopOffset: destination major loop offset

bool enableSrcMinorLoopOffset: enable source minor loop offset

bool enableDstMinorLoopOffset: enable dest minor loop offset

int32_t minorLoopOffset: burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink: channel link when major loop complete

uint32_t majorLoopLinkChannel: major loop link channel number

bool enableChannelMinorLoopLink: channel link when minor loop complete

uint32_t minorLoopLinkChannel: minor loop link channel number

edma_tcd_t *linkTCD: pointer to the link transfer control descriptor

struct _edma_config

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableContinuousLinkMode: Enable (true) continuous link mode. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself.

bool enableMasterIdReplication: Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink: Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError: Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode: Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration: Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]: channel preemption configuration

struct _edma_handle

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback: Callback function for major count exhausted.

void *userData: Callback function parameter.

EDMA_ChannelType *channelBase: eDMA peripheral channel base address.

EDMA_Type *base: eDMA peripheral base address

EDMA_TCDType *tcdBase: eDMA peripheral tcd base address.

edma_tcd_t *tcdPool: Pointer to memory stored TCDs.

uint32_t channel: eDMA channel number.

volatile int8_t header: The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail: The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed: The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize: The total number of TCD slots in the queue.

eDMA core Driver#

enum _edma_tcd_type

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag: Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag: Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t: edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t: edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t: eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t: edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t: edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t: edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType: EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType

typedef void EDMA_Type

DMA_CORE_MP_CSR_EDBG_MASK

DMA_CORE_MP_CSR_ERCA_MASK

DMA_CORE_MP_CSR_HAE_MASK

DMA_CORE_MP_CSR_HALT_MASK

DMA_CORE_MP_CSR_GCLC_MASK

DMA_CORE_MP_CSR_GMRC_MASK

DMA_CORE_MP_CSR_EDBG(x)

DMA_CORE_MP_CSR_ERCA(x)

DMA_CORE_MP_CSR_HAE(x)

DMA_CORE_MP_CSR_HALT(x)

DMA_CORE_MP_CSR_GCLC(x)

DMA_CORE_MP_CSR_GMRC(x)

DMA_CSR_INTMAJOR_MASK

DMA_CSR_INTHALF_MASK

DMA_CSR_DREQ_MASK

DMA_CSR_ESG_MASK

DMA_CSR_BWC_MASK

DMA_CSR_BWC(x)

DMA_CSR_START_MASK

DMA_CITER_ELINKNO_CITER_MASK

DMA_BITER_ELINKNO_BITER_MASK

DMA_CITER_ELINKNO_CITER_SHIFT

DMA_CITER_ELINKYES_CITER_MASK

DMA_CITER_ELINKYES_CITER_SHIFT

DMA_ATTR_SMOD_MASK

DMA_ATTR_DMOD_MASK

DMA_CITER_ELINKNO_ELINK_MASK

DMA_CSR_MAJORELINK_MASK

DMA_BITER_ELINKYES_ELINK_MASK

DMA_CITER_ELINKYES_ELINK_MASK

DMA_CSR_MAJORLINKCH_MASK

DMA_BITER_ELINKYES_LINKCH_MASK

DMA_CITER_ELINKYES_LINKCH_MASK

DMA_NBYTES_MLOFFYES_MLOFF_MASK

DMA_NBYTES_MLOFFYES_DMLOE_MASK

DMA_NBYTES_MLOFFYES_SMLOE_MASK

DMA_NBYTES_MLOFFNO_NBYTES_MASK

DMA_ATTR_DMOD(x)

DMA_ATTR_SMOD(x)

DMA_BITER_ELINKYES_LINKCH(x)

DMA_CITER_ELINKYES_LINKCH(x)

DMA_NBYTES_MLOFFYES_MLOFF(x)

DMA_NBYTES_MLOFFYES_DMLOE(x)

DMA_NBYTES_MLOFFYES_SMLOE(x)

DMA_NBYTES_MLOFFNO_NBYTES(x)

DMA_NBYTES_MLOFFYES_NBYTES(x)

DMA_ATTR_DSIZE(x)

DMA_ATTR_SSIZE(x)

DMA_CSR_DREQ(x)

DMA_CSR_MAJORLINKCH(x)

DMA_CH_MATTR_WCACHE(x)

DMA_CH_MATTR_RCACHE(x)

DMA_CH_CSR_SIGNEXT_MASK

DMA_CH_CSR_SIGNEXT_SHIFT

DMA_CH_CSR_SWAP_MASK

DMA_CH_CSR_SWAP_SHIFT

DMA_CH_SBR_INSTR_MASK

DMA_CH_SBR_INSTR_SHIFT

DMA_CH_SBR_EMI_MASK

DMA_CH_SBR_EMI_SHIFT

DMA_CH_MUX_SOURCE(x)

DMA_ERR_DBE_FLAG: DMA error flag.

DMA_ERR_SBE_FLAG

DMA_ERR_SGE_FLAG

DMA_ERR_NCE_FLAG

DMA_ERR_DOE_FLAG

DMA_ERR_DAE_FLAG

DMA_ERR_SOE_FLAG

DMA_ERR_SAE_FLAG

DMA_ERR_ERRCHAN_FLAG

DMA_ERR_ECX_FLAG

DMA_ERR_FLAG

DMA_CLEAR_DONE_STATUS(base, channel): get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)

DMA_ENABLE_ERROR_INT(base, channel): enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)

DMA_CLEAR_ERROR_STATUS(base, channel): get/clear error status

DMA_GET_ERROR_STATUS(base, channel)

DMA_CLEAR_INT_STATUS(base, channel): get/clear INT status

DMA_GET_INT_STATUS(base, channel)

DMA_ENABLE_MAJOR_INT(base, channel): enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)

DMA_DISABLE_MAJOR_INT(base, channel)

DMA_DISABLE_HALF_INT(base, channel)

EDMA_TCD_ALIGN_SIZE: EDMA tcd align size.

EDMA_CORE_BASE(base): EDMA base address convert macro.

EDMA_MP_BASE(base)

EDMA_CHANNEL_BASE(base, channel)

EDMA_TCD_BASE(base, channel)

EDMA_TCD_TYPE(x): EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag): EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)

EDMA_TCD_ATTR(tcd, flag)

EDMA_TCD_NBYTES(tcd, flag)

EDMA_TCD_SLAST(tcd, flag)

EDMA_TCD_DADDR(tcd, flag)

EDMA_TCD_DOFF(tcd, flag)

EDMA_TCD_CITER(tcd, flag)

EDMA_TCD_DLAST_SGA(tcd, flag)

EDMA_TCD_CSR(tcd, flag)

EDMA_TCD_BITER(tcd, flag)

struct _edma_core_mp

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT: Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR: Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI: Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint32_t SADDR_HIGH: SADDR HIGH register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t SLAST_SDA_HIGH: SLAST SDA HIGH register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint32_t DADDR_HIGH: DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH: DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

uint8_t RESERVED[16]: Aligned 64 bytes

struct _edma4_core_tcd

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

struct _edma_core_tcd: #include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS

Public Members

struct _edma_core_mp EDMA5_REG

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW: Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH: Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW: Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH: Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH: Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW: Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH: Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]: Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]: Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]: Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS

Public Members

struct _edma_core_channel EDMA5_REG

struct _edma_core_channel EDMA4_REG

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX: Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS

Public Members

edma4_core_tcd_t edma4_tcd

eDMA soc Driver#

ENET: Ethernet MAC Driver#

void ENET_GetDefaultConfig(enet_config_t *config)

Gets the ENET default configuration structure.

The purpose of this API is to get the default ENET MAC controller configure structure for ENET_Init(). User may use the initialized structure unchanged in ENET_Init(), or modify some fields of the structure before calling ENET_Init(). Example:

enet_config_t config;
ENET_GetDefaultConfig(&config);

Parameters:

config – The ENET mac controller configuration structure pointer.

status_t ENET_Up(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz)

Initializes the ENET module.

This function initializes the module with the ENET configuration.

Note

ENET has two buffer descriptors legacy buffer descriptors and enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor by defining “ENET_ENHANCEDBUFFERDESCRIPTOR_MODE” and calling ENET_Ptp1588Configure() to configure the 1588 feature and related buffers after calling ENET_Up().

Parameters:

base – ENET peripheral base address.
handle – ENET handler pointer.
config – ENET mac configuration structure pointer. The “enet_config_t” type mac configuration return from ENET_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.
bufferConfig – ENET buffer configuration structure pointer. The buffer configuration should be prepared for ENET Initialization. It is the start address of “ringNum” enet_buffer_config structures. To support added multi-ring features in some soc and compatible with the previous enet driver version. For single ring supported, this bufferConfig is a buffer configure structure pointer, for multi-ring supported and used case, this bufferConfig pointer should be a buffer configure structure array pointer.
macAddr – ENET mac address of Ethernet device. This MAC address should be provided.
srcClock_Hz – The internal module clock source for MII clock.

Return values:

kStatus_Success – Succeed to initialize the ethernet driver.
kStatus_ENET_InitMemoryFail – Init fails since buffer memory is not enough.

status_t ENET_Init(ENET_Type *base, enet_handle_t *handle, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr, uint32_t srcClock_Hz)

Initializes the ENET module.

This function ungates the module clock and initializes it with the ENET configuration.

Note

Parameters:

base – ENET peripheral base address.
handle – ENET handler pointer.
config – ENET mac configuration structure pointer. The “enet_config_t” type mac configuration return from ENET_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.
bufferConfig – ENET buffer configuration structure pointer. The buffer configuration should be prepared for ENET Initialization. It is the start address of “ringNum” enet_buffer_config structures. To support added multi-ring features in some soc and compatible with the previous enet driver version. For single ring supported, this bufferConfig is a buffer configure structure pointer, for multi-ring supported and used case, this bufferConfig pointer should be a buffer configure structure array pointer.
macAddr – ENET mac address of Ethernet device. This MAC address should be provided.
srcClock_Hz – The internal module clock source for MII clock.

Return values:

kStatus_Success – Succeed to initialize the ethernet driver.
kStatus_ENET_InitMemoryFail – Init fails since buffer memory is not enough.

void ENET_Down(ENET_Type *base)

Stops the ENET module.

This function disables the ENET module.

Parameters:

base – ENET peripheral base address.

void ENET_Deinit(ENET_Type *base)

Deinitializes the ENET module.

This function gates the module clock, clears ENET interrupts, and disables the ENET module.

Parameters:

base – ENET peripheral base address.

static inline void ENET_Reset(ENET_Type *base)

Resets the ENET module.

This function restores the ENET module to reset state. Note that this function sets all registers to reset state. As a result, the ENET module can’t work after calling this function.

Parameters:

base – ENET peripheral base address.

void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)

Sets the ENET MII speed and duplex.

This API is provided to dynamically change the speed and dulpex for MAC.

Parameters:

base – ENET peripheral base address.
speed – The speed of the RMII mode.
duplex – The duplex of the RMII mode.

void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled)

Sets the ENET SMI(serial management interface)- MII management interface.

Parameters:

base – ENET peripheral base address.
srcClock_Hz – This is the ENET module clock frequency. See clock distribution.
isPreambleDisabled – The preamble disable flag.
- true Enables the preamble.
- false Disables the preamble.

static inline bool ENET_GetSMI(ENET_Type *base)

Gets the ENET SMI- MII management interface configuration.

This API is used to get the SMI configuration to check whether the MII management interface has been set.

Parameters:

base – ENET peripheral base address.

Returns:

The SMI setup status true or false.

static inline uint32_t ENET_ReadSMIData(ENET_Type *base)

Reads data from the PHY register through an SMI interface.

Parameters:

base – ENET peripheral base address.

Returns:

The data read from PHY

static inline void ENET_StartSMIWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data)

Sends the MDIO IEEE802.3 Clause 22 format write command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOWrite() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address. Range from 0 ~ 31.
regAddr – The PHY register address. Range from 0 ~ 31.
operation – The write operation.
data – The data written to PHY.

static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_read_t operation)

Sends the MDIO IEEE802.3 Clause 22 format read command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIORead() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address. Range from 0 ~ 31.
regAddr – The PHY register address. Range from 0 ~ 31.
operation – The read operation.

status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

MDIO write with IEEE802.3 Clause 22 format.

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address. Range from 0 ~ 31.
regAddr – The PHY register. Range from 0 ~ 31.
data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 Clause 22 format.

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address. Range from 0 ~ 31.
regAddr – The PHY register. Range from 0 ~ 31.
pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

static inline void ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr)

Sends the MDIO IEEE802.3 Clause 45 format write register command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOC45Write()/ENET_MDIOC45Read() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.

static inline void ENET_StartExtC45SMIWriteData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t data)

Sends the MDIO IEEE802.3 Clause 45 format write data command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOC45Write() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
data – The data written to PHY.

static inline void ENET_StartExtC45SMIReadData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr)

Sends the MDIO IEEE802.3 Clause 45 format read data command.

After calling this function, need to check whether the transmission is over then do next MDIO operation. For ease of use, encapsulated ENET_MDIOC45Read() can be called. For customized requirements, implement with combining separated APIs.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.

status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

MDIO write with IEEE802.3 Clause 45 format.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 Clause 45 format.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled)

Control the usage of the delayed tx/rx RGMII clock.

Parameters:

base – ENET peripheral base address.
txEnabled – Enable or disable to generate the delayed version of RGMII_TXC.
rxEnabled – Enable or disable to use the delayed version of RGMII_RXC.

void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)

Sets the ENET module Mac address.

Parameters:

base – ENET peripheral base address.
macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.

void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)

Gets the ENET module Mac address.

Parameters:

base – ENET peripheral base address.
macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.

void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address)

Adds the ENET device to a multicast group.

Parameters:

base – ENET peripheral base address.
address – The six-byte multicast group address which is provided by application.

void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address)

Moves the ENET device from a multicast group.

Parameters:

base – ENET peripheral base address.
address – The six-byte multicast group address which is provided by application.

static inline void ENET_ActiveRead(ENET_Type *base)

Activates frame reception for multiple rings.

This function is to active the enet read process.

Note

This must be called after the MAC configuration and state are ready. It must be called after the ENET_Init(). This should be called when the frame reception is required.

Parameters:

base – ENET peripheral base address.

static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable)

Enables/disables the MAC to enter sleep mode. This function is used to set the MAC enter sleep mode. When entering sleep mode, the magic frame wakeup interrupt should be enabled to wake up MAC from the sleep mode and reset it to normal mode.

Parameters:

base – ENET peripheral base address.
enable – True enable sleep mode, false disable sleep mode.

static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption)

Gets ENET transmit and receive accelerator functions from MAC controller.

Parameters:

base – ENET peripheral base address.
txAccelOption – The transmit accelerator option. The “enet_tx_accelerator_t” is recommended to be used to as the mask to get the exact the accelerator option.
rxAccelOption – The receive accelerator option. The “enet_rx_accelerator_t” is recommended to be used to as the mask to get the exact the accelerator option.

static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)

Enables the ENET interrupt.

This function enables the ENET interrupt according to the provided mask. The mask is a logical OR of enumeration members. See enet_interrupt_enable_t. For example, to enable the TX frame interrupt and RX frame interrupt, do the following.

ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);

Parameters:

base – ENET peripheral base address.
mask – ENET interrupts to enable. This is a logical OR of the enumeration enet_interrupt_enable_t.

static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)

Disables the ENET interrupt.

This function disables the ENET interrupts according to the provided mask. The mask is a logical OR of enumeration members. See enet_interrupt_enable_t. For example, to disable the TX frame interrupt and RX frame interrupt, do the following.

ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);

Parameters:

base – ENET peripheral base address.
mask – ENET interrupts to disable. This is a logical OR of the enumeration enet_interrupt_enable_t.

static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base)

Gets the ENET interrupt status flag.

Parameters:

base – ENET peripheral base address.

Returns:

The event status of the interrupt source. This is the logical OR of members of the enumeration enet_interrupt_enable_t.

static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask)

Clears the ENET interrupt events status flag.

This function clears enabled ENET interrupts according to the provided mask. The mask is a logical OR of enumeration members. See the enet_interrupt_enable_t. For example, to clear the TX frame interrupt and RX frame interrupt, do the following.

ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);

Parameters:

base – ENET peripheral base address.
mask – ENET interrupt source to be cleared. This is the logical OR of members of the enumeration enet_interrupt_enable_t.

void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler)

Set the second level Rx IRQ handler.

Parameters:

base – ENET peripheral base address.
ISRHandler – The handler to install.

void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler)

Set the second level Tx IRQ handler.

Parameters:

base – ENET peripheral base address.
ISRHandler – The handler to install.

void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler)

Set the second level Err IRQ handler.

Parameters:

base – ENET peripheral base address.
ISRHandler – The handler to install.

void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId)

Gets the error statistics of a received frame for ENET specified ring.

This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. This is an example.

status = ENET_GetRxFrameSize(&g_handle, &length, 0);
if (status == kStatus_ENET_RxFrameError)
{
    Comments: Get the error information of the received frame.
    ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic, 0);
    Comments: update the receive buffer.
    ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0);
}

Parameters:

handle – The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init.
eErrorStatic – The error statistics structure pointer.
ringId – The ring index, range from 0 ~ (FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) - 1).

void ENET_EnableStatistics(ENET_Type *base, bool enable)

Enables/disables collection of transfer statistics.

Note that this function does not reset any of the already collected data, use the function ENET_ResetStatistics to clear the transfer statistics if needed.

Parameters:

base – ENET peripheral base address.
enable – True enable statistics collection, false disable statistics collection.

void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics)

Gets transfer statistics.

Copies the actual value of hardware counters into the provided structure. Calling this function does not reset the counters in hardware.

Parameters:

base – ENET peripheral base address.
statistics – The statistics structure pointer.

void ENET_ResetStatistics(ENET_Type *base)

Resets transfer statistics.

Sets the value of hardware transfer counters to zero.

Parameters:

base – ENET peripheral base address.

status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId)

Gets the size of the read frame for specified ring.

This function gets a received frame size from the ENET buffer descriptors.

Note

The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to receive frame and update the BD if the result is not “kStatus_ENET_RxFrameEmpty”.

Parameters:

handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.
length – The length of the valid frame received.
ringId – The ring index or ring number.

Return values:

kStatus_ENET_RxFrameEmpty – No frame received. Should not call ENET_ReadFrame to read frame.
kStatus_ENET_RxFrameError – Data error happens. ENET_ReadFrame should be called with NULL data and NULL length to update the receive buffers.
kStatus_Success – Receive a frame Successfully then the ENET_ReadFrame should be called with the right data buffer and the captured data length input.

status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts)

Reads a frame from the ENET device. This function reads a frame (both the data and the length) from the ENET buffer descriptors. User can get timestamp through ts pointer if the ts is not NULL.

Note

It doesn’t store the timestamp in the receive timestamp queue. The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time consumption. This is an example:

uint32_t length;
enet_handle_t g_handle;
Comments: Get the received frame size firstly.
status = ENET_GetRxFrameSize(&g_handle, &length, 0);
if (length != 0)
{
    Comments: Allocate memory here with the size of "length"
    uint8_t *data = memory allocate interface;
    if (!data)
    {
        ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL);
        Comments: Add the console warning log.
    }
    else
    {
        status = ENET_ReadFrame(ENET, &g_handle, data, length, 0, NULL);
        Comments: Call stack input API to deliver the data to stack
    }
}
else if (status == kStatus_ENET_RxFrameError)
{
    Comments: Update the received buffer when a error frame is received.
    ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0, NULL);
}

Parameters:

base – ENET peripheral base address.
handle – The ENET handler structure. This is the same handler pointer used in the ENET_Init.
data – The data buffer provided by user to store the frame which memory size should be at least “length”.
length – The size of the data buffer which is still the length of the received frame.
ringId – The ring index or ring number.
ts – The timestamp address to store received timestamp.

Returns:

The execute status, successful or failure.

status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length, uint8_t ringId, bool tsFlag, void *context)

Transmits an ENET frame for specified ring.

Note

The CRC is automatically appended to the data. Input the data to send without the CRC. This API uses memcpy to copy data from DMA buffer to application buffer, 4 bytes aligned data buffer in 32 bits platforms provided by user may let compiler use optimization instruction to reduce time consumption.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
data – The data buffer provided by user to send.
length – The length of the data to send.
ringId – The ring index or ring number.
tsFlag – Timestamp enable flag.
context – Used by user to handle some events after transmit over.

Return values:

kStatus_Success – Send frame succeed.
kStatus_ENET_TxFrameBusy – Transmit buffer descriptor is busy under transmission. The transmit busy happens when the data send rate is over the MAC capacity. The waiting mechanism is recommended to be added after each call return with kStatus_ENET_TxFrameBusy.

status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId)

Enable or disable tx descriptors reclaim mechanism.

Note

This function must be called when no pending send frame action. Set enable if you want to reclaim context or timestamp in interrupt.

Parameters:

handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
isEnable – Enable or disable flag.
ringId – The ring index or ring number.

Return values:

kStatus_Success – Succeed to enable/disable Tx reclaim.
kStatus_Fail – Fail to enable/disable Tx reclaim.

void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId)

Reclaim tx descriptors. This function is used to update the tx descriptor status and store the tx timestamp when the 1588 feature is enabled. This is called by the transmit interupt IRQ handler after the complete of a frame transmission.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
ringId – The ring index or ring number.

status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId)

Receives one frame in specified BD ring with zero copy.

This function uses the user-defined allocation and free callbacks. Every time application gets one frame through this function, driver stores the buffer address(es) in enet_buffer_struct_t and allocate new buffer(s) for the BD(s). If there’s no memory buffer in the pool, this function drops current one frame to keep the Rx frame in BD ring is as fresh as possible.

Note

Application must provide a memory pool including at least BD number + n buffers in order for this function to work properly, because each BD must always take one buffer while driver is running, then other extra n buffer(s) can be taken by application. Here n is the ceil(max_frame_length(set by RCR) / bd_rx_size(set by MRBR)). Application must also provide an array structure in rxFrame->rxBuffArray with n index to receive one complete frame in any case.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
rxFrame – The received frame information structure provided by user.
ringId – The ring index or ring number.

Return values:

kStatus_Success – Succeed to get one frame and allocate new memory for Rx buffer.
kStatus_ENET_RxFrameEmpty – There’s no Rx frame in the BD.
kStatus_ENET_RxFrameError – There’s issue in this receiving.
kStatus_ENET_RxFrameDrop – There’s no new buffer memory for BD, drop this frame.

status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId)

Sends one frame in specified BD ring with zero copy.

This function supports scattered buffer transmit, user needs to provide the buffer array.

Note

Tx reclaim should be enabled to ensure the Tx buffer ownership can be given back to application after Tx is over.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
txFrame – The Tx frame structure.
ringId – The ring index or ring number.

Return values:

kStatus_Success – Succeed to send one frame.
kStatus_ENET_TxFrameBusy – The BD is not ready for Tx or the reclaim operation still not finishs.
kStatus_ENET_TxFrameOverLen – The Tx frame length is over max ethernet frame length.

void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)

The transmit IRQ handler.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer.

void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle)

The receive IRQ handler.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer.

void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)

Some special IRQ handler including the error, mii, wakeup irq handler.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer.

void ENET_Ptp1588IRQHandler(ENET_Type *base)

the common IRQ handler for the 1588 irq handler.

This is used for the 1588 timer interrupt.

Parameters:

base – ENET peripheral base address.

void ENET_CommonFrame0IRQHandler(ENET_Type *base)

the common IRQ handler for the tx/rx/error etc irq handler.

This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0).

Parameters:

base – ENET peripheral base address.

FSL_ENET_DRIVER_VERSION: Defines the driver version.

ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK: Empty bit mask.

ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK: Software owner one mask.

ENET_BUFFDESCRIPTOR_RX_WRAP_MASK: Next buffer descriptor is the start address.

ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask: Software owner two mask.

ENET_BUFFDESCRIPTOR_RX_LAST_MASK: Last BD of the frame mask.

ENET_BUFFDESCRIPTOR_RX_MISS_MASK: Received because of the promiscuous mode.

ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK: Broadcast packet mask.

ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK: Multicast packet mask.

ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK: Length violation mask.

ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK: Non-octet aligned frame mask.

ENET_BUFFDESCRIPTOR_RX_CRC_MASK: CRC error mask.

ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK: FIFO overrun mask.

ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK: Frame is truncated mask.

ENET_BUFFDESCRIPTOR_TX_READY_MASK: Ready bit mask.

ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK: Software owner one mask.

ENET_BUFFDESCRIPTOR_TX_WRAP_MASK: Wrap buffer descriptor mask.

ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK: Software owner two mask.

ENET_BUFFDESCRIPTOR_TX_LAST_MASK: Last BD of the frame mask.

ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK: Transmit CRC mask.

ENET_FRAME_MAX_FRAMELEN: Default maximum Ethernet frame size without VLAN tag.

ENET_FRAME_VLAN_TAGLEN: Ethernet single VLAN tag size.

ENET_FRAME_CRC_LEN: CRC size in a frame.

ENET_FRAME_TX_LEN_LIMITATION(x)

ENET_FIFO_MIN_RX_FULL: ENET minimum receive FIFO full.

ENET_RX_MIN_BUFFERSIZE: ENET minimum buffer size.

ENET_PHY_MAXADDRESS: Maximum PHY address.

ENET_TX_INTERRUPT: Enet Tx interrupt flag.

ENET_RX_INTERRUPT: Enet Rx interrupt flag.

ENET_TS_INTERRUPT: Enet timestamp interrupt flag.

ENET_ERR_INTERRUPT: Enet error interrupt flag.

Defines the status return codes for transaction.

Values:

enumerator kStatus_ENET_InitMemoryFail: Init fails since buffer memory is not enough.

enumerator kStatus_ENET_RxFrameError: A frame received but data error happen.

enumerator kStatus_ENET_RxFrameFail: Failed to receive a frame.

enumerator kStatus_ENET_RxFrameEmpty: No frame arrive.

enumerator kStatus_ENET_RxFrameDrop: Rx frame is dropped since no buffer memory.

enumerator kStatus_ENET_TxFrameOverLen: Tx frame over length.

enumerator kStatus_ENET_TxFrameBusy: Tx buffer descriptors are under process.

enumerator kStatus_ENET_TxFrameFail: Transmit frame fail.

enum _enet_mii_mode

Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY.

Values:

enumerator kENET_MiiMode: MII mode for data interface.

enumerator kENET_RmiiMode: RMII mode for data interface.

enumerator kENET_RgmiiMode: RGMII mode for data interface.

enum _enet_mii_speed

Defines the 10/100/1000 Mbps speed for the MII data interface.

Notice: “kENET_MiiSpeed1000M” only supported when mii mode is “kENET_RgmiiMode”.

Values:

enumerator kENET_MiiSpeed10M: Speed 10 Mbps.

enumerator kENET_MiiSpeed100M: Speed 100 Mbps.

enumerator kENET_MiiSpeed1000M: Speed 1000M bps.

enum _enet_mii_duplex

Defines the half or full duplex for the MII data interface.

Values:

enumerator kENET_MiiHalfDuplex: Half duplex mode.

enumerator kENET_MiiFullDuplex: Full duplex mode.

enum _enet_mii_write

Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

Values:

enumerator kENET_MiiWriteNoCompliant: Write frame operation, but not MII-compliant.

enumerator kENET_MiiWriteValidFrame: Write frame operation for a valid MII management frame.

enum _enet_mii_read

Defines the read operation for the MII management frame.

Values:

enumerator kENET_MiiReadValidFrame: Read frame operation for a valid MII management frame.

enumerator kENET_MiiReadNoCompliant: Read frame operation, but not MII-compliant.

enum _enet_mii_extend_opcode

Define the MII opcode for extended MDIO_CLAUSES_45 Frame.

Values:

enumerator kENET_MiiAddrWrite_C45: Address Write operation.

enumerator kENET_MiiWriteFrame_C45: Write frame operation for a valid MII management frame.

enumerator kENET_MiiReadFrame_C45: Read frame operation for a valid MII management frame.

enum _enet_special_control_flag

Defines a special configuration for ENET MAC controller.

These control flags are provided for special user requirements. Normally, these control flags are unused for ENET initialization. For special requirements, set the flags to macSpecialConfig in the enet_config_t. The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store and forward. FIFO store and forward means that the FIFO read/send is started when a complete frame is stored in TX/RX FIFO. If this flag is set, configure rxFifoFullThreshold and txFifoWatermark in the enet_config_t.

Values:

enumerator kENET_ControlFlowControlEnable: Enable ENET flow control: pause frame.

enumerator kENET_ControlRxPayloadCheckEnable: Enable ENET receive payload length check.

enumerator kENET_ControlRxPadRemoveEnable: Padding is removed from received frames.

enumerator kENET_ControlRxBroadCastRejectEnable: Enable broadcast frame reject.

enumerator kENET_ControlMacAddrInsert: Enable MAC address insert.

enumerator kENET_ControlStoreAndFwdDisable: Enable FIFO store and forward.

enumerator kENET_ControlSMIPreambleDisable: Enable SMI preamble.

enumerator kENET_ControlPromiscuousEnable: Enable promiscuous mode.

enumerator kENET_ControlMIILoopEnable: Enable ENET MII loop back.

enumerator kENET_ControlVLANTagEnable: Enable normal VLAN (single vlan tag).

enumerator kENET_ControlSVLANEnable: Enable S-VLAN.

enumerator kENET_ControlVLANUseSecondTag: Enable extracting the second vlan tag for further processing.

enum _enet_interrupt_enable

List of interrupts supported by the peripheral. This enumeration uses one-bit encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

Values:

enumerator kENET_BabrInterrupt: Babbling receive error interrupt source

enumerator kENET_BabtInterrupt: Babbling transmit error interrupt source

enumerator kENET_GraceStopInterrupt: Graceful stop complete interrupt source

enumerator kENET_TxFrameInterrupt: TX FRAME interrupt source

enumerator kENET_TxBufferInterrupt: TX BUFFER interrupt source

enumerator kENET_RxFrameInterrupt: RX FRAME interrupt source

enumerator kENET_RxBufferInterrupt: RX BUFFER interrupt source

enumerator kENET_MiiInterrupt: MII interrupt source

enumerator kENET_EBusERInterrupt: Ethernet bus error interrupt source

enumerator kENET_LateCollisionInterrupt: Late collision interrupt source

enumerator kENET_RetryLimitInterrupt: Collision Retry Limit interrupt source

enumerator kENET_UnderrunInterrupt: Transmit FIFO underrun interrupt source

enumerator kENET_PayloadRxInterrupt: Payload Receive error interrupt source

enumerator kENET_WakeupInterrupt: WAKEUP interrupt source

enumerator kENET_TsAvailInterrupt: TS AVAIL interrupt source for PTP

enumerator kENET_TsTimerInterrupt: TS WRAP interrupt source for PTP

enum _enet_event

Defines the common interrupt event for callback use.

Values:

enumerator kENET_RxEvent: Receive event.

enumerator kENET_TxEvent: Transmit event.

enumerator kENET_ErrEvent: Error event: BABR/BABT/EBERR/LC/RL/UN/PLR .

enumerator kENET_WakeUpEvent: Wake up from sleep mode event.

enumerator kENET_TimeStampEvent: Time stamp event.

enumerator kENET_TimeStampAvailEvent: Time stamp available event.

enum _enet_idle_slope

Defines certain idle slope for bandwidth fraction.

Values:

enumerator kENET_IdleSlope1: The bandwidth fraction is about 0.002.

enumerator kENET_IdleSlope2: The bandwidth fraction is about 0.003.

enumerator kENET_IdleSlope4: The bandwidth fraction is about 0.008.

enumerator kENET_IdleSlope8: The bandwidth fraction is about 0.02.

enumerator kENET_IdleSlope16: The bandwidth fraction is about 0.03.

enumerator kENET_IdleSlope32: The bandwidth fraction is about 0.06.

enumerator kENET_IdleSlope64: The bandwidth fraction is about 0.11.

enumerator kENET_IdleSlope128: The bandwidth fraction is about 0.20.

enumerator kENET_IdleSlope256: The bandwidth fraction is about 0.33.

enumerator kENET_IdleSlope384: The bandwidth fraction is about 0.43.

enumerator kENET_IdleSlope512: The bandwidth fraction is about 0.50.

enumerator kENET_IdleSlope640: The bandwidth fraction is about 0.56.

enumerator kENET_IdleSlope768: The bandwidth fraction is about 0.60.

enumerator kENET_IdleSlope896: The bandwidth fraction is about 0.64.

enumerator kENET_IdleSlope1024: The bandwidth fraction is about 0.67.

enumerator kENET_IdleSlope1152: The bandwidth fraction is about 0.69.

enumerator kENET_IdleSlope1280: The bandwidth fraction is about 0.71.

enumerator kENET_IdleSlope1408: The bandwidth fraction is about 0.73.

enumerator kENET_IdleSlope1536: The bandwidth fraction is about 0.75.

enum _enet_tx_accelerator

Defines the transmit accelerator configuration.

Note that the hardware does not insert ICMPv6 protocol checksums as mentioned in errata ERR052152.

Values:

enumerator kENET_TxAccelIsShift16Enabled: Transmit FIFO shift-16.

enumerator kENET_TxAccelIpCheckEnabled: Insert IP header checksum.

enumerator kENET_TxAccelProtoCheckEnabled: Insert protocol checksum (TCP, UDP, ICMPv4).

enum _enet_rx_accelerator

Defines the receive accelerator configuration.

Note that the hardware does not validate ICMPv6 protocol checksums as mentioned in errata ERR052152.

Values:

enumerator kENET_RxAccelPadRemoveEnabled: Padding removal for short IP frames.

enumerator kENET_RxAccelIpCheckEnabled: Discard with wrong IP header checksum.

enumerator kENET_RxAccelProtoCheckEnabled: Discard with wrong protocol checksum (TCP, UDP, ICMPv4).

enumerator kENET_RxAccelMacCheckEnabled: Discard with Mac layer errors.

enumerator kENET_RxAccelisShift16Enabled: Receive FIFO shift-16.

typedef enum _enet_mii_mode enet_mii_mode_t: Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY.

typedef enum _enet_mii_speed enet_mii_speed_t

Defines the 10/100/1000 Mbps speed for the MII data interface.

Notice: “kENET_MiiSpeed1000M” only supported when mii mode is “kENET_RgmiiMode”.

typedef enum _enet_mii_duplex enet_mii_duplex_t: Defines the half or full duplex for the MII data interface.

typedef enum _enet_mii_write enet_mii_write_t: Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

typedef enum _enet_mii_read enet_mii_read_t: Defines the read operation for the MII management frame.

typedef enum _enet_mii_extend_opcode enet_mii_extend_opcode: Define the MII opcode for extended MDIO_CLAUSES_45 Frame.

typedef enum _enet_special_control_flag enet_special_control_flag_t

Defines a special configuration for ENET MAC controller.

typedef enum _enet_interrupt_enable enet_interrupt_enable_t: List of interrupts supported by the peripheral. This enumeration uses one-bit encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

typedef enum _enet_event enet_event_t: Defines the common interrupt event for callback use.

typedef enum _enet_idle_slope enet_idle_slope_t: Defines certain idle slope for bandwidth fraction.

typedef enum _enet_tx_accelerator enet_tx_accelerator_t

Defines the transmit accelerator configuration.

Note that the hardware does not insert ICMPv6 protocol checksums as mentioned in errata ERR052152.

typedef enum _enet_rx_accelerator enet_rx_accelerator_t

Defines the receive accelerator configuration.

Note that the hardware does not validate ICMPv6 protocol checksums as mentioned in errata ERR052152.

typedef struct _enet_rx_bd_struct enet_rx_bd_struct_t: Defines the receive buffer descriptor structure for the little endian system.

typedef struct _enet_tx_bd_struct enet_tx_bd_struct_t: Defines the enhanced transmit buffer descriptor structure for the little endian system.

typedef struct _enet_data_error_stats enet_data_error_stats_t: Defines the ENET data error statistics structure.

typedef struct _enet_rx_frame_error enet_rx_frame_error_t: Defines the Rx frame error structure.

typedef struct _enet_transfer_stats enet_transfer_stats_t: Defines the ENET transfer statistics structure.

typedef struct enet_frame_info enet_frame_info_t: Defines the frame info structure.

typedef struct _enet_tx_dirty_ring enet_tx_dirty_ring_t: Defines the ENET transmit dirty addresses ring/queue structure.

typedef void *(*enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId): Defines the ENET Rx memory buffer alloc function pointer.

typedef void (*enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId): Defines the ENET Rx memory buffer free function pointer.

typedef struct _enet_buffer_config enet_buffer_config_t

Defines the receive buffer descriptor configuration structure.

Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.

The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.
The aligned transmit and receive buffer descriptor start address must be at least 64 bit aligned. However, it’s recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. buffer descriptors should be put in non-cacheable region when cache is enabled.
The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. Receive buffers should be continuous with the total size equal to “rxBdNumber * rxBuffSizeAlign”. Transmit buffers should be continuous with the total size equal to “txBdNumber * txBuffSizeAlign”. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.

typedef struct _enet_intcoalesce_config enet_intcoalesce_config_t: Defines the interrupt coalescing configure structure.

typedef struct _enet_avb_config enet_avb_config_t

Defines the ENET AVB Configure structure.

This is used for to configure the extended ring 1 and ring 2.

The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel.

If CMP1,2,3 are not unused, please set them to the same value as CMP0.

The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75.

typedef struct _enet_handle enet_handle_t

typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, enet_frame_info_t *frameInfo, void *userData): ENET callback function.

typedef struct _enet_config enet_config_t

Defines the basic configuration structure for the ENET device.

Note:

macSpecialConfig is used for a special control configuration, A logical OR of “enet_special_control_flag_t”. For a special configuration for MAC, set this parameter to 0.
txWatermark is used for a cut-through operation. It is in steps of 64 bytes: 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. 2 - 128 bytes written to TX FIFO …. 3 - 192 bytes written to TX FIFO …. The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO …. txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 or for larger bus access latency 3 or larger due to contention for the system bus.
rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. If the end of the frame is stored in FIFO and the frame size if smaller than the txWatermark, the frame is still transmitted. The rule is the same for rxFifoFullThreshold in the receive direction.
When “kENET_ControlFlowControlEnable” is set in the macSpecialConfig, ensure that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold are set for flow control enabled case.
When “kENET_ControlStoreAndFwdDisabled” is set in the macSpecialConfig, ensure that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable.
The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator are disabled. The “enet_tx_accelerator_t” and “enet_rx_accelerator_t” are recommended to be used to enable the transmit and receive accelerator. After the accelerators are enabled, the store and forward feature should be enabled. As a result, kENET_ControlStoreAndFwdDisabled should not be set.
The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading.

typedef struct _enet_tx_bd_ring enet_tx_bd_ring_t: Defines the ENET transmit buffer descriptor ring/queue structure.

typedef struct _enet_rx_bd_ring enet_rx_bd_ring_t: Defines the ENET receive buffer descriptor ring/queue structure.

typedef struct _enet_buffer_struct enet_buffer_struct_t

typedef struct _enet_rx_frame_attribute_struct enet_rx_frame_attribute_t

typedef struct _enet_rx_frame_struct enet_rx_frame_struct_t

typedef struct _enet_tx_frame_struct enet_tx_frame_struct_t

typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle): Define interrupt IRQ handler.

const clock_ip_name_t s_enetClock[]: Pointers to enet clocks for each instance.

const clock_ip_name_t s_enetExtraClock[]

uint32_t ENET_GetInstance(ENET_Type *base)

Get the ENET instance from peripheral base address.

Parameters:

base – ENET peripheral base address.

Returns:

ENET instance.

ENET_BUFFDESCRIPTOR_RX_ERR_MASK: Defines the receive error status flag mask.

struct _enet_rx_bd_struct

#include <fsl_enet.h>

Defines the receive buffer descriptor structure for the little endian system.

Public Members

uint16_t length: Buffer descriptor data length.

uint16_t control: Buffer descriptor control and status.

uint32_t buffer: Data buffer pointer.

struct _enet_tx_bd_struct

#include <fsl_enet.h>

Defines the enhanced transmit buffer descriptor structure for the little endian system.

Public Members

uint16_t length: Buffer descriptor data length.

uint16_t control: Buffer descriptor control and status.

uint32_t buffer: Data buffer pointer.

struct _enet_data_error_stats

#include <fsl_enet.h>

Defines the ENET data error statistics structure.

Public Members

uint32_t statsRxLenGreaterErr: Receive length greater than RCR[MAX_FL].

uint32_t statsRxAlignErr: Receive non-octet alignment/

uint32_t statsRxFcsErr: Receive CRC error.

uint32_t statsRxOverRunErr: Receive over run.

uint32_t statsRxTruncateErr: Receive truncate.

struct _enet_rx_frame_error

#include <fsl_enet.h>

Defines the Rx frame error structure.

Public Members

bool statsRxTruncateErr: Receive truncate.

bool statsRxOverRunErr: Receive over run.

bool statsRxFcsErr: Receive CRC error.

bool statsRxAlignErr: Receive non-octet alignment.

bool statsRxLenGreaterErr: Receive length greater than RCR[MAX_FL].

struct _enet_transfer_stats

#include <fsl_enet.h>

Defines the ENET transfer statistics structure.

Public Members

uint32_t statsRxFrameCount: Rx frame number.

uint32_t statsRxFrameOk: Good Rx frame number.

uint32_t statsRxCrcErr: Rx frame number with CRC error.

uint32_t statsRxAlignErr: Rx frame number with alignment error.

uint32_t statsRxDropInvalidSFD: Dropped frame number due to invalid SFD.

uint32_t statsRxFifoOverflowErr: Rx FIFO overflow count.

uint32_t statsTxFrameCount: Tx frame number.

uint32_t statsTxFrameOk: Good Tx frame number.

uint32_t statsTxCrcAlignErr: The transmit frame is error.

uint32_t statsTxFifoUnderRunErr: Tx FIFO underrun count.

struct enet_frame_info

#include <fsl_enet.h>

Defines the frame info structure.

Public Members

void *context: User specified data

struct _enet_tx_dirty_ring

#include <fsl_enet.h>

Defines the ENET transmit dirty addresses ring/queue structure.

Public Members

enet_frame_info_t *txDirtyBase: Dirty buffer descriptor base address pointer.

uint16_t txGenIdx: tx generate index.

uint16_t txConsumIdx: tx consume index.

uint16_t txRingLen: tx ring length.

bool isFull: tx ring is full flag.

struct _enet_buffer_config

#include <fsl_enet.h>

Defines the receive buffer descriptor configuration structure.

Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.

The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.
The aligned transmit and receive buffer descriptor start address must be at least 64 bit aligned. However, it’s recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. buffer descriptors should be put in non-cacheable region when cache is enabled.
The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. Receive buffers should be continuous with the total size equal to “rxBdNumber * rxBuffSizeAlign”. Transmit buffers should be continuous with the total size equal to “txBdNumber * txBuffSizeAlign”. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of “ENET_BUFF_ALIGNMENT” and the cache line size.

Public Members

uint16_t rxBdNumber: Receive buffer descriptor number.

uint16_t txBdNumber: Transmit buffer descriptor number.

uint16_t rxBuffSizeAlign: Aligned receive data buffer size.

uint16_t txBuffSizeAlign: Aligned transmit data buffer size.

volatile enet_rx_bd_struct_t *rxBdStartAddrAlign: Aligned receive buffer descriptor start address: should be non-cacheable.

volatile enet_tx_bd_struct_t *txBdStartAddrAlign: Aligned transmit buffer descriptor start address: should be non-cacheable.

uint8_t *rxBufferAlign: Receive data buffer start address.

uint8_t *txBufferAlign: Transmit data buffer start address.

bool rxMaintainEnable: Receive buffer cache maintain.

bool txMaintainEnable: Transmit buffer cache maintain.

enet_frame_info_t *txFrameInfo: Transmit frame information start address.

struct _enet_intcoalesce_config

#include <fsl_enet.h>

Defines the interrupt coalescing configure structure.

Public Members

uint8_t txCoalesceFrameCount[1]: Transmit interrupt coalescing frame count threshold.

uint16_t txCoalesceTimeCount[1]: Transmit interrupt coalescing timer count threshold.

uint8_t rxCoalesceFrameCount[1]: Receive interrupt coalescing frame count threshold.

uint16_t rxCoalesceTimeCount[1]: Receive interrupt coalescing timer count threshold.

struct _enet_avb_config

#include <fsl_enet.h>

Defines the ENET AVB Configure structure.

This is used for to configure the extended ring 1 and ring 2.

The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel.

If CMP1,2,3 are not unused, please set them to the same value as CMP0.

The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75.

Public Members

uint16_t rxClassifyMatch[1 - 1]: The classification match value for the ring.

enet_idle_slope_t idleSlope[1 - 1]: The idle slope for certian bandwidth fraction.

struct _enet_config

#include <fsl_enet.h>

Defines the basic configuration structure for the ENET device.

Note:

macSpecialConfig is used for a special control configuration, A logical OR of “enet_special_control_flag_t”. For a special configuration for MAC, set this parameter to 0.
txWatermark is used for a cut-through operation. It is in steps of 64 bytes: 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. 2 - 128 bytes written to TX FIFO …. 3 - 192 bytes written to TX FIFO …. The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO …. txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 or for larger bus access latency 3 or larger due to contention for the system bus.
rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. If the end of the frame is stored in FIFO and the frame size if smaller than the txWatermark, the frame is still transmitted. The rule is the same for rxFifoFullThreshold in the receive direction.
When “kENET_ControlFlowControlEnable” is set in the macSpecialConfig, ensure that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold are set for flow control enabled case.
When “kENET_ControlStoreAndFwdDisabled” is set in the macSpecialConfig, ensure that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable.
The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator are disabled. The “enet_tx_accelerator_t” and “enet_rx_accelerator_t” are recommended to be used to enable the transmit and receive accelerator. After the accelerators are enabled, the store and forward feature should be enabled. As a result, kENET_ControlStoreAndFwdDisabled should not be set.
The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading.

Public Members

uint32_t macSpecialConfig: Mac special configuration. A logical OR of “enet_special_control_flag_t”.

uint32_t interrupt: Mac interrupt source. A logical OR of “enet_interrupt_enable_t”.

uint16_t rxMaxFrameLen: Receive maximum frame length.

enet_mii_mode_t miiMode: MII mode.

enet_mii_speed_t miiSpeed: MII Speed.

enet_mii_duplex_t miiDuplex: MII duplex.

uint8_t rxAccelerConfig: Receive accelerator, A logical OR of “enet_rx_accelerator_t”.

uint8_t txAccelerConfig: Transmit accelerator, A logical OR of “enet_rx_accelerator_t”.

uint16_t pauseDuration: For flow control enabled case: Pause duration.

uint8_t rxFifoEmptyThreshold: For flow control enabled case: when RX FIFO level reaches this value, it makes MAC generate XOFF pause frame.

uint8_t rxFifoStatEmptyThreshold: For flow control enabled case: number of frames in the receive FIFO, independent of size, that can be accept. If the limit is reached, reception continues and a pause frame is triggered.

uint8_t rxFifoFullThreshold: For store and forward disable case, the data required in RX FIFO to notify the MAC receive ready status.

uint8_t txFifoWatermark: For store and forward disable case, the data required in TX FIFO before a frame transmit start.

enet_intcoalesce_config_t *intCoalesceCfg: If the interrupt coalsecence is not required in the ring n(0,1,2), please set to NULL.

uint8_t ringNum: Number of used rings. default with 1 — single ring.

enet_rx_alloc_callback_t rxBuffAlloc: Callback function to alloc memory, must be provided for zero-copy Rx.

enet_rx_free_callback_t rxBuffFree: Callback function to free memory, must be provided for zero-copy Rx.

enet_callback_t callback: General callback function.

void *userData: Callback function parameter.

struct _enet_tx_bd_ring

#include <fsl_enet.h>

Defines the ENET transmit buffer descriptor ring/queue structure.

Public Members

volatile enet_tx_bd_struct_t *txBdBase: Buffer descriptor base address pointer.

uint16_t txGenIdx: The current available transmit buffer descriptor pointer.

uint16_t txConsumIdx: Transmit consume index.

volatile uint16_t txDescUsed: Transmit descriptor used number.

uint16_t txRingLen: Transmit ring length.

struct _enet_rx_bd_ring

#include <fsl_enet.h>

Defines the ENET receive buffer descriptor ring/queue structure.

Public Members

volatile enet_rx_bd_struct_t *rxBdBase: Buffer descriptor base address pointer.

uint16_t rxGenIdx: The current available receive buffer descriptor pointer.

uint16_t rxRingLen: Receive ring length.

struct _enet_handle

#include <fsl_enet.h>

Defines the ENET handler structure.

Public Members

enet_rx_bd_ring_t rxBdRing[1]: Receive buffer descriptor.

enet_tx_bd_ring_t txBdRing[1]: Transmit buffer descriptor.

uint16_t rxBuffSizeAlign[1]: Receive buffer size alignment.

uint16_t txBuffSizeAlign[1]: Transmit buffer size alignment.

bool rxMaintainEnable[1]: Receive buffer cache maintain.

bool txMaintainEnable[1]: Transmit buffer cache maintain.

uint8_t ringNum: Number of used rings.

enet_callback_t callback: Callback function.

void *userData: Callback function parameter.

enet_tx_dirty_ring_t txDirtyRing[1]: Ring to store tx frame information.

bool txReclaimEnable[1]: Tx reclaim enable flag.

enet_rx_alloc_callback_t rxBuffAlloc: Callback function to alloc memory for zero copy Rx.

enet_rx_free_callback_t rxBuffFree: Callback function to free memory for zero copy Rx.

uint8_t multicastCount[64]: Multicast collisions counter

uint32_t enetClock: The clock of enet peripheral, to caculate core cycles for PTP timestamp.

uint32_t tsDelayCount: The count of core cycles for PTP timestamp capture delay.

struct _enet_buffer_struct

Public Members

void *buffer: The buffer store the whole or partial frame.

uint16_t length: The byte length of this buffer.

struct _enet_rx_frame_attribute_struct

Public Members

bool promiscuous: This frame is received because of promiscuous mode.

struct _enet_rx_frame_struct

Public Members

enet_buffer_struct_t *rxBuffArray: Rx frame buffer structure.

uint16_t totLen: Rx frame total length.

enet_rx_frame_attribute_t rxAttribute: Rx frame attribute structure.

enet_rx_frame_error_t rxFrameError: Rx frame error.

struct _enet_tx_frame_struct

Public Members

enet_buffer_struct_t *txBuffArray: Tx frame buffer structure.

uint32_t txBuffNum: Buffer number of this Tx frame.

void *context: Driver reclaims and gives it in Tx over callback, usually store network packet header.

EQOS-TSN: Ethernet QoS with TSN Driver#

Enet_qos_qos#

void ENET_QOS_GetDefaultConfig(enet_qos_config_t *config)

Gets the ENET default configuration structure.

The purpose of this API is to get the default ENET configure structure for ENET_QOS_Init(). User may use the initialized structure unchanged in ENET_QOS_Init(), or modify some fields of the structure before calling ENET_QOS_Init(). Example:

enet_qos_config_t config;
ENET_QOS_GetDefaultConfig(&config);

Parameters:

config – The ENET mac controller configuration structure pointer.

status_t ENET_QOS_Up(ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz)

Initializes the ENET module.

This function initializes it with the ENET basic configuration.

Parameters:

base – ENET peripheral base address.
config – ENET mac configuration structure pointer. The “enet_qos_config_t” type mac configuration return from ENET_QOS_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.
macAddr – Pointer to ENET mac address array of Ethernet device. This MAC address should be provided.
macCount – Count of macAddr in the ENET mac address array
refclkSrc_Hz – ENET input reference clock.

status_t ENET_QOS_Init(ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz)

Initializes the ENET module.

This function ungates the module clock and initializes it with the ENET basic configuration.

Parameters:

base – ENET peripheral base address.
config – ENET mac configuration structure pointer. The “enet_qos_config_t” type mac configuration return from ENET_QOS_GetDefaultConfig can be used directly. It is also possible to verify the Mac configuration using other methods.
macAddr – Pointer to ENET mac address array of Ethernet device. This MAC address should be provided.
macCount – Count of macAddr in the ENET mac address array
refclkSrc_Hz – ENET input reference clock.

void ENET_QOS_Down(ENET_QOS_Type *base)

Stops the ENET module.

This function disables the ENET module.

Parameters:

base – ENET peripheral base address.

void ENET_QOS_Deinit(ENET_QOS_Type *base)

Deinitializes the ENET module.

This function gates the module clock and disables the ENET module.

Parameters:

base – ENET peripheral base address.

uint32_t ENET_QOS_GetInstance(ENET_QOS_Type *base)

Get the ENET instance from peripheral base address.

Parameters:

base – ENET peripheral base address.

Returns:

ENET instance.

status_t ENET_QOS_DescriptorInit(ENET_QOS_Type *base, enet_qos_config_t *config, enet_qos_buffer_config_t *bufferConfig)

Initialize for all ENET descriptors.

Note

This function is do all tx/rx descriptors initialization. Because this API read all interrupt registers first and then set the interrupt flag for all descriptors, if the interrupt register is set. so the descriptor initialization should be called after ENET_QOS_Init(), ENET_QOS_EnableInterrupts() and ENET_QOS_CreateHandle()(if transactional APIs are used).

Parameters:

base – ENET peripheral base address.
config – The configuration for ENET.
bufferConfig – All buffers configuration.

status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handle)

Allocates Rx buffers for all BDs. It’s used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function will populate initial buffers in all BDs for receiving. Then ENET_QOS_GetRxFrame() is used to get Rx frame with zero copy, it will allocate new buffer to replace the buffer in BD taken by application application should free those buffers after they’re used.

Note

This function should be called after ENET_QOS_CreateHandler() and buffer allocating callback function should be ready.

Parameters:

base – ENET_QOS peripheral base address.
handle – The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.

void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle)

Frees Rx buffers in all BDs. It’s used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function will free left buffers in all BDs.

Parameters:

base – ENET_QOS peripheral base address.
handle – The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.

void ENET_QOS_StartRxTx(ENET_QOS_Type *base, uint8_t txRingNum, uint8_t rxRingNum)

Starts the ENET rx/tx. This function enable the tx/rx and starts the rx/tx DMA. This shall be set after ENET initialization and before starting to receive the data.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required.

Parameters:

base – ENET peripheral base address.
rxRingNum – The number of the used rx rings. It shall not be larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with 1, the ring 0 will be used.
txRingNum – The number of the used tx rings. It shall not be larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with 1, the ring 0 will be used.

status_t ENET_QOS_SetMII(ENET_QOS_Type *base, enet_qos_mii_speed_t speed, enet_qos_mii_duplex_t duplex)

Sets the ENET MII speed and duplex.

This API is provided to dynamically change the speed and duplex for MAC.

Parameters:

base – ENET peripheral base address.
speed – The speed of the RMII mode.
duplex – The duplex of the RMII mode.

Returns:

kStatus_Success The ENET MII speed and duplex has been set successfully.

Returns:

kStatus_InvalidArgument Could not set the desired ENET MII speed and duplex combination.

void ENET_QOS_SetSMI(ENET_QOS_Type *base, uint32_t csrClock_Hz)

Sets the ENET SMI(serial management interface)- MII management interface.

Parameters:

base – ENET peripheral base address.
csrClock_Hz – CSR clock frequency in HZ

static inline bool ENET_QOS_IsSMIBusy(ENET_QOS_Type *base)

Checks if the SMI is busy.

Parameters:

base – ENET peripheral base address.

Returns:

The status of MII Busy status.

static inline uint16_t ENET_QOS_ReadSMIData(ENET_QOS_Type *base)

Reads data from the PHY register through SMI interface.

Parameters:

base – ENET peripheral base address.

Returns:

The data read from PHY

void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

Sends the MDIO IEEE802.3 Clause 22 format write command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address.
regAddr – The PHY register address.
data – The data written to PHY.

void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr)

Sends the MDIO IEEE802.3 Clause 22 format read command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address.
regAddr – The PHY register address.

void ENET_QOS_StartExtC45SMIWrite(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

Sends the MDIO IEEE802.3 Clause 45 format write command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
data – The data written to PHY.

void ENET_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr)

Sends the MDIO IEEE802.3 Clause 45 format read command. After send command, user needs to check whether the transmission is over with ENET_QOS_IsSMIBusy().

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.

status_t ENET_QOS_MDIOWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data)

MDIO write with IEEE802.3 MDIO Clause 22 format.

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address.
regAddr – The PHY register.
data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_QOS_MDIORead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 MDIO Clause 22 format.

Parameters:

base – ENET peripheral base address.
phyAddr – The PHY address.
regAddr – The PHY register.
pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_QOS_MDIOC45Write(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data)

MDIO write with IEEE802.3 Clause 45 format.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
data – The data written to PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

status_t ENET_QOS_MDIOC45Read(ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData)

MDIO read with IEEE802.3 Clause 45 format.

Parameters:

base – ENET peripheral base address.
portAddr – The MDIO port address(PHY address).
devAddr – The device address.
regAddr – The PHY register address.
pData – The data read from PHY.

Returns:

kStatus_Success MDIO access succeeds.

Returns:

kStatus_Timeout MDIO access timeout.

static inline void ENET_QOS_SetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)

Sets the ENET module Mac address.

Parameters:

base – ENET peripheral base address.
macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.
index – Configure macAddr to MAC_ADDRESS[index] register.

void ENET_QOS_GetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)

Gets the ENET module Mac address.

Parameters:

base – ENET peripheral base address.
macAddr – The six-byte Mac address pointer. The pointer is allocated by application and input into the API.
index – Get macAddr from MAC_ADDRESS[index] register.

void ENET_QOS_AddMulticastGroup(ENET_QOS_Type *base, uint8_t *address)

Adds the ENET_QOS device to a multicast group.

Parameters:

base – ENET_QOS peripheral base address.
address – The six-byte multicast group address which is provided by application.

void ENET_QOS_LeaveMulticastGroup(ENET_QOS_Type *base, uint8_t *address)

Moves the ENET_QOS device from a multicast group.

Parameters:

base – ENET_QOS peripheral base address.
address – The six-byte multicast group address which is provided by application.

static inline void ENET_QOS_AcceptAllMulticast(ENET_QOS_Type *base)

Enable ENET device to accept all multicast frames.

Parameters:

base – ENET peripheral base address.

static inline void ENET_QOS_RejectAllMulticast(ENET_QOS_Type *base)

ENET device reject to accept all multicast frames.

Parameters:

base – ENET peripheral base address.

void ENET_QOS_EnterPowerDown(ENET_QOS_Type *base, uint32_t *wakeFilter)

Set the MAC to enter into power down mode. the remote power wake up frame and magic frame can wake up the ENET from the power down mode.

Parameters:

base – ENET peripheral base address.
wakeFilter – The wakeFilter provided to configure the wake up frame filter. Set the wakeFilter to NULL is not required. But if you have the filter requirement, please make sure the wakeFilter pointer shall be eight continuous 32-bits configuration.

static inline void ENET_QOS_ExitPowerDown(ENET_QOS_Type *base)

Set the MAC to exit power down mode. Exit from the power down mode and recover to normal work mode.

Parameters:

base – ENET peripheral base address.

status_t ENET_QOS_EnableRxParser(ENET_QOS_Type *base, bool enable)

Enable/Disable Rx parser,please notice that for enable/disable Rx Parser, should better disable Receive first.

Parameters:

base – ENET_QOS peripheral base address.
enable – Enable/Disable Rx parser function

Return values:

kStatus_Success – Configure rx parser success.
kStatus_ENET_QOS_Timeout – Poll status flag timeout.

void ENET_QOS_EnableInterrupts(ENET_QOS_Type *base, uint32_t mask)

Enables the ENET DMA and MAC interrupts.

This function enables the ENET interrupt according to the provided mask. The mask is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t. For example, to enable the dma and mac interrupt, do the following.

ENET_QOS_EnableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);

Parameters:

base – ENET peripheral base address.
mask – ENET interrupts to enable. This is a logical OR of both enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.

void ENET_QOS_DisableInterrupts(ENET_QOS_Type *base, uint32_t mask)

Disables the ENET DMA and MAC interrupts.

This function disables the ENET interrupt according to the provided mask. The mask is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t. For example, to disable the dma and mac interrupt, do the following.

ENET_QOS_DisableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);

Parameters:

base – ENET peripheral base address.
mask – ENET interrupts to disables. This is a logical OR of both enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.

static inline uint32_t ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel)

Gets the ENET DMA interrupt status flag.

Parameters:

base – ENET peripheral base address.
channel – The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.

Returns:

The event status of the interrupt source. This is the logical OR of members of the enumeration :: enet_qos_dma_interrupt_enable_t.

static inline void ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel, uint32_t mask)

Clear the ENET DMA interrupt status flag.

Parameters:

base – ENET peripheral base address.
channel – The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
mask – The interrupt status to be cleared. This is the logical OR of members of the enumeration :: enet_qos_dma_interrupt_enable_t.

static inline uint32_t ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type *base)

Gets the ENET MAC interrupt status flag.

Parameters:

base – ENET peripheral base address.

Returns:

The event status of the interrupt source. Use the enum in enet_qos_mac_interrupt_enable_t and right shift ENET_QOS_MACINT_ENUM_OFFSET to mask the returned value to get the exact interrupt status.

void ENET_QOS_ClearMacInterruptStatus(ENET_QOS_Type *base, uint32_t mask)

Clears the ENET mac interrupt events status flag.

This function clears enabled ENET interrupts according to the provided mask. The mask is a logical OR of enumeration members. See the enet_qos_mac_interrupt_enable_t. For example, to clear the TX frame interrupt and RX frame interrupt, do the following.

ENET_QOS_ClearMacInterruptStatus(ENET, kENET_QOS_MacPmt);

Parameters:

base – ENET peripheral base address.
mask – ENET interrupt source to be cleared. This is the logical OR of members of the enumeration :: enet_qos_mac_interrupt_enable_t.

static inline bool ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t *txDesc)

Get the tx descriptor DMA Own flag.

Parameters:

txDesc – The given tx descriptor.

Return values:

True – the dma own tx descriptor, false application own tx descriptor.

void ENET_QOS_SetupTxDescriptor(enet_qos_tx_bd_struct_t *txDesc, void *buffer1, uint32_t bytes1, void *buffer2, uint32_t bytes2, uint32_t framelen, bool intEnable, bool tsEnable, enet_qos_desc_flag flag, uint8_t slotNum)

Setup a given tx descriptor. This function is a low level functional API to setup or prepare a given tx descriptor.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required. Transmit buffers are ‘zero-copy’ buffers, so the buffer must remain in memory until the packet has been fully transmitted. The buffers should be free or requeued in the transmit interrupt irq handler.

Parameters:

txDesc – The given tx descriptor.
buffer1 – The first buffer address in the descriptor.
bytes1 – The bytes in the fist buffer.
buffer2 – The second buffer address in the descriptor.
bytes2 – The bytes in the second buffer.
framelen – The length of the frame to be transmitted.
intEnable – Interrupt enable flag.
tsEnable – The timestamp enable.
flag – The flag of this tx descriptor, enet_qos_desc_flag .
slotNum – The slot num used for AV only.

static inline void ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)

Update the tx descriptor tail pointer. This function is a low level functional API to update the the tx descriptor tail. This is called after you setup a new tx descriptor to update the tail pointer to make the new descriptor accessible by DMA.

Parameters:

base – ENET peripheral base address.
channel – The tx DMA channel.
txDescTailAddrAlign – The new tx tail pointer address.

static inline void ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)

Update the rx descriptor tail pointer. This function is a low level functional API to update the the rx descriptor tail. This is called after you setup a new rx descriptor to update the tail pointer to make the new descriptor accessible by DMA and to anouse the rx poll command for DMA.

Parameters:

base – ENET peripheral base address.
channel – The rx DMA channel.
rxDescTailAddrAlign – The new rx tail pointer address.

static inline uint32_t ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc)

Gets the context in the ENET rx descriptor. This function is a low level functional API to get the the status flag from a given rx descriptor.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required.

Parameters:

rxDesc – The given rx descriptor.

Return values:

The – RDES3 regions for write-back format rx buffer descriptor.

void ENET_QOS_UpdateRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable)

Updates the buffers and the own status for a given rx descriptor. This function is a low level functional API to Updates the buffers and the own status for a given rx descriptor.

Note

This must be called after all the ENET initialization. And should be called when the ENET receive/transmit is required.

Parameters:

rxDesc – The given rx descriptor.
buffer1 – The first buffer address in the descriptor.
buffer2 – The second buffer address in the descriptor.
intEnable – Interrupt enable flag.
doubleBuffEnable – The double buffer enable flag.

status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryCount)

Configure flexible rx parser.

This function is used to configure the flexible rx parser table.

Parameters:

base – ENET peripheral base address..
rxpConfig – The rx parser configuration pointer.
entryCount – The rx parser entry count.

Return values:

kStatus_Success – Configure rx parser success.
kStatus_ENET_QOS_Timeout – Poll status flag timeout.

status_t ENET_QOS_ReadRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryIndex)

Read flexible rx parser configuration at specified index.

This function is used to read flexible rx parser configuration at specified index.

Parameters:

base – ENET peripheral base address..
rxpConfig – The rx parser configuration pointer.
entryIndex – The rx parser entry index to read, start from 0.

Return values:

kStatus_Success – Configure rx parser success.
kStatus_ENET_QOS_Timeout – Poll status flag timeout.

status_t ENET_QOS_EstProgramGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t ptpClk_Hz)

Program Gate Control List.

This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)

Parameters:

base – ENET peripheral base address..
gcl – Pointer to the Gate Control List structure.
ptpClk_Hz – frequency of the PTP clock.

status_t ENET_QOS_EstReadGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t listLen, bool hwList)

Read Gate Control List.

This function is used to read the Enhanced Scheduled Transmisson list. (IEEE802.1Qbv)

Parameters:

base – ENET peripheral base address..
gcl – Pointer to the Gate Control List structure.
listLen – length of the provided opList array in gcl structure.
hwList – Boolean if True read HW list, false read SW list.

static inline void ENET_QOS_FpeEnable(ENET_QOS_Type *base)

Enable Frame Preemption.

This function is used to enable frame preemption. (IEEE802.1Qbu)

Parameters:

base – ENET peripheral base address..

static inline void ENET_QOS_FpeDisable(ENET_QOS_Type *base)

Disable Frame Preemption.

This function is used to disable frame preemption. (IEEE802.1Qbu)

Parameters:

base – ENET peripheral base address..

static inline void ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type *base, uint8_t queueMask)

Configure preemptable transmit queues.

This function is used to configure the preemptable queues. (IEEE802.1Qbu)

Parameters:

base – ENET peripheral base address..
queueMask – bitmask representing queues to set in preemptable mode. The N-th bit represents the queue N.

void ENET_QOS_AVBConfigure(ENET_QOS_Type *base, const enet_qos_cbs_config_t *config, uint8_t queueIndex)

Sets the ENET AVB feature.

ENET_QOS AVB feature configuration, set transmit bandwidth. This API is called when the AVB feature is required.

Parameters:

base – ENET_QOS peripheral base address.
config – The ENET_QOS AVB feature configuration structure.
queueIndex – ENET_QOS queue index.

void ENET_QOS_GetStatistics(ENET_QOS_Type *base, enet_qos_transfer_stats_t *statistics)

Gets statistical data in transfer.

Parameters:

base – ENET_QOS peripheral base address.
statistics – The statistics structure pointer.

void ENET_QOS_CreateHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_config_t *config, enet_qos_buffer_config_t *bufferConfig, enet_qos_callback_t callback, void *userData)

Create ENET Handler.

This is a transactional API and it’s provided to store all data which are needed during the whole transactional process. This API should not be used when you use functional APIs to do data tx/rx. This is function will store many data/flag for transactional use, so all configure API such as ENET_QOS_Init(), ENET_QOS_DescriptorInit(), ENET_QOS_EnableInterrupts() etc.

Note

as our transactional transmit API use the zero-copy transmit buffer. so there are two thing we emphasize here:

tx buffer free/requeue for application should be done in the tx interrupt handler. Please set callback: kENET_QOS_TxIntEvent with tx buffer free/requeue process APIs.
the tx interrupt is forced to open.

Parameters:

base – ENET peripheral base address.
handle – ENET handler.
config – ENET configuration.
bufferConfig – ENET buffer configuration.
callback – The callback function.
userData – The application data.

status_t ENET_QOS_GetRxFrameSize(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint32_t *length, uint8_t channel)

Gets the size of the read frame. This function gets a received frame size from the ENET buffer descriptors.

Note

The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. After calling ENET_QOS_GetRxFrameSize, ENET_QOS_ReadFrame() should be called to update the receive buffers If the result is not “kStatus_ENET_QOS_RxFrameEmpty”.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
length – The length of the valid frame received.
channel – The DMAC channel for the rx.

Return values:

kStatus_ENET_QOS_RxFrameEmpty – No frame received. Should not call ENET_QOS_ReadFrame to read frame.
kStatus_ENET_QOS_RxFrameError – Data error happens. ENET_QOS_ReadFrame should be called with NULL data and NULL length to update the receive buffers.
kStatus_Success – Receive a frame Successfully then the ENET_QOS_ReadFrame should be called with the right data buffer and the captured data length input.

status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel, enet_qos_ptp_time_t *ts)

Reads a frame from the ENET device. This function reads a frame from the ENET DMA descriptors. The ENET_QOS_GetRxFrameSize should be used to get the size of the prepared data buffer. For example use rx dma channel 0:

uint32_t length;
enet_qos_handle_t g_handle;
status = ENET_QOS_GetRxFrameSize(&g_handle, &length, 0);
if (length != 0)
{
    uint8_t *data = memory allocate interface;
    if (!data)
    {
        ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
    }
    else
    {
       status = ENET_QOS_ReadFrame(ENET, &g_handle, data, length, 0);
    }
}
else if (status == kStatus_ENET_QOS_RxFrameError)
{
    ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
}

Parameters:

base – ENET peripheral base address.
handle – The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
data – The data buffer provided by user to store the frame which memory size should be at least “length”.
length – The size of the data buffer which is still the length of the received frame.
channel – The rx DMA channel. shall not be larger than 2.
ts – Pointer to the structure enet_qos_ptp_time_t to save frame timestamp.

Returns:

The execute status, successful or failure.

status_t ENET_QOS_SendFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel, bool isNeedTs, void *context, enet_qos_tx_offload_t txOffloadOps)

Transmits an ENET frame.

Note

The CRC is automatically appended to the data. Input the data to send without the CRC.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
data – The data buffer provided by user to be send.
length – The length of the data to be send.
channel – Channel to send the frame, same with queue index.
isNeedTs – True to enable timestamp save for the frame
context – pointer to user context to be kept in the tx dirty frame information.
txOffloadOps – The Tx frame checksum offload option.

Return values:

kStatus_Success – Send frame succeed.
kStatus_ENET_QOS_TxFrameBusy – Transmit buffer descriptor is busy under transmission. The transmit busy happens when the data send rate is over the MAC capacity. The waiting mechanism is recommended to be added after each call return with kStatus_ENET_QOS_TxFrameBusy.

void ENET_QOS_ReclaimTxDescriptor(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t channel)

Reclaim tx descriptors. This function is used to update the tx descriptor status and store the tx timestamp when the 1588 feature is enabled. This is called by the transmit interrupt IRQ handler after the complete of a frame transmission.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
channel – The tx DMA channel.

void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle)

The ENET IRQ handler.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer.

void ENET_QOS_SetISRHandler(ENET_QOS_Type *base, enet_qos_isr_t ISRHandler)

Set the second level IRQ handler, allow user to overwrite the default second level weak IRQ handler.

Parameters:

base – ENET peripheral base address.
ISRHandler – The handler to install.

status_t ENET_QOS_Ptp1588CorrectTimerInCoarse(ENET_QOS_Type *base, enet_qos_systime_op operation, uint32_t second, uint32_t nanosecond)

Correct the ENET PTP 1588 timer in coarse method.

Parameters:

base – ENET peripheral base address.
operation – The system time operation, refer to “enet_qos_systime_op”
second – The correction second.
nanosecond – The correction nanosecond.

status_t ENET_QOS_Ptp1588CorrectTimerInFine(ENET_QOS_Type *base, uint32_t addend)

Correct the ENET PTP 1588 timer in fine method.

Note

Should take refer to the chapter “System time correction” and see the description for the “fine correction method”.

Parameters:

base – ENET peripheral base address.
addend – The addend value to be set in the fine method

static inline uint32_t ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type *base)

Get the ENET Time stamp current addend value.

Parameters:

base – ENET peripheral base address.

Returns:

The addend value.

void ENET_QOS_Ptp1588GetTimerNoIRQDisable(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond)

Gets the current ENET time from the PTP 1588 timer without IRQ disable.

Parameters:

base – ENET peripheral base address.
second – The PTP 1588 system timer second.
nanosecond – The PTP 1588 system timer nanosecond. For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.

static inline status_t ENET_Ptp1588PpsControl(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, enet_qos_ptp_pps_trgt_mode_t trgtMode, enet_qos_ptp_pps_cmd_t cmd)

Sets the ENET PTP 1588 PPS control. All channels operate in flexible PPS output mode.

Parameters:

base – ENET peripheral base address.
instance – The ENET QOS PTP PPS instance.
trgtMode – The target time register mode.
cmd – The target flexible PPS output control command.

status_t ENET_QOS_Ptp1588PpsSetTrgtTime(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, uint32_t seconds, uint32_t nanoseconds)

Sets the ENET OQS PTP 1588 PPS target time registers.

Parameters:

base – ENET QOS peripheral base address.
instance – The ENET QOS PTP PPS instance.
seconds – The target seconds.
nanoseconds – The target nanoseconds.

static inline void ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, uint32_t width)

Sets the ENET OQS PTP 1588 PPS output signal interval.

Parameters:

base – ENET QOS peripheral base address.
instance – The ENET QOS PTP PPS instance.
width – Signal Width. It is stored in terms of number of units of sub-second increment value. The width value must be lesser than interval value.

static inline void ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type *base, enet_qos_ptp_pps_instance_t instance, uint32_t interval)

Sets the ENET OQS PTP 1588 PPS output signal width.

Parameters:

base – ENET QOS peripheral base address.
instance – The ENET QOS PTP PPS instance.
interval – Signal Interval. It is stored in terms of number of units of sub-second increment value.

void ENET_QOS_Ptp1588GetTimer(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond)

Gets the current ENET time from the PTP 1588 timer.

Parameters:

base – ENET peripheral base address.
second – The PTP 1588 system timer second.
nanosecond – The PTP 1588 system timer nanosecond. For the unit of the nanosecond is 1ns.so the nanosecond is the real nanosecond.

void ENET_QOS_GetTxFrame(enet_qos_handle_t *handle, enet_qos_frame_info_t *txFrame, uint8_t channel)

Gets the time stamp of the transmit frame.

This function is used for PTP stack to get the timestamp captured by the ENET driver.

Parameters:

handle – The ENET handler pointer.This is the same state pointer used in ENET_QOS_Init.
txFrame – Input parameter, pointer to enet_qos_frame_info_t for saving read out frame information.
channel – Channel for searching the tx frame.

status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_rx_frame_struct_t *rxFrame, uint8_t channel)

Receives one frame in specified BD ring with zero copy.

This function will use the user-defined allocate and free callback. Every time application gets one frame through this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.

Note

This function will drop current frame and update related BDs as available for DMA if new buffers allocating fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer) to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there’s always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according to specific design in this case.

Parameters:

base – ENET peripheral base address.
handle – The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
rxFrame – The received frame information structure provided by user.
channel – Channel for searching the rx frame.

Return values:

kStatus_Success – Succeed to get one frame and allocate new memory for Rx buffer.
kStatus_ENET_QOS_RxFrameEmpty – There’s no Rx frame in the BD.
kStatus_ENET_QOS_RxFrameError – There’s issue in this receiving.
kStatus_ENET_QOS_RxFrameDrop – There’s no new buffer memory for BD, drop this frame.

FSL_ENET_QOS_DRIVER_VERSION: Defines the driver version.

ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK

Defines for read format.

Buffer1 address valid.

ENET_QOS_RXDESCRIP_RD_BUFF2VALID_MASK: Buffer2 address valid.

ENET_QOS_RXDESCRIP_RD_IOC_MASK: Interrupt enable on complete.

ENET_QOS_RXDESCRIP_RD_OWN_MASK: Own bit.

ENET_QOS_RXDESCRIP_WR_ERR_MASK: Defines for write back format.

ENET_QOS_RXDESCRIP_WR_PYLOAD_MASK

ENET_QOS_RXDESCRIP_WR_PTPMSGTYPE_MASK

ENET_QOS_RXDESCRIP_WR_PTPTYPE_MASK

ENET_QOS_RXDESCRIP_WR_PTPVERSION_MASK

ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK

ENET_QOS_RXDESCRIP_WR_PACKETLEN_MASK

ENET_QOS_RXDESCRIP_WR_ERRSUM_MASK

ENET_QOS_RXDESCRIP_WR_TYPE_MASK

ENET_QOS_RXDESCRIP_WR_DE_MASK

ENET_QOS_RXDESCRIP_WR_RE_MASK

ENET_QOS_RXDESCRIP_WR_OE_MASK

ENET_QOS_RXDESCRIP_WR_RWT_MASK

ENET_QOS_RXDESCRIP_WR_GP_MASK

ENET_QOS_RXDESCRIP_WR_CRC_MASK

ENET_QOS_RXDESCRIP_WR_RS0V_MASK

ENET_QOS_RXDESCRIP_WR_RS1V_MASK

ENET_QOS_RXDESCRIP_WR_RS2V_MASK

ENET_QOS_RXDESCRIP_WR_LD_MASK

ENET_QOS_RXDESCRIP_WR_FD_MASK

ENET_QOS_RXDESCRIP_WR_CTXT_MASK

ENET_QOS_RXDESCRIP_WR_OWN_MASK

ENET_QOS_RXDESCRIP_WR_SA_FAILURE_MASK

ENET_QOS_RXDESCRIP_WR_DA_FAILURE_MASK

ENET_QOS_TXDESCRIP_RD_BL1_MASK: Defines for read format.

ENET_QOS_TXDESCRIP_RD_BL2_MASK

ENET_QOS_TXDESCRIP_RD_BL1(n)

ENET_QOS_TXDESCRIP_RD_BL2(n)

ENET_QOS_TXDESCRIP_RD_TTSE_MASK

ENET_QOS_TXDESCRIP_RD_IOC_MASK

ENET_QOS_TXDESCRIP_RD_FL_MASK

ENET_QOS_TXDESCRIP_RD_FL(n)

ENET_QOS_TXDESCRIP_RD_CIC(n)

ENET_QOS_TXDESCRIP_RD_TSE_MASK

ENET_QOS_TXDESCRIP_RD_SLOT(n)

ENET_QOS_TXDESCRIP_RD_SAIC(n)

ENET_QOS_TXDESCRIP_RD_CPC(n)

ENET_QOS_TXDESCRIP_RD_LDFD(n)

ENET_QOS_TXDESCRIP_RD_LD_MASK

ENET_QOS_TXDESCRIP_RD_FD_MASK

ENET_QOS_TXDESCRIP_RD_CTXT_MASK

ENET_QOS_TXDESCRIP_RD_OWN_MASK

ENET_QOS_TXDESCRIP_WB_TTSS_MASK: Defines for write back format.

ENET_QOS_ABNORM_INT_MASK

ENET_QOS_NORM_INT_MASK

ENET_QOS_RING_NUM_MAX: The Maximum number of tx/rx descriptor rings.

ENET_QOS_FRAME_MAX_FRAMELEN: Default maximum Ethernet frame size.

ENET_QOS_FCS_LEN: Ethernet FCS length.

ENET_QOS_ADDR_ALIGNMENT: Recommended Ethernet buffer alignment.

ENET_QOS_BUFF_ALIGNMENT: Receive buffer alignment shall be 4bytes-aligned.

ENET_QOS_MTL_RXFIFOSIZE: The rx fifo size.

ENET_QOS_MTL_TXFIFOSIZE: The tx fifo size.

ENET_QOS_MACINT_ENUM_OFFSET: The offest for mac interrupt in enum type.

ENET_QOS_RXP_ENTRY_COUNT: RXP table entry count, implied by FRPES in MAC_HW_FEATURE3

ENET_QOS_RXP_BUFFER_SIZE: RXP Buffer size, implied by FRPBS in MAC_HW_FEATURE3

ENET_QOS_EST_WID: Width of the time interval in Gate Control List

ENET_QOS_EST_DEP: Maxmimum depth of Gate Control List

Defines the status return codes for transaction.

Values:

enumerator kStatus_ENET_QOS_InitMemoryFail: Init fails since buffer memory is not enough.

enumerator kStatus_ENET_QOS_RxFrameError: A frame received but data error happen.

enumerator kStatus_ENET_QOS_RxFrameFail: Failed to receive a frame.

enumerator kStatus_ENET_QOS_RxFrameEmpty: No frame arrive.

enumerator kStatus_ENET_QOS_RxFrameDrop: Rx frame is dropped since no buffer memory.

enumerator kStatus_ENET_QOS_TxFrameBusy: Transmit descriptors are under process.

enumerator kStatus_ENET_QOS_TxFrameFail: Transmit frame fail.

enumerator kStatus_ENET_QOS_TxFrameOverLen: Transmit oversize.

enumerator kStatus_ENET_QOS_Est_SwListBusy: SW Gcl List not yet processed by HW.

enumerator kStatus_ENET_QOS_Est_SwListWriteAbort: SW Gcl List write aborted .

enumerator kStatus_ENET_QOS_Est_InvalidParameter: Invalid parameter in Gcl List .

enumerator kStatus_ENET_QOS_Est_BtrError: Base Time Error when loading list.

enumerator kStatus_ENET_QOS_TrgtBusy: Target time register busy.

enumerator kStatus_ENET_QOS_Timeout: Target time register busy.

enumerator kStatus_ENET_QOS_PpsBusy: Pps command busy.

enum _enet_qos_mii_mode

Defines the MII/RGMII mode for data interface between the MAC and the PHY.

Values:

enumerator kENET_QOS_MiiMode: MII mode for data interface.

enumerator kENET_QOS_RgmiiMode: RGMII mode for data interface.

enumerator kENET_QOS_RmiiMode: RMII mode for data interface.

enum _enet_qos_mii_speed

Defines the 10/100/1000 Mbps speed for the MII data interface.

Values:

enumerator kENET_QOS_MiiSpeed10M: Speed 10 Mbps.

enumerator kENET_QOS_MiiSpeed100M: Speed 100 Mbps.

enumerator kENET_QOS_MiiSpeed1000M: Speed 1000 Mbps.

enumerator kENET_QOS_MiiSpeed2500M: Speed 2500 Mbps.

enum _enet_qos_mii_duplex

Defines the half or full duplex for the MII data interface.

Values:

enumerator kENET_QOS_MiiHalfDuplex: Half duplex mode.

enumerator kENET_QOS_MiiFullDuplex: Full duplex mode.

enum _enet_qos_mii_normal_opcode

Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

Values:

enumerator kENET_QOS_MiiWriteFrame: Write frame operation for a valid MII management frame.

enumerator kENET_QOS_MiiReadFrame: Read frame operation for a valid MII management frame.

enum _enet_qos_dma_burstlen

Define the DMA maximum transmit burst length.

Values:

enumerator kENET_QOS_BurstLen1: DMA burst length 1.

enumerator kENET_QOS_BurstLen2: DMA burst length 2.

enumerator kENET_QOS_BurstLen4: DMA burst length 4.

enumerator kENET_QOS_BurstLen8: DMA burst length 8.

enumerator kENET_QOS_BurstLen16: DMA burst length 16.

enumerator kENET_QOS_BurstLen32: DMA burst length 32.

enumerator kENET_QOS_BurstLen64: DMA burst length 64. eight times enabled.

enumerator kENET_QOS_BurstLen128: DMA burst length 128. eight times enabled.

enumerator kENET_QOS_BurstLen256: DMA burst length 256. eight times enabled.

enum _enet_qos_desc_flag

Define the flag for the descriptor.

Values:

enumerator kENET_QOS_MiddleFlag: It’s a middle descriptor of the frame.

enumerator kENET_QOS_LastFlagOnly: It’s the last descriptor of the frame.

enumerator kENET_QOS_FirstFlagOnly: It’s the first descriptor of the frame.

enumerator kENET_QOS_FirstLastFlag: It’s the first and last descriptor of the frame.

enum _enet_qos_systime_op

Define the system time adjust operation control.

Values:

enumerator kENET_QOS_SystimeAdd: System time add to.

enumerator kENET_QOS_SystimeSubtract: System time subtract.

enum _enet_qos_ts_rollover_type

Define the system time rollover control.

Values:

enumerator kENET_QOS_BinaryRollover: System time binary rollover.

enumerator kENET_QOS_DigitalRollover: System time digital rollover.

enum _enet_qos_special_config

Defines some special configuration for ENET.

These control flags are provided for special user requirements. Normally, these is no need to set this control flags for ENET initialization. But if you have some special requirements, set the flags to specialControl in the enet_qos_config_t.

Note

“kENET_QOS_StoreAndForward” is recommended to be set.

Values:

enumerator kENET_QOS_DescDoubleBuffer: The double buffer is used in the tx/rx descriptor.

enumerator kENET_QOS_StoreAndForward: The rx/tx store and forward enable.

enumerator kENET_QOS_PromiscuousEnable: The promiscuous enabled.

enumerator kENET_QOS_FlowControlEnable: The flow control enabled.

enumerator kENET_QOS_BroadCastRxDisable: The broadcast disabled.

enumerator kENET_QOS_MulticastAllEnable: All multicast are passed.

enumerator kENET_QOS_8023AS2KPacket: 8023as support for 2K packets.

enumerator kENET_QOS_HashMulticastEnable: The multicast packets are filtered through hash table.

enumerator kENET_QOS_RxChecksumOffloadEnable: The Rx checksum offload enabled.

enum _enet_qos_dma_interrupt_enable

List of DMA interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

Values:

enumerator kENET_QOS_DmaTx: Tx interrupt.

enumerator kENET_QOS_DmaTxStop: Tx stop interrupt.

enumerator kENET_QOS_DmaTxBuffUnavail: Tx buffer unavailable.

enumerator kENET_QOS_DmaRx: Rx interrupt.

enumerator kENET_QOS_DmaRxBuffUnavail: Rx buffer unavailable.

enumerator kENET_QOS_DmaRxStop: Rx stop.

enumerator kENET_QOS_DmaRxWatchdogTimeout: Rx watchdog timeout.

enumerator kENET_QOS_DmaEarlyTx: Early transmit.

enumerator kENET_QOS_DmaEarlyRx: Early receive.

enumerator kENET_QOS_DmaBusErr: Fatal bus error.

enum _enet_qos_mac_interrupt_enable

List of mac interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

Values:

enumerator kENET_QOS_MacTimestamp

enum _enet_qos_event

Defines the common interrupt event for callback use.

Values:

enumerator kENET_QOS_RxIntEvent: Receive interrupt event.

enumerator kENET_QOS_TxIntEvent: Transmit interrupt event.

enumerator kENET_QOS_WakeUpIntEvent: Wake up interrupt event.

enumerator kENET_QOS_TimeStampIntEvent: Time stamp interrupt event.

enum _enet_qos_queue_mode

Define the MTL mode for multiple queues/rings.

Values:

enumerator kENET_QOS_AVB_Mode: Enable queue in AVB mode.

enumerator kENET_QOS_DCB_Mode: Enable queue in DCB mode.

enum _enet_qos_mtl_multiqueue_txsche

Define the MTL tx scheduling algorithm for multiple queues/rings.

Values:

enumerator kENET_QOS_txWeightRR: Tx weight round-robin.

enumerator kENET_QOS_txWeightFQ: Tx weight fair queuing.

enumerator kENET_QOS_txDefictWeightRR: Tx deficit weighted round-robin.

enumerator kENET_QOS_txStrPrio: Tx strict priority.

enum _enet_qos_mtl_multiqueue_rxsche

Define the MTL rx scheduling algorithm for multiple queues/rings.

Values:

enumerator kENET_QOS_rxStrPrio: Rx strict priority, Queue 0 has the lowest priority.

enumerator kENET_QOS_rxWeightStrPrio: Weighted Strict Priority.

enum _enet_qos_mtl_rxqueuemap

Define the MTL rx queue and DMA channel mapping.

Values:

enumerator kENET_QOS_StaticDirctMap: The received fame in rx Qn(n = 0,1) directly map to dma channel n.

enumerator kENET_QOS_DynamicMap: The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.

enum _enet_qos_rx_queue_route

Defines the package type for receive queue routing.

Values:

enumerator kENET_QOS_PacketNoQ

enumerator kENET_QOS_PacketAVCPQ

enumerator kENET_QOS_PacketPTPQ

enumerator kENET_QOS_PacketUPQ

enumerator kENET_QOS_PacketMCBCQ

enum _enet_qos_ptp_event_type

Defines the ENET PTP message related constant.

Values:

enumerator kENET_QOS_PtpEventMsgType: PTP event message type.

enumerator kENET_QOS_PtpSrcPortIdLen: PTP message sequence id length.

enumerator kENET_QOS_PtpEventPort: PTP event port number.

enumerator kENET_QOS_PtpGnrlPort: PTP general port number.

enum _enet_qos_ptp_pps_instance

Defines the PPS instance numbers.

Values:

enumerator kENET_QOS_PtpPpsIstance0: PPS instance 0.

enumerator kENET_QOS_PtpPpsIstance1: PPS instance 1.

enumerator kENET_QOS_PtpPpsIstance2: PPS instance 2.

enumerator kENET_QOS_PtpPpsIstance3: PPS instance 3.

enum _enet_qos_ptp_pps_trgt_mode

Defines the Target Time register mode.

Values:

enumerator kENET_QOS_PtpPpsTrgtModeOnlyInt: Only interrupts.

enumerator kENET_QOS_PtpPpsTrgtModeIntSt: Both interrupt and output signal.

enumerator kENET_QOS_PtpPpsTrgtModeOnlySt: Only output signal.

enum _enet_qos_ptp_pps_cmd

Defines commands for ppscmd register.

Values:

enumerator kENET_QOS_PtpPpsCmdNC: No Command.

enumerator kENET_QOS_PtpPpsCmdSSP: Start Single Pulse.

enumerator kENET_QOS_PtpPpsCmdSPT: Start Pulse Train.

enumerator kENET_QOS_PtpPpsCmdCS: Cancel Start.

enumerator kENET_QOS_PtpPpsCmdSPTAT: Stop Pulse Train At Time.

enumerator kENET_QOS_PtpPpsCmdSPTI: Stop Pulse Train Immediately.

enumerator kENET_QOS_PtpPpsCmdCSPT: Cancel Stop Pulse Train.

enum _enet_qos_ets_list_length

Defines the enmueration of ETS list length.

Values:

enumerator kENET_QOS_Ets_List_64: List length of 64

enumerator kENET_QOS_Ets_List_128: List length of 128

enumerator kENET_QOS_Ets_List_256: List length of 256

enumerator kENET_QOS_Ets_List_512: List length of 512

enumerator kENET_QOS_Ets_List_1024: List length of 1024

enum _enet_qos_ets_gccr_addr

Defines the enmueration of ETS gate control address.

Values:

enumerator kENET_QOS_Ets_btr_low: BTR Low

enumerator kENET_QOS_Ets_btr_high: BTR High

enumerator kENET_QOS_Ets_ctr_low: CTR Low

enumerator kENET_QOS_Ets_ctr_high: CTR High

enumerator kENET_QOS_Ets_ter: TER

enumerator kENET_QOS_Ets_llr: LLR

enum _enet_qos_rxp_dma_chn

Defines the enmueration of DMA channel used for rx parser entry.

Values:

enumerator kENET_QOS_Rxp_DMAChn0: DMA Channel 0 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn1: DMA Channel 1 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn2: DMA Channel 2 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn3: DMA Channel 3 used for RXP entry match

enumerator kENET_QOS_Rxp_DMAChn4: DMA Channel 4 used for RXP entry match

enum _enet_qos_tx_offload

Define the Tx checksum offload options.

Values:

enumerator kENET_QOS_TxOffloadDisable: Disable Tx checksum offload.

enumerator kENET_QOS_TxOffloadIPHeader: Enable IP header checksum calculation and insertion.

enumerator kENET_QOS_TxOffloadIPHeaderPlusPayload: Enable IP header and payload checksum calculation and insertion.

enumerator kENET_QOS_TxOffloadAll: Enable IP header, payload and pseudo header checksum calculation and insertion.

typedef enum _enet_qos_mii_mode enet_qos_mii_mode_t: Defines the MII/RGMII mode for data interface between the MAC and the PHY.

typedef enum _enet_qos_mii_speed enet_qos_mii_speed_t: Defines the 10/100/1000 Mbps speed for the MII data interface.

typedef enum _enet_qos_mii_duplex enet_qos_mii_duplex_t: Defines the half or full duplex for the MII data interface.

typedef enum _enet_qos_mii_normal_opcode enet_qos_mii_normal_opcode: Define the MII opcode for normal MDIO_CLAUSES_22 Frame.

typedef enum _enet_qos_dma_burstlen enet_qos_dma_burstlen: Define the DMA maximum transmit burst length.

typedef enum _enet_qos_desc_flag enet_qos_desc_flag: Define the flag for the descriptor.

typedef enum _enet_qos_systime_op enet_qos_systime_op: Define the system time adjust operation control.

typedef enum _enet_qos_ts_rollover_type enet_qos_ts_rollover_type: Define the system time rollover control.

typedef enum _enet_qos_special_config enet_qos_special_config_t

Defines some special configuration for ENET.

Note

“kENET_QOS_StoreAndForward” is recommended to be set.

typedef enum _enet_qos_dma_interrupt_enable enet_qos_dma_interrupt_enable_t: List of DMA interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

typedef enum _enet_qos_mac_interrupt_enable enet_qos_mac_interrupt_enable_t: List of mac interrupts supported by the ENET interrupt. This enumeration uses one-bot encoding to allow a logical OR of multiple members.

typedef enum _enet_qos_event enet_qos_event_t: Defines the common interrupt event for callback use.

typedef enum _enet_qos_queue_mode enet_qos_queue_mode_t: Define the MTL mode for multiple queues/rings.

typedef enum _enet_qos_mtl_multiqueue_txsche enet_qos_mtl_multiqueue_txsche: Define the MTL tx scheduling algorithm for multiple queues/rings.

typedef enum _enet_qos_mtl_multiqueue_rxsche enet_qos_mtl_multiqueue_rxsche: Define the MTL rx scheduling algorithm for multiple queues/rings.

typedef enum _enet_qos_mtl_rxqueuemap enet_qos_mtl_rxqueuemap_t: Define the MTL rx queue and DMA channel mapping.

typedef enum _enet_qos_rx_queue_route enet_qos_rx_queue_route_t: Defines the package type for receive queue routing.

typedef enum _enet_qos_ptp_event_type enet_qos_ptp_event_type_t: Defines the ENET PTP message related constant.

typedef enum _enet_qos_ptp_pps_instance enet_qos_ptp_pps_instance_t: Defines the PPS instance numbers.

typedef enum _enet_qos_ptp_pps_trgt_mode enet_qos_ptp_pps_trgt_mode_t: Defines the Target Time register mode.

typedef enum _enet_qos_ptp_pps_cmd enet_qos_ptp_pps_cmd_t: Defines commands for ppscmd register.

typedef enum _enet_qos_ets_list_length enet_qos_ets_list_length_t: Defines the enmueration of ETS list length.

typedef enum _enet_qos_ets_gccr_addr enet_qos_ets_gccr_addr_t: Defines the enmueration of ETS gate control address.

typedef enum _enet_qos_rxp_dma_chn enet_qos_rxp_dma_chn_t: Defines the enmueration of DMA channel used for rx parser entry.

typedef enum _enet_qos_tx_offload enet_qos_tx_offload_t: Define the Tx checksum offload options.

typedef struct _enet_qos_rx_bd_struct enet_qos_rx_bd_struct_t: Defines the receive descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the receive descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the receive data process.

typedef struct _enet_qos_tx_bd_struct enet_qos_tx_bd_struct_t: Defines the transmit descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the transmit descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the transmit data process.

typedef struct _enet_qos_tx_bd_config_struct enet_qos_tx_bd_config_struct_t: Defines the Tx BD configuration structure.

typedef struct _enet_qos_ptp_time enet_qos_ptp_time_t: Defines the ENET PTP time stamp structure.

typedef struct enet_qos_frame_info enet_qos_frame_info_t: Defines the frame info structure.

typedef struct _enet_qos_tx_dirty_ring enet_qos_tx_dirty_ring_t: Defines the ENET transmit dirty addresses ring/queue structure.

typedef struct _enet_qos_ptp_config enet_qos_ptp_config_t: Defines the ENET PTP configuration structure.

typedef struct _enet_qos_est_gate_op enet_qos_est_gate_op_t: Defines the EST gate operation structure.

typedef struct _enet_qos_est_gcl enet_qos_est_gcl_t: Defines the EST gate control list structure.

typedef struct _enet_qos_rxp_config enet_qos_rxp_config_t: Defines the ENET_QOS Rx parser configuration structure.

typedef struct _enet_qos_buffer_config enet_qos_buffer_config_t

Defines the buffer descriptor configure structure.

Note

The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
The recommended minimum tx/rx ring length is 4.
The tx/rx descriptor tail address shall be the address pointer to the address just after the end of the last last descriptor. because only the descriptors between the start address and the tail address will be used by DMA.
The descriptor address is the start address of all used contiguous memory. for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories for rx descriptor ring 0.
The “*rxBufferstartAddr” is the first element of rxRingLen (2*rxRingLen for double buffers) rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the address of a rxRingLen or 2*rxRingLen array.

typedef struct _enet_qos_cbs_config enet_qos_cbs_config_t: Defines the CBS configuration for queue.

typedef struct enet_qos_tx_queue_config enet_qos_queue_tx_config_t: Defines the queue configuration structure.

typedef struct enet_qos_rx_queue_config enet_qos_queue_rx_config_t: Defines the queue configuration structure.

typedef struct enet_qos_multiqueue_config enet_qos_multiqueue_config_t: Defines the configuration when multi-queue is used.

typedef void *(*enet_qos_rx_alloc_callback_t)(ENET_QOS_Type *base, void *userData, uint8_t channel): Defines the Rx memory buffer alloc function pointer.

typedef void (*enet_qos_rx_free_callback_t)(ENET_QOS_Type *base, void *buffer, void *userData, uint8_t channel): Defines the Rx memory buffer free function pointer.

typedef struct _enet_qos_config enet_qos_config_t: Defines the basic configuration structure for the ENET device.

Note

Default the signal queue is used so the “*multiqueueCfg” is set default with NULL. Set the pointer with a valid configuration pointer if the multiple queues are required. If multiple queue is enabled, please make sure the buffer configuration for all are prepared also.

typedef struct _enet_qos_handle enet_qos_handle_t

typedef void (*enet_qos_callback_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_event_t event, uint8_t channel, void *userData): ENET callback function.

typedef struct _enet_qos_tx_bd_ring enet_qos_tx_bd_ring_t: Defines the ENET transmit buffer descriptor ring/queue structure.

typedef struct _enet_qos_rx_bd_ring enet_qos_rx_bd_ring_t: Defines the ENET receive buffer descriptor ring/queue structure.

typedef struct _enet_qos_state enet_qos_state_t: Defines the ENET state structure.

Note

The structure contains saved state for the instance. It could be stored in enet_qos_handle_t, but that’s used only with the transactional API.

typedef struct _enet_qos_buffer_struct enet_qos_buffer_struct_t: Defines the frame buffer structure.

typedef struct _enet_qos_rx_frame_error enet_qos_rx_frame_error_t: Defines the Rx frame error structure.

typedef struct _enet_qos_rx_frame_attribute_struct enet_qos_rx_frame_attribute_t

typedef struct _enet_qos_rx_frame_struct enet_qos_rx_frame_struct_t: Defines the Rx frame data structure.

typedef struct _enet_qos_transfer_stats enet_qos_transfer_stats_t: Defines the ENET QOS transfer statistics structure.

typedef void (*enet_qos_isr_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle)

const clock_ip_name_t s_enetqosClock[]: Pointers to enet clocks for each instance.

void ENET_QOS_SetSYSControl(enet_qos_mii_mode_t miiMode)

Set ENET system configuration.

Note

User needs to provide the implementation because the implementation is SoC specific. This function set the phy selection and enable clock. It should be called before any other ethernet operation.

Parameters:

miiMode – The MII/RGMII/RMII mode for interface between the phy and Ethernet.

void ENET_QOS_EnableClock(bool enable): Enable/Disable ENET qos clock.

Note

User needs to provide the implementation because the implementation is SoC specific. This function should be called before config RMII mode.

struct _enet_qos_rx_bd_struct

#include <fsl_enet_qos.h>

Defines the receive descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the receive descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the receive data process.

Public Members

__IO uint32_t buff1Addr: Buffer 1 address

__IO uint32_t reserved: Reserved

__IO uint32_t buff2Addr: Buffer 2 or next descriptor address

__IO uint32_t control: Buffer 1/2 byte counts and control

struct _enet_qos_tx_bd_struct

#include <fsl_enet_qos.h>

Defines the transmit descriptor structure has the read-format and write-back format structure. They both has the same size with different region definition. so we define the read-format region as the transmit descriptor structure Use the read-format region mask bits in the descriptor initialization Use the write-back format region mask bits in the transmit data process.

Public Members

__IO uint32_t buff1Addr: Buffer 1 address

__IO uint32_t buff2Addr: Buffer 2 address

__IO uint32_t buffLen: Buffer 1/2 byte counts

__IO uint32_t controlStat: TDES control and status word

struct _enet_qos_tx_bd_config_struct

#include <fsl_enet_qos.h>

Defines the Tx BD configuration structure.

Public Members

void *buffer1: The first buffer address in the descriptor.

uint32_t bytes1: The bytes in the fist buffer.

void *buffer2: The second buffer address in the descriptor.

uint32_t bytes2: The bytes in the second buffer.

uint32_t framelen: The length of the frame to be transmitted.

bool intEnable: Interrupt enable flag.

bool tsEnable: The timestamp enable.

enet_qos_tx_offload_t txOffloadOps: The Tx checksum offload option.

enet_qos_desc_flag flag: The flag of this tx desciriptor, see “enet_qos_desc_flag”.

struct _enet_qos_ptp_time

#include <fsl_enet_qos.h>

Defines the ENET PTP time stamp structure.

Public Members

uint64_t second: Second.

uint32_t nanosecond: Nanosecond.

struct enet_qos_frame_info

#include <fsl_enet_qos.h>

Defines the frame info structure.

Public Members

void *context: User specified data, could be buffer address for free

bool isTsAvail: Flag indicates timestamp available status

enet_qos_ptp_time_t timeStamp: Timestamp of frame

struct _enet_qos_tx_dirty_ring

#include <fsl_enet_qos.h>

Defines the ENET transmit dirty addresses ring/queue structure.

Public Members

enet_qos_frame_info_t *txDirtyBase: Dirty buffer descriptor base address pointer.

uint16_t txGenIdx: tx generate index.

uint16_t txConsumIdx: tx consume index.

uint16_t txRingLen: tx ring length.

bool isFull: tx ring is full flag, add this parameter to avoid waste one element.

struct _enet_qos_ptp_config

#include <fsl_enet_qos.h>

Defines the ENET PTP configuration structure.

Public Members

bool fineUpdateEnable: Use the fine update.

uint32_t defaultAddend: Default addend value when fine update is enable, could be 2^32 / (refClk_Hz / ENET_QOS_MICRSECS_ONESECOND / ENET_QOS_SYSTIME_REQUIRED_CLK_MHZ).

bool ptp1588V2Enable: The desired system time frequency. Must be lower than reference clock. (Only used with fine correction method). ptp 1588 version 2 is used.

enet_qos_ts_rollover_type tsRollover: 1588 time nanosecond rollover.

struct _enet_qos_est_gate_op: #include <fsl_enet_qos.h>

Defines the EST gate operation structure.

struct _enet_qos_est_gcl

#include <fsl_enet_qos.h>

Defines the EST gate control list structure.

Public Members

bool enable: Enable or disable EST

uint64_t cycleTime: Base Time 32 bits seconds 32 bits nanoseconds

uint32_t extTime: Cycle Time 32 bits seconds 32 bits nanoseconds

uint32_t numEntries: Time Extension 32 bits seconds 32 bits nanoseconds

enet_qos_est_gate_op_t *opList: Number of entries

struct _enet_qos_rxp_config

#include <fsl_enet_qos.h>

Defines the ENET_QOS Rx parser configuration structure.

Public Members

uint32_t matchEnable: 4-byte match data used for comparing with incoming packet

uint8_t acceptFrame: When matchEnable is set to 1, the matchData is used for comparing

uint8_t rejectFrame: When acceptFrame = 1 and data is matched, the frame will be sent to DMA channel

uint8_t inverseMatch: When rejectFrame = 1 and data is matched, the frame will be dropped

uint8_t nextControl: Inverse match

uint8_t reserved: Next instruction indexing control

uint8_t frameOffset: Reserved control fields

uint8_t okIndex: Frame offset in the packet data to be compared for match, in terms of 4 bytes.

uint8_t dmaChannel: Memory Index to be used next.

uint32_t reserved2: The DMA channel enet_qos_rxp_dma_chn_t used for receiving the frame when frame match and acceptFrame = 1

struct _enet_qos_buffer_config

#include <fsl_enet_qos.h>

Defines the buffer descriptor configure structure.

Note

The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
The recommended minimum tx/rx ring length is 4.
The tx/rx descriptor tail address shall be the address pointer to the address just after the end of the last last descriptor. because only the descriptors between the start address and the tail address will be used by DMA.
The descriptor address is the start address of all used contiguous memory. for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories for rx descriptor ring 0.
The “*rxBufferstartAddr” is the first element of rxRingLen (2*rxRingLen for double buffers) rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the address of a rxRingLen or 2*rxRingLen array.

Public Members

uint8_t rxRingLen: The length of receive buffer descriptor ring.

uint8_t txRingLen: The length of transmit buffer descriptor ring.

enet_qos_tx_bd_struct_t *txDescStartAddrAlign: Aligned transmit descriptor start address.

enet_qos_tx_bd_struct_t *txDescTailAddrAlign: Aligned transmit descriptor tail address.

enet_qos_frame_info_t *txDirtyStartAddr: Start address of the dirty tx frame information.

enet_qos_rx_bd_struct_t *rxDescStartAddrAlign: Aligned receive descriptor start address.

enet_qos_rx_bd_struct_t *rxDescTailAddrAlign: Aligned receive descriptor tail address.

uint32_t *rxBufferStartAddr: Start address of the rx buffers.

uint32_t rxBuffSizeAlign: Aligned receive data buffer size.

bool rxBuffNeedMaintain: Whether receive data buffer need cache maintain.

struct _enet_qos_cbs_config

#include <fsl_enet_qos.h>

Defines the CBS configuration for queue.

Public Members

uint16_t sendSlope: Send slope configuration.

uint16_t idleSlope: Idle slope configuration.

uint32_t highCredit: High credit.

uint32_t lowCredit: Low credit.

struct enet_qos_tx_queue_config

#include <fsl_enet_qos.h>

Defines the queue configuration structure.

Public Members

enet_qos_queue_mode_t mode: tx queue mode configuration.

uint32_t weight: Refer to the MTL TxQ Quantum Weight register.

uint32_t priority: Refer to Transmit Queue Priority Mapping register.

enet_qos_cbs_config_t *cbsConfig: CBS configuration if queue use AVB mode.

struct enet_qos_rx_queue_config

#include <fsl_enet_qos.h>

Defines the queue configuration structure.

Public Members

enet_qos_queue_mode_t mode: rx queue mode configuration.

uint8_t mapChannel: tx queue map dma channel.

uint32_t priority: Rx queue priority.

enet_qos_rx_queue_route_t packetRoute: Receive packet routing.

struct enet_qos_multiqueue_config

#include <fsl_enet_qos.h>

Defines the configuration when multi-queue is used.

Public Members

enet_qos_dma_burstlen burstLen: Burst len for the multi-queue.

uint8_t txQueueUse: Used Tx queue count.

enet_qos_mtl_multiqueue_txsche mtltxSche: Transmit schedule for multi-queue.

enet_qos_queue_tx_config_t txQueueConfig[ENET_QOS_DMA_CH_COUNT]: Tx Queue configuration.

uint8_t rxQueueUse: Used Rx queue count.

enet_qos_mtl_multiqueue_rxsche mtlrxSche: Receive schedule for multi-queue.

enet_qos_queue_rx_config_t rxQueueConfig[ENET_QOS_DMA_CH_COUNT]: Rx Queue configuration.

struct _enet_qos_config

#include <fsl_enet_qos.h>

Defines the basic configuration structure for the ENET device.

Note

Default the signal queue is used so the “*multiqueueCfg” is set default with NULL. Set the pointer with a valid configuration pointer if the multiple queues are required. If multiple queue is enabled, please make sure the buffer configuration for all are prepared also.

Public Members

uint16_t specialControl: The logic or of enet_qos_special_config_t

enet_qos_multiqueue_config_t *multiqueueCfg: Use multi-queue.

enet_qos_mii_mode_t miiMode: MII mode.

enet_qos_mii_speed_t miiSpeed: MII Speed.

enet_qos_mii_duplex_t miiDuplex: MII duplex.

uint16_t pauseDuration: Used in the tx flow control frame, only valid when kENET_QOS_FlowControlEnable is set.

enet_qos_ptp_config_t *ptpConfig: PTP 1588 feature configuration

uint32_t csrClock_Hz: CSR clock frequency in HZ.

enet_qos_rx_alloc_callback_t rxBuffAlloc: Callback to alloc memory, must be provided for zero-copy Rx.

enet_qos_rx_free_callback_t rxBuffFree: Callback to free memory, must be provided for zero-copy Rx.

struct _enet_qos_tx_bd_ring

#include <fsl_enet_qos.h>

Defines the ENET transmit buffer descriptor ring/queue structure.

Public Members

enet_qos_tx_bd_struct_t *txBdBase: Buffer descriptor base address pointer.

uint16_t txGenIdx: tx generate index.

uint16_t txConsumIdx: tx consume index.

volatile uint16_t txDescUsed: tx descriptor used number.

uint16_t txRingLen: tx ring length.

struct _enet_qos_rx_bd_ring

#include <fsl_enet_qos.h>

Defines the ENET receive buffer descriptor ring/queue structure.

Public Members

enet_qos_rx_bd_struct_t *rxBdBase: Buffer descriptor base address pointer.

uint16_t rxGenIdx: The current available receive buffer descriptor pointer.

uint16_t rxRingLen: Receive ring length.

uint32_t rxBuffSizeAlign: Receive buffer size.

struct _enet_qos_handle

#include <fsl_enet_qos.h>

Defines the ENET handler structure.

Public Members

uint8_t txQueueUse: Used tx queue count.

uint8_t rxQueueUse: Used rx queue count.

bool doubleBuffEnable: The double buffer is used in the descriptor.

bool rxintEnable: Rx interrupt enabled.

bool rxMaintainEnable[ENET_QOS_DMA_CH_COUNT]: Rx buffer cache maintain enabled.

enet_qos_rx_bd_ring_t rxBdRing[ENET_QOS_DMA_CH_COUNT]: Receive buffer descriptor.

enet_qos_tx_bd_ring_t txBdRing[ENET_QOS_DMA_CH_COUNT]: Transmit buffer descriptor.

enet_qos_tx_dirty_ring_t txDirtyRing[ENET_QOS_DMA_CH_COUNT]: Transmit dirty buffers addresses.

uint32_t *rxBufferStartAddr[ENET_QOS_DMA_CH_COUNT]: Rx buffer start address for reInitialize.

enet_qos_callback_t callback: Callback function.

void *userData: Callback function parameter.

uint8_t multicastCount[64]: Multicast collisions counter

enet_qos_rx_alloc_callback_t rxBuffAlloc: Callback to alloc memory, must be provided for zero-copy Rx.

enet_qos_rx_free_callback_t rxBuffFree: Callback to free memory, must be provided for zero-copy Rx.

struct _enet_qos_state

#include <fsl_enet_qos.h>

Defines the ENET state structure.

Note

The structure contains saved state for the instance. It could be stored in enet_qos_handle_t, but that’s used only with the transactional API.

Public Members

enet_qos_mii_mode_t miiMode: MII mode.

struct _enet_qos_buffer_struct

#include <fsl_enet_qos.h>

Defines the frame buffer structure.

Public Members

void *buffer: The buffer store the whole or partial frame.

uint16_t length: The byte length of this buffer.

struct _enet_qos_rx_frame_error

#include <fsl_enet_qos.h>

Defines the Rx frame error structure.

Public Members

bool rxDstAddrFilterErr: Destination Address Filter Fail.

bool rxSrcAddrFilterErr: SA Address Filter Fail.

bool rxDribbleErr: Dribble error.

bool rxReceiveErr: Receive error.

bool rxOverFlowErr: Receive over flow.

bool rxWatchDogErr: Watch dog timeout.

bool rxGaintPacketErr: Receive gaint packet.

bool rxCrcErr: Receive CRC error.

struct _enet_qos_rx_frame_attribute_struct

Public Members

bool isTsAvail: Rx frame timestamp is available or not.

enet_qos_ptp_time_t timestamp: The nanosecond part timestamp of this Rx frame.

struct _enet_qos_rx_frame_struct

#include <fsl_enet_qos.h>

Defines the Rx frame data structure.

Public Members

enet_qos_buffer_struct_t *rxBuffArray: Rx frame buffer structure.

uint16_t totLen: Rx frame total length.

enet_qos_rx_frame_attribute_t rxAttribute: Rx frame attribute structure.

enet_qos_rx_frame_error_t rxFrameError: Rx frame error.

struct _enet_qos_transfer_stats

#include <fsl_enet_qos.h>

Defines the ENET QOS transfer statistics structure.

Public Members

uint32_t statsRxFrameCount: Rx frame number.

uint32_t statsRxCrcErr: Rx frame number with CRC error.

uint32_t statsRxAlignErr: Rx frame number with alignment error.

uint32_t statsRxLengthErr: Rx frame length field doesn’t equal to packet size.

uint32_t statsRxFifoOverflowErr: Rx FIFO overflow count.

uint32_t statsTxFrameCount: Tx frame number.

uint32_t statsTxFifoUnderRunErr: Tx FIFO underrun count.

FGPIO Driver#

FlexCAN: Flex Controller Area Network Driver#

FlexCAN Driver#

bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base)

Determine whether the FlexCAN instance support CAN FD mode at run time.

Note

Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.

uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx)

Get Mailbox offset number by dword.

This function gets the offset number of the specified mailbox. Mailbox is not consecutive between memory regions when payload is not 8 bytes so need to calculate the specified mailbox address. For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword after the 0x4002_4080, which is actually the address of mailbox MB[1].CS.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – Mailbox index.

Returns:

Mailbox address offset in word.

status_t FLEXCAN_EnterFreezeMode(CAN_Type *base)

Enter FlexCAN Freeze Mode.

This function makes the FlexCAN work under Freeze Mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

status_t FLEXCAN_ExitFreezeMode(CAN_Type *base)

Exit FlexCAN Freeze Mode.

This function makes the FlexCAN leave Freeze Mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

uint32_t FLEXCAN_GetInstance(CAN_Type *base)

Get the FlexCAN instance from peripheral base address.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN instance.

bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit Rates for classical CAN.

This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 v4.2.0 and previous version document.

Parameters:

base – FlexCAN peripheral base address.
bitRate – The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration.

void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_Init function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t bitRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)

Calculates the improved timing values by specific bit rates for CANFD.

This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based on the recommendation of the CiA 1301 v1.0.0 document.

Parameters:

base – FlexCAN peripheral base address.
bitRate – The CANFD bus control speed in bps defined by user.
bitRateFD – The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate switching.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration

void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_FDInit function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.bitRateFD            = 2000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.
dataSize – FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs to be less than or equal to this value.
brs – True if bit rate switch is enabled in FD mode.

void FLEXCAN_Deinit(CAN_Type *base)

De-initializes a FlexCAN instance.

This function disables the FlexCAN module clock and sets all register values to the reset value.

Parameters:

base – FlexCAN peripheral base address.

void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig)

Gets the default configuration structure.

This function initializes the FlexCAN configuration structure to default values. The default values are as follows. flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig->bitRate = 1000000U; flexcanConfig->bitRateFD = 2000000U; flexcanConfig->maxMbNum = 16; flexcanConfig->enableLoopBack = false; flexcanConfig->enableSelfWakeup = false; flexcanConfig->enableIndividMask = false; flexcanConfig->disableSelfReception = false; flexcanConfig->enableListenOnlyMode = false; flexcanConfig->enableDoze = false; flexcanConfig->enablePretendedeNetworking = false; flexcanConfig->enableMemoryErrorControl = true; flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; flexcanConfig->enableTransceiverDelayMeasure = true; flexcanConfig->enableRemoteRequestFrameStored = true; flexcanConfig->payloadEndianness = kFLEXCAN_bigEndian; flexcanConfig.timingConfig = timingConfig;

Parameters:

pConfig – Pointer to the FlexCAN configuration structure.

void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN classical CAN protocol timing characteristic.

This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.

Note

Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps)

Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.

This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.

Note

Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().

Parameters:

base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRate_Bps – Bit rate in Bps.

Returns:

kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.

void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)

Sets the FlexCAN CANFD data phase timing characteristic.

This function gives user settings to CANFD data phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() to set both Nominal/Data bit Rate instead.

Note

Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps)

Set bit rate of FlexCAN FD frame.

This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing values.

Parameters:

base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRateN_Bps – Nominal bit Rate in Bps.
bitRateD_Bps – Data bit Rate in Bps.

Returns:

kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.

void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive message buffer global mask.

This function sets the global mask for the FlexCAN message buffer in a matching process. The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().

Parameters:

base – FlexCAN peripheral base address.
mask – Rx Message Buffer Global Mask value.

void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)

Sets the FlexCAN receive FIFO global mask.

This function sets the global mask for FlexCAN FIFO in a matching process.

Parameters:

base – FlexCAN peripheral base address.
mask – Rx Fifo Global Mask value.

void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)

Sets the FlexCAN receive individual mask.

This function sets the individual mask for the FlexCAN matching process. The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to the Rx Filter with the same index. Note that only the first 32 individual masks can be used as the Rx FIFO filter mask.

Parameters:

base – FlexCAN peripheral base address.
maskIdx – The Index of individual Mask.
mask – Rx Individual Mask value.

void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
- true: Enable Tx Message Buffer.
- false: Disable Tx Message Buffer.

void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer. User should invoke this API when CTRL2[RRS]=1. When CTRL2[RRS]=1, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbEmpty, kFLEXCAN_RxMbFull or kFLEXCAN_RxMbOverrun. Message buffer will store the remote frame in the same fashion of a data frame. No automatic remote response frame will be generated. User need to setup another message buffer to respond remote request.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
- true: Enable Rx Message Buffer.
- false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)

Configures a FlexCAN Message Buffer identifier.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
- true: Enable Tx Message Buffer.
- false: Disable Tx Message Buffer.

void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
- true: Enable Rx Message Buffer.
- false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetFDMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)

Configures a FlexCAN Message Buffer identifier.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetRemoteResponseMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pFrame)

Configures a FlexCAN Remote Response Message Buffer.

User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbRanswer. If there is a matching ID, then this mailbox content will be transmitted as response. The received remote request frame is not stored in receive buffer. It is only used to trigger a transmission of a frame in response.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pFrame – Pointer to CAN message frame structure for response.

void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable)

Configures the FlexCAN Legacy Rx FIFO.

This function configures the FlexCAN Rx FIFO with given configuration.

Note

Legacy Rx FIFO only can receive classic CAN message.

Parameters:

base – FlexCAN peripheral base address.
pRxFifoConfig – Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Legacy Rx FIFO.
- true: Enable Legacy Rx FIFO.
- false: Disable Legacy Rx FIFO.

void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable)

Configures the FlexCAN Enhanced Rx FIFO.

This function configures the Enhanced Rx FIFO with given configuration.

Note

Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time.

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Enhanced Rx FIFO.
- true: Enable Enhanced Rx FIFO.
- false: Disable Enhanced Rx FIFO.

void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig)

Configures the FlexCAN Pretended Networking mode.

This function configures the FlexCAN Pretended Networking mode with given configuration.

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Rx FIFO configuration structure.

static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)

Gets the FlexCAN module interrupt flags.

This function gets all FlexCAN status flags. The flags are returned as the logical OR value of the enumerators _flexcan_flags. To check the specific status, compare the return value with enumerators in _flexcan_flags.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.

static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)

Clears status flags with the provided mask.

This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag can’t be cleared by this function.

Parameters:

base – FlexCAN peripheral base address.
mask – The status flags to be cleared, it is logical OR value of _flexcan_flags.

static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)

Gets the FlexCAN Bus Error Counter value.

This function gets the FlexCAN Bus Error Counter value for both Tx and Rx direction. These values may be needed in the upper layer error handling.

Parameters:

base – FlexCAN peripheral base address.
txErrBuf – Buffer to store Tx Error Counter value.
rxErrBuf – Buffer to store Rx Error Counter value.

static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN low 64 Message Buffer interrupt flags.

This function gets the interrupt flags of a given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Gets the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN low 64 Message Buffer interrupt flags.

This function clears the interrupt flags of a given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)

Clears the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus)

Gets the FlexCAN Memory Error Report registers status.

This function gets the FlexCAN Memory Error Report registers status.

Parameters:

base – FlexCAN peripheral base address.
errorStatus – Pointer to FlexCAN Memory Error Report registers status structure.

static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)

Gets the FlexCAN Number of Matches when in Pretended Networking.

This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event.

Parameters:

base – FlexCAN peripheral base address.

Returns:

The number of received wake up msessages.

static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)

Gets the number of FlexCAN Enhanced Rx FIFO available frames.

This function gets the number of CAN messages stored in the Enhanced Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.

Returns:

The number of available CAN messages stored in the Enhanced Rx FIFO.

static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN interrupts according to the provided mask.

This function enables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

base – FlexCAN peripheral base address.
mask – The interrupts to enable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN interrupts according to the provided mask.

This function disables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

base – FlexCAN peripheral base address.
mask – The interrupts to disable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN low 64 Message Buffer interrupts.

This function enables the interrupts of given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Enables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN low 64 Message Buffer interrupts.

This function disables the interrupts of given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)

Disables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)

Enables or disables the FlexCAN Rx FIFO DMA request.

This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
enable – true to enable, false to disable.

static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)

Gets the Rx FIFO Head address.

This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN Rx FIFO Head address.

static inline status_t FLEXCAN_Enable(CAN_Type *base, bool enable)

Enables or disables the FlexCAN module operation.

This function enables or disables the FlexCAN module.

Parameters:

base – FlexCAN base pointer.
enable – true to enable, false to disable.

Returns:

kStatus_Success Enable FlexCAN module successful kStatus_Timeout Timeout when wait for Low-Power Mode Acknowledge

status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame)

Writes a FlexCAN Message to the Transmit Message Buffer.

This function writes a CAN Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN Message transmit. After that the function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Receive Message Buffer.

This function reads a CAN message from a specified Receive Message Buffer. The function fills a receive CAN message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame)

Writes a FlexCAN FD Message to the Transmit Message Buffer.

This function writes a CAN FD Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN FD Message transmit. After that the function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN FD Message from Receive Message Buffer.

This function reads a CAN FD message from a specified Receive Message Buffer. The function fills a receive CAN FD message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.

status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Legacy Rx FIFO.

This function reads a CAN message from the FlexCAN Legacy Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)

Reads a FlexCAN Message from Enhanced Rx FIFO.

This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Reads a FlexCAN Message from Wake Up MB.

This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The last message is stored in WMB3.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.
mbIdx – The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.

Return values:

kStatus_Success – - Read Message from Wake up Message Buffer successfully.
kStatus_Fail – - Wake up Message Buffer has no valid content.

status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.

void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.

status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame)

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame)

Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)

Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
kStatus_Timeout – - Failed to receive frames within specific time.

void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData)

Initializes the FlexCAN handle.

This function initializes the FlexCAN handle, which can be used for other FlexCAN transactional APIs. Usually, for a specified FlexCAN instance, call this API once to get the initialized handle.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
callback – The callback function.
userData – The parameter of the callback function.

status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the flexcan_fifo_transfer_t.

Return values:

kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives a message from Enhanced Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@

Return values:

kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx)

Gets the detail index of Mailbox’s Timestamp by handle.

Then function can only be used when calling non-blocking Data transfer (TX/RX) API, After TX/RX data transfer done (User can get the status by handler’s callback function), we can get the detail index of Mailbox’s timestamp by handle, Detail non-blocking data transfer API (TX/RX) contain. -FLEXCAN_TransferSendNonBlocking -FLEXCAN_TransferFDSendNonBlocking -FLEXCAN_TransferReceiveNonBlocking -FLEXCAN_TransferFDReceiveNonBlocking -FLEXCAN_TransferReceiveFifoNonBlocking

Parameters:

handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

Return values:

the – index of mailbox ‘s timestamp stored in the handle.

static inline uint32_t FLEXCAN_GetHighResolutionTimeStamp(CAN_Type *base, uint8_t mbIdx)

void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Rx FIFO process.

This function aborts the interrupt driven message receive from Rx FIFO process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle)

Aborts the interrupt driven message receive from Enhanced Rx FIFO process.

This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN IRQ handle function.

This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_MbHandleIRQ(CAN_Type *base, flexcan_handle_t *handle, uint32_t startMbIdx, uint32_t endMbIdx)

FlexCAN Message Buffer IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
startMbIdx – First Message Buffer to handle.
endMbIdx – Last Message Buffer to handle.

void FLEXCAN_EhancedRxFifoHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Ehanced Rx FIFO IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_BusoffErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Bus Off, Error and Warning IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_PNWakeUpHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Pretended Networking Wake-up IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_MemoryErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)

FlexCAN Memory Error IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

FSL_FLEXCAN_DRIVER_VERSION: FlexCAN driver version.

FlexCAN transfer status.

Values:

enumerator kStatus_FLEXCAN_TxBusy: Tx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_TxIdle: Tx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_TxSwitchToRx: Remote Message is send out and Message buffer changed to Receive one.

enumerator kStatus_FLEXCAN_RxBusy: Rx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_RxIdle: Rx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_RxOverflow: Rx Message Buffer is Overflowed.

enumerator kStatus_FLEXCAN_RxFifoBusy: Rx Message FIFO is Busy.

enumerator kStatus_FLEXCAN_RxFifoIdle: Rx Message FIFO is Idle.

enumerator kStatus_FLEXCAN_RxFifoOverflow: Rx Message FIFO is overflowed.

enumerator kStatus_FLEXCAN_RxFifoWarning: Rx Message FIFO is almost overflowed.

enumerator kStatus_FLEXCAN_RxFifoDisabled: Rx Message FIFO is disabled during reading.

enumerator kStatus_FLEXCAN_ErrorStatus: FlexCAN Module Error and Status.

enumerator kStatus_FLEXCAN_WakeUp: FlexCAN is waken up from STOP mode.

enumerator kStatus_FLEXCAN_UnHandled: UnHadled Interrupt asserted.

enumerator kStatus_FLEXCAN_RxRemote: Rx Remote Message Received in Mail box.

enumerator kStatus_FLEXCAN_RxFifoUnderflow: Enhanced Rx Message FIFO is underflow.

enumerator kStatus_FLEXCAN_MemoryError: FlexCAN Memory Error.

enum _flexcan_frame_format

FlexCAN frame format.

Values:

enumerator kFLEXCAN_FrameFormatStandard: Standard frame format attribute.

enumerator kFLEXCAN_FrameFormatExtend: Extend frame format attribute.

enum _flexcan_frame_type

FlexCAN frame type.

Values:

enumerator kFLEXCAN_FrameTypeData: Data frame type attribute.

enumerator kFLEXCAN_FrameTypeRemote: Remote frame type attribute.

enum _flexcan_clock_source

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

Values:

enumerator kFLEXCAN_ClkSrcOsc: FlexCAN Protocol Engine clock from Oscillator.

enumerator kFLEXCAN_ClkSrcPeri: FlexCAN Protocol Engine clock from Peripheral Clock.

enumerator kFLEXCAN_ClkSrc0: FlexCAN Protocol Engine clock selected by user as SRC == 0.

enumerator kFLEXCAN_ClkSrc1: FlexCAN Protocol Engine clock selected by user as SRC == 1.

enum _flexcan_wake_up_source

FlexCAN wake up source.

Values:

enumerator kFLEXCAN_WakeupSrcUnfiltered: FlexCAN uses unfiltered Rx input to detect edge.

enumerator kFLEXCAN_WakeupSrcFiltered: FlexCAN uses filtered Rx input to detect edge.

enum _flexcan_endianness

FlexCAN payload endianness.

Values:

enumerator kFLEXCAN_bigEndian: Transmit frame with MSB first, receive frame with big-endian format.

enumerator kFLEXCAN_littleEndian: Transmit frame with LSB first, receive frame with little-endian format.

enum _flexcan_MB_timestamp_base

FlexCAN timebase used for capturing 16-bit TIME_STAMP field of message buffer.

Values:

enumerator kFLEXCAN_CANTimer: FlexCAN free-running timer.

enumerator kFLEXCAN_Lower16bitsHRTimer: Lower 16 bits of high-resolution on-chip timer.

enumerator kFLEXCAN_Upper16bitsHRTimer: Upper 16 bits of high-resolution on-chip timer.

enum _flexcan_capture_point

FlexCAN capture point of 32-bit high resolution timebase during a CAN frame.

Values:

enumerator kFLEXCAN_CANFrameID2ndBit: Second bit of identifier field of any frame is on the CAN bus. HR_TIME_STAMPn register will not capture 32-bit counter value.

enumerator kFLEXCAN_CANFrameEnd: End of the CAN frame.

enumerator kFLEXCAN_CANFrameStart: Start of the CAN frame.

enumerator kFLEXCAN_CANFDFrameRes: Start of frame for classical CAN frames; res bit for CAN FD frames.

enum _flexcan_rx_fifo_filter_type

FlexCAN Rx Fifo Filter type.

Values:

enumerator kFLEXCAN_RxFifoFilterTypeA: One full ID (standard and extended) per ID Filter element.

enumerator kFLEXCAN_RxFifoFilterTypeB: Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeC: Four partial 8-bit Standard or extended ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeD: All frames rejected.

enum _flexcan_mb_size

FlexCAN Message Buffer Payload size.

Values:

enumerator kFLEXCAN_8BperMB: Selects 8 bytes per Message Buffer.

enumerator kFLEXCAN_16BperMB: Selects 16 bytes per Message Buffer.

enumerator kFLEXCAN_32BperMB: Selects 32 bytes per Message Buffer.

enumerator kFLEXCAN_64BperMB: Selects 64 bytes per Message Buffer.

enum _flexcan_fd_frame_length

FlexCAN CAN FD frame supporting data length (available DLC values).

For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, the high order bytes that do not fit the Payload size will lose.

Values:

enumerator kFLEXCAN_0BperFrame: Frame contains 0 valid data bytes.

enumerator kFLEXCAN_1BperFrame: Frame contains 1 valid data bytes.

enumerator kFLEXCAN_2BperFrame: Frame contains 2 valid data bytes.

enumerator kFLEXCAN_3BperFrame: Frame contains 3 valid data bytes.

enumerator kFLEXCAN_4BperFrame: Frame contains 4 valid data bytes.

enumerator kFLEXCAN_5BperFrame: Frame contains 5 valid data bytes.

enumerator kFLEXCAN_6BperFrame: Frame contains 6 valid data bytes.

enumerator kFLEXCAN_7BperFrame: Frame contains 7 valid data bytes.

enumerator kFLEXCAN_8BperFrame: Frame contains 8 valid data bytes.

enumerator kFLEXCAN_12BperFrame: Frame contains 12 valid data bytes.

enumerator kFLEXCAN_16BperFrame: Frame contains 16 valid data bytes.

enumerator kFLEXCAN_20BperFrame: Frame contains 20 valid data bytes.

enumerator kFLEXCAN_24BperFrame: Frame contains 24 valid data bytes.

enumerator kFLEXCAN_32BperFrame: Frame contains 32 valid data bytes.

enumerator kFLEXCAN_48BperFrame: Frame contains 48 valid data bytes.

enumerator kFLEXCAN_64BperFrame: Frame contains 64 valid data bytes.

enum _flexcan_efifo_dma_per_read_length

FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

Values:

enumerator kFLEXCAN_1WordPerRead: Transfer 1 32-bit words (CS).

enumerator kFLEXCAN_2WordPerRead: Transfer 2 32-bit words (CS + ID).

enumerator kFLEXCAN_3WordPerRead: Transfer 3 32-bit words (CS + ID + 1~4 bytes data).

enumerator kFLEXCAN_4WordPerRead: Transfer 4 32-bit words (CS + ID + 5~8 bytes data).

enumerator kFLEXCAN_5WordPerRead: Transfer 5 32-bit words (CS + ID + 9~12 bytes data).

enumerator kFLEXCAN_6WordPerRead: Transfer 6 32-bit words (CS + ID + 13~16 bytes data).

enumerator kFLEXCAN_7WordPerRead: Transfer 7 32-bit words (CS + ID + 17~20 bytes data).

enumerator kFLEXCAN_8WordPerRead: Transfer 8 32-bit words (CS + ID + 21~24 bytes data).

enumerator kFLEXCAN_9WordPerRead: Transfer 9 32-bit words (CS + ID + 25~28 bytes data).

enumerator kFLEXCAN_10WordPerRead: Transfer 10 32-bit words (CS + ID + 29~32 bytes data).

enumerator kFLEXCAN_11WordPerRead: Transfer 11 32-bit words (CS + ID + 33~36 bytes data).

enumerator kFLEXCAN_12WordPerRead: Transfer 12 32-bit words (CS + ID + 37~40 bytes data).

enumerator kFLEXCAN_13WordPerRead: Transfer 13 32-bit words (CS + ID + 41~44 bytes data).

enumerator kFLEXCAN_14WordPerRead: Transfer 14 32-bit words (CS + ID + 45~48 bytes data).

enumerator kFLEXCAN_15WordPerRead: Transfer 15 32-bit words (CS + ID + 49~52 bytes data).

enumerator kFLEXCAN_16WordPerRead: Transfer 16 32-bit words (CS + ID + 53~56 bytes data).

enumerator kFLEXCAN_17WordPerRead: Transfer 17 32-bit words (CS + ID + 57~60 bytes data).

enumerator kFLEXCAN_18WordPerRead: Transfer 18 32-bit words (CS + ID + 61~64 bytes data).

enumerator kFLEXCAN_19WordPerRead: Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).

enumerator kFLEXCAN_20WordPerRead: Transfer 20 32-bit words (CS + ID + 64 bytes data + ID HIT + HR timestamp).

enum _flexcan_rx_fifo_priority

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

Values:

enumerator kFLEXCAN_RxFifoPrioLow: Matching process start from Rx Message Buffer first.

enumerator kFLEXCAN_RxFifoPrioHigh: Matching process start from Enhanced/Legacy Rx FIFO first.

enum _flexcan_interrupt_enable

FlexCAN interrupt enable enumerations.

This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.

Note

FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.

Values:

enumerator kFLEXCAN_BusOffInterruptEnable: Bus Off interrupt, use bit 15.

enumerator kFLEXCAN_ErrorInterruptEnable: CAN Error interrupt, use bit 14.

enumerator kFLEXCAN_TxWarningInterruptEnable: Tx Warning interrupt, use bit 11.

enumerator kFLEXCAN_RxWarningInterruptEnable: Rx Warning interrupt, use bit 10.

enumerator kFLEXCAN_FDErrorInterruptEnable: CAN FD Error interrupt, use bit 31.

enumerator kFLEXCAN_PNMatchWakeUpInterruptEnable: PN Match Wake Up interrupt, use high word bit 17.

enumerator kFLEXCAN_PNTimeoutWakeUpInterruptEnable: PN Timeout Wake Up interrupt, use high word bit 16. Enhanced Rx FIFO Underflow interrupt, use high word bit 31.

enumerator kFLEXCAN_ERxFifoUnderflowInterruptEnable: Enhanced Rx FIFO Overflow interrupt, use high word bit 30.

enumerator kFLEXCAN_ERxFifoOverflowInterruptEnable: Enhanced Rx FIFO Watermark interrupt, use high word bit 29.

enumerator kFLEXCAN_ERxFifoWatermarkInterruptEnable: Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28.

enumerator kFLEXCAN_ERxFifoDataAvlInterruptEnable

enumerator kFLEXCAN_HostAccessNCErrorInterruptEnable: Host Access With Non-Correctable Errors interrupt, use high word bit 0.

enumerator kFLEXCAN_FlexCanAccessNCErrorInterruptEnable: FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2.

enumerator kFLEXCAN_HostOrFlexCanCErrorInterruptEnable: Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3.

enum _flexcan_flags

FlexCAN status flags.

This provides constants for the FlexCAN status flags for use in the FlexCAN functions.

Note

The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to read status flags and distinguish which error is occur using _flexcan_error_flags enumerations.

Values:

enumerator kFLEXCAN_ErrorOverrunFlag: Error Overrun Status.

enumerator kFLEXCAN_FDErrorIntFlag: CAN FD Error Interrupt Flag.

enumerator kFLEXCAN_BusoffDoneIntFlag: Bus Off process completed Interrupt Flag.

enumerator kFLEXCAN_SynchFlag: CAN Synchronization Status.

enumerator kFLEXCAN_TxWarningIntFlag: Tx Warning Interrupt Flag.

enumerator kFLEXCAN_RxWarningIntFlag: Rx Warning Interrupt Flag.

enumerator kFLEXCAN_IdleFlag: FlexCAN In IDLE Status.

enumerator kFLEXCAN_FaultConfinementFlag: FlexCAN Fault Confinement State.

enumerator kFLEXCAN_TransmittingFlag: FlexCAN In Transmission Status.

enumerator kFLEXCAN_ReceivingFlag: FlexCAN In Reception Status.

enumerator kFLEXCAN_BusOffIntFlag: Bus Off Interrupt Flag.

enumerator kFLEXCAN_ErrorIntFlag: CAN Error Interrupt Flag.

enumerator kFLEXCAN_ErrorFlag

enumerator kFLEXCAN_PNMatchIntFlag: PN Matching Event Interrupt Flag.

enumerator kFLEXCAN_PNTimeoutIntFlag: PN Timeout Event Interrupt Flag.

enumerator kFLEXCAN_ERxFifoUnderflowIntFlag: Enhanced Rx FIFO underflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoOverflowIntFlag: Enhanced Rx FIFO overflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoWatermarkIntFlag: Enhanced Rx FIFO watermark Interrupt Flag.

enumerator kFLEXCAN_ERxFifoDataAvlIntFlag: Enhanced Rx FIFO data available Interrupt Flag.

enumerator kFLEXCAN_ERxFifoEmptyFlag: Enhanced Rx FIFO empty status.

enumerator kFLEXCAN_ERxFifoFullFlag: Enhanced Rx FIFO full status.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorIntFlag: Host Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag: FlexCAN Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_CorrectableErrorIntFlag: Correctable Error Interrupt Flag.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag: Host Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag: FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_CorrectableErrorOverrunFlag: Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_AllMemoryErrorIntFlag: All Memory Error Interrupt Flags.

enumerator kFLEXCAN_AllMemoryErrorFlag: All Memory Error Flags.

enum _flexcan_error_flags

FlexCAN error status flags.

The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. This enumerations should be used with KFLEXCAN_ErrorFlag in _flexcan_flags enumerations to ditermine which error is generated.

Values:

enumerator kFLEXCAN_FDStuffingError: Stuffing Error.

enumerator kFLEXCAN_FDFormError: Form Error.

enumerator kFLEXCAN_FDCrcError: Cyclic Redundancy Check Error.

enumerator kFLEXCAN_FDBit0Error: Unable to send dominant bit.

enumerator kFLEXCAN_FDBit1Error: Unable to send recessive bit.

enumerator kFLEXCAN_TxErrorWarningFlag: Tx Error Warning Status.

enumerator kFLEXCAN_RxErrorWarningFlag: Rx Error Warning Status.

enumerator kFLEXCAN_StuffingError: Stuffing Error.

enumerator kFLEXCAN_FormError: Form Error.

enumerator kFLEXCAN_CrcError: Cyclic Redundancy Check Error.

enumerator kFLEXCAN_AckError: Received no ACK on transmission.

enumerator kFLEXCAN_Bit0Error: Unable to send dominant bit.

enumerator kFLEXCAN_Bit1Error: Unable to send recessive bit.

FlexCAN Legacy Rx FIFO status flags.

The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies more Message Buffer space), Rx FIFO status flags are mapped to the corresponding Message Buffer status flags.

Values:

enumerator kFLEXCAN_RxFifoOverflowFlag: Rx FIFO overflow flag.

enumerator kFLEXCAN_RxFifoWarningFlag: Rx FIFO almost full flag.

enumerator kFLEXCAN_RxFifoFrameAvlFlag: Frames available in Rx FIFO flag.

enum _flexcan_memory_error_type

FlexCAN Memory Error Type.

Values:

enumerator kFLEXCAN_CorrectableError: The memory error is correctable which means on bit error.

enumerator kFLEXCAN_NonCorrectableError: The memory error is non-correctable which means two bit errors.

enum _flexcan_memory_access_type

FlexCAN Memory Access Type.

Values:

enumerator kFLEXCAN_MoveOutFlexCanAccess: The memory error was detected during move-out FlexCAN access.

enumerator kFLEXCAN_MoveInAccess: The memory error was detected during move-in FlexCAN access.

enumerator kFLEXCAN_TxArbitrationAccess: The memory error was detected during Tx Arbitration FlexCAN access.

enumerator kFLEXCAN_RxMatchingAccess: The memory error was detected during Rx Matching FlexCAN access.

enumerator kFLEXCAN_MoveOutHostAccess: The memory error was detected during Rx Matching Host (CPU) access.

enum _flexcan_byte_error_syndrome

FlexCAN Memory Error Byte Syndrome.

Values:

enumerator kFLEXCAN_NoError: No bit error in this byte.

enumerator kFLEXCAN_ParityBits0Error: Parity bit 0 error in this byte.

enumerator kFLEXCAN_ParityBits1Error: Parity bit 1 error in this byte.

enumerator kFLEXCAN_ParityBits2Error: Parity bit 2 error in this byte.

enumerator kFLEXCAN_ParityBits3Error: Parity bit 3 error in this byte.

enumerator kFLEXCAN_ParityBits4Error: Parity bit 4 error in this byte.

enumerator kFLEXCAN_DataBits0Error: Data bit 0 error in this byte.

enumerator kFLEXCAN_DataBits1Error: Data bit 1 error in this byte.

enumerator kFLEXCAN_DataBits2Error: Data bit 2 error in this byte.

enumerator kFLEXCAN_DataBits3Error: Data bit 3 error in this byte.

enumerator kFLEXCAN_DataBits4Error: Data bit 4 error in this byte.

enumerator kFLEXCAN_DataBits5Error: Data bit 5 error in this byte.

enumerator kFLEXCAN_DataBits6Error: Data bit 6 error in this byte.

enumerator kFLEXCAN_DataBits7Error: Data bit 7 error in this byte.

enumerator kFLEXCAN_AllZeroError: All-zeros non-correctable error in this byte.

enumerator kFLEXCAN_AllOneError: All-ones non-correctable error in this byte.

enumerator kFLEXCAN_NonCorrectableErrors: Non-correctable error in this byte.

enum _flexcan_pn_match_source

FlexCAN Pretended Networking match source selection.

Values:

enumerator kFLEXCAN_PNMatSrcID: Message match with ID filtering.

enumerator kFLEXCAN_PNMatSrcIDAndData: Message match with ID filtering and payload filtering.

enum _flexcan_pn_match_mode

FlexCAN Pretended Networking mode match type.

Values:

enumerator kFLEXCAN_PNMatModeEqual: Match upon ID/Payload contents against an exact target value.

enumerator kFLEXCAN_PNMatModeGreater: Match upon an ID/Payload value greater than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeSmaller: Match upon an ID/Payload value smaller than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeRange: Match upon an ID/Payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit

typedef enum _flexcan_frame_format flexcan_frame_format_t: FlexCAN frame format.

typedef enum _flexcan_frame_type flexcan_frame_type_t: FlexCAN frame type.

typedef enum _flexcan_clock_source flexcan_clock_source_t

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

typedef enum _flexcan_wake_up_source flexcan_wake_up_source_t: FlexCAN wake up source.

typedef enum _flexcan_endianness flexcan_endianness_t: FlexCAN payload endianness.

typedef enum _flexcan_MB_timestamp_base flexcan_MB_timestamp_base_t: FlexCAN timebase used for capturing 16-bit TIME_STAMP field of message buffer.

typedef enum _flexcan_capture_point flexcan_capture_point_t: FlexCAN capture point of 32-bit high resolution timebase during a CAN frame.

typedef enum _flexcan_rx_fifo_filter_type flexcan_rx_fifo_filter_type_t: FlexCAN Rx Fifo Filter type.

typedef enum _flexcan_mb_size flexcan_mb_size_t: FlexCAN Message Buffer Payload size.

typedef enum _flexcan_efifo_dma_per_read_length flexcan_efifo_dma_per_read_length_t: FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

typedef enum _flexcan_rx_fifo_priority flexcan_rx_fifo_priority_t

FlexCAN Enhanced/Legacy Rx FIFO priority.

typedef enum _flexcan_memory_error_type flexcan_memory_error_type_t: FlexCAN Memory Error Type.

typedef enum _flexcan_memory_access_type flexcan_memory_access_type_t: FlexCAN Memory Access Type.

typedef enum _flexcan_byte_error_syndrome flexcan_byte_error_syndrome_t: FlexCAN Memory Error Byte Syndrome.

typedef struct _flexcan_memory_error_report_status flexcan_memory_error_report_status_t

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

typedef struct _flexcan_frame flexcan_frame_t: FlexCAN message frame structure.

typedef struct _flexcan_fd_frame flexcan_fd_frame_t

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

typedef struct _flexcan_timing_config flexcan_timing_config_t: FlexCAN protocol timing characteristic configuration structure.

typedef struct _flexcan_config flexcan_config_t

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

typedef struct _flexcan_rx_mb_config flexcan_rx_mb_config_t

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

typedef enum _flexcan_pn_match_source flexcan_pn_match_source_t: FlexCAN Pretended Networking match source selection.

typedef enum _flexcan_pn_match_mode flexcan_pn_match_mode_t: FlexCAN Pretended Networking mode match type.

typedef struct _flexcan_pn_config flexcan_pn_config_t

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

typedef struct _flexcan_rx_fifo_config flexcan_rx_fifo_config_t: FlexCAN Legacy Rx FIFO configuration structure.

typedef struct _flexcan_enhanced_rx_fifo_std_id_filter flexcan_enhanced_rx_fifo_std_id_filter_t: FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter flexcan_enhanced_rx_fifo_ext_id_filter_t: FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_config flexcan_enhanced_rx_fifo_config_t: FlexCAN Enhanced Rx FIFO configuration structure.

typedef struct _flexcan_mb_transfer flexcan_mb_transfer_t: FlexCAN Message Buffer transfer.

typedef struct _flexcan_fifo_transfer flexcan_fifo_transfer_t: FlexCAN Rx FIFO transfer.

typedef struct _flexcan_handle flexcan_handle_t: FlexCAN handle structure definition.

typedef void (*flexcan_transfer_callback_t)(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)

FLEXCAN_WAIT_TIMEOUT

FLEXCAN_POLLING_TIMEOUT: Max loops to wait for polling transfer.

FLEXCAN_MODULE_TIMEOUT: Max loops to wait for FlexCAN register access complete.

DLC_LENGTH_DECODE(dlc): FlexCAN frame length helper macro.

FLEXCAN_ID_STD(id)

FlexCAN Frame ID helper macro.

Standard Frame ID helper macro.

FLEXCAN_ID_EXT(id): Extend Frame ID helper macro.

FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)

FlexCAN Rx Message Buffer Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide): Extend Rx Message Buffer Mask helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)

FlexCAN Legacy Rx FIFO Mask helper macro.

Standard Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide): Standard Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide): Standard Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id): Standard Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id): Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id): Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id): Standard Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide): Extend Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide): Extend Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide): Extend Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id): Extend Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id): Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id): Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id): Extend Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide)

FlexCAN Rx FIFO Filter helper macro.

Standard Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide): Standard Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide): Standard Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id): Standard Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id): Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id): Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id): Standard Rx FIFO Filter helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide): Extend Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide): Extend Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide): Extend Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id): Extend Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id): Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id): Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id): Extend Rx FIFO Filter helper macro Type C lower part helper macro.

ENHANCED_RX_FIFO_FSCH(x): FlexCAN Enhanced Rx FIFO Filter and Mask helper macro.

RTR_STD_HIGH(x)

RTR_STD_LOW(x)

RTR_EXT(x)

ID_STD_LOW(id)

ID_STD_HIGH(id)

ID_EXT(id)

FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask): Standard ID filter element with filter + mask scheme.

FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask): Standard ID filter element with filter range.

FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2): Standard ID filter element with two filters without masks.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr): Extended ID filter element with filter + mask scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask): Extended ID filter element with filter + mask scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr): Extended ID filter element with range scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask): Extended ID filter element with range scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2): Extended ID filter element with two filters without masks low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1): Extended ID filter element with two filters without masks high word.

FLEXCAN_PN_STD_MASK(id, rtr)

FlexCAN Pretended Networking ID Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_PN_EXT_MASK(id, rtr): Extend Rx Message Buffer Mask helper macro.

FLEXCAN_PN_INT_MASK(x): FlexCAN interrupt/status flag helper macro.

FLEXCAN_PN_INT_UNMASK(x)

FLEXCAN_PN_STATUS_MASK(x)

FLEXCAN_PN_STATUS_UNMASK(x)

FLEXCAN_EFIFO_INT_MASK(x)

FLEXCAN_EFIFO_INT_UNMASK(x)

FLEXCAN_EFIFO_STATUS_MASK(x)

FLEXCAN_EFIFO_STATUS_UNMASK(x)

FLEXCAN_MECR_INT_MASK(x)

FLEXCAN_MECR_INT_UNMASK(x)

FLEXCAN_MECR_STATUS_MASK(x)

FLEXCAN_MECR_STATUS_UNMASK(x)

FLEXCAN_ERROR_AND_STATUS_INT_FLAG

FLEXCAN_PNWAKE_UP_FLAG

FLEXCAN_WAKE_UP_FLAG

FLEXCAN_MEMORY_ERROR_INT_FLAG

FLEXCAN_ENHANCED_RX_FIFO_INT_FLAG: FlexCAN Enhanced Rx FIFO base address helper macro.

E_RX_FIFO(base)

FLEXCAN_CALLBACK(x)

FlexCAN transfer callback function.

The FlexCAN transfer callback returns a value from the underlying layer. If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of Message Buffer that generate transfer event. If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be Ignored.

struct _flexcan_memory_error_report_status

#include <fsl_flexcan.h>

FlexCAN memory error register status structure.

Public Members

flexcan_memory_error_type_t errorType: The type of memory error that giving rise to the report.

flexcan_memory_access_type_t accessType: The type of memory access that giving rise to the memory error.

uint16_t accessAddress: The address where memory error detected.

uint32_t errorData: The raw data word read from memory with error.

struct _flexcan_frame: #include <fsl_flexcan.h>

FlexCAN message frame structure.

struct _flexcan_fd_frame

#include <fsl_flexcan.h>

CAN FD message frame structure.

Public Members

uint32_t idhit: Note

ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is correct. CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive mode).

uint32_t hrtimestamp: Note

HR timestamp offset is changed dynamically according to data length code (DLC). External 32-bit on-chip timer high-resolution timestamp.

struct _flexcan_timing_config

#include <fsl_flexcan.h>

FlexCAN protocol timing characteristic configuration structure.

Public Members

uint32_t preDivider: Classic CAN or CAN FD nominal phase bit rate prescaler.

uint32_t rJumpwidth: Classic CAN or CAN FD nominal phase Re-sync Jump Width.

uint32_t phaseSeg1: Classic CAN or CAN FD nominal phase Segment 1.

uint32_t phaseSeg2: Classic CAN or CAN FD nominal phase Segment 2.

uint32_t propSeg: Classic CAN or CAN FD nominal phase Propagation Segment.

uint32_t fpreDivider: CAN FD data phase bit rate prescaler.

uint32_t frJumpwidth: CAN FD data phase Re-sync Jump Width.

uint32_t fphaseSeg1: CAN FD data phase Phase Segment 1.

uint32_t fphaseSeg2: CAN FD data phase Phase Segment 2.

uint32_t fpropSeg: CAN FD data phase Propagation Segment.

struct _flexcan_config

#include <fsl_flexcan.h>

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

Public Members

flexcan_clock_source_t clkSrc: Clock source for FlexCAN Protocol Engine.

flexcan_wake_up_source_t wakeupSrc: Wake up source selection.

uint8_t maxMbNum: The maximum number of Message Buffers used by user.

bool enableLoopBack: Enable or Disable Loop Back Self Test Mode.

bool enableTimerSync: Enable or Disable Timer Synchronization.

bool enableIndividMask: Enable or Disable Rx Individual Mask and Queue feature.

bool disableSelfReception: Enable or Disable Self Reflection.

bool enableListenOnlyMode: Enable or Disable Listen Only Mode.

bool enableDoze: Enable or Disable Doze Mode.

bool enablePretendedeNetworking: Enable or Disable the Pretended Networking mode.

bool enableMemoryErrorControl: Enable or Disable the memory errors detection and correction mechanism.

bool enableNonCorrectableErrorEnterFreeze: Enable or Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode.

bool enableTransceiverDelayMeasure: Enable or Disable the transceiver delay measurement, when it is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset.

bool enableRemoteRequestFrameStored: true: Store Remote Request Frame in the same fashion of data frame. false: Generate an automatic Remote Response Frame.

flexcan_endianness_t payloadEndianness: Selects the byte order for the payload of transmit and receive frames, see flexcan_endianness_t.

bool enableExternalTimeTick: true: External time tick clocks the free-running timer. false: FlexCAN bit clock clocks the free-running timer.

flexcan_MB_timestamp_base_t captureTimeBase: Timebase of message buffer 16-bit TIME_STAMP field.

flexcan_capture_point_t capturePoint: Point in time when 32-bit timebase is captured during CAN frame.

struct _flexcan_rx_mb_config

#include <fsl_flexcan.h>

FlexCAN Receive Message Buffer configuration structure.

Public Members

uint32_t id: CAN Message Buffer Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

flexcan_frame_format_t format: CAN Frame Identifier format(Standard of Extend).

flexcan_frame_type_t type: CAN Frame Type(Data or Remote for classical CAN only).

struct _flexcan_pn_config

#include <fsl_flexcan.h>

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

Public Members

bool enableTimeout: Enable or Disable timeout event trigger wakeup.

uint16_t timeoutValue: The timeout value that generates a wakeup event, the counter timer is incremented based on 64 times the CAN Bit Time unit.

bool enableMatch: Enable or Disable match event trigger wakeup.

flexcan_pn_match_source_t matchSrc: Selects the match source (ID and/or data match) to trigger wakeup.

uint8_t matchNum: The number of times a given message must match the predefined ID and/or data before generating a wakeup event, range in 0x1 ~ 0xFF.

flexcan_pn_match_mode_t idMatchMode: The ID match type.

flexcan_pn_match_mode_t dataMatchMode: The data match type.

uint32_t idLower: The ID target values 1 which used either for ID match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in ID match “range detection”.

uint32_t idUpper

The ID target values 2 which used only as the upper limit value in ID match “range

detection” or used to store the ID mask in “equal to”.

uint8_t lengthLower

The lower limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

uint8_t lengthUpper

The upper limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

struct _flexcan_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Legacy Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable: Pointer to the FlexCAN Legacy Rx FIFO identifier filter table.

uint8_t idFilterNum: The FlexCAN Legacy Rx FIFO Filter elements quantity.

flexcan_rx_fifo_filter_type_t idFilterType: The FlexCAN Legacy Rx FIFO Filter type.

flexcan_rx_fifo_priority_t priority: The FlexCAN Legacy Rx FIFO receive priority.

struct _flexcan_enhanced_rx_fifo_std_id_filter

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

Public Members

uint32_t filterType: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1: CAN Frame Type(DATA or REMOTE).

uint32_t rtr2: CAN Frame Identifier(STD or EXT format).

uint32_t std2: Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_ext_id_filter

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

Public Members

uint32_t filterType: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1: CAN Frame Type(DATA or REMOTE).

uint32_t rtr2: CAN Frame Identifier(STD or EXT format).

uint32_t std2: Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_config

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable: Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member occupies 32 bit word, table size should be equal to idFilterNum. There are two types of Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table members), the extended-ID filter element needs to be placed in front of the table.

uint8_t idFilterPairNum: idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two standard ID filter elements.

uint8_t extendIdFilterNum: The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO identifier filter table, each extended-ID filter element occupies 2 words, extendIdFilterNum need less than or equal to idFilterPairNum.

uint8_t fifoWatermark: (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO which can trigger FIFO watermark interrupt or a DMA request.

flexcan_efifo_dma_per_read_length_t dmaPerReadLength: Define the length of each read of the Enhanced RX FIFO element by the DAM, see _flexcan_fd_frame_length.

flexcan_rx_fifo_priority_t priority: The FlexCAN Enhanced Rx FIFO receive priority.

struct _flexcan_mb_transfer

#include <fsl_flexcan.h>

FlexCAN Message Buffer transfer.

Public Members

flexcan_frame_t *frame: The buffer of CAN Message to be transfer.

uint8_t mbIdx: The index of Message buffer used to transfer Message.

struct _flexcan_fifo_transfer

#include <fsl_flexcan.h>

FlexCAN Rx FIFO transfer.

Public Members

flexcan_fd_frame_t *framefd: The buffer of CAN Message to be received from Enhanced Rx FIFO.

flexcan_frame_t *frame: The buffer of CAN Message to be received from Legacy Rx FIFO.

size_t frameNum: Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO.

struct _flexcan_handle

#include <fsl_flexcan.h>

FlexCAN handle structure.

Public Members

flexcan_transfer_callback_t callback: Callback function.

void *userData: FlexCAN callback function parameter.

flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]: The buffer for received CAN data from Message Buffers.

flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]: The buffer for received CAN FD data from Message Buffers.

flexcan_frame_t *volatile rxFifoFrameBuf: The buffer for received CAN data from Legacy Rx FIFO.

flexcan_fd_frame_t *volatile rxFifoFDFrameBuf: The buffer for received CAN FD data from Ehanced Rx FIFO.

size_t rxFifoFrameNum: The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO.

size_t rxFifoTransferTotalNum: Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO.

volatile uint8_t mbState[CAN_WORD1_COUNT]: Message Buffer transfer state.

volatile uint8_t rxFifoState: Rx FIFO transfer state.

volatile uint32_t timestamp[CAN_WORD1_COUNT]: Mailbox transfer timestamp.

struct byteStatus

Public Members

bool byteIsRead: The byte n (0~3) was read or not. The type of error and which bit in byte (n) is affected by the error.

struct __unnamed18__

Public Members

uint32_t timestamp: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length: CAN frame data length in bytes (Range: 0~8).

uint32_t type: CAN Frame Type(DATA or REMOTE).

uint32_t format: CAN Frame Identifier(STD or EXT format).

uint32_t __pad0__: Reserved.

uint32_t idhit: CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode).

struct __unnamed20__

Public Members

uint32_t id: CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__: Reserved.

union __unnamed22__

Public Members

struct _flexcan_frame

struct _flexcan_frame

struct __unnamed24__

Public Members

uint32_t dataWord0: CAN Frame payload word0.

uint32_t dataWord1: CAN Frame payload word1.

struct __unnamed26__

Public Members

uint8_t dataByte3: CAN Frame payload byte3.

uint8_t dataByte2: CAN Frame payload byte2.

uint8_t dataByte1: CAN Frame payload byte1.

uint8_t dataByte0: CAN Frame payload byte0.

uint8_t dataByte7: CAN Frame payload byte7.

uint8_t dataByte6: CAN Frame payload byte6.

uint8_t dataByte5: CAN Frame payload byte5.

uint8_t dataByte4: CAN Frame payload byte4.

struct __unnamed28__

Public Members

uint32_t timestamp: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t type: CAN Frame Type(DATA only).

uint32_t format: CAN Frame Identifier(STD or EXT format).

uint32_t srr: Substitute Remote request.

uint32_t esi: Error State Indicator.

uint32_t brs: Bit Rate Switch.

uint32_t edl: Extended Data Length.

struct __unnamed30__

Public Members

uint32_t id: CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__: Reserved.

union __unnamed32__

Public Members

struct _flexcan_fd_frame

struct _flexcan_fd_frame

struct __unnamed34__

Public Members

uint32_t dataWord[16]: CAN FD Frame payload, 16 double word maximum.

struct __unnamed36__

Public Members

uint8_t dataByte3: CAN Frame payload byte3.

uint8_t dataByte2: CAN Frame payload byte2.

uint8_t dataByte1: CAN Frame payload byte1.

uint8_t dataByte0: CAN Frame payload byte0.

uint8_t dataByte7: CAN Frame payload byte7.

uint8_t dataByte6: CAN Frame payload byte6.

uint8_t dataByte5: CAN Frame payload byte5.

uint8_t dataByte4: CAN Frame payload byte4.

union __unnamed38__

Public Members

struct _flexcan_config

struct _flexcan_config

struct __unnamed40__

Public Members

uint32_t baudRate: FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t baudRateFD: FlexCAN FD bit rate in bps, for CANFD data phase.

struct __unnamed42__

Public Members

uint32_t bitRate: FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t bitRateFD: FlexCAN FD bit rate in bps, for CANFD data phase.

union __unnamed44__

Public Members

struct _flexcan_pn_config

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

struct _flexcan_pn_config

struct __unnamed48__

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

Public Members

uint32_t lowerWord0: CAN Frame payload word0.

uint32_t lowerWord1: CAN Frame payload word1.

struct __unnamed50__

Public Members

uint8_t lowerByte3: CAN Frame payload byte3.

uint8_t lowerByte2: CAN Frame payload byte2.

uint8_t lowerByte1: CAN Frame payload byte1.

uint8_t lowerByte0: CAN Frame payload byte0.

uint8_t lowerByte7: CAN Frame payload byte7.

uint8_t lowerByte6: CAN Frame payload byte6.

uint8_t lowerByte5: CAN Frame payload byte5.

uint8_t lowerByte4: CAN Frame payload byte4.

union __unnamed46__

Public Members

struct _flexcan_pn_config

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

struct _flexcan_pn_config

struct __unnamed52__

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

Public Members

uint32_t upperWord0: CAN Frame payload word0.

uint32_t upperWord1: CAN Frame payload word1.

struct __unnamed54__

Public Members

uint8_t upperByte3: CAN Frame payload byte3.

uint8_t upperByte2: CAN Frame payload byte2.

uint8_t upperByte1: CAN Frame payload byte1.

uint8_t upperByte0: CAN Frame payload byte0.

uint8_t upperByte7: CAN Frame payload byte7.

uint8_t upperByte6: CAN Frame payload byte6.

uint8_t upperByte5: CAN Frame payload byte5.

uint8_t upperByte4: CAN Frame payload byte4.

FlexCAN eDMA Driver#

void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_edma_transfer_callback_t callback, void *userData, edma_handle_t *rxFifoEdmaHandle)

Initializes the FlexCAN handle, which is used in transactional functions.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxFifoEdmaHandle – User-requested DMA handle for Rx FIFO DMA transfer.

void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, flexcan_fifo_transfer_t *pFifoXfer, edma_transfer_config_t *pEdmaConfig)

Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.

This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.

Parameters:

base – FlexCAN peripheral base address.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.
pEdmaConfig – The user configuration structure of type edma_transfer_t.

status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, flexcan_edma_handle_t *handle, edma_transfer_config_t *pEdmaConfig)

Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.

This function to Update edma transfer confiugration and Start eDMA transfer

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pEdmaConfig – The user configuration structure of type edma_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN Message from the Legacy Rx FIFO using eDMA.

This function receives the CAN Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)

Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.

status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)

Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.

This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

FSL_FLEXCAN_EDMA_DRIVER_VERSION: FlexCAN EDMA driver version.

typedef struct _flexcan_edma_handle flexcan_edma_handle_t

typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData): FlexCAN transfer callback function.

struct _flexcan_edma_handle

#include <fsl_flexcan_edma.h>

FlexCAN eDMA handle.

Public Members

flexcan_edma_transfer_callback_t callback: Callback function.

void *userData: FlexCAN callback function parameter.

edma_handle_t *rxFifoEdmaHandle: The EDMA handler for Rx FIFO.

volatile uint8_t rxFifoState: Rx FIFO transfer state.

size_t frameNum: The number of messages that need to be received.

flexcan_fd_frame_t *framefd: Point to the buffer of CAN Message to be received from Enhanced Rx FIFO.

FlexIO: FlexIO Driver#

FlexIO Driver#

void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)

Gets the default configuration to configure the FlexIO module. The configuration can used directly to call the FLEXIO_Configure().

Example:

flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);

Parameters:

userConfig – pointer to flexio_config_t structure

void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)

Configures the FlexIO with a FlexIO configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().

Example

flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);

Parameters:

base – FlexIO peripheral base address
userConfig – pointer to flexio_config_t structure

void FLEXIO_Deinit(FLEXIO_Type *base)

Gates the FlexIO clock. Call this API to stop the FlexIO clock.

Note

After calling this API, call the FLEXO_Init to use the FlexIO module.

Parameters:

base – FlexIO peripheral base address

uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)

Get instance number for FLEXIO module.

Parameters:

base – FLEXIO peripheral base address.

void FLEXIO_Reset(FLEXIO_Type *base)

Resets the FlexIO module.

Parameters:

base – FlexIO peripheral base address

static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)

Enables the FlexIO module operation.

Parameters:

base – FlexIO peripheral base address
enable – true to enable, false to disable.

static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)

Reads the input data on each of the FlexIO pins.

Parameters:

base – FlexIO peripheral base address

Returns:

FlexIO pin input data

static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)

Gets the current state pointer for state mode use.

Parameters:

base – FlexIO peripheral base address

Returns:

current State pointer

void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)

Configures the shifter with the shifter configuration. The configuration structure covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper mode, select which timer controls the shifter to shift, whether to generate start bit/stop bit, and the polarity of start bit and stop bit.

Example

flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);

Parameters:

base – FlexIO peripheral base address
index – Shifter index
shifterConfig – Pointer to flexio_shifter_config_t structure

void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)

Configures the timer with the timer configuration. The configuration structure covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper mode, select trigger source for timer and the timer pin output and the timing for timer.

Example

flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);

Parameters:

base – FlexIO peripheral base address
index – Timer index
timerConfig – Pointer to the flexio_timer_config_t structure

static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)

This function set the value of the prescaler on flexio channels.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.
index – Timer index
clocksource – Set clock value

static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the shifter error interrupt. The interrupt won’t generate when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)

Disables the timer status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)

Gets the shifter status flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Shifter status flags

static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter status flags.

Note

For clearing multiple shifter status flags, for example, two shifter status flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)

Gets the shifter error flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Shifter error flags

static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)

Clears the shifter error flags.

Note

For clearing multiple shifter error flags, for example, two shifter error flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)

Gets the timer status flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Timer status flags

static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)

Clears the timer status flags.

Note

For clearing multiple timer status flags, for example, two timer status flags, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)

Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set.

Note

For multiple shifter status DMA enables, for example, calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
enable – True to enable, false to disable.

uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)

Gets the shifter buffer address for the DMA transfer usage.

Parameters:

base – FlexIO peripheral base address
type – Shifter type of flexio_shifter_buffer_type_t
index – Shifter index

Returns:

Corresponding shifter buffer index

status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)

Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.
handle – Pointer to the handler for FlexIO simulated peripheral.
isr – FlexIO simulated peripheral interrupt handler.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_UnregisterHandleIRQ(void *base)

Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 0.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)

Sets the output level of the multiple FLEXIO pins to the logic 1.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple FLEXIO pins.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the FLEXIO pins to the logic 1 or 0.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.
output – FLEXIO pin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)

Enables the FLEXIO output pin function.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)

Reads the current input value of the FLEXIO pin.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

Return values:

FLEXIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.

static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)

Gets the FLEXIO input pin status.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

Return values:

FLEXIO – port input status

0: corresponding pin input capture no status.
1: corresponding pin input capture rising or falling edge.

static inline void FLEXIO_SetPinLevel(FLEXIO_Type *base, uint8_t pin, bool level)

Sets the FLEXIO output pin level.

Parameters:

base – FlexIO peripheral base address
pin – FlexIO pin number.
level – FlexIO output pin level to set, can be either 0 or 1.

static inline bool FLEXIO_GetPinOverride(const FLEXIO_Type *const base, uint8_t pin)

Gets the enabled status of a FLEXIO output pin.

Parameters:

base – FlexIO peripheral base address
pin – FlexIO pin number.

Return values:

FlexIO – port enabled status

0: corresponding output pin is in disabled state.
1: corresponding output pin is in enabled state.

static inline void FLEXIO_ConfigPinOverride(FLEXIO_Type *base, uint8_t pin, bool enabled)

Enables or disables a FLEXIO output pin.

Parameters:

base – FlexIO peripheral base address
pin – Flexio pin number.
enabled – Enable or disable the FlexIO pin.

static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)

Clears the multiple FLEXIO input pins status.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

FSL_FLEXIO_DRIVER_VERSION: FlexIO driver version.

enum _flexio_timer_trigger_polarity

Define time of timer trigger polarity.

Values:

enumerator kFLEXIO_TimerTriggerPolarityActiveHigh: Active high.

enumerator kFLEXIO_TimerTriggerPolarityActiveLow: Active low.

enum _flexio_timer_trigger_source

Define type of timer trigger source.

Values:

enumerator kFLEXIO_TimerTriggerSourceExternal: External trigger selected.

enumerator kFLEXIO_TimerTriggerSourceInternal: Internal trigger selected.

enum _flexio_pin_config

Define type of timer/shifter pin configuration.

Values:

enumerator kFLEXIO_PinConfigOutputDisabled: Pin output disabled.

enumerator kFLEXIO_PinConfigOpenDrainOrBidirection: Pin open drain or bidirectional output enable.

enumerator kFLEXIO_PinConfigBidirectionOutputData: Pin bidirectional output data.

enumerator kFLEXIO_PinConfigOutput: Pin output.

enum _flexio_pin_polarity

Definition of pin polarity.

Values:

enumerator kFLEXIO_PinActiveHigh: Active high.

enumerator kFLEXIO_PinActiveLow: Active low.

enum _flexio_timer_mode

Define type of timer work mode.

Values:

enumerator kFLEXIO_TimerModeDisabled: Timer Disabled.

enumerator kFLEXIO_TimerModeDual8BitBaudBit: Dual 8-bit counters baud/bit mode.

enumerator kFLEXIO_TimerModeDual8BitPWM: Dual 8-bit counters PWM mode.

enumerator kFLEXIO_TimerModeSingle16Bit: Single 16-bit counter mode.

enumerator kFLEXIO_TimerModeDual8BitPWMLow: Dual 8-bit counters PWM Low mode.

enum _flexio_timer_output

Define type of timer initial output or timer reset condition.

Values:

enumerator kFLEXIO_TimerOutputOneNotAffectedByReset: Logic one when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputZeroNotAffectedByReset: Logic zero when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputOneAffectedByReset: Logic one when enabled and on timer reset.

enumerator kFLEXIO_TimerOutputZeroAffectedByReset: Logic zero when enabled and on timer reset.

enum _flexio_timer_decrement_source

Define type of timer decrement.

Values:

enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput: Decrement counter on FlexIO clock, Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput: Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnPinInputShiftPinInput: Decrement counter on Pin input (both edges), Shift clock equals Pin input.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput: Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

enum _flexio_timer_reset_condition

Define type of timer reset condition.

Values:

enumerator kFLEXIO_TimerResetNever: Timer never reset.

enumerator kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput: Timer reset on Timer Pin equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput: Timer reset on Timer Trigger equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerPinRisingEdge: Timer reset on Timer Pin rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerRisingEdge: Timer reset on Trigger rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerBothEdge: Timer reset on Trigger rising or falling edge.

enum _flexio_timer_disable_condition

Define type of timer disable condition.

Values:

enumerator kFLEXIO_TimerDisableNever: Timer never disabled.

enumerator kFLEXIO_TimerDisableOnPreTimerDisable: Timer disabled on Timer N-1 disable.

enumerator kFLEXIO_TimerDisableOnTimerCompare: Timer disabled on Timer compare.

enumerator kFLEXIO_TimerDisableOnTimerCompareTriggerLow: Timer disabled on Timer compare and Trigger Low.

enumerator kFLEXIO_TimerDisableOnPinBothEdge: Timer disabled on Pin rising or falling edge.

enumerator kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh: Timer disabled on Pin rising or falling edge provided Trigger is high.

enumerator kFLEXIO_TimerDisableOnTriggerFallingEdge: Timer disabled on Trigger falling edge.

enum _flexio_timer_enable_condition

Define type of timer enable condition.

Values:

enumerator kFLEXIO_TimerEnabledAlways: Timer always enabled.

enumerator kFLEXIO_TimerEnableOnPrevTimerEnable: Timer enabled on Timer N-1 enable.

enumerator kFLEXIO_TimerEnableOnTriggerHigh: Timer enabled on Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerHighPinHigh: Timer enabled on Trigger high and Pin high.

enumerator kFLEXIO_TimerEnableOnPinRisingEdge: Timer enabled on Pin rising edge.

enumerator kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh: Timer enabled on Pin rising edge and Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerRisingEdge: Timer enabled on Trigger rising edge.

enumerator kFLEXIO_TimerEnableOnTriggerBothEdge: Timer enabled on Trigger rising or falling edge.

enum _flexio_timer_stop_bit_condition

Define type of timer stop bit generate condition.

Values:

enumerator kFLEXIO_TimerStopBitDisabled: Stop bit disabled.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompare: Stop bit is enabled on timer compare.

enumerator kFLEXIO_TimerStopBitEnableOnTimerDisable: Stop bit is enabled on timer disable.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompareDisable: Stop bit is enabled on timer compare and timer disable.

enum _flexio_timer_start_bit_condition

Define type of timer start bit generate condition.

Values:

enumerator kFLEXIO_TimerStartBitDisabled: Start bit disabled.

enumerator kFLEXIO_TimerStartBitEnabled: Start bit enabled.

enum _flexio_timer_output_state

FlexIO as PWM channel output state.

Values:

enumerator kFLEXIO_PwmLow: The output state of PWM channel is low

enumerator kFLEXIO_PwmHigh: The output state of PWM channel is high

enum _flexio_shifter_timer_polarity

Define type of timer polarity for shifter control.

Values:

enumerator kFLEXIO_ShifterTimerPolarityOnPositive: Shift on positive edge of shift clock.

enumerator kFLEXIO_ShifterTimerPolarityOnNegitive: Shift on negative edge of shift clock.

enum _flexio_shifter_mode

Define type of shifter working mode.

Values:

enumerator kFLEXIO_ShifterDisabled: Shifter is disabled.

enumerator kFLEXIO_ShifterModeReceive: Receive mode.

enumerator kFLEXIO_ShifterModeTransmit: Transmit mode.

enumerator kFLEXIO_ShifterModeMatchStore: Match store mode.

enumerator kFLEXIO_ShifterModeMatchContinuous: Match continuous mode.

enumerator kFLEXIO_ShifterModeState: SHIFTBUF contents are used for storing programmable state attributes.

enumerator kFLEXIO_ShifterModeLogic: SHIFTBUF contents are used for implementing programmable logic look up table.

enum _flexio_shifter_input_source

Define type of shifter input source.

Values:

enumerator kFLEXIO_ShifterInputFromPin: Shifter input from pin.

enumerator kFLEXIO_ShifterInputFromNextShifterOutput: Shifter input from Shifter N+1.

enum _flexio_shifter_stop_bit

Define of STOP bit configuration.

Values:

enumerator kFLEXIO_ShifterStopBitDisable: Disable shifter stop bit.

enumerator kFLEXIO_ShifterStopBitLow: Set shifter stop bit to logic low level.

enumerator kFLEXIO_ShifterStopBitHigh: Set shifter stop bit to logic high level.

enum _flexio_shifter_start_bit

Define type of START bit configuration.

Values:

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable: Disable shifter start bit, transmitter loads data on enable.

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnShift: Disable shifter start bit, transmitter loads data on first shift.

enumerator kFLEXIO_ShifterStartBitLow: Set shifter start bit to logic low level.

enumerator kFLEXIO_ShifterStartBitHigh: Set shifter start bit to logic high level.

enum _flexio_shifter_buffer_type

Define FlexIO shifter buffer type.

Values:

enumerator kFLEXIO_ShifterBuffer: Shifter Buffer N Register.

enumerator kFLEXIO_ShifterBufferBitSwapped: Shifter Buffer N Bit Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferByteSwapped: Shifter Buffer N Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferBitByteSwapped: Shifter Buffer N Bit Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleByteSwapped: Shifter Buffer N Nibble Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferHalfWordSwapped: Shifter Buffer N Half Word Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleSwapped: Shifter Buffer N Nibble Swapped Register.

enum _flexio_gpio_direction

FLEXIO gpio direction definition.

Values:

enumerator kFLEXIO_DigitalInput: Set current pin as digital input

enumerator kFLEXIO_DigitalOutput: Set current pin as digital output

enum _flexio_pin_input_config

FLEXIO gpio input config.

Values:

enumerator kFLEXIO_InputInterruptDisabled: Interrupt request is disabled.

enumerator kFLEXIO_InputInterruptEnable: Interrupt request is enable.

enumerator kFLEXIO_FlagRisingEdgeEnable: Input pin flag on rising edge.

enumerator kFLEXIO_FlagFallingEdgeEnable: Input pin flag on falling edge.

typedef enum _flexio_timer_trigger_polarity flexio_timer_trigger_polarity_t: Define time of timer trigger polarity.

typedef enum _flexio_timer_trigger_source flexio_timer_trigger_source_t: Define type of timer trigger source.

typedef enum _flexio_pin_config flexio_pin_config_t: Define type of timer/shifter pin configuration.

typedef enum _flexio_pin_polarity flexio_pin_polarity_t: Definition of pin polarity.

typedef enum _flexio_timer_mode flexio_timer_mode_t: Define type of timer work mode.

typedef enum _flexio_timer_output flexio_timer_output_t: Define type of timer initial output or timer reset condition.

typedef enum _flexio_timer_decrement_source flexio_timer_decrement_source_t: Define type of timer decrement.

typedef enum _flexio_timer_reset_condition flexio_timer_reset_condition_t: Define type of timer reset condition.

typedef enum _flexio_timer_disable_condition flexio_timer_disable_condition_t: Define type of timer disable condition.

typedef enum _flexio_timer_enable_condition flexio_timer_enable_condition_t: Define type of timer enable condition.

typedef enum _flexio_timer_stop_bit_condition flexio_timer_stop_bit_condition_t: Define type of timer stop bit generate condition.

typedef enum _flexio_timer_start_bit_condition flexio_timer_start_bit_condition_t: Define type of timer start bit generate condition.

typedef enum _flexio_timer_output_state flexio_timer_output_state_t: FlexIO as PWM channel output state.

typedef enum _flexio_shifter_timer_polarity flexio_shifter_timer_polarity_t: Define type of timer polarity for shifter control.

typedef enum _flexio_shifter_mode flexio_shifter_mode_t: Define type of shifter working mode.

typedef enum _flexio_shifter_input_source flexio_shifter_input_source_t: Define type of shifter input source.

typedef enum _flexio_shifter_stop_bit flexio_shifter_stop_bit_t: Define of STOP bit configuration.

typedef enum _flexio_shifter_start_bit flexio_shifter_start_bit_t: Define type of START bit configuration.

typedef enum _flexio_shifter_buffer_type flexio_shifter_buffer_type_t: Define FlexIO shifter buffer type.

typedef struct _flexio_config_ flexio_config_t: Define FlexIO user configuration structure.

typedef struct _flexio_timer_config flexio_timer_config_t: Define FlexIO timer configuration structure.

typedef struct _flexio_shifter_config flexio_shifter_config_t: Define FlexIO shifter configuration structure.

typedef enum _flexio_gpio_direction flexio_gpio_direction_t: FLEXIO gpio direction definition.

typedef enum _flexio_pin_input_config flexio_pin_input_config_t: FLEXIO gpio input config.

typedef struct _flexio_gpio_config flexio_gpio_config_t

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

typedef void (*flexio_isr_t)(void *base, void *handle): typedef for FlexIO simulated driver interrupt handler.

FLEXIO_Type *const s_flexioBases[]: Pointers to flexio bases for each instance.

const clock_ip_name_t s_flexioClocks[]: Pointers to flexio clocks for each instance.

void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)

Configure a FLEXIO pin used by the board.

To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. Then, call the FLEXIO_SetPinConfig() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalInput,
  0U,
  kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
}
Define a digital output pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalOutput,
  0U,
  0U
}

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.
config – FLEXIO pin configuration pointer.

FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x): Calculate FlexIO timer trigger.

FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x)

FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)

struct _flexio_config_

#include <fsl_flexio.h>

Define FlexIO user configuration structure.

Public Members

bool enableFlexio: Enable/disable FlexIO module

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

struct _flexio_timer_config

#include <fsl_flexio.h>

Define FlexIO timer configuration structure.

Public Members

uint32_t triggerSelect: The internal trigger selection number using MACROs.

flexio_timer_trigger_polarity_t triggerPolarity: Trigger Polarity.

flexio_timer_trigger_source_t triggerSource: Trigger Source, internal (see ‘trgsel’) or external.

flexio_pin_config_t pinConfig: Timer Pin Configuration.

uint32_t pinSelect: Timer Pin number Select.

flexio_pin_polarity_t pinPolarity: Timer Pin Polarity.

flexio_timer_mode_t timerMode: Timer work Mode.

flexio_timer_output_t timerOutput: Configures the initial state of the Timer Output and whether it is affected by the Timer reset.

flexio_timer_decrement_source_t timerDecrement: Configures the source of the Timer decrement and the source of the Shift clock.

flexio_timer_reset_condition_t timerReset: Configures the condition that causes the timer counter (and optionally the timer output) to be reset.

flexio_timer_disable_condition_t timerDisable: Configures the condition that causes the Timer to be disabled and stop decrementing.

flexio_timer_enable_condition_t timerEnable: Configures the condition that causes the Timer to be enabled and start decrementing.

flexio_timer_stop_bit_condition_t timerStop: Timer STOP Bit generation.

flexio_timer_start_bit_condition_t timerStart: Timer STRAT Bit generation.

uint32_t timerCompare: Value for Timer Compare N Register.

struct _flexio_shifter_config

#include <fsl_flexio.h>

Define FlexIO shifter configuration structure.

Public Members

uint32_t timerSelect: Selects which Timer is used for controlling the logic/shift register and generating the Shift clock.

flexio_shifter_timer_polarity_t timerPolarity: Timer Polarity.

flexio_pin_config_t pinConfig: Shifter Pin Configuration.

uint32_t pinSelect: Shifter Pin number Select.

flexio_pin_polarity_t pinPolarity: Shifter Pin Polarity.

flexio_shifter_mode_t shifterMode: Configures the mode of the Shifter.

uint32_t parallelWidth: Configures the parallel width when using parallel mode.

flexio_shifter_input_source_t inputSource: Selects the input source for the shifter.

flexio_shifter_stop_bit_t shifterStop: Shifter STOP bit.

flexio_shifter_start_bit_t shifterStart: Shifter START bit.

struct _flexio_gpio_config

#include <fsl_flexio.h>

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

Public Members

flexio_gpio_direction_t pinDirection: FLEXIO pin direction, input or output

uint8_t outputLogic: Set a default output logic, which has no use in input

uint8_t inputConfig: Set an input config

FlexIO eDMA I2S Driver#

void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S eDMA handle.

This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the FlexIO I2S Rx eDMA handle.

This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S Tx audio format.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred. This function also sets the eDMA parameter according to format.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.

status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S transfer using DMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.

Return values:

kStatus_Success – Start a FlexIO I2S eDMA send successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_TxBusy – FlexIO I2S is busy sending data.

status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs a non-blocking FlexIO I2S receive using eDMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.

Return values:

kStatus_Success – Start a FlexIO I2S eDMA receive successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_RxBusy – FlexIO I2S is busy receiving data.

void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S transfer using eDMA.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.

void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)

Aborts a FlexIO I2S receive using eDMA.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.

status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)

Get the remaining bytes to be received.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes received.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION: FlexIO I2S EDMA driver version 2.1.9.

typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t

typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, status_t status, void *userData): FlexIO I2S eDMA transfer callback function for finish and error.

struct _flexio_i2s_edma_handle

#include <fsl_flexio_i2s_edma.h>

FlexIO I2S DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle: DMA handler for FlexIO I2S send

uint8_t bytesPerFrame: Bytes in a frame

uint8_t nbytes: eDMA minor byte transfer count initially configured.

uint32_t state: Internal state for FlexIO I2S eDMA transfer

flexio_i2s_edma_callback_t callback: Callback for users while transfer finish or error occurred

void *userData: User callback parameter

edma_tcd_t tcd[(4U) + 1U]: TCD pool for eDMA transfer.

flexio_i2s_transfer_t queue[(4U)]: Transfer queue storing queued transfer.

size_t transferSize[(4U)]: Data bytes need to transfer

volatile uint8_t queueUser: Index for user to queue transfer.

volatile uint8_t queueDriver: Index for driver to get the transfer data and size

FlexIO eDMA SPI Driver#

status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI master eDMA handle.

This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional APIs. For a specified FlexIO SPI instance, call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.

status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI master eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.

static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)

Initializes the FlexIO SPI slave eDMA handle.

This function initializes the FlexIO SPI slave eDMA handle.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer)

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, size_t *count)

Gets the number of bytes transferred so far using FlexIO SPI slave eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.

FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION: FlexIO SPI EDMA driver version.

typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t: typedef for flexio_spi_master_edma_handle_t in advance.

typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t: Slave handle is the same with master handle.

typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, status_t status, void *userData): FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, status_t status, void *userData): FlexIO SPI slave callback for finished transmit.

struct _flexio_spi_master_edma_handle

#include <fsl_flexio_spi_edma.h>

FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.

Public Members

size_t transferSize: Total bytes to be transferred.

uint8_t nbytes: eDMA minor byte transfer count initially configured.

bool txInProgress: Send transfer in progress

bool rxInProgress: Receive transfer in progress

edma_handle_t *txHandle: DMA handler for SPI send

edma_handle_t *rxHandle: DMA handler for SPI receive

flexio_spi_master_edma_transfer_callback_t callback: Callback for SPI DMA transfer

void *userData: User Data for SPI DMA callback

FlexIO eDMA UART Driver#

status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the UART handle which is used in transactional functions.

Parameters:

base – Pointer to FLEXIO_UART_Type.
handle – Pointer to flexio_uart_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxEdmaHandle – User requested DMA handle for RX DMA transfer.
txEdmaHandle – User requested DMA handle for TX DMA transfer.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent out, the send callback function is called.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – UART handle pointer.
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXIO_UART_TxBusy – Previous transfer on going.

status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is a non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_UART_RxBusy – Previous transfer on going.

void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the sent data which using eDMA.

This function aborts sent data which using eDMA.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure

void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)

Aborts the receive data which using eDMA.

This function aborts the receive data which using eDMA.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure

status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes sent out.

This function gets the number of bytes sent out.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

FSL_FLEXIO_UART_EDMA_DRIVER_VERSION: FlexIO UART EDMA driver version.

typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t

typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, status_t status, void *userData): UART transfer callback function.

struct _flexio_uart_edma_handle

#include <fsl_flexio_uart_edma.h>

UART eDMA handle.

Public Members

flexio_uart_edma_transfer_callback_t callback: Callback function.

void *userData: UART callback function parameter.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

edma_handle_t *txEdmaHandle: The eDMA TX channel used.

edma_handle_t *rxEdmaHandle: The eDMA RX channel used.

uint8_t nbytes: eDMA minor byte transfer count initially configured.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

FlexIO I2C Master Driver#

status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)

Make sure the bus isn’t already pulled down.

Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure..

Return values:

kStatus_Success –
kStatus_FLEXIO_I2C_Busy –

status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C hardware configuration.

Example

FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
masterConfig – Pointer to flexio_i2c_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Initialization successful
kStatus_InvalidArgument – The source clock exceed upper range limitation

void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)

De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master shifer and timer config, module can’t work unless the FLEXIO_I2C_MasterInit is called.

Parameters:

base – pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO module. The configuration can be used directly for calling the FLEXIO_I2C_MasterInit().

Example:

flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);

Parameters:

masterConfig – Pointer to flexio_i2c_master_config_t structure.

static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)

Enables/disables the FlexIO module operation.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
enable – Pass true to enable module, false does not have any effect.

uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)

Gets the FlexIO I2C master status flags.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure

Returns:

Status flag, use status flag to AND _flexio_i2c_master_status_flags can get the related status.

void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)

Clears the FlexIO I2C master status flags.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
- kFLEXIO_I2C_RxFullFlag
- kFLEXIO_I2C_ReceiveNakFlag

void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Enables the FlexIO i2c master interrupt requests.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source. Currently only one interrupt request source:
- kFLEXIO_I2C_TransferCompleteInterruptEnable

void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)

Disables the FlexIO I2C master interrupt requests.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source.

void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the FlexIO I2C master transfer baudrate.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
baudRate_Bps – the baud rate value in HZ
srcClock_Hz – source clock in HZ

void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)

Sends START + 7-bit address to the bus.

Note

This API should be called when the transfer configuration is ready to send a START signal and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address is put into the data register but the address transfer is not finished on the bus. Ensure that the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
address – 7-bit address.
direction – transfer direction. This parameter is one of the values in flexio_i2c_direction_t:
- kFLEXIO_I2C_Write: Transmit
- kFLEXIO_I2C_Read: Receive

void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)

Sends the stop signal on the bus.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)

Sends the repeated start signal on the bus.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)

Sends the stop signal when transfer is still on-going.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)

Configures the sent ACK/NAK for the following byte.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
enable – True to configure send ACK, false configure to send NAK.

status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)

Sets the number of bytes to be transferred from a start signal to a stop signal.

Note

Call this API before a transfer begins because the timer generates a number of clocks according to the number of bytes that need to be transferred.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
count – Number of bytes need to be transferred from a start signal to a re-start/stop signal

Return values:

kStatus_Success – Successfully configured the count.
kStatus_InvalidArgument – Input argument is invalid.

static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)

Writes one byte of data to the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
data – a byte of data.

static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)

Reads one byte of data from the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the data is ready in the register.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

Returns:

data byte read.

status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)

Sends a buffer of data in bytes.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
txBuff – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Nak – Receive NAK during writing data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
rxBuff – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to receiving NAK.

Parameters:

base – pointer to FLEXIO_I2C_Type structure.
xfer – pointer to flexio_i2c_master_transfer_t structure.

Returns:

status of status_t.

status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, void *userData)

Initializes the I2C handle which is used in transactional functions.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
callback – Pointer to user callback function.
userData – User param passed to the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/isr table out of range.

status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer)

Performs a master interrupt non-blocking transfer on the I2C bus.

Note

The API returns immediately after the transfer initiates. Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
xfer – pointer to flexio_i2c_master_transfer_t structure

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_FLEXIO_I2C_Busy – FlexIO I2C is not idle, is running another transfer.

status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)

Master interrupt handler.

Parameters:

i2cType – Pointer to FLEXIO_I2C_Type structure
i2cHandle – Pointer to flexio_i2c_master_transfer_t structure

FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION

FlexIO I2C transfer status.

Values:

enumerator kStatus_FLEXIO_I2C_Busy: I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Idle: I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Nak: NAK received during transfer.

enumerator kStatus_FLEXIO_I2C_Timeout: Timeout polling status flags.

enum _flexio_i2c_master_interrupt

Define FlexIO I2C master interrupt mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyInterruptEnable: Tx buffer empty interrupt enable.

enumerator kFLEXIO_I2C_RxFullInterruptEnable: Rx buffer full interrupt enable.

enum _flexio_i2c_master_status_flags

Define FlexIO I2C master status mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyFlag: Tx shifter empty flag.

enumerator kFLEXIO_I2C_RxFullFlag: Rx shifter full/Transfer complete flag.

enumerator kFLEXIO_I2C_ReceiveNakFlag: Receive NAK flag.

enum _flexio_i2c_direction

Direction of master transfer.

Values:

enumerator kFLEXIO_I2C_Write: Master send to slave.

enumerator kFLEXIO_I2C_Read: Master receive from slave.

typedef enum _flexio_i2c_direction flexio_i2c_direction_t: Direction of master transfer.

typedef struct _flexio_i2c_type FLEXIO_I2C_Type: Define FlexIO I2C master access structure typedef.

typedef struct _flexio_i2c_master_config flexio_i2c_master_config_t: Define FlexIO I2C master user configuration structure.

typedef struct _flexio_i2c_master_transfer flexio_i2c_master_transfer_t: Define FlexIO I2C master transfer structure.

typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t: FlexIO I2C master handle typedef.

typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, status_t status, void *userData): FlexIO I2C master transfer callback typedef.

I2C_RETRY_TIMES: Retry times for waiting flag.

struct _flexio_i2c_type

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer.

uint8_t SDAPinIndex: Pin select for I2C SDA.

uint8_t SCLPinIndex: Pin select for I2C SCL.

uint8_t shifterIndex[2]: Shifter index used in FlexIO I2C.

uint8_t timerIndex[3]: Timer index used in FlexIO I2C.

uint32_t baudrate: Master transfer baudrate, used to calculate delay time.

struct _flexio_i2c_master_config

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master user configuration structure.

Public Members

bool enableMaster: Enables the FlexIO I2C peripheral at initialization time.

bool enableInDoze: Enable/disable FlexIO operation in doze mode.

bool enableInDebug: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps: Baud rate in Bps.

struct _flexio_i2c_master_transfer

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master transfer structure.

Public Members

uint32_t flags: Transfer flag which controls the transfer, reserved for FlexIO I2C.

uint8_t slaveAddress: 7-bit slave address.

flexio_i2c_direction_t direction: Transfer direction, read or write.

uint32_t subaddress: Sub address. Transferred MSB first.

uint8_t subaddressSize: Size of sub address.

uint8_t volatile *data: Transfer buffer.

volatile size_t dataSize: Transfer size.

struct _flexio_i2c_master_handle

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master handle structure.

Public Members

flexio_i2c_master_transfer_t transfer: FlexIO I2C master transfer copy.

size_t transferSize: Total bytes to be transferred.

uint8_t state: Transfer state maintained during transfer.

flexio_i2c_master_transfer_callback_t completionCallback: Callback function called at transfer event. Callback function called at transfer event.

void *userData: Callback parameter passed to callback function.

bool needRestart: Whether master needs to send re-start signal.

FlexIO I2S Driver#

void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)

Initializes the FlexIO I2S.

This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. The configuration structure can be filled by the user, or be set with default values by FLEXIO_I2S_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault because the clock is not enabled.

Parameters:

base – FlexIO I2S base pointer
config – FlexIO I2S configure structure.

void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)

Sets the FlexIO I2S configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify some fields of the structure before calling FLEXIO_I2S_Init().

Parameters:

config – pointer to master configuration structure

void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)

De-initializes the FlexIO I2S.

Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, call the FLEXO_I2S_Init to use the FlexIO I2S module.

Parameters:

base – FlexIO I2S base pointer

static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S module operation.

Parameters:

base – Pointer to FLEXIO_I2S_Type
enable – True to enable, false dose not have any effect.

uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S status flags.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.

void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Enables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
mask – interrupt source

void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)

Disables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – pointer to FLEXIO_I2S_Type structure
mask – interrupt source

static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Tx DMA requests.

Parameters:

base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.

static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)

Enables/disables the FlexIO I2S Rx DMA requests.

Parameters:

base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S send data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s send data register address.

static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)

Gets the FlexIO I2S receive data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s receive data register address.

void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format in master mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – I2S master clock source frequency in Hz.

void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)

Configures the FlexIO I2S audio format in slave mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.

status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)

Sends data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
txData – Pointer to the data to be written.
size – Bytes to be written.

Return values:

kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)

Writes data into a data register.

Parameters:

base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
data – Data to be written.

status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)

Receives a piece of data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

base – FlexIO I2S base pointer
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
rxData – Pointer to the data to be read.
size – Bytes to be read.

Return values:

kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)

Reads a data from the data register.

Parameters:

base – FlexIO I2S base pointer

Returns:

Data read from data register.

void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.

void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)

Configures the FlexIO I2S audio format.

Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – FlexIO I2S handle pointer.
format – Pointer to audio data format structure.
srcClock_Hz – FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.

void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)

Initializes the FlexIO I2S receive handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.

status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_FLEXIO_I2S_TxBusy – Previous transmission still not finished, data not all written to TX register yet.
kStatus_InvalidArgument – The input parameter is invalid.

status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

kStatus_Success – Successfully start the data receive.
kStatus_FLEXIO_I2S_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.

void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current send.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)

Aborts the current receive.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be sent.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)

Gets the remaining bytes to be received.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes recieved.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

Returns:

count Bytes received.

void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)

Tx interrupt handler.

Parameters:

i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure

void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)

Rx interrupt handler.

Parameters:

i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure.

FSL_FLEXIO_I2S_DRIVER_VERSION: FlexIO I2S driver version 2.2.2.

FlexIO I2S transfer status.

Values:

enumerator kStatus_FLEXIO_I2S_Idle: FlexIO I2S is in idle state

enumerator kStatus_FLEXIO_I2S_TxBusy: FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_RxBusy: FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_Error: FlexIO I2S error occurred

enumerator kStatus_FLEXIO_I2S_QueueFull: FlexIO I2S transfer queue is full.

enumerator kStatus_FLEXIO_I2S_Timeout: FlexIO I2S timeout polling status flags.

enum _flexio_i2s_master_slave

Master or slave mode.

Values:

enumerator kFLEXIO_I2S_Master: Master mode

enumerator kFLEXIO_I2S_Slave: Slave mode

_flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_I2S_RxDataRegFullInterruptEnable: Receive buffer full interrupt enable.

_flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_I2S_RxDataRegFullFlag: Receive buffer full flag.

enum _flexio_i2s_sample_rate

Audio sample rate.

Values:

enumerator kFLEXIO_I2S_SampleRate8KHz: Sample rate 8000Hz

enumerator kFLEXIO_I2S_SampleRate11025Hz: Sample rate 11025Hz

enumerator kFLEXIO_I2S_SampleRate12KHz: Sample rate 12000Hz

enumerator kFLEXIO_I2S_SampleRate16KHz: Sample rate 16000Hz

enumerator kFLEXIO_I2S_SampleRate22050Hz: Sample rate 22050Hz

enumerator kFLEXIO_I2S_SampleRate24KHz: Sample rate 24000Hz

enumerator kFLEXIO_I2S_SampleRate32KHz: Sample rate 32000Hz

enumerator kFLEXIO_I2S_SampleRate44100Hz: Sample rate 44100Hz

enumerator kFLEXIO_I2S_SampleRate48KHz: Sample rate 48000Hz

enumerator kFLEXIO_I2S_SampleRate96KHz: Sample rate 96000Hz

enum _flexio_i2s_word_width

Audio word width.

Values:

enumerator kFLEXIO_I2S_WordWidth8bits: Audio data width 8 bits

enumerator kFLEXIO_I2S_WordWidth16bits: Audio data width 16 bits

enumerator kFLEXIO_I2S_WordWidth24bits: Audio data width 24 bits

enumerator kFLEXIO_I2S_WordWidth32bits: Audio data width 32 bits

typedef struct _flexio_i2s_type FLEXIO_I2S_Type: Define FlexIO I2S access structure typedef.

typedef enum _flexio_i2s_master_slave flexio_i2s_master_slave_t: Master or slave mode.

typedef struct _flexio_i2s_config flexio_i2s_config_t: FlexIO I2S configure structure.

typedef struct _flexio_i2s_format flexio_i2s_format_t: FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

typedef enum _flexio_i2s_sample_rate flexio_i2s_sample_rate_t: Audio sample rate.

typedef enum _flexio_i2s_word_width flexio_i2s_word_width_t: Audio word width.

typedef struct _flexio_i2s_transfer flexio_i2s_transfer_t: Define FlexIO I2S transfer structure.

typedef struct _flexio_i2s_handle flexio_i2s_handle_t

typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, status_t status, void *userData): FlexIO I2S xfer callback prototype.

I2S_RETRY_TIMES: Retry times for waiting flag.

FLEXIO_I2S_XFER_QUEUE_SIZE: FlexIO I2S transfer queue size, user can refine it according to use case.

struct _flexio_i2s_type

#include <fsl_flexio_i2s.h>

Define FlexIO I2S access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer

uint8_t txPinIndex: Tx data pin index in FlexIO pins

uint8_t rxPinIndex: Rx data pin index

uint8_t bclkPinIndex: Bit clock pin index

uint8_t fsPinIndex: Frame sync pin index

uint8_t txShifterIndex: Tx data shifter index

uint8_t rxShifterIndex: Rx data shifter index

uint8_t bclkTimerIndex: Bit clock timer index

uint8_t fsTimerIndex: Frame sync timer index

struct _flexio_i2s_config

#include <fsl_flexio_i2s.h>

FlexIO I2S configure structure.

Public Members

bool enableI2S: Enable FlexIO I2S

flexio_i2s_master_slave_t masterSlave: Master or slave

flexio_pin_polarity_t txPinPolarity: Tx data pin polarity, active high or low

flexio_pin_polarity_t rxPinPolarity: Rx data pin polarity

flexio_pin_polarity_t bclkPinPolarity: Bit clock pin polarity

flexio_pin_polarity_t fsPinPolarity: Frame sync pin polarity

flexio_shifter_timer_polarity_t txTimerPolarity: Tx data valid on bclk rising or falling edge

flexio_shifter_timer_polarity_t rxTimerPolarity: Rx data valid on bclk rising or falling edge

struct _flexio_i2s_format

#include <fsl_flexio_i2s.h>

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

Public Members

uint8_t bitWidth: Bit width of audio data, always 8/16/24/32 bits

uint32_t sampleRate_Hz: Sample rate of the audio data

struct _flexio_i2s_transfer

#include <fsl_flexio_i2s.h>

Define FlexIO I2S transfer structure.

Public Members

uint8_t *data: Data buffer start pointer

size_t dataSize: Bytes to be transferred.

struct _flexio_i2s_handle

#include <fsl_flexio_i2s.h>

Define FlexIO I2S handle structure.

Public Members

uint32_t state: Internal state

flexio_i2s_callback_t callback: Callback function called at transfer event

void *userData: Callback parameter passed to callback function

uint8_t bitWidth: Bit width for transfer, 8/16/24/32bits

flexio_i2s_transfer_t queue[(4U)]: Transfer queue storing queued transfer

size_t transferSize[(4U)]: Data bytes need to transfer

volatile uint8_t queueUser: Index for user to queue transfer

volatile uint8_t queueDriver: Index for driver to get the transfer data and size

FlexIO SPI Driver#

void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, and configures the FlexIO SPI with FlexIO SPI master configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_MasterGetDefaultConfig().

Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);

Note

1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
masterConfig – Pointer to the flexio_spi_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)

Resets the FlexIO SPI timer and shifter config.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)

Gets the default configuration to configure the FlexIO SPI master. The configuration can be used directly by calling the FLEXIO_SPI_MasterConfigure(). Example:

flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

masterConfig – Pointer to the flexio_spi_master_config_t structure.

void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_SlaveGetDefaultConfig().

Note

1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)

Gates the FlexIO clock.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)

Gets the default configuration to configure the FlexIO SPI slave. The configuration can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). Example:

flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)

Gets FlexIO SPI status flags.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.

Returns:

status flag; Use the status flag to AND the following flag mask and get the status.

kFLEXIO_SPI_TxEmptyFlag
kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)

Clears FlexIO SPI status flags.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – status flag The parameter can be any combination of the following values:
- kFLEXIO_SPI_TxEmptyFlag
- kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Enables the FlexIO SPI interrupt.

This function enables the FlexIO SPI interrupt.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source. The parameter can be any combination of the following values:
- kFLEXIO_SPI_RxFullInterruptEnable
- kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)

Disables the FlexIO SPI interrupt.

This function disables the FlexIO SPI interrupt.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source The parameter can be any combination of the following values:
- kFLEXIO_SPI_RxFullInterruptEnable
- kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)

Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – SPI DMA source.
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI transmit data register address for MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI transmit data register address.

static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Gets the FlexIO SPI receive data register address for the MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI receive data register address.

static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)

Enables/disables the FlexIO SPI module operation.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.
enable – True to enable, false does not have any effect.

void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)

Sets baud rate for the FlexIO SPI transfer, which is only used for the master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
baudRate_Bps – Baud Rate needed in Hz.
srcClockHz – SPI source clock frequency in Hz.

static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)

Writes one byte of data, which is sent using the MSB method.

Note

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
data – 8/16/32 bit data.

static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)

Reads 8 bit/16 bit data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

8 bit/16 bit data received.

status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, size_t size)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The data bytes to send.
size – The number of data bytes to send.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, size_t size)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The buffer to store the received bytes.
size – The number of data bytes to be received.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

base – pointer to FLEXIO_SPI_Type structure
xfer – FlexIO SPI transfer structure, see flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)

Flush tx/rx shifters.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.

status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Master handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer)

Master transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)

Aborts the master data transfer, which used IRQ.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI master IRQ handler function.

Parameters:

spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, void *userData)

Initializes the FlexIO SPI Slave handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer)

Slave transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
base – Pointer to the FLEXIO_SPI_Type structure.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle; it is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)

Aborts the slave data transfer which used IRQ, share same API with master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, size_t *count)

Gets the data transfer status which used IRQ, share same API with master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)

FlexIO SPI slave IRQ handler function.

Parameters:

spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

FSL_FLEXIO_SPI_DRIVER_VERSION: FlexIO SPI driver version.

Error codes for the FlexIO SPI driver.

Values:

enumerator kStatus_FLEXIO_SPI_Busy: FlexIO SPI is busy.

enumerator kStatus_FLEXIO_SPI_Idle: SPI is idle

enumerator kStatus_FLEXIO_SPI_Error: FlexIO SPI error.

enumerator kStatus_FLEXIO_SPI_Timeout: FlexIO SPI timeout polling status flags.

enum _flexio_spi_clock_phase

FlexIO SPI clock phase configuration.

Values:

enumerator kFLEXIO_SPI_ClockPhaseFirstEdge: First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

enumerator kFLEXIO_SPI_ClockPhaseSecondEdge: First edge on SPSCK occurs at the start of the first cycle of a data transfer.

enum _flexio_spi_shift_direction

FlexIO SPI data shifter direction options.

Values:

enumerator kFLEXIO_SPI_MsbFirst: Data transfers start with most significant bit.

enumerator kFLEXIO_SPI_LsbFirst: Data transfers start with least significant bit.

enum _flexio_spi_data_bitcount_mode

FlexIO SPI data length mode options.

Values:

enumerator kFLEXIO_SPI_8BitMode: 8-bit data transmission mode.

enumerator kFLEXIO_SPI_16BitMode: 16-bit data transmission mode.

enumerator kFLEXIO_SPI_32BitMode: 32-bit data transmission mode.

enum _flexio_spi_interrupt_enable

Define FlexIO SPI interrupt mask.

Values:

enumerator kFLEXIO_SPI_TxEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_SPI_RxFullInterruptEnable: Receive buffer full interrupt enable.

enum _flexio_spi_status_flags

Define FlexIO SPI status mask.

Values:

enumerator kFLEXIO_SPI_TxBufferEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_SPI_RxBufferFullFlag: Receive buffer full flag.

enum _flexio_spi_dma_enable

Define FlexIO SPI DMA mask.

Values:

enumerator kFLEXIO_SPI_TxDmaEnable: Tx DMA request source

enumerator kFLEXIO_SPI_RxDmaEnable: Rx DMA request source

enumerator kFLEXIO_SPI_DmaAllEnable: All DMA request source

enum _flexio_spi_transfer_flags

Define FlexIO SPI transfer flags.

Note

Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag.

Values:

enumerator kFLEXIO_SPI_8bitMsb: FlexIO SPI 8-bit MSB first

enumerator kFLEXIO_SPI_8bitLsb: FlexIO SPI 8-bit LSB first

enumerator kFLEXIO_SPI_16bitMsb: FlexIO SPI 16-bit MSB first

enumerator kFLEXIO_SPI_16bitLsb: FlexIO SPI 16-bit LSB first

enumerator kFLEXIO_SPI_32bitMsb: FlexIO SPI 32-bit MSB first

enumerator kFLEXIO_SPI_32bitLsb: FlexIO SPI 32-bit LSB first

enumerator kFLEXIO_SPI_csContinuous: Enable the CS signal continuous mode

typedef enum _flexio_spi_clock_phase flexio_spi_clock_phase_t: FlexIO SPI clock phase configuration.

typedef enum _flexio_spi_shift_direction flexio_spi_shift_direction_t: FlexIO SPI data shifter direction options.

typedef enum _flexio_spi_data_bitcount_mode flexio_spi_data_bitcount_mode_t: FlexIO SPI data length mode options.

typedef struct _flexio_spi_type FLEXIO_SPI_Type: Define FlexIO SPI access structure typedef.

typedef struct _flexio_spi_master_config flexio_spi_master_config_t: Define FlexIO SPI master configuration structure.

typedef struct _flexio_spi_slave_config flexio_spi_slave_config_t: Define FlexIO SPI slave configuration structure.

typedef struct _flexio_spi_transfer flexio_spi_transfer_t: Define FlexIO SPI transfer structure.

typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t: typedef for flexio_spi_master_handle_t in advance.

typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t: Slave handle is the same with master handle.

typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, status_t status, void *userData): FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, status_t status, void *userData): FlexIO SPI slave callback for finished transmit.

FLEXIO_SPI_DUMMYDATA: FlexIO SPI dummy transfer data, the data is sent while txData is NULL.

SPI_RETRY_TIMES: Retry times for waiting flag.

FLEXIO_SPI_XFER_DATA_FORMAT(flag): Get the transfer data format of width and bit order.

struct _flexio_spi_type

#include <fsl_flexio_spi.h>

Define FlexIO SPI access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer.

uint8_t SDOPinIndex: Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as GPIO input and disable all pull up/down in application.

uint8_t SDIPinIndex: Pin select for data input.

uint8_t SCKPinIndex: Pin select for clock.

uint8_t CSnPinIndex: Pin select for enable.

uint8_t shifterIndex[2]: Shifter index used in FlexIO SPI.

uint8_t timerIndex[2]: Timer index used in FlexIO SPI.

struct _flexio_spi_master_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI master configuration structure.

Public Members

bool enableMaster: Enable/disable FlexIO SPI master after configuration.

bool enableInDoze: Enable/disable FlexIO operation in doze mode.

bool enableInDebug: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps: Baud rate in Bps.

flexio_spi_clock_phase_t phase: Clock phase.

flexio_spi_data_bitcount_mode_t dataMode: 8bit or 16bit mode.

struct _flexio_spi_slave_config

#include <fsl_flexio_spi.h>

Define FlexIO SPI slave configuration structure.

Public Members

bool enableSlave: Enable/disable FlexIO SPI slave after configuration.

bool enableInDoze: Enable/disable FlexIO operation in doze mode.

bool enableInDebug: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_spi_clock_phase_t phase: Clock phase.

flexio_spi_data_bitcount_mode_t dataMode: 8bit or 16bit mode.

struct _flexio_spi_transfer

#include <fsl_flexio_spi.h>

Define FlexIO SPI transfer structure.

Public Members

const uint8_t *txData: Send buffer.

uint8_t *rxData: Receive buffer.

size_t dataSize: Transfer bytes.

uint8_t flags: FlexIO SPI control flag, MSB first or LSB first.

struct _flexio_spi_master_handle

#include <fsl_flexio_spi.h>

Define FlexIO SPI handle structure.

Public Members

const uint8_t *txData: Transfer buffer.

uint8_t *rxData: Receive buffer.

size_t transferSize: Total bytes to be transferred.

volatile size_t txRemainingBytes: Send data remaining in bytes.

volatile size_t rxRemainingBytes: Receive data remaining in bytes.

volatile uint32_t state: FlexIO SPI internal state.

uint8_t bytePerFrame: SPI mode, 2bytes or 1byte in a frame

flexio_spi_shift_direction_t direction: Shift direction.

flexio_spi_master_transfer_callback_t callback: FlexIO SPI callback.

void *userData: Callback parameter.

bool isCsContinuous: Is current transfer using CS continuous mode.

uint32_t timer1Cfg: TIMER1 TIMCFG regiser value backup.

FlexIO UART Driver#

status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)

Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART hardware, and configures the FlexIO UART with FlexIO UART configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_UART_GetDefaultConfig().

Example

FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
userConfig – Pointer to the flexio_uart_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Configuration success.
kStatus_FLEXIO_UART_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)

Resets the FlexIO UART shifter and timer config.

Note

After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.

Parameters:

base – Pointer to FLEXIO_UART_Type structure

void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)

Gets the default configuration to configure the FlexIO UART. The configuration can be used directly for calling the FLEXIO_UART_Init(). Example:

flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);

Parameters:

userConfig – Pointer to the flexio_uart_config_t structure.

uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)

Gets the FlexIO UART status flags.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART status flags.

void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)

Gets the FlexIO UART status flags.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
- kFLEXIO_UART_TxDataRegEmptyFlag
- kFLEXIO_UART_RxEmptyFlag
- kFLEXIO_UART_RxOverRunFlag

void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Enables the FlexIO UART interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.

void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)

Disables the FlexIO UART interrupt.

This function disables the FlexIO UART interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.

static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UARt transmit data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART transmit data register address.

static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)

Gets the FlexIO UART receive data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART receive data register address.

static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART transmit DMA. This function enables/disables the FlexIO UART Tx DMA, which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.

static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART receive DMA. This function enables/disables the FlexIO UART Rx DMA, which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.

static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)

Enables/disables the FlexIO UART module operation.

Parameters:

base – Pointer to the FLEXIO_UART_Type.
enable – True to enable, false does not have any effect.

static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
buffer – The buffer to store the received bytes.

status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, void *userData)

Initializes the UART handle.

This function initializes the FlexIO UART handle, which can be used for other FlexIO UART transactional APIs. Call this API once to get the initialized handle.

The UART driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

base – to FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

Note

When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO UART driver calls the callback function and passes the kStatus_FLEXIO_UART_TxIdle as status parameter.

Note

The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – FlexIO UART transfer structure. See flexio_uart_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_UART_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainBytes to find out how many bytes are still not sent out.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the UART driver. When new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – UART transfer structure. See flexio_uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_UART_RxBusy – Previous receive request is not finished.

void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)

FlexIO UART IRQ handler function.

This function processes the FlexIO UART transmit and receives the IRQ request.

Parameters:

uartType – Pointer to the FLEXIO_UART_Type structure.
uartHandle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)

Flush tx/rx shifters.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

FSL_FLEXIO_UART_DRIVER_VERSION: FlexIO UART driver version.

Error codes for the UART driver.

Values:

enumerator kStatus_FLEXIO_UART_TxBusy: Transmitter is busy.

enumerator kStatus_FLEXIO_UART_RxBusy: Receiver is busy.

enumerator kStatus_FLEXIO_UART_TxIdle: UART transmitter is idle.

enumerator kStatus_FLEXIO_UART_RxIdle: UART receiver is idle.

enumerator kStatus_FLEXIO_UART_ERROR: ERROR happens on UART.

enumerator kStatus_FLEXIO_UART_RxRingBufferOverrun: UART RX software ring buffer overrun.

enumerator kStatus_FLEXIO_UART_RxHardwareOverrun: UART RX receiver overrun.

enumerator kStatus_FLEXIO_UART_Timeout: UART times out.

enumerator kStatus_FLEXIO_UART_BaudrateNotSupport: Baudrate is not supported in current clock source

enum _flexio_uart_bit_count_per_char

FlexIO UART bit count per char.

Values:

enumerator kFLEXIO_UART_7BitsPerChar: 7-bit data characters

enumerator kFLEXIO_UART_8BitsPerChar: 8-bit data characters

enumerator kFLEXIO_UART_9BitsPerChar: 9-bit data characters

enum _flexio_uart_interrupt_enable

Define FlexIO UART interrupt mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_UART_RxDataRegFullInterruptEnable: Receive buffer full interrupt enable.

enum _flexio_uart_status_flags

Define FlexIO UART status mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyFlag: Transmit buffer empty flag.

enumerator kFLEXIO_UART_RxDataRegFullFlag: Receive buffer full flag.

enumerator kFLEXIO_UART_RxOverRunFlag: Receive buffer over run flag.

typedef enum _flexio_uart_bit_count_per_char flexio_uart_bit_count_per_char_t: FlexIO UART bit count per char.

typedef struct _flexio_uart_type FLEXIO_UART_Type: Define FlexIO UART access structure typedef.

typedef struct _flexio_uart_config flexio_uart_config_t: Define FlexIO UART user configuration structure.

typedef struct _flexio_uart_transfer flexio_uart_transfer_t: Define FlexIO UART transfer structure.

typedef struct _flexio_uart_handle flexio_uart_handle_t

typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, status_t status, void *userData): FlexIO UART transfer callback function.

UART_RETRY_TIMES: Retry times for waiting flag.

struct _flexio_uart_type

#include <fsl_flexio_uart.h>

Define FlexIO UART access structure typedef.

Public Members

FLEXIO_Type *flexioBase: FlexIO base pointer.

uint8_t TxPinIndex: Pin select for UART_Tx.

uint8_t RxPinIndex: Pin select for UART_Rx.

uint8_t shifterIndex[2]: Shifter index used in FlexIO UART.

uint8_t timerIndex[2]: Timer index used in FlexIO UART.

struct _flexio_uart_config

#include <fsl_flexio_uart.h>

Define FlexIO UART user configuration structure.

Public Members

bool enableUart: Enable/disable FlexIO UART TX & RX.

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps: Baud rate in Bps.

flexio_uart_bit_count_per_char_t bitCountPerChar: number of bits, 7/8/9 -bit

struct _flexio_uart_transfer

#include <fsl_flexio_uart.h>

Define FlexIO UART transfer structure.

Public Members

size_t dataSize: Transfer size

struct _flexio_uart_handle

#include <fsl_flexio_uart.h>

Define FLEXIO UART handle structure.

Public Members

const uint8_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize: Size of the remaining data to send.

uint8_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize: Size of the remaining data to receive.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

uint8_t *rxRingBuffer: Start address of the receiver ring buffer.

size_t rxRingBufferSize: Size of the ring buffer.

volatile uint16_t rxRingBufferHead: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail: Index for the user to get data from the ring buffer.

flexio_uart_transfer_callback_t callback: Callback function.

void *userData: UART callback function parameter.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

union __unnamed105__

Public Members

uint8_t *data: The buffer of data to be transfer.

uint8_t *rxData: The buffer to receive data.

const uint8_t *txData: The buffer of data to be sent.

FLEXSPI: Flexible Serial Peripheral Interface Driver#

uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)

Get the instance number for FLEXSPI.

Parameters:

base – FLEXSPI base pointer.

status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)

Check and clear IP command execution errors.

Parameters:

base – FLEXSPI base pointer.
status – interrupt status.

void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)

Initializes the FLEXSPI module and internal state.

This function enables the clock for FLEXSPI and also configures the FLEXSPI with the input configure parameters. Users should call this function before any FLEXSPI operations.

Parameters:

base – FLEXSPI peripheral base address.
config – FLEXSPI configure structure.

void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)

Gets default settings for FLEXSPI.

Parameters:

config – FLEXSPI configuration structure.

void FLEXSPI_Deinit(FLEXSPI_Type *base)

Deinitializes the FLEXSPI module.

Clears the FLEXSPI state and FLEXSPI module registers.

Parameters:

base – FLEXSPI peripheral base address.

void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)

Update FLEXSPI DLL value depending on currently flexspi root clock.

Parameters:

base – FLEXSPI peripheral base address.
config – Flash configuration parameters.
port – FLEXSPI Operation port.

void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)

Configures the connected device parameter.

This function configures the connected device relevant parameters, such as the size, command, and so on. The flash configuration value cannot have a default value. The user needs to configure it according to the connected device.

Parameters:

base – FLEXSPI peripheral base address.
config – Flash configuration parameters.
port – FLEXSPI Operation port.

void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)

Software reset for the FLEXSPI logic.

This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.

Parameters:

base – FLEXSPI peripheral base address.

static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)

Enables or disables the FLEXSPI module.

Parameters:

base – FLEXSPI peripheral base address.
enable – True means enable FLEXSPI, false means disable.

void FLEXSPI_UpdateAhbBuffersSettings(FLEXSPI_Type *base, flexspi_ahbBuffers_ctrl_t *ptrAhbBufferCtrl)

Update all AHB buffers’ settings, including buffer size, master ID.

Parameters:

base – FLEXSPI peripheral base address.
ptrAhbBufferCtrl – Pointer to structure flexspi_ahbBuffers_ctrl_t which store all AHB buffers’ settings.

static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)

Enables the FLEXSPI interrupts.

Parameters:

base – FLEXSPI peripheral base address.
mask – FLEXSPI interrupt source.

static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)

Disable the FLEXSPI interrupts.

Parameters:

base – FLEXSPI peripheral base address.
mask – FLEXSPI interrupt source.

static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)

Enables or disables FLEXSPI IP Tx FIFO DMA requests.

Parameters:

base – FLEXSPI peripheral base address.
enable – Enable flag for transmit DMA request. Pass true for enable, false for disable.

static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)

Enables or disables FLEXSPI IP Rx FIFO DMA requests.

Parameters:

base – FLEXSPI peripheral base address.
enable – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)

Gets FLEXSPI IP tx fifo address for DMA transfer.

Parameters:

base – FLEXSPI peripheral base address.

Return values:

The – tx fifo address.

static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)

Gets FLEXSPI IP rx fifo address for DMA transfer.

Parameters:

base – FLEXSPI peripheral base address.

Return values:

The – rx fifo address.

static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)

Clears the FLEXSPI IP FIFO logic.

Parameters:

base – FLEXSPI peripheral base address.
txFifo – Pass true to reset TX FIFO.
rxFifo – Pass true to reset RX FIFO.

static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)

Gets the valid data entries in the FLEXSPI FIFOs.

Parameters:

base – FLEXSPI peripheral base address.
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required.

static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)

Get the FLEXSPI interrupt status flags.

Parameters:

base – FLEXSPI peripheral base address.

Return values:

interrupt – status flag, use status flag to AND flexspi_flags_t could get the related status.

static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)

Get the FLEXSPI interrupt status flags.

Parameters:

base – FLEXSPI peripheral base address.
mask – FLEXSPI interrupt source.

static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)

Gets the trigger source of current command sequence granted by arbitrator.

Parameters:

base – FLEXSPI peripheral base address.

Return values:

trigger – source of current command sequence.

static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)

Gets the error code when IP command error detected.

Parameters:

base – FLEXSPI peripheral base address.
index – Pointer to a uint8_t type variable to receive the sequence index when error detected.

Return values:

error – code when IP command error detected.

static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)

Gets the error code when AHB command error detected.

Parameters:

base – FLEXSPI peripheral base address.
index – Pointer to a uint8_t type variable to receive the sequence index when error detected.

Return values:

error – code when AHB command error detected.

static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)

Returns whether the bus is idle.

Parameters:

base – FLEXSPI peripheral base address.

Return values:

true – Bus is idle.
false – Bus is busy.

void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource)

Update read sample clock source.

Parameters:

base – FLEXSPI peripheral base address.
clockSource – clockSource of type flexspi_read_sample_clock_t

void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)

Updates the LUT table.

Parameters:

base – FLEXSPI peripheral base address.
index – From which index start to update. It could be any index of the LUT table, which also allows user to update command content inside a command. Each command consists of up to 8 instructions and occupy 4*32-bit memory.
cmd – Command sequence array.
count – Number of sequences.

static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)

Writes data into FIFO.

Parameters:

base – FLEXSPI peripheral base address
data – The data bytes to send
fifoIndex – Destination fifo index.

static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)

Receives data from data FIFO.

Parameters:

base – FLEXSPI peripheral base address
fifoIndex – Source fifo index.

Returns:

The data in the FIFO.

status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)

Sends a buffer of data bytes using blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – FLEXSPI peripheral base address
buffer – The data bytes to send
size – The number of data bytes to send

Return values:

kStatus_Success – write success without error
kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout
kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected
kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)

Receives a buffer of data bytes using a blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – FLEXSPI peripheral base address
buffer – The data bytes to send
size – The number of data bytes to receive

Return values:

kStatus_Success – read success without error
kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout
kStatus_FLEXSPI_IpCommandSequenceError – IP command sequencen error detected
kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)

Execute command to transfer a buffer data bytes using a blocking method.

Parameters:

base – FLEXSPI peripheral base address
xfer – pointer to the transfer structure.

Return values:

kStatus_Success – command transfer success without error
kStatus_FLEXSPI_SequenceExecutionTimeout – sequence execution timeout
kStatus_FLEXSPI_IpCommandSequenceError – IP command sequence error detected
kStatus_FLEXSPI_IpCommandGrantTimeout – IP command grant timeout detected

void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, void *userData)

Initializes the FLEXSPI handle which is used in transactional functions.

Parameters:

base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure to store the transfer state.
callback – pointer to user callback function.
userData – user parameter passed to the callback function.

status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)

Performs a interrupt non-blocking transfer on the FLEXSPI bus.

Note

Calling the API returns immediately after transfer initiates. The user needs to call FLEXSPI_GetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or FLEXSPI could not read data properly.

Parameters:

base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure which stores the transfer state.
xfer – pointer to flexspi_transfer_t structure.

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_FLEXSPI_Busy – Previous transmission still not finished.

status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure which stores the transfer state

void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)

Master interrupt handler.

Parameters:

base – FLEXSPI peripheral base address.
handle – pointer to flexspi_handle_t structure.

FSL_FLEXSPI_DRIVER_VERSION: FLEXSPI driver version.

Status structure of FLEXSPI.

Values:

enumerator kStatus_FLEXSPI_Busy: FLEXSPI is busy

enumerator kStatus_FLEXSPI_SequenceExecutionTimeout: Sequence execution timeout error occurred during FLEXSPI transfer.

enumerator kStatus_FLEXSPI_IpCommandSequenceError: IP command Sequence execution timeout error occurred during FLEXSPI transfer.

enumerator kStatus_FLEXSPI_IpCommandGrantTimeout: IP command grant timeout error occurred during FLEXSPI transfer.

CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command.

Values:

enumerator kFLEXSPI_Command_STOP: Stop execution, deassert CS.

enumerator kFLEXSPI_Command_SDR: Transmit Command code to Flash, using SDR mode.

enumerator kFLEXSPI_Command_RADDR_SDR: Transmit Row Address to Flash, using SDR mode.

enumerator kFLEXSPI_Command_CADDR_SDR: Transmit Column Address to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE1_SDR: Transmit 1-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE2_SDR: Transmit 2-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE4_SDR: Transmit 4-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_MODE8_SDR: Transmit 8-bit Mode bits to Flash, using SDR mode.

enumerator kFLEXSPI_Command_WRITE_SDR: Transmit Programming Data to Flash, using SDR mode.

enumerator kFLEXSPI_Command_READ_SDR: Receive Read Data from Flash, using SDR mode.

enumerator kFLEXSPI_Command_LEARN_SDR: Receive Read Data or Preamble bit from Flash, SDR mode.

enumerator kFLEXSPI_Command_DATSZ_SDR: Transmit Read/Program Data size (byte) to Flash, SDR mode.

enumerator kFLEXSPI_Command_DUMMY_SDR: Leave data lines undriven by FlexSPI controller.

enumerator kFLEXSPI_Command_DUMMY_RWDS_SDR: Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.

enumerator kFLEXSPI_Command_DDR: Transmit Command code to Flash, using DDR mode.

enumerator kFLEXSPI_Command_RADDR_DDR: Transmit Row Address to Flash, using DDR mode.

enumerator kFLEXSPI_Command_CADDR_DDR: Transmit Column Address to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE1_DDR: Transmit 1-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE2_DDR: Transmit 2-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE4_DDR: Transmit 4-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_MODE8_DDR: Transmit 8-bit Mode bits to Flash, using DDR mode.

enumerator kFLEXSPI_Command_WRITE_DDR: Transmit Programming Data to Flash, using DDR mode.

enumerator kFLEXSPI_Command_READ_DDR: Receive Read Data from Flash, using DDR mode.

enumerator kFLEXSPI_Command_LEARN_DDR: Receive Read Data or Preamble bit from Flash, DDR mode.

enumerator kFLEXSPI_Command_DATSZ_DDR: Transmit Read/Program Data size (byte) to Flash, DDR mode.

enumerator kFLEXSPI_Command_DUMMY_DDR: Leave data lines undriven by FlexSPI controller.

enumerator kFLEXSPI_Command_DUMMY_RWDS_DDR: Leave data lines undriven by FlexSPI controller, dummy cycles decided by RWDS.

enumerator kFLEXSPI_Command_JUMP_ON_CS: Stop execution, deassert CS and save operand[7:0] as the instruction start pointer for next sequence

enum _flexspi_pad

pad definition of FLEXSPI, use to form LUT instruction.

Values:

enumerator kFLEXSPI_1PAD: Transmit command/address and transmit/receive data only through DATA0/DATA1.

enumerator kFLEXSPI_2PAD: Transmit command/address and transmit/receive data only through DATA[1:0].

enumerator kFLEXSPI_4PAD: Transmit command/address and transmit/receive data only through DATA[3:0].

enumerator kFLEXSPI_8PAD: Transmit command/address and transmit/receive data only through DATA[7:0].

enum _flexspi_flags

FLEXSPI interrupt status flags.

Values:

enumerator kFLEXSPI_SequenceExecutionTimeoutFlag: Sequence execution timeout.

enumerator kFLEXSPI_AhbBusErrorFlag: AHB Bus error flag.

enumerator kFLEXSPI_SckStoppedBecauseTxEmptyFlag: SCK is stopped during command sequence because Async TX FIFO empty.

enumerator kFLEXSPI_SckStoppedBecauseRxFullFlag: SCK is stopped during command sequence because Async RX FIFO full.

enumerator kFLEXSPI_IpTxFifoWatermarkEmptyFlag: IP TX FIFO WaterMark empty.

enumerator kFLEXSPI_IpRxFifoWatermarkAvailableFlag: IP RX FIFO WaterMark available.

enumerator kFLEXSPI_AhbCommandSequenceErrorFlag: AHB triggered Command Sequences Error.

enumerator kFLEXSPI_IpCommandSequenceErrorFlag: IP triggered Command Sequences Error.

enumerator kFLEXSPI_AhbCommandGrantTimeoutFlag: AHB triggered Command Sequences Grant Timeout.

enumerator kFLEXSPI_IpCommandGrantTimeoutFlag: IP triggered Command Sequences Grant Timeout.

enumerator kFLEXSPI_IpCommandExecutionDoneFlag: IP triggered Command Sequences Execution finished.

enumerator kFLEXSPI_AllInterruptFlags: All flags.

enum _flexspi_read_sample_clock

FLEXSPI sample clock source selection for Flash Reading.

Values:

enumerator kFLEXSPI_ReadSampleClkLoopbackInternally: Dummy Read strobe generated by FlexSPI Controller and loopback internally.

enumerator kFLEXSPI_ReadSampleClkLoopbackFromDqsPad: Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.

enumerator kFLEXSPI_ReadSampleClkLoopbackFromSckPad: SCK output clock and loopback from SCK pad.

enumerator kFLEXSPI_ReadSampleClkExternalInputFromDqsPad: Flash provided Read strobe and input from DQS pad.

enum _flexspi_cs_interval_cycle_unit

FLEXSPI interval unit for flash device select.

Values:

enumerator kFLEXSPI_CsIntervalUnit1SckCycle: Chip selection interval: CSINTERVAL * 1 serial clock cycle.

enumerator kFLEXSPI_CsIntervalUnit256SckCycle: Chip selection interval: CSINTERVAL * 256 serial clock cycle.

enum _flexspi_ahb_write_wait_unit

FLEXSPI AHB wait interval unit for writing.

Values:

enumerator kFLEXSPI_AhbWriteWaitUnit2AhbCycle: AWRWAIT unit is 2 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit8AhbCycle: AWRWAIT unit is 8 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit32AhbCycle: AWRWAIT unit is 32 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit128AhbCycle: AWRWAIT unit is 128 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit512AhbCycle: AWRWAIT unit is 512 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit2048AhbCycle: AWRWAIT unit is 2048 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit8192AhbCycle: AWRWAIT unit is 8192 ahb clock cycle.

enumerator kFLEXSPI_AhbWriteWaitUnit32768AhbCycle: AWRWAIT unit is 32768 ahb clock cycle.

enum _flexspi_ip_error_code

Error Code when IP command Error detected.

Values:

enumerator kFLEXSPI_IpCmdErrorNoError: No error.

enumerator kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd: IP command with JMP_ON_CS instruction used.

enumerator kFLEXSPI_IpCmdErrorUnknownOpCode: Unknown instruction opcode in the sequence.

enumerator kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.

enumerator kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.

enumerator kFLEXSPI_IpCmdErrorInvalidAddress: Flash access start address exceed the whole flash address range (A1/A2/B1/B2).

enumerator kFLEXSPI_IpCmdErrorSequenceExecutionTimeout: Sequence execution timeout.

enumerator kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss: Flash boundary crossed.

enum _flexspi_ahb_error_code

Error Code when AHB command Error detected.

Values:

enumerator kFLEXSPI_AhbCmdErrorNoError: No error.

enumerator kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd: AHB Write command with JMP_ON_CS instruction used in the sequence.

enumerator kFLEXSPI_AhbCmdErrorUnknownOpCode: Unknown instruction opcode in the sequence.

enumerator kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.

enumerator kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.

enumerator kFLEXSPI_AhbCmdSequenceExecutionTimeout: Sequence execution timeout.

enum _flexspi_port

FLEXSPI operation port select.

Values:

enumerator kFLEXSPI_PortA1: Access flash on A1 port.

enumerator kFLEXSPI_PortA2: Access flash on A2 port.

enumerator kFLEXSPI_PortCount

enum _flexspi_arb_command_source

Trigger source of current command sequence granted by arbitrator.

Values:

enumerator kFLEXSPI_AhbReadCommand

enumerator kFLEXSPI_AhbWriteCommand

enumerator kFLEXSPI_IpCommand

enumerator kFLEXSPI_SuspendedCommand

enum _flexspi_command_type

Command type.

Values:

enumerator kFLEXSPI_Command: FlexSPI operation: Only command, both TX and Rx buffer are ignored.

enumerator kFLEXSPI_Config: FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT.

enumerator kFLEXSPI_Read

enumerator kFLEXSPI_Write

typedef enum _flexspi_pad flexspi_pad_t: pad definition of FLEXSPI, use to form LUT instruction.

typedef enum _flexspi_flags flexspi_flags_t: FLEXSPI interrupt status flags.

typedef enum _flexspi_read_sample_clock flexspi_read_sample_clock_t: FLEXSPI sample clock source selection for Flash Reading.

typedef enum _flexspi_cs_interval_cycle_unit flexspi_cs_interval_cycle_unit_t: FLEXSPI interval unit for flash device select.

typedef enum _flexspi_ahb_write_wait_unit flexspi_ahb_write_wait_unit_t: FLEXSPI AHB wait interval unit for writing.

typedef enum _flexspi_ip_error_code flexspi_ip_error_code_t: Error Code when IP command Error detected.

typedef enum _flexspi_ahb_error_code flexspi_ahb_error_code_t: Error Code when AHB command Error detected.

typedef enum _flexspi_port flexspi_port_t: FLEXSPI operation port select.

typedef enum _flexspi_arb_command_source flexspi_arb_command_source_t: Trigger source of current command sequence granted by arbitrator.

typedef enum _flexspi_command_type flexspi_command_type_t: Command type.

typedef struct _flexspi_ahbBuffer_config flexspi_ahbBuffer_config_t

typedef struct _flexspi_ahbBuffers_ctrl flexspi_ahbBuffers_ctrl_t: Structure to control all AHB buffers.

typedef struct _flexspi_config flexspi_config_t: FLEXSPI configuration structure.

typedef struct _flexspi_device_config flexspi_device_config_t: External device configuration items.

typedef struct _flexspi_transfer flexspi_transfer_t: Transfer structure for FLEXSPI.

typedef struct _flexspi_handle flexspi_handle_t

typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, flexspi_handle_t *handle, status_t status, void *userData): FLEXSPI transfer callback function.

typedef struct _flexspi_addr_map_config flexspi_addr_map_config_t: Address mapping configuration structure.

FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT

FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1): Formula to form FLEXSPI instructions in LUT table.

struct _flexspi_ahbBuffer_config

Public Members

uint8_t priority: This priority for AHB Master Read which this AHB RX Buffer is assigned.

uint8_t masterIndex: AHB Master ID the AHB RX Buffer is assigned.

uint16_t bufferSize: AHB buffer size in byte.

bool enablePrefetch: AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows prefetch disable/enable separately for each master.

struct _flexspi_ahbBuffers_ctrl

#include <fsl_flexspi.h>

Structure to control all AHB buffers.

Public Members

flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)]: Configurations of all AHB buffers.

struct _flexspi_config

#include <fsl_flexspi.h>

FLEXSPI configuration structure.

Public Members

flexspi_read_sample_clock_t rxSampleClock: Sample Clock source selection for Flash Reading.

bool enableSckFreeRunning: Enable/disable SCK output free-running.

bool enableDoze: Enable/disable doze mode support.

bool enableHalfSpeedAccess: Enable/disable divide by 2 of the clock for half speed commands.

flexspi_read_sample_clock_t rxSampleClockPortB: Sample Clock source_b selection for Flash Reading.

bool rxSampleClockDiff: Sample Clock source or source_b selection for Flash Reading.

bool enableSameConfigForAll: Enable/disable same configuration for all connected devices when enabled, same configuration in FLASHA1CRx is applied to all.

uint16_t seqTimeoutCycle: Timeout wait cycle for command sequence execution, timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles.

uint8_t ipGrantTimeoutCycle: Timeout wait cycle for IP command grant, timeout after ipGrantTimeoutCycle*1024 AHB clock cycles.

uint8_t txWatermark: FLEXSPI IP transmit watermark value.

uint8_t rxWatermark: FLEXSPI receive watermark value.

struct _flexspi_device_config

#include <fsl_flexspi.h>

External device configuration items.

Public Members

uint32_t flexspiRootClk: FLEXSPI serial root clock.

bool isSck2Enabled: FLEXSPI use SCK2.

uint32_t flashSize: Flash size in KByte.

bool addressShift: Address shift.

flexspi_cs_interval_cycle_unit_t CSIntervalUnit: CS interval unit, 1 or 256 cycle.

uint16_t CSInterval: CS line assert interval, multiply CS interval unit to get the CS line assert interval cycles.

uint8_t CSHoldTime: CS line hold time.

uint8_t CSSetupTime: CS line setup time.

uint8_t dataValidTime: Data valid time for external device.

uint8_t columnspace: Column space size.

bool enableWordAddress: If enable word address.

uint8_t AWRSeqIndex: Sequence ID for AHB write command.

uint8_t AWRSeqNumber: Sequence number for AHB write command.

uint8_t ARDSeqIndex: Sequence ID for AHB read command.

uint8_t ARDSeqNumber: Sequence number for AHB read command.

flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit: AHB write wait unit.

uint16_t AHBWriteWaitInterval: AHB write wait interval, multiply AHB write interval unit to get the AHB write wait cycles.

bool enableWriteMask: Enable/Disable FLEXSPI drive DQS pin as write mask when writing to external device.

bool isFroClockSource: Is FRO clock source or not.

struct _flexspi_transfer

#include <fsl_flexspi.h>

Transfer structure for FLEXSPI.

Public Members

uint32_t deviceAddress: Operation device address.

flexspi_port_t port: Operation port.

flexspi_command_type_t cmdType: Execution command type.

uint8_t seqIndex: Sequence ID for command.

uint8_t SeqNumber: Sequence number for command.

uint32_t *data: Data buffer.

size_t dataSize: Data size in bytes.

struct _flexspi_handle

#include <fsl_flexspi.h>

Transfer handle structure for FLEXSPI.

Public Members

uint32_t state: Internal state for FLEXSPI transfer

uint8_t *data: Data buffer.

size_t dataSize: Remaining Data size in bytes.

size_t transferTotalSize: Total Data size in bytes.

flexspi_transfer_callback_t completionCallback: Callback for users while transfer finish or error occurred

void *userData: FLEXSPI callback function parameter.

struct _flexspi_addr_map_config

#include <fsl_flexspi.h>

Address mapping configuration structure.

Public Members

uint32_t addrStart: Remapping start address.

uint32_t addrEnd: Remapping end address.

uint32_t addrOffset: Address offset.

bool remapEnable: Enable address remapping.

struct ahbConfig

Public Members

uint8_t ahbGrantTimeoutCycle: Timeout wait cycle for AHB command grant, timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles.

uint16_t ahbBusTimeoutCycle: Timeout wait cycle for AHB read/write access, timeout after ahbBusTimeoutCycle*1024 AHB clock cycles.

uint8_t resumeWaitCycle: Wait cycle for idle state before suspended command sequence resume, timeout after ahbBusTimeoutCycle AHB clock cycles.

bool disableAhbReadResume: True: Suspended AHB read prefetch does not resume once aborted; False: Suspended AHB read prefetch resumes when AHB is IDLE.

flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)]: AHB buffer size.

bool enableClearAHBBufferOpt: Enable/disable automatically clean AHB RX Buffer and TX Buffer when FLEXSPI returns STOP mode ACK.

bool enableReadAddressOpt: Enable/disable remove AHB read burst start address alignment limitation. when enable, there is no AHB read burst start address alignment limitation.

bool enableAHBPrefetch: Enable/disable AHB read prefetch feature, when enabled, FLEXSPI will fetch more data than current AHB burst.

bool enableAHBBufferable: Enable/disable AHB bufferable write access support, when enabled, FLEXSPI return before waiting for command execution finished.

bool enableAHBCachable: Enable AHB bus cachable read access support.

FLEXSPI eDMA Driver#

void FLEXSPI_TransferCreateHandleEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle, edma_handle_t *rxDmaHandle)

Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback.

Parameters:

base – FLEXSPI peripheral base address
handle – Pointer to flexspi_edma_handle_t structure
callback – FLEXSPI callback, NULL means no callback.
userData – User callback function data.
txDmaHandle – User requested DMA handle for TX DMA transfer.
rxDmaHandle – User requested DMA handle for RX DMA transfer.

void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_edma_transfer_nsize_t nsize)

Update FLEXSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE).

I3C: I3C Driver#

FSL_I3C_DRIVER_VERSION: I3C driver version.

I3C status return codes.

Values:

enumerator kStatus_I3C_Busy: The master is already performing a transfer.

enumerator kStatus_I3C_Idle: The slave driver is idle.

enumerator kStatus_I3C_Nak: The slave device sent a NAK in response to an address.

enumerator kStatus_I3C_WriteAbort: The slave device sent a NAK in response to a write.

enumerator kStatus_I3C_Term: The master terminates slave read.

enumerator kStatus_I3C_HdrParityError: Parity error from DDR read.

enumerator kStatus_I3C_CrcError: CRC error from DDR read.

enumerator kStatus_I3C_ReadFifoError: Read from M/SRDATAB register when FIFO empty.

enumerator kStatus_I3C_WriteFifoError: Write to M/SWDATAB register when FIFO full.

enumerator kStatus_I3C_MsgError: Message SDR/DDR mismatch or read/write message in wrong state

enumerator kStatus_I3C_InvalidReq: Invalid use of request.

enumerator kStatus_I3C_Timeout: The module has stalled too long in a frame.

enumerator kStatus_I3C_SlaveCountExceed: The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

enumerator kStatus_I3C_IBIWon: The I3C slave event IBI or MR or HJ won the arbitration on a header address.

enumerator kStatus_I3C_OverrunError: Slave internal from-bus buffer/FIFO overrun.

enumerator kStatus_I3C_UnderrunError: Slave internal to-bus buffer/FIFO underrun

enumerator kStatus_I3C_UnderrunNak: Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kStatus_I3C_InvalidStart: Slave invalid start flag

enumerator kStatus_I3C_SdrParityError: SDR parity error

enumerator kStatus_I3C_S0S1Error: S0 or S1 error

enum _i3c_hdr_mode

I3C HDR modes.

Values:

enumerator kI3C_HDRModeNone

enumerator kI3C_HDRModeDDR

enumerator kI3C_HDRModeTSP

enumerator kI3C_HDRModeTSL

typedef enum _i3c_hdr_mode i3c_hdr_mode_t: I3C HDR modes.

typedef struct _i3c_device_info i3c_device_info_t: I3C device information.

I3C_RETRY_TIMES

Max loops to wait for I3C operation status complete.

This is the maximum number of loops to wait for I3C operation status complete. If set to 0, it will wait indefinitely.

I3C_MAX_DEVCNT

I3C_IBI_BUFF_SIZE

struct _i3c_device_info

#include <fsl_i3c.h>

I3C device information.

Public Members

uint8_t dynamicAddr: Device dynamic address.

uint8_t staticAddr: Static address.

uint8_t dcr: Device characteristics register information.

uint8_t bcr: Bus characteristics register information.

uint16_t vendorID: Device vendor ID(manufacture ID).

uint32_t partNumber: Device part number info

uint16_t maxReadLength: Maximum read length.

uint16_t maxWriteLength: Maximum write length.

uint8_t hdrMode: Support hdr mode, could be OR logic in i3c_hdr_mode.

I3C Common Driver#

typedef struct _i3c_config i3c_config_t

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

uint32_t I3C_GetInstance(I3C_Type *base)

Get which instance current I3C is used.

Parameters:

base – The I3C peripheral base address.

void I3C_GetDefaultConfig(i3c_config_t *config)

Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.

This function provides the following default configuration for I3C:

config->disableTimeout config->hKeep config->enableOpenDrainStop config->enableOpenDrainHigh config->baudRate_Hzconfig->baudRate_Hzconfig->baudRate_Hzconfig->masterDynamicAddress config->slowClock_Hz config->enableSlave config->vendorID config->enableRandomPart config->partNumber config->dcr config->bcr config->hdrMode config->nakAllRequest config->ignoreS0S1Error config->offline config->matchSlaveStartStop 

notranslate">

config->enableMaster                 = kI3C_MasterCapable; = false; = kI3C_MasterHighKeeperNone; = true; = true; class="o">.i2cBaud          = 400000U; class="o">.i3cPushPullBaud  = 12500000U; class="o">.i3cOpenDrainBaud = 2500000U; = 0x0AU; = 1000000U; = true; = 0x11BU; = false; = 0; = 0; = 0; = (uint8_t)kI3C_HDRModeDDR; = false; = false; = false; = false;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().

Parameters:

config – [out] User provided configuration structure for default values. Refer to i3c_config_t. 







void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)

Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration. 

Parameters:

base – The I3C peripheral base address. 
config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







struct _i3c_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C module, could both initialize master and slave functionality. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster

Enable master mode. 




bool disableTimeout

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep

High keeper mode setting. 




bool enableOpenDrainStop

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay

I3C SCL delay after Repeated START. 




uint8_t masterDynamicAddress

Main master dynamic address configuration. 




uint32_t maxWriteLength

Maximum write length. 




uint32_t maxReadLength

Maximum read length. 




bool enableSlave

Whether to enable slave. 




uint8_t staticAddr

Static address. 




uint16_t vendorID

Device vendor ID(manufacture ID). 




uint32_t partNumber

Device part number info 




uint8_t dcr

Device characteristics register information. 




uint8_t bcr

Bus characteristics register information. 




uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode. 




bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed. 







I3C Master Driver#


void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)

Provides a default configuration for the I3C master peripheral. 
This function provides the following default configuration for the I3C master peripheral: 
masterConfig->enableMaster            = kI3C_MasterOn;
masterConfig->disableTimeout          = false;
masterConfig->hKeep                   = kI3C_MasterHighKeeperNone;
masterConfig->enableOpenDrainStop     = true;
masterConfig->enableOpenDrainHigh     = true;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busType                 = kI3C_TypeI2C;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with I3C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to i3c_master_config_t. 







void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the I3C master peripheral. 
This function enables the peripheral clock and initializes the I3C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The I3C peripheral base address. 
masterConfig – User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







void I3C_MasterDeinit(I3C_Type *base)

Deinitializes the I3C master peripheral. 
This function disables the I3C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The I3C peripheral base address. 







status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)





status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)





status_t I3C_CheckForBusyBus(I3C_Type *base)





static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)

Set I3C module master mode. 

Parameters:

base – The I3C peripheral base address. 
enable – Enable master mode. 







void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral. 
This function provides the following default configuration for the I3C slave peripheral: 
slaveConfig->enableslave             = true;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t. 







void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral. 
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

base – The I3C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. 







void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral. 
This function disables the I3C slave peripheral and gates the clock.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave. 

Parameters:

base – The I3C peripheral base address. 
isEnable – Enable or disable. 







static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)

Gets the I3C master status flags. 
A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_master_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C master status flag state. 
The following status register flags can be cleared:

kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag


Attempts to clear other flags has no effect.

See also
_i3c_master_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_master_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags(). 







static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)

Gets the I3C master error status flags. 
A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_master_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C master error status flag state. 

See also
_i3c_master_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_master_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags(). 







i3c_master_state_t I3C_MasterGetState(I3C_Type *base)

Gets the I3C master state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C master state. 






static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags. 
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Attempts to clear other flags has no effect.

See also
_i3c_slave_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags(). 







static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags. 
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state. 

See also
_i3c_slave_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags(). 







i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C slave activity state, refer i3c_slave_activity_state_t. 






status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)





static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C master interrupt requests. 
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C master interrupt requests. 
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C master interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C master interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests. 
Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests. 
Only below flags can be disabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C master DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C master transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Master Transmit Data Register address. 






static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C master receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Master Receive Data Register address. 






static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Transmit Data Register address. 






static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Receive Data Register address. 






static inline void I3C_MasterSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C master FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C master FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz)

Sets the I3C bus frequency for master transactions. 
The I3C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Parameters:

base – The I3C peripheral base address. 
baudRate_Hz – Pointer to structure of requested bus frequency in Hertz. 
sourceClock_Hz – I3C functional clock frequency in Hertz. 







static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)

Returns whether the bus is idle. 
Requires the master mode to be enabled.

Parameters:

base – The I3C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







status_t I3C_MasterStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)

Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified in the call. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the a address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 







status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)

Sends a START signal and slave address on the I2C/I3C bus. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 







status_t I3C_MasterRepeatedStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)

Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified in the call. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize configuration.

Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes. 


Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 






static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)

Sends a repeated START signal and slave address on the I2C/I3C bus. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address.

Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 






status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)

Performs a polling send transfer on the I2C/I3C bus. 
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_I3C_Nak.

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. 


Return values:

kStatus_Success – Data was sent successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Nak – The slave device sent a NAK in response to an address. 
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)

Performs a polling receive transfer on the I2C/I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Term – The master terminates slave read. 
kStatus_I3C_HdrParityError – Parity error from DDR read. 
kStatus_I3C_CrcError – CRC error from DDR read. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_MasterStop(I3C_Type *base)

Sends a STOP signal on the I2C/I3C bus. 
This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

base – The I3C peripheral base address. 


Return values:

kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_InvalidReq – Invalid use of request. 







void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq)

I3C master emit request. 

Parameters:

base – The I3C peripheral base address. 
masterReq – I3C master request of type i3c_bus_request_t







static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)

I3C master emit request. 

Parameters:

base – The I3C peripheral base address. 
ibiResponse – I3C master emit IBI response of type i3c_ibi_response_t







void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)

I3C master register IBI rule. 

Parameters:

base – The I3C peripheral base address. 
ibiRule – Pointer to ibi rule description of type i3c_register_ibi_addr_t







void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)

I3C master get IBI rule. 

Parameters:

base – The I3C peripheral base address. 
ibiRule – Pointer to store the read out ibi rule description. 







i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base)

I3C master get IBI Type. 

Parameters:

base – The I3C peripheral base address. 


Return values:
i3c_ibi_type_t – Type of i3c_ibi_type_t. 






static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)

I3C master get IBI Address. 

Parameters:

base – The I3C peripheral base address. 


Return values:
The – 8-bit IBI address. 






status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint8_t *addressList, uint32_t count, i3c_master_daa_baudrate_t *daaBaudRate)

Performs a DAA in the i3c bus with specified temporary baud rate. 

Parameters:

base – The I3C peripheral base address. 
addressList – The pointer for address list which is used to do DAA. 
count – The address count in the address list. 
daaBaudRate – The temporary baud rate in DAA process, NULL for using initial setting. The initial setting is set back between the completion of the DAA and the return of this function. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. 







static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)

Performs a DAA in the i3c bus. 

Parameters:

base – The I3C peripheral base address. 
addressList – The pointer for address list which is used to do DAA. 
count – The address count in the address list. The initial setting is set back between the completion of the DAA and the return of this function. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. 







i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count)

Get device information list after DAA process is done. 

Parameters:

base – The I3C peripheral base address. 
count – [out] The pointer to store the available device count. 


Returns:
Pointer to the i3c_device_info_t array. 






void I3C_MasterClearDeviceCount(I3C_Type *base)

Clear the global device count which represents current devices number on the bus. When user resets all dynamic addresses on the bus, should call this API. 

Parameters:

base – The I3C peripheral base address. 







status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C/I3C bus. 

Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.


Parameters:

base – The I3C peripheral base address. 
transfer – Pointer to the transfer structure. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_IBIWon – The I3C slave event IBI or MR or HJ won the arbitration on a header address. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Nak – The slave device sent a NAK in response to an address. 
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write. 
kStatus_I3C_Term – The master terminates slave read. 
kStatus_I3C_HdrParityError – Parity error from DDR read. 
kStatus_I3C_CrcError – CRC error from DDR read. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty. 
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






void I3C_MasterTransferCreateHandle(I3C_Type *base, i3c_master_handle_t *handle, const i3c_master_transfer_callback_t *callback, void *userData)

Creates a new handle for the I3C master non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The I3C peripheral base address. 
handle – [out] Pointer to the I3C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C/I3C bus. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 







status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)

Terminates a non-blocking I3C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the I3C peripheral’s IRQ priority.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 







void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
intHandle – Pointer to the I3C master driver handle. 







enum _i3c_master_flags

I3C master peripheral flags. 
The following status register flags can be cleared:

kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag


All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_MasterBetweenFlag

Between messages/DAAs flag 




enumerator kI3C_MasterNackDetectFlag

NACK detected flag 




enumerator kI3C_MasterSlaveStartFlag

Slave request start flag 




enumerator kI3C_MasterControlDoneFlag

Master request complete flag 




enumerator kI3C_MasterCompleteFlag

Transfer complete flag 




enumerator kI3C_MasterRxReadyFlag

Rx data ready in Rx buffer flag 




enumerator kI3C_MasterTxReadyFlag

Tx buffer ready for Tx data flag 




enumerator kI3C_MasterArbitrationWonFlag

Header address won arbitration flag 




enumerator kI3C_MasterErrorFlag

Error occurred flag 




enumerator kI3C_MasterSlave2MasterFlag

Switch from slave to master flag 




enumerator kI3C_MasterClearFlags







enum _i3c_master_error_flags

I3C master error flags to indicate the causes. 

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_MasterErrorNackFlag

Slave NACKed the last address 




enumerator kI3C_MasterErrorWriteAbortFlag

Slave NACKed the write data 




enumerator kI3C_MasterErrorParityFlag

Parity error from DDR read 




enumerator kI3C_MasterErrorCrcFlag

CRC error from DDR read 




enumerator kI3C_MasterErrorReadFlag

Read from MRDATAB register when FIFO empty 




enumerator kI3C_MasterErrorWriteFlag

Write to MWDATAB register when FIFO full 




enumerator kI3C_MasterErrorMsgFlag

Message SDR/DDR mismatch or read/write message in wrong state 




enumerator kI3C_MasterErrorInvalidReqFlag

Invalid use of request 




enumerator kI3C_MasterErrorTimeoutFlag

The module has stalled too long in a frame 




enumerator kI3C_MasterAllErrorFlags

All error flags 






enum _i3c_master_state

I3C working master state. 
Values:


enumerator kI3C_MasterStateIdle

Bus stopped. 




enumerator kI3C_MasterStateSlvReq

Bus stopped but slave holding SDA low. 




enumerator kI3C_MasterStateMsgSdr

In SDR Message mode from using MWMSG_SDR. 




enumerator kI3C_MasterStateNormAct

In normal active SDR mode. 




enumerator kI3C_MasterStateDdr

In DDR Message mode. 




enumerator kI3C_MasterStateDaa

In ENTDAA mode. 




enumerator kI3C_MasterStateIbiAck

Waiting on IBI ACK/NACK decision. 




enumerator kI3C_MasterStateIbiRcv

Receiving IBI. 






enum _i3c_master_enable

I3C master enable configuration. 
Values:


enumerator kI3C_MasterOff

Master off. 




enumerator kI3C_MasterOn

Master on. 




enumerator kI3C_MasterCapable

Master capable. 






enum _i3c_master_hkeep

I3C high keeper configuration. 
Values:


enumerator kI3C_MasterHighKeeperNone

Use PUR to hold SCL high. 




enumerator kI3C_MasterHighKeeperWiredIn

Use pin_HK controls. 




enumerator kI3C_MasterPassiveSDA

Hi-Z for Bus Free and hold SDA. 




enumerator kI3C_MasterPassiveSDASCL

Hi-Z both for Bus Free, and can Hi-Z SDA for hold. 






enum _i3c_bus_request

Emits the requested operation when doing in pieces vs. by message. 
Values:


enumerator kI3C_RequestNone

No request. 




enumerator kI3C_RequestEmitStartAddr

Request to emit start and address on bus. 




enumerator kI3C_RequestEmitStop

Request to emit stop on bus. 




enumerator kI3C_RequestIbiAckNack

Manual IBI ACK or NACK. 




enumerator kI3C_RequestProcessDAA

Process DAA. 




enumerator kI3C_RequestForceExit

Request to force exit. 




enumerator kI3C_RequestAutoIbi

Hold in stopped state, but Auto-emit START,7E. 






enum _i3c_bus_type

Bus type with EmitStartAddr. 
Values:


enumerator kI3C_TypeI3CSdr

SDR mode of I3C. 




enumerator kI3C_TypeI2C

Standard i2c protocol. 




enumerator kI3C_TypeI3CDdr

HDR-DDR mode of I3C. 






enum _i3c_ibi_response

IBI response. 
Values:


enumerator kI3C_IbiRespAck

ACK with no mandatory byte. 




enumerator kI3C_IbiRespNack

NACK. 




enumerator kI3C_IbiRespAckMandatory

ACK with mandatory byte. 




enumerator kI3C_IbiRespManual

Reserved. 






enum _i3c_ibi_type

IBI type. 
Values:


enumerator kI3C_IbiNormal

In-band interrupt. 




enumerator kI3C_IbiHotJoin

slave hot join. 




enumerator kI3C_IbiMasterRequest

slave master ship request. 






enum _i3c_ibi_state

IBI state. 
Values:


enumerator kI3C_IbiReady

In-band interrupt ready state, ready for user to handle. 




enumerator kI3C_IbiDataBuffNeed

In-band interrupt need data buffer for data receive. 




enumerator kI3C_IbiAckNackPending

In-band interrupt Ack/Nack pending for decision. 






enum _i3c_direction

Direction of master and slave transfers. 
Values:


enumerator kI3C_Write

Master transmit. 




enumerator kI3C_Read

Master receive. 






enum _i3c_tx_trigger_level

Watermark of TX int/dma trigger level. 
Values:


enumerator kI3C_TxTriggerOnEmpty

Trigger on empty. 




enumerator kI3C_TxTriggerUntilOneQuarterOrLess

Trigger on 1/4 full or less. 




enumerator kI3C_TxTriggerUntilOneHalfOrLess

Trigger on 1/2 full or less. 




enumerator kI3C_TxTriggerUntilOneLessThanFull

Trigger on 1 less than full or less. 






enum _i3c_rx_trigger_level

Watermark of RX int/dma trigger level. 
Values:


enumerator kI3C_RxTriggerOnNotEmpty

Trigger on not empty. 




enumerator kI3C_RxTriggerUntilOneQuarterOrMore

Trigger on 1/4 full or more. 




enumerator kI3C_RxTriggerUntilOneHalfOrMore

Trigger on 1/2 full or more. 




enumerator kI3C_RxTriggerUntilThreeQuarterOrMore

Trigger on 3/4 full or more. 






enum _i3c_rx_term_ops

I3C master read termination operations. 
Values:


enumerator kI3C_RxTermDisable

Master doesn’t terminate read, used for CCC transfer. 




enumerator kI3C_RxAutoTerm

Master auto terminate read after receiving specified bytes(<=255). 




enumerator kI3C_RxTermLastByte

Master terminates read at any time after START, no length limitation. 






enum _i3c_start_scl_delay

I3C start SCL delay options. 
Values:


enumerator kI3C_NoDelay

No delay. 




enumerator kI3C_IncreaseSclHalfPeriod

Increases SCL clock period by 1/2. 




enumerator kI3C_IncreaseSclOnePeriod

Increases SCL clock period by 1. 




enumerator kI3C_IncreaseSclOneAndHalfPeriod

Increases SCL clock period by 1 1/2 






enum _i3c_master_transfer_flags

Transfer option flags. 

Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _i3c_master_transfer::flags field. 

Values:


enumerator kI3C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal. 




enumerator kI3C_TransferNoStartFlag

Don’t send a start condition, address, and sub address 




enumerator kI3C_TransferRepeatedStartFlag

Send a repeated start condition 




enumerator kI3C_TransferNoStopFlag

Don’t send a stop condition. 




enumerator kI3C_TransferWordsFlag

Transfer in words, else transfer in bytes. 




enumerator kI3C_TransferDisableRxTermFlag

Disable Rx termination. Note: It’s for I3C CCC transfer. 




enumerator kI3C_TransferRxAutoTermFlag

Set Rx auto-termination. Note: It’s adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. 




enumerator kI3C_TransferStartWithBroadcastAddr

Start transfer with 0x7E, then read/write data with device address. 






typedef enum _i3c_master_state i3c_master_state_t

I3C working master state. 




typedef enum _i3c_master_enable i3c_master_enable_t

I3C master enable configuration. 




typedef enum _i3c_master_hkeep i3c_master_hkeep_t

I3C high keeper configuration. 




typedef enum _i3c_bus_request i3c_bus_request_t

Emits the requested operation when doing in pieces vs. by message. 




typedef enum _i3c_bus_type i3c_bus_type_t

Bus type with EmitStartAddr. 




typedef enum _i3c_ibi_response i3c_ibi_response_t

IBI response. 




typedef enum _i3c_ibi_type i3c_ibi_type_t

IBI type. 




typedef enum _i3c_ibi_state i3c_ibi_state_t

IBI state. 




typedef enum _i3c_direction i3c_direction_t

Direction of master and slave transfers. 




typedef enum _i3c_tx_trigger_level i3c_tx_trigger_level_t

Watermark of TX int/dma trigger level. 




typedef enum _i3c_rx_trigger_level i3c_rx_trigger_level_t

Watermark of RX int/dma trigger level. 




typedef enum _i3c_rx_term_ops i3c_rx_term_ops_t

I3C master read termination operations. 




typedef enum _i3c_start_scl_delay i3c_start_scl_delay_t

I3C start SCL delay options. 




typedef struct _i3c_register_ibi_addr i3c_register_ibi_addr_t

Structure with setting master IBI rules and slave registry. 




typedef struct _i3c_baudrate i3c_baudrate_hz_t

Structure with I3C baudrate settings. 




typedef struct _i3c_master_daa_baudrate i3c_master_daa_baudrate_t

I3C DAA baud rate configuration. 




typedef struct _i3c_master_config i3c_master_config_t

Structure with settings to initialize the I3C master module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef struct _i3c_master_transfer i3c_master_transfer_t





typedef struct _i3c_master_handle i3c_master_handle_t





typedef struct _i3c_master_transfer_callback i3c_master_transfer_callback_t

i3c master callback functions. 




typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle)

Typedef for master interrupt handler. 




struct _i3c_register_ibi_addr


#include <fsl_i3c.h>
Structure with setting master IBI rules and slave registry. 

Public Members


uint8_t address[5]

Address array for registry. 




bool i3cFastStart

Allow the START header to run as push-pull speed if all dynamic addresses take MSB 0. 




bool ibiHasPayload

Whether the address array has mandatory IBI byte. 







struct _i3c_baudrate


#include <fsl_i3c.h>
Structure with I3C baudrate settings. 

Public Members


uint32_t i2cBaud

Desired I2C baud rate in Hertz. 




uint32_t i3cPushPullBaud

Desired I3C push-pull baud rate in Hertz. 




uint32_t i3cOpenDrainBaud

Desired I3C open-drain baud rate in Hertz. 







struct _i3c_master_daa_baudrate


#include <fsl_i3c.h>
I3C DAA baud rate configuration. 

Public Members


uint32_t sourceClock_Hz

FCLK, function clock in Hertz. 




uint32_t i3cPushPullBaud

Desired I3C push-pull baud rate in Hertz. 




uint32_t i3cOpenDrainBaud

Desired I3C open-drain baud rate in Hertz. 







struct _i3c_master_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C master module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster

Enable master mode. 




bool disableTimeout

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep

High keeper mode setting. 




bool enableOpenDrainStop

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay

I3C SCL delay after Repeated START. 







struct _i3c_master_transfer_callback


#include <fsl_i3c.h>
i3c master callback functions. 

Public Members


void (*slave2Master)(I3C_Type *base, void *userData)

Transfer complete callback 




void (*ibiCallback)(I3C_Type *base, i3c_master_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)

IBI event callback 




void (*transferComplete)(I3C_Type *base, i3c_master_handle_t *handle, status_t completionStatus, void *userData)

Transfer complete callback 







struct _i3c_master_transfer


#include <fsl_i3c.h>
Non-blocking transfer descriptor structure. 
This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. 

Public Members


uint32_t flags

Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. Set to 0 or kI3C_TransferDefaultFlag for normal transfers. 




uint8_t slaveAddress

The 7-bit slave address. 




i3c_direction_t direction

Either kI3C_Read or kI3C_Write. 




uint32_t subaddress

Sub address. Transferred MSB first. 




size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes. 




void *data

Pointer to data to transfer. 




size_t dataSize

Number of bytes to transfer. 




i3c_bus_type_t busType

bus type. 




i3c_ibi_response_t ibiResponse

ibi response during transfer. 







struct _i3c_master_handle


#include <fsl_i3c.h>
Driver handle for master non-blocking APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


uint8_t state

Transfer state machine current state. 




uint32_t remainingBytes

Remaining byte count in current state. 




i3c_rx_term_ops_t rxTermOps

Read termination operation. 




i3c_master_transfer_t transfer

Copy of the current transfer info. 




uint8_t ibiAddress

Slave address which request IBI. 




uint8_t *ibiBuff

Pointer to IBI buffer to keep ibi bytes. 




size_t ibiPayloadSize

IBI payload size. 




i3c_ibi_type_t ibiType

IBI type. 




i3c_master_transfer_callback_t callback

Callback functions pointer. 




void *userData

Application data passed to callback. 







I3C Master DMA Driver#


void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, const i3c_master_edma_callback_t *callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)

Create a new handle for the I3C master DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function. 







status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I3C bus. 
The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 







status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress. 







void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)

Terminates a non-blocking I3C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the DMA peripheral’s IRQ priority.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 







void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
i3cHandle – Pointer to the I3C master DMA driver handle. 







typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t





typedef struct _i3c_master_edma_callback i3c_master_edma_callback_t

i3c master callback functions. 




struct _i3c_master_edma_callback


#include <fsl_i3c_edma.h>
i3c master callback functions. 

Public Members


void (*slave2Master)(I3C_Type *base, void *userData)

Target asks for controller request. 




void (*ibiCallback)(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)

IBI event callback. 




void (*transferComplete)(I3C_Type *base, i3c_master_edma_handle_t *handle, status_t status, void *userData)

Transfer complete callback. 







struct _i3c_master_edma_handle


#include <fsl_i3c_edma.h>
Driver handle for master EDMA APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


I3C_Type *base

I3C base pointer. 




uint8_t state

Transfer state machine current state. 




uint32_t transferCount

Indicates progress of the transfer 




uint8_t subaddressBuffer[4]

Saving subaddress command. 




uint8_t subaddressCount

Saving command count. 




i3c_master_transfer_t transfer

Copy of the current transfer info. 




i3c_master_edma_callback_t callback

Callback function pointer. 




void *userData

Application data passed to callback. 




edma_handle_t *rxDmaHandle

Handle for receive DMA channel. 




edma_handle_t *txDmaHandle

Handle for transmit DMA channel. 




bool ibiFlag

IBIWON flag. 




uint8_t ibiAddress

Slave address which request IBI. 




uint8_t *ibiBuff

Pointer to IBI buffer to keep ibi bytes. 




size_t ibiPayloadSize

IBI payload size. 




i3c_ibi_type_t ibiType

IBI type. 




status_t result

Transfer result. 







I3C Slave Driver#


void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral. 
This function provides the following default configuration for the I3C slave peripheral: 
slaveConfig->enableslave             = true;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t. 







void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral. 
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

base – The I3C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. 







void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral. 
This function disables the I3C slave peripheral and gates the clock.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave. 

Parameters:

base – The I3C peripheral base address. 
isEnable – Enable or disable. 







static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags. 
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Attempts to clear other flags has no effect.

See also
_i3c_slave_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags(). 







static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags. 
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state. 

See also
_i3c_slave_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags(). 







i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C slave activity state, refer i3c_slave_activity_state_t. 






status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)





static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests. 
Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests. 
Only below flags can be disabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Transmit Data Register address. 






static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Receive Data Register address. 






static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






void I3C_SlaveTransferCreateHandle(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the I3C slave non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The I3C peripheral base address. 
handle – [out] Pointer to the I3C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers. 
Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of i3c_slave_transfer_event_t enumerators for the events you wish to receive. The kI3C_SlaveTransmitEvent and kI3C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI3C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI3C_SlaveAllEvents to enable all events.


Return values:

kStatus_Success – Slave transfers were successfully started. 
kStatus_I3C_Busy – Slave transfers have already been started on this handle. 







status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to i2c_slave_handle_t structure. 
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – 







void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle)

Aborts the slave non-blocking transfers. 

Note
This API could be called at any time to stop slave for handling the bus events. 


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 







void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
intHandle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 







enum _i3c_slave_flags

I3C slave peripheral flags. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_SlaveNotStopFlag

Slave status not stop flag 




enumerator kI3C_SlaveMessageFlag

Slave status message, indicating slave is listening to the bus traffic or responding 




enumerator kI3C_SlaveRequiredReadFlag

Slave status required, either is master doing SDR read from slave, or is IBI pushing out. 




enumerator kI3C_SlaveRequiredWriteFlag

Slave status request write, master is doing SDR write to slave, except slave in ENTDAA mode 




enumerator kI3C_SlaveBusDAAFlag

I3C bus is in ENTDAA mode 




enumerator kI3C_SlaveBusHDRModeFlag

I3C bus is in HDR mode 




enumerator kI3C_SlaveBusStartFlag

Start/Re-start event is seen since the bus was last cleared 




enumerator kI3C_SlaveMatchedFlag

Slave address(dynamic/static) matched since last cleared 




enumerator kI3C_SlaveBusStopFlag

Stop event is seen since the bus was last cleared 




enumerator kI3C_SlaveRxReadyFlag

Rx data ready in rx buffer flag 




enumerator kI3C_SlaveTxReadyFlag

Tx buffer ready for Tx data flag 




enumerator kI3C_SlaveDynamicAddrChangedFlag

Slave dynamic address has been assigned, re-assigned, or lost 




enumerator kI3C_SlaveReceivedCCCFlag

Slave received Common command code 




enumerator kI3C_SlaveErrorFlag

Error occurred flag 




enumerator kI3C_SlaveHDRCommandMatchFlag

High data rate command match 




enumerator kI3C_SlaveCCCHandledFlag

Slave received Common command code is handled by I3C module 




enumerator kI3C_SlaveEventSentFlag

Slave IBI/P2P/MR/HJ event has been sent 




enumerator kI3C_SlaveIbiDisableFlag

Slave in band interrupt is disabled. 




enumerator kI3C_SlaveMasterRequestDisabledFlag

Slave master request is disabled. 




enumerator kI3C_SlaveHotJoinDisabledFlag

Slave Hot-Join is disabled. 




enumerator kI3C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer. 




enumerator kI3C_SlaveAllIrqFlags







enum _i3c_slave_error_flags

I3C slave error flags to indicate the causes. 

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_SlaveErrorOverrunFlag

Slave internal from-bus buffer/FIFO overrun. 




enumerator kI3C_SlaveErrorUnderrunFlag

Slave internal to-bus buffer/FIFO underrun 




enumerator kI3C_SlaveErrorUnderrunNakFlag

Slave internal from-bus buffer/FIFO underrun and NACK error 




enumerator kI3C_SlaveErrorTermFlag

Terminate error from master 




enumerator kI3C_SlaveErrorInvalidStartFlag

Slave invalid start flag 




enumerator kI3C_SlaveErrorSdrParityFlag

SDR parity error 




enumerator kI3C_SlaveErrorHdrParityFlag

HDR parity error 




enumerator kI3C_SlaveErrorHdrCRCFlag

HDR-DDR CRC error 




enumerator kI3C_SlaveErrorS0S1Flag

S0 or S1 error 




enumerator kI3C_SlaveErrorOverreadFlag

Over-read error 




enumerator kI3C_SlaveErrorOverwriteFlag

Over-write error 






enum _i3c_slave_event

I3C slave.event. 
Values:


enumerator kI3C_SlaveEventNormal

Normal mode. 




enumerator kI3C_SlaveEventIBI

In band interrupt event. 




enumerator kI3C_SlaveEventMasterReq

Master request event. 




enumerator kI3C_SlaveEventHotJoinReq

Hot-join event. 






enum _i3c_slave_activity_state

I3C slave.activity state. 
Values:


enumerator kI3C_SlaveNoLatency

Normal bus operation 




enumerator kI3C_SlaveLatency1Ms

1ms of latency. 




enumerator kI3C_SlaveLatency100Ms

100ms of latency. 




enumerator kI3C_SlaveLatency10S

10s latency. 






enum _i3c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 

Values:


enumerator kI3C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start. 




enumerator kI3C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role). 




enumerator kI3C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kI3C_SlaveRequiredTransmitEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kI3C_SlaveStartEvent

A start/repeated start was detected. 




enumerator kI3C_SlaveHDRCommandMatchEvent

Slave Match HDR Command. 




enumerator kI3C_SlaveCompletionEvent

A stop was detected, completing the transfer. 




enumerator kI3C_SlaveRequestSentEvent

Slave request event sent. 




enumerator kI3C_SlaveReceivedCCCEvent

Slave received CCC event, need to handle by application. 




enumerator kI3C_SlaveAllEvents

Bit mask of all available events. 






typedef enum _i3c_slave_event i3c_slave_event_t

I3C slave.event. 




typedef enum _i3c_slave_activity_state i3c_slave_activity_state_t

I3C slave.activity state. 




typedef struct _i3c_slave_config i3c_slave_config_t

Structure with settings to initialize the I3C slave module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _i3c_slave_transfer_event i3c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 





typedef struct _i3c_slave_transfer i3c_slave_transfer_t

I3C slave transfer structure. 




typedef struct _i3c_slave_handle i3c_slave_handle_t





typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type. 
This callback is used only for the slave non-blocking transfer API. To install a callback, use the I3C_SlaveSetCallback() function after you have created a handle.

Param base:
Base address for the I3C instance on which the event occurred. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle)

Typedef for slave interrupt handler. 




struct _i3c_slave_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C slave module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableSlave

Whether to enable slave. 




uint8_t staticAddr

Static address. 




uint16_t vendorID

Device vendor ID(manufacture ID). 




uint32_t partNumber

Device part number info 




uint8_t dcr

Device characteristics register information. 




uint8_t bcr

Bus characteristics register information. 




uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode. 




bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed. 




uint32_t maxWriteLength

Maximum write length. 




uint32_t maxReadLength

Maximum read length. 







struct _i3c_slave_transfer


#include <fsl_i3c.h>
I3C slave transfer structure. 

Public Members


uint32_t event

Reason the callback is being invoked. 




uint8_t *txData

Transfer buffer 




size_t txDataSize

Transfer size 




uint8_t *rxData

Transfer buffer 




size_t rxDataSize

Transfer size 




status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent. 




size_t transferredCount

Number of bytes actually transferred since start or last repeated start. 







struct _i3c_slave_handle


#include <fsl_i3c.h>
I3C slave handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


i3c_slave_transfer_t transfer

I3C slave transfer copy. 




bool isBusy

Whether transfer is busy. 




bool wasTransmit

Whether the last transfer was a transmit. 




uint32_t eventMask

Mask of enabled events. 




uint32_t transferredCount

Count of bytes transferred. 




i3c_slave_transfer_callback_t callback

Callback function called at transfer event. 




void *userData

Callback parameter passed to callback. 




size_t txFifoSize

Tx Fifo size 







I3C Slave DMA Driver#


void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)

Create a new handle for the I3C slave DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function. 







status_t I3C_SlaveTransferEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_transfer_t *transfer, uint32_t eventMask)

Prepares for a non-blocking DMA-based transaction on the I3C bus. 
The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when there’s bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned with master application to ensure the transfer is executed as expected. Callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C slave driver handle. 
transfer – The pointer to the transfer descriptor. 
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. The transmit and receive events is not allowed to be enabled. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 
kStatus_Fail – The transaction can’t be set. 







void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)

Abort a slave edma non-blocking transfer in a early time. 

Parameters:

base – I3C peripheral base address 
handle – pointer to i3c_slave_edma_handle_t structure 







void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
i3cHandle – Pointer to the I3C slave DMA driver handle. 







typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t





typedef struct _i3c_slave_edma_transfer i3c_slave_edma_transfer_t

I3C slave transfer structure. 




typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData)

Slave event callback function pointer type. 
This callback is used only for the slave DMA transfer API.

Param base:
Base address for the I3C instance on which the event occurred. 

Param handle:
Pointer to slave DMA transfer handle. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _i3c_slave_edma_transfer


#include <fsl_i3c_edma.h>
I3C slave transfer structure. 

Public Members


uint32_t event

Reason the callback is being invoked. 




uint8_t *txData

Transfer buffer 




size_t txDataSize

Transfer size 




uint8_t *rxData

Transfer buffer 




size_t rxDataSize

Transfer size 




status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent. 







struct _i3c_slave_edma_handle


#include <fsl_i3c_edma.h>
I3C slave edma handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


I3C_Type *base

I3C base pointer. 




i3c_slave_edma_transfer_t transfer

I3C slave transfer copy. 




bool isBusy

Whether transfer is busy. 




bool wasTransmit

Whether the last transfer was a transmit. 




bool isDdrMode

Whether this is HDR-DDR transfer. 




uint32_t eventMask

Mask of enabled events. 




i3c_slave_edma_callback_t callback

Callback function called at transfer event. 




edma_handle_t *rxDmaHandle

Handle for receive DMA channel. 




edma_handle_t *txDmaHandle

Handle for transmit DMA channel. 




void *userData

Callback parameter passed to callback. 







Common Driver#


FSL_COMMON_DRIVER_VERSION

common driver version. 




DEBUG_CONSOLE_DEVICE_TYPE_NONE

No debug console. 




DEBUG_CONSOLE_DEVICE_TYPE_UART

Debug console based on UART. 




DEBUG_CONSOLE_DEVICE_TYPE_LPUART

Debug console based on LPUART. 




DEBUG_CONSOLE_DEVICE_TYPE_LPSCI

Debug console based on LPSCI. 




DEBUG_CONSOLE_DEVICE_TYPE_USBCDC

Debug console based on USBCDC. 




DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM

Debug console based on FLEXCOMM. 




DEBUG_CONSOLE_DEVICE_TYPE_IUART

Debug console based on i.MX UART. 




DEBUG_CONSOLE_DEVICE_TYPE_VUSART

Debug console based on LPC_VUSART. 




DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART

Debug console based on LPC_USART. 




DEBUG_CONSOLE_DEVICE_TYPE_SWO

Debug console based on SWO. 




DEBUG_CONSOLE_DEVICE_TYPE_QSCI

Debug console based on QSCI. 




MIN(a, b)

Computes the minimum of a and b. 




MAX(a, b)

Computes the maximum of a and b. 




UINT16_MAX

Max value of uint16_t type. 




UINT32_MAX

Max value of uint32_t type. 




MCUX_MASK_INVERT_8(mask)

8-bit mask inversion. 




MCUX_MASK_INVERT_16(mask)

16-bit mask inversion. 




MCUX_MASK_INVERT_32(mask)

32-bit mask inversion for completeness. 




MCUX_REG_WRITE8(reg, value)

8-bit register write macro 




MCUX_REG_WRITE16(reg, value)

16-bit register write macro 




MCUX_REG_WRITE32(reg, value)

32-bit register write macro 




MCUX_REG_READ8(reg)

8-bit register read macro 




MCUX_REG_READ16(reg)

16-bit register read macro 




MCUX_REG_READ32(reg)

32-bit register read macro 




MCUX_REG_BIT_SET8(reg, mask)

8-bit register bit set macro 




MCUX_REG_BIT_SET16(reg, mask)

16-bit register bit set macro 




MCUX_REG_BIT_SET32(reg, mask)

32-bit register bit set macro 




MCUX_REG_BIT_CLEAR8(reg, mask)

8-bit register bit clear macro 




MCUX_REG_BIT_CLEAR16(reg, mask)

16-bit register bit clear macro 




MCUX_REG_BIT_CLEAR32(reg, mask)

32-bit register bit clear macro 




MCUX_REG_BIT_GET8(reg, mask)

8-bit register bit get macro 




MCUX_REG_BIT_GET16(reg, mask)

16-bit register bit get macro 




MCUX_REG_BIT_GET32(reg, mask)

32-bit register bit get macro 




MCUX_REG_MODIFY8(reg, mask, value)

32-bit register read-modify-write macro 




MCUX_REG_MODIFY16(reg, mask, value)

16-bit register read-modify-write macro 




MCUX_REG_MODIFY32(reg, mask, value)

32-bit register read-modify-write macro 




SDK_ATOMIC_LOCAL_ADD(addr, val)

Add value val from the variable at address address. 




SDK_ATOMIC_LOCAL_SUB(addr, val)

Subtract value val to the variable at address address. 




SDK_ATOMIC_LOCAL_SET(addr, bits)

Set the bits specifiled by bits to the variable at address address. 




SDK_ATOMIC_LOCAL_CLEAR(addr, bits)

Clear the bits specifiled by bits to the variable at address address. 




SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)

Toggle the bits specifiled by bits to the variable at address address. 




SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)

For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits. 




SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)

For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false . 




SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)

For the variable at address address, set as newValue value and return old value. 




USEC_TO_COUNT(us, clockFreqInHz)

Macro to convert a microsecond period to raw count value 




COUNT_TO_USEC(count, clockFreqInHz)

Macro to convert a raw count value to microsecond 




MSEC_TO_COUNT(ms, clockFreqInHz)

Macro to convert a millisecond period to raw count value 




COUNT_TO_MSEC(count, clockFreqInHz)

Macro to convert a raw count value to millisecond 




SDK_ISR_EXIT_BARRIER





SDK_ALIGN(var, alignbytes)

Macro to define a variable with alignbytes alignment 




SDK_SIZEALIGN(var, alignbytes)

Macro to define a variable with L1 d-cache line size alignment
Macro to define a variable with L2 cache line size alignment
Macro to change a value to a given size aligned value (rounded up) 




SDK_SIZEALIGN_UP(var, alignbytes)

Macro to change a value to a given size aligned value (rounded up), the wrapper of SDK_SIZEALIGN 




SDK_SIZEALIGN_DOWN(var, alignbytes)

Macro to change a value to a given size aligned value (rounded down) 




SDK_IS_ALIGNED(var, alignbytes)

Macro to check if a value is aligned to a given size 




AT_NONCACHEABLE_SECTION(var)

Define a variable var, and place it in non-cacheable section. 




AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)

Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes. 




AT_NONCACHEABLE_SECTION_INIT(var)

Define a variable var with initial value, and place it in non-cacheable section. 




AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)

Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes. 




AT_CACHE_LINE_SECTION(var)

Define a variable var, which is cache line size aligned and be placed in CacheLineData section. 




AT_CACHE_LINE_SECTION_INIT(var)

Define a variable var with initial value, which is cache line size aligned and be placed in CacheLineData.init section. 




AT_QUICKACCESS_SECTION_CODE(func)

Place function in a section which can be accessed quickly by core. 




AT_QUICKACCESS_SECTION_DATA(var)

Place data in a section which can be accessed quickly by core. 




AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)

Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes. 




MCUX_RAMFUNC

Function attribute to place function in RAM. For example, to place function my_func in ram, use like: 
MCUX_RAMFUNC my_func







RAMFUNCTION_SECTION_CODE(func)

Place function in ram. 




enum _status_groups

Status group numbers. 
Values:


enumerator kStatusGroup_Generic

Group number for generic status codes. 




enumerator kStatusGroup_FLASH

Group number for FLASH status codes. 




enumerator kStatusGroup_LPSPI

Group number for LPSPI status codes. 




enumerator kStatusGroup_FLEXIO_SPI

Group number for FLEXIO SPI status codes. 




enumerator kStatusGroup_DSPI

Group number for DSPI status codes. 




enumerator kStatusGroup_FLEXIO_UART

Group number for FLEXIO UART status codes. 




enumerator kStatusGroup_FLEXIO_I2C

Group number for FLEXIO I2C status codes. 




enumerator kStatusGroup_LPI2C

Group number for LPI2C status codes. 




enumerator kStatusGroup_UART

Group number for UART status codes. 




enumerator kStatusGroup_I2C

Group number for UART status codes. 




enumerator kStatusGroup_LPSCI

Group number for LPSCI status codes. 




enumerator kStatusGroup_LPUART

Group number for LPUART status codes. 




enumerator kStatusGroup_SPI

Group number for SPI status code. 




enumerator kStatusGroup_XRDC

Group number for XRDC status code. 




enumerator kStatusGroup_SEMA42

Group number for SEMA42 status code. 




enumerator kStatusGroup_SDHC

Group number for SDHC status code 




enumerator kStatusGroup_SDMMC

Group number for SDMMC status code 




enumerator kStatusGroup_SAI

Group number for SAI status code 




enumerator kStatusGroup_MCG

Group number for MCG status codes. 




enumerator kStatusGroup_SCG

Group number for SCG status codes. 




enumerator kStatusGroup_SDSPI

Group number for SDSPI status codes. 




enumerator kStatusGroup_FLEXIO_I2S

Group number for FLEXIO I2S status codes 




enumerator kStatusGroup_FLEXIO_MCULCD

Group number for FLEXIO LCD status codes 




enumerator kStatusGroup_FLASHIAP

Group number for FLASHIAP status codes 




enumerator kStatusGroup_FLEXCOMM_I2C

Group number for FLEXCOMM I2C status codes 




enumerator kStatusGroup_I2S

Group number for I2S status codes 




enumerator kStatusGroup_IUART

Group number for IUART status codes 




enumerator kStatusGroup_CSI

Group number for CSI status codes 




enumerator kStatusGroup_MIPI_DSI

Group number for MIPI DSI status codes 




enumerator kStatusGroup_SDRAMC

Group number for SDRAMC status codes. 




enumerator kStatusGroup_POWER

Group number for POWER status codes. 




enumerator kStatusGroup_ENET

Group number for ENET status codes. 




enumerator kStatusGroup_PHY

Group number for PHY status codes. 




enumerator kStatusGroup_TRGMUX

Group number for TRGMUX status codes. 




enumerator kStatusGroup_SMARTCARD

Group number for SMARTCARD status codes. 




enumerator kStatusGroup_LMEM

Group number for LMEM status codes. 




enumerator kStatusGroup_QSPI

Group number for QSPI status codes. 




enumerator kStatusGroup_DMA

Group number for DMA status codes. 




enumerator kStatusGroup_EDMA

Group number for EDMA status codes. 




enumerator kStatusGroup_DMAMGR

Group number for DMAMGR status codes. 




enumerator kStatusGroup_FLEXCAN

Group number for FlexCAN status codes. 




enumerator kStatusGroup_LTC

Group number for LTC status codes. 




enumerator kStatusGroup_FLEXIO_CAMERA

Group number for FLEXIO CAMERA status codes. 




enumerator kStatusGroup_LPC_SPI

Group number for LPC_SPI status codes. 




enumerator kStatusGroup_LPC_USART

Group number for LPC_USART status codes. 




enumerator kStatusGroup_DMIC

Group number for DMIC status codes. 




enumerator kStatusGroup_SDIF

Group number for SDIF status codes. 




enumerator kStatusGroup_SPIFI

Group number for SPIFI status codes. 




enumerator kStatusGroup_OTP

Group number for OTP status codes. 




enumerator kStatusGroup_MCAN

Group number for MCAN status codes. 




enumerator kStatusGroup_CAAM

Group number for CAAM status codes. 




enumerator kStatusGroup_ECSPI

Group number for ECSPI status codes. 




enumerator kStatusGroup_USDHC

Group number for USDHC status codes. 




enumerator kStatusGroup_LPC_I2C

Group number for LPC_I2C status codes. 




enumerator kStatusGroup_DCP

Group number for DCP status codes. 




enumerator kStatusGroup_MSCAN

Group number for MSCAN status codes. 




enumerator kStatusGroup_ESAI

Group number for ESAI status codes. 




enumerator kStatusGroup_FLEXSPI

Group number for FLEXSPI status codes. 




enumerator kStatusGroup_MMDC

Group number for MMDC status codes. 




enumerator kStatusGroup_PDM

Group number for MIC status codes. 




enumerator kStatusGroup_SDMA

Group number for SDMA status codes. 




enumerator kStatusGroup_ICS

Group number for ICS status codes. 




enumerator kStatusGroup_SPDIF

Group number for SPDIF status codes. 




enumerator kStatusGroup_LPC_MINISPI

Group number for LPC_MINISPI status codes. 




enumerator kStatusGroup_HASHCRYPT

Group number for Hashcrypt status codes 




enumerator kStatusGroup_LPC_SPI_SSP

Group number for LPC_SPI_SSP status codes. 




enumerator kStatusGroup_I3C

Group number for I3C status codes 




enumerator kStatusGroup_LPC_I2C_1

Group number for LPC_I2C_1 status codes. 




enumerator kStatusGroup_NOTIFIER

Group number for NOTIFIER status codes. 




enumerator kStatusGroup_DebugConsole

Group number for debug console status codes. 




enumerator kStatusGroup_SEMC

Group number for SEMC status codes. 




enumerator kStatusGroup_ApplicationRangeStart

Starting number for application groups. 




enumerator kStatusGroup_IAP

Group number for IAP status codes 




enumerator kStatusGroup_SFA

Group number for SFA status codes 




enumerator kStatusGroup_SPC

Group number for SPC status codes. 




enumerator kStatusGroup_PUF

Group number for PUF status codes. 




enumerator kStatusGroup_TOUCH_PANEL

Group number for touch panel status codes 




enumerator kStatusGroup_VBAT

Group number for VBAT status codes 




enumerator kStatusGroup_XSPI

Group number for XSPI status codes 




enumerator kStatusGroup_PNGDEC

Group number for PNGDEC status codes 




enumerator kStatusGroup_JPEGDEC

Group number for JPEGDEC status codes 




enumerator kStatusGroup_AUDMIX

Group number for AUDMIX status codes 




enumerator kStatusGroup_HAL_GPIO

Group number for HAL GPIO status codes. 




enumerator kStatusGroup_HAL_UART

Group number for HAL UART status codes. 




enumerator kStatusGroup_HAL_TIMER

Group number for HAL TIMER status codes. 




enumerator kStatusGroup_HAL_SPI

Group number for HAL SPI status codes. 




enumerator kStatusGroup_HAL_I2C

Group number for HAL I2C status codes. 




enumerator kStatusGroup_HAL_FLASH

Group number for HAL FLASH status codes. 




enumerator kStatusGroup_HAL_PWM

Group number for HAL PWM status codes. 




enumerator kStatusGroup_HAL_RNG

Group number for HAL RNG status codes. 




enumerator kStatusGroup_HAL_I2S

Group number for HAL I2S status codes. 




enumerator kStatusGroup_HAL_ADC_SENSOR

Group number for HAL ADC SENSOR status codes. 




enumerator kStatusGroup_TIMERMANAGER

Group number for TiMER MANAGER status codes. 




enumerator kStatusGroup_SERIALMANAGER

Group number for SERIAL MANAGER status codes. 




enumerator kStatusGroup_LED

Group number for LED status codes. 




enumerator kStatusGroup_BUTTON

Group number for BUTTON status codes. 




enumerator kStatusGroup_EXTERN_EEPROM

Group number for EXTERN EEPROM status codes. 




enumerator kStatusGroup_SHELL

Group number for SHELL status codes. 




enumerator kStatusGroup_MEM_MANAGER

Group number for MEM MANAGER status codes. 




enumerator kStatusGroup_LIST

Group number for List status codes. 




enumerator kStatusGroup_OSA

Group number for OSA status codes. 




enumerator kStatusGroup_COMMON_TASK

Group number for Common task status codes. 




enumerator kStatusGroup_MSG

Group number for messaging status codes. 




enumerator kStatusGroup_SDK_OCOTP

Group number for OCOTP status codes. 




enumerator kStatusGroup_SDK_FLEXSPINOR

Group number for FLEXSPINOR status codes. 




enumerator kStatusGroup_CODEC

Group number for codec status codes. 




enumerator kStatusGroup_ASRC

Group number for codec status ASRC. 




enumerator kStatusGroup_OTFAD

Group number for codec status codes. 




enumerator kStatusGroup_SDIOSLV

Group number for SDIOSLV status codes. 




enumerator kStatusGroup_MECC

Group number for MECC status codes. 




enumerator kStatusGroup_ENET_QOS

Group number for ENET_QOS status codes. 




enumerator kStatusGroup_LOG

Group number for LOG status codes. 




enumerator kStatusGroup_I3CBUS

Group number for I3CBUS status codes. 




enumerator kStatusGroup_QSCI

Group number for QSCI status codes. 




enumerator kStatusGroup_ELEMU

Group number for ELEMU status codes. 




enumerator kStatusGroup_QUEUEDSPI

Group number for QSPI status codes. 




enumerator kStatusGroup_POWER_MANAGER

Group number for POWER_MANAGER status codes. 




enumerator kStatusGroup_IPED

Group number for IPED status codes. 




enumerator kStatusGroup_ELS_PKC

Group number for ELS PKC status codes. 




enumerator kStatusGroup_CSS_PKC

Group number for CSS PKC status codes. 




enumerator kStatusGroup_HOSTIF

Group number for HOSTIF status codes. 




enumerator kStatusGroup_CLIF

Group number for CLIF status codes. 




enumerator kStatusGroup_BMA

Group number for BMA status codes. 




enumerator kStatusGroup_NETC

Group number for NETC status codes. 




enumerator kStatusGroup_ELE

Group number for ELE status codes. 




enumerator kStatusGroup_GLIKEY

Group number for GLIKEY status codes. 




enumerator kStatusGroup_AON_POWER

Group number for AON_POWER status codes. 




enumerator kStatusGroup_AON_COMMON

Group number for AON_COMMON status codes. 




enumerator kStatusGroup_ENDAT3

Group number for ENDAT3 status codes. 




enumerator kStatusGroup_HIPERFACE

Group number for HIPERFACE status codes. 




enumerator kStatusGroup_NPX

Group number for NPX status codes. 




enumerator kStatusGroup_ELA_CSEC

Group number for ELA_CSEC status codes. 




enumerator kStatusGroup_FLEXIO_T_FORMAT

Group number for T-format status codes. 




enumerator kStatusGroup_FLEXIO_A_FORMAT

Group number for A-format status codes. 




enumerator kStatusGroup_LPC_QSPI

Group number for LPC QSPI status codes. 







Generic status return codes. 
Values:


enumerator kStatus_Success

Generic status for Success. 




enumerator kStatus_Fail

Generic status for Fail. 




enumerator kStatus_ReadOnly

Generic status for read only failure. 




enumerator kStatus_OutOfRange

Generic status for out of range access. 




enumerator kStatus_InvalidArgument

Generic status for invalid argument check. 




enumerator kStatus_Timeout

Generic status for timeout. 




enumerator kStatus_NoTransferInProgress

Generic status for no transfer in progress. 




enumerator kStatus_Busy

Generic status for module is busy. 




enumerator kStatus_NoData

Generic status for no data is found for the operation. 






typedef int32_t status_t

Type used for all status and error return values. 




void *SDK_Malloc(size_t size, size_t alignbytes)

Allocate memory with given alignment and aligned size. 
This is provided to support the dynamically allocated memory used in cache-able region. 

Parameters:

size – The length required to malloc. 
alignbytes – The alignment size. 


Return values:
The – allocated memory. 






void SDK_Free(void *ptr)

Free memory. 

Parameters:

ptr – The memory to be release. 







void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer. 

Parameters:

delayTime_us – Delay time in unit of microsecond. 
coreClock_Hz – Core clock frequency with Hz. 







static inline status_t EnableIRQ(IRQn_Type interrupt)

Enable specific interrupt. 
Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number. 


Return values:

kStatus_Success – Interrupt enabled successfully 
kStatus_Fail – Failed to enable the interrupt 







static inline status_t DisableIRQ(IRQn_Type interrupt)

Disable specific interrupt. 
Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number. 


Return values:

kStatus_Success – Interrupt disabled successfully 
kStatus_Fail – Failed to disable the interrupt 







static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)

Enable the IRQ, and also set the interrupt priority. 
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to Enable. 
priNum – Priority number set to interrupt controller register. 


Return values:

kStatus_Success – Interrupt priority set successfully 
kStatus_Fail – Failed to set the interrupt priority. 







static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)

Set the IRQ priority. 
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to set. 
priNum – Priority number set to interrupt controller register.


Return values:

kStatus_Success – Interrupt priority set successfully 
kStatus_Fail – Failed to set the interrupt priority. 







static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)

Clear the pending IRQ flag. 
Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.
This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The flag which IRQ to clear.


Return values:

kStatus_Success – Interrupt priority set successfully 
kStatus_Fail – Failed to set the interrupt priority. 







static inline uint32_t DisableGlobalIRQ(void)

Disable the global IRQ. 
Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:
Current primask value. 






static inline void EnableGlobalIRQ(uint32_t primask)

Enable the global IRQ. 
Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ(). 







static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)





static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)





FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ

Macro to use the default weak IRQ handler in drivers. 




MAKE_STATUS(group, code)

Construct a status code value from a group and code number. 




MAKE_VERSION(major, minor, bugfix)

Construct the version number for drivers. 
The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).
| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0






ARRAY_SIZE(x)

Computes the number of elements in an array. 




UINT64_H(X)

Macro to get upper 32 bits of a 64-bit value 




UINT64_L(X)

Macro to get lower 32 bits of a 64-bit value 




SUPPRESS_FALL_THROUGH_WARNING()

For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement. 




MSDK_REG_SECURE_ADDR(x)

Convert the register address to the one used in secure mode. 




MSDK_REG_NONSECURE_ADDR(x)

Convert the register address to the one used in non-secure mode. 




MSDK_HAS_DWT_CYCCNT

The chip supports DWT CYCCNT or not. 




MSDK_INVALID_IRQ_HANDLER

Invalid IRQ handler address. 




LPI2C: Low Power Inter-Integrated Circuit Driver#


void LPI2C_DriverIRQHandler(uint32_t instance)

LPI2C driver IRQ handler common entry. 
This function provides the common IRQ request entry for LPI2C.

Parameters:

instance – LPI2C instance. 







FSL_LPI2C_DRIVER_VERSION

LPI2C driver version. 





LPI2C status return codes. 
Values:


enumerator kStatus_LPI2C_Busy

The master is already performing a transfer. 




enumerator kStatus_LPI2C_Idle

The slave driver is idle. 




enumerator kStatus_LPI2C_Nak

The slave device sent a NAK in response to a byte. 




enumerator kStatus_LPI2C_FifoError

FIFO under run or overrun. 




enumerator kStatus_LPI2C_BitError

Transferred bit was not seen on the bus. 




enumerator kStatus_LPI2C_ArbitrationLost

Arbitration lost error. 




enumerator kStatus_LPI2C_PinLowTimeout

SCL or SDA were held low longer than the timeout. 




enumerator kStatus_LPI2C_NoTransferInProgress

Attempt to abort a transfer when one is not in progress. 




enumerator kStatus_LPI2C_DmaRequestFail

DMA request failed. 




enumerator kStatus_LPI2C_Timeout

Timeout polling status flags. 






IRQn_Type const kLpi2cMasterIrqs[]

Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs. 




IRQn_Type const kLpi2cSlaveIrqs[]





lpi2c_master_isr_t s_lpi2cMasterIsr

Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs. 




void *s_lpi2cMasterHandle[]

Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs. 




uint32_t LPI2C_GetInstance(LPI2C_Type *base)

Returns an instance number given a base address. 
If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

base – The LPI2C peripheral base address. 


Returns:
LPI2C instance number starting from 0. 






I2C_RETRY_TIMES

Retry times for waiting flag. 




LPI2C Master Driver#


void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)

Provides a default configuration for the LPI2C master peripheral. 
This function provides the following default configuration for the LPI2C master peripheral: 
masterConfig->enableMaster            = true;
masterConfig->debugEnable             = false;
masterConfig->ignoreAck               = false;
masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busIdleTimeout_ns       = 0;
masterConfig->pinLowTimeout_ns        = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable      = false;
masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t. 







void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C master peripheral. 
This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The LPI2C peripheral base address. 
masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







void LPI2C_MasterDeinit(LPI2C_Type *base)

Deinitializes the LPI2C master peripheral. 
This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address. 







void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)

Configures LPI2C master data match feature. 

Parameters:

base – The LPI2C peripheral base address. 
matchConfig – Settings for the data match feature. 







status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)

Convert provided flags to status code, and clear any errors if present. 

Parameters:

base – The LPI2C peripheral base address. 
status – Current status flags value that will be checked. 


Return values:

kStatus_Success – 
kStatus_LPI2C_PinLowTimeout – 
kStatus_LPI2C_ArbitrationLost – 
kStatus_LPI2C_Nak – 
kStatus_LPI2C_FifoError – 







status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)

Make sure the bus isn’t already busy. 
A busy bus is allowed if we are the one driving it.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

kStatus_Success – 
kStatus_LPI2C_Busy – 







static inline void LPI2C_MasterReset(LPI2C_Type *base)

Performs a software reset. 
Restores the LPI2C master peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address. 







static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as master. 

Parameters:

base – The LPI2C peripheral base address. 
enable – Pass true to enable or false to disable the specified LPI2C as master. 







static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C master status flags. 
A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_lpi2c_master_flags



Parameters:

base – The LPI2C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C master status flag state. 
The following status register flags can be cleared:

kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag


Attempts to clear other flags has no effect.

See also
_lpi2c_master_flags. 



Parameters:

base – The LPI2C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags(). 







static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C master interrupt requests. 
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C master interrupt requests. 
All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C master interrupt requests. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)

Enables or disables LPI2C master DMA requests. 

Parameters:

base – The LPI2C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 







static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)

Gets LPI2C master transmit data register address for DMA transfer. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
The LPI2C Master Transmit Data Register address. 






static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)

Gets LPI2C master receive data register address for DMA transfer. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
The LPI2C Master Receive Data Register address. 






static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)

Sets the watermarks for LPI2C master FIFOs. 

Parameters:

base – The LPI2C peripheral base address. 
txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated. 
rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated. 







static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of words in the LPI2C master FIFOs. 

Parameters:

base – The LPI2C peripheral base address. 
txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required. 







void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)

Sets the I2C bus frequency for master transactions. 
The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note
Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.


Parameters:

base – The LPI2C peripheral base address. 
sourceClock_Hz – LPI2C functional clock frequency in Hertz. 
baudRate_Hz – Requested bus frequency in Hertz. 







static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle. 
Requires the master mode to be enabled.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a START signal and slave address on the I2C bus. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The LPI2C peripheral base address. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 







static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a repeated START signal and slave address on the I2C bus. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.

Note
This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The LPI2C peripheral base address. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 







status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)

Performs a polling send transfer on the I2C bus. 
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.

Parameters:

base – The LPI2C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Return values:

kStatus_Success – Data was sent successfully. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or over run. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or overrun. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







status_t LPI2C_MasterStop(LPI2C_Type *base)

Sends a STOP signal on the I2C bus. 
This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or overrun. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C bus. 

Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.


Parameters:

base – The LPI2C peripheral base address. 
transfer – Pointer to the transfer structure. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_LPI2C_Busy – Another master is currently utilizing the bus. 
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte. 
kStatus_LPI2C_FifoError – FIFO under run or overrun. 
kStatus_LPI2C_ArbitrationLost – Arbitration lost error. 
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout. 







void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C master non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The LPI2C peripheral base address. 
handle – [out] Pointer to the LPI2C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 







status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 







void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The LPI2C peripheral base address. 
lpi2cMasterHandle – Pointer to the LPI2C master driver handle. 







enum _lpi2c_master_flags

LPI2C master peripheral flags. 
The following status register flags can be cleared:

kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag


All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kLPI2C_MasterTxReadyFlag

Transmit data flag 




enumerator kLPI2C_MasterRxReadyFlag

Receive data flag 




enumerator kLPI2C_MasterEndOfPacketFlag

End Packet flag 




enumerator kLPI2C_MasterStopDetectFlag

Stop detect flag 




enumerator kLPI2C_MasterNackDetectFlag

NACK detect flag 




enumerator kLPI2C_MasterArbitrationLostFlag

Arbitration lost flag 




enumerator kLPI2C_MasterFifoErrFlag

FIFO error flag 




enumerator kLPI2C_MasterPinLowTimeoutFlag

Pin low timeout flag 




enumerator kLPI2C_MasterDataMatchFlag

Data match flag 




enumerator kLPI2C_MasterBusyFlag

Master busy flag 




enumerator kLPI2C_MasterBusBusyFlag

Bus busy flag 




enumerator kLPI2C_MasterClearFlags

All flags which are cleared by the driver upon starting a transfer. 




enumerator kLPI2C_MasterIrqFlags

IRQ sources enabled by the non-blocking transactional API. 




enumerator kLPI2C_MasterErrorFlags

Errors to check for. 






enum _lpi2c_direction

Direction of master and slave transfers. 
Values:


enumerator kLPI2C_Write

Master transmit. 




enumerator kLPI2C_Read

Master receive. 






enum _lpi2c_master_pin_config

LPI2C pin configuration. 
Values:


enumerator kLPI2C_2PinOpenDrain

LPI2C Configured for 2-pin open drain mode 




enumerator kLPI2C_2PinOutputOnly

LPI2C Configured for 2-pin output only mode (ultra-fast mode) 




enumerator kLPI2C_2PinPushPull

LPI2C Configured for 2-pin push-pull mode 




enumerator kLPI2C_4PinPushPull

LPI2C Configured for 4-pin push-pull mode 




enumerator kLPI2C_2PinOpenDrainWithSeparateSlave

LPI2C Configured for 2-pin open drain mode with separate LPI2C slave 




enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave

LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave 




enumerator kLPI2C_2PinPushPullWithSeparateSlave

LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave 




enumerator kLPI2C_4PinPushPullWithInvertedOutput

LPI2C Configured for 4-pin push-pull mode(inverted outputs) 






enum _lpi2c_host_request_source

LPI2C master host request selection. 
Values:


enumerator kLPI2C_HostRequestExternalPin

Select the LPI2C_HREQ pin as the host request input 




enumerator kLPI2C_HostRequestInputTrigger

Select the input trigger as the host request input 






enum _lpi2c_host_request_polarity

LPI2C master host request pin polarity configuration. 
Values:


enumerator kLPI2C_HostRequestPinActiveLow

Configure the LPI2C_HREQ pin active low 




enumerator kLPI2C_HostRequestPinActiveHigh

Configure the LPI2C_HREQ pin active high 






enum _lpi2c_data_match_config_mode

LPI2C master data match configuration modes. 
Values:


enumerator kLPI2C_MatchDisabled

LPI2C Match Disabled 




enumerator kLPI2C_1stWordEqualsM0OrM1

LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 




enumerator kLPI2C_AnyWordEqualsM0OrM1

LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 




enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1

LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 




enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1

LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 




enumerator kLPI2C_1stWordAndM1EqualsM0AndM1

LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 




enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1

LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 






enum _lpi2c_master_transfer_flags

Transfer option flags. 

Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field. 

Values:


enumerator kLPI2C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal. 




enumerator kLPI2C_TransferNoStartFlag

Don’t send a start condition, address, and sub address 




enumerator kLPI2C_TransferRepeatedStartFlag

Send a repeated start condition 




enumerator kLPI2C_TransferNoStopFlag

Don’t send a stop condition. 






typedef enum _lpi2c_direction lpi2c_direction_t

Direction of master and slave transfers. 




typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t

LPI2C pin configuration. 




typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t

LPI2C master host request selection. 




typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t

LPI2C master host request pin polarity configuration. 




typedef struct _lpi2c_master_config lpi2c_master_config_t

Structure with settings to initialize the LPI2C master module. 
This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t

LPI2C master data match configuration modes. 




typedef struct _lpi2c_match_config lpi2c_data_match_config_t

LPI2C master data match configuration structure. 




typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t

LPI2C master descriptor of the transfer. 




typedef struct _lpi2c_master_handle lpi2c_master_handle_t

LPI2C master handle of the transfer. 




typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)

Master completion callback function pointer type. 
This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().

Param base:
The LPI2C peripheral base address. 

Param handle:
Pointer to the LPI2C master driver handle. 

Param completionStatus:
Either kStatus_Success or an error code describing how the transfer completed. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)

Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs. 




struct _lpi2c_master_config


#include <fsl_lpi2c.h>
Structure with settings to initialize the LPI2C master module. 
This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableMaster

Whether to enable master mode. 




bool enableDoze

Whether master is enabled in doze mode. 




bool debugEnable

Enable transfers to continue when halted in debug mode. 




bool ignoreAck

Whether to ignore ACK/NACK. 




lpi2c_master_pin_config_t pinConfig

The pin configuration option. 




uint32_t baudRate_Hz

Desired baud rate in Hertz. 




uint32_t busIdleTimeout_ns

Bus idle timeout in nanoseconds. Set to 0 to disable. 




uint32_t pinLowTimeout_ns

Pin low timeout in nanoseconds. Set to 0 to disable. 




uint8_t sdaGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. 




uint8_t sclGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. 




struct _lpi2c_master_config hostRequest

Host request options. 







struct _lpi2c_match_config


#include <fsl_lpi2c.h>
LPI2C master data match configuration structure. 

Public Members


lpi2c_data_match_config_mode_t matchMode

Data match configuration setting. 




bool rxDataMatchOnly

When set to true, received data is ignored until a successful match. 




uint32_t match0

Match value 0. 




uint32_t match1

Match value 1. 







struct _lpi2c_master_transfer


#include <fsl_lpi2c.h>
Non-blocking transfer descriptor structure. 
This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. 

Public Members


uint32_t flags

Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers. 




uint16_t slaveAddress

The 7-bit slave address. 




lpi2c_direction_t direction

Either kLPI2C_Read or kLPI2C_Write. 




uint32_t subaddress

Sub address. Transferred MSB first. 




size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes. 




void *data

Pointer to data to transfer. 




size_t dataSize

Number of bytes to transfer. 







struct _lpi2c_master_handle


#include <fsl_lpi2c.h>
Driver handle for master non-blocking APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


uint8_t state

Transfer state machine current state. 




uint16_t remainingBytes

Remaining byte count in current state. 




uint8_t *buf

Buffer pointer for current state. 




uint16_t commandBuffer[6]

LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] 




lpi2c_master_transfer_t transfer

Copy of the current transfer info. 




lpi2c_master_transfer_callback_t completionCallback

Callback function pointer. 




void *userData

Application data passed to callback. 







struct hostRequest


Public Members


bool enable

Enable host request. 




lpi2c_host_request_source_t source

Host request source. 




lpi2c_host_request_polarity_t polarity

Host request pin polarity. 







LPI2C Master DMA Driver#


void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)

Create a new handle for the LPI2C master DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.
For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The LPI2C peripheral base address. 
handle – [out] Pointer to the LPI2C master driver handle. 
rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I2C bus. 
The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 







status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress. 







status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to the LPI2C master driver handle. 


Return values:

kStatus_Success – A transaction was successfully aborted. 
kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress. 







typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t

LPI2C master EDMA handle of the transfer. 




typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)

Master DMA completion callback function pointer type. 
This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().

Param base:
The LPI2C peripheral base address. 

Param handle:
Handle associated with the completed transfer. 

Param completionStatus:
Either kStatus_Success or an error code describing how the transfer completed. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _lpi2c_master_edma_handle


#include <fsl_lpi2c_edma.h>
Driver handle for master DMA APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


LPI2C_Type *base

LPI2C base pointer. 




bool isBusy

Transfer state machine current state. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




uint16_t commandBuffer[20]

LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words] 




lpi2c_master_transfer_t transfer

Copy of the current transfer info. 




lpi2c_master_edma_transfer_callback_t completionCallback

Callback function pointer. 




void *userData

Application data passed to callback. 




edma_handle_t *rx

Handle for receive DMA channel. 




edma_handle_t *tx

Handle for transmit DMA channel. 




edma_tcd_t tcds[3]

Software TCD. Three are allocated to provide enough room to align to 32-bytes. 







LPI2C Slave Driver#


void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)

Provides a default configuration for the LPI2C slave peripheral. 
This function provides the following default configuration for the LPI2C slave peripheral: 
slaveConfig->enableSlave               = true;
slaveConfig->address0                  = 0U;
slaveConfig->address1                  = 0U;
slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable          = true;
slaveConfig->filterEnable              = true;
slaveConfig->enableGeneralCall         = false;
slaveConfig->sclStall.enableAck        = false;
slaveConfig->sclStall.enableTx         = true;
slaveConfig->sclStall.enableRx         = true;
slaveConfig->sclStall.enableAddress    = true;
slaveConfig->ignoreAck                 = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns   = 0;
slaveConfig->sclGlitchFilterWidth_ns   = 0;
slaveConfig->dataValidDelay_ns         = 0;
slaveConfig->clockHoldTime_ns          = 0;



After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.

Parameters:

slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t. 







void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C slave peripheral. 
This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.

Parameters:

base – The LPI2C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time. 







void LPI2C_SlaveDeinit(LPI2C_Type *base)

Deinitializes the LPI2C slave peripheral. 
This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address. 







static inline void LPI2C_SlaveReset(LPI2C_Type *base)

Performs a software reset of the LPI2C slave peripheral. 

Parameters:

base – The LPI2C peripheral base address. 







static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as slave. 

Parameters:

base – The LPI2C peripheral base address. 
enable – Pass true to enable or false to disable the specified LPI2C as slave. 







static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C slave status flags. 
A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_lpi2c_slave_flags



Parameters:

base – The LPI2C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C status flag state. 
The following status register flags can be cleared:

kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag


Attempts to clear other flags has no effect.

See also
_lpi2c_slave_flags. 



Parameters:

base – The LPI2C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags(). 







static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C slave interrupt requests. 
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C slave interrupt requests. 
All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C slave interrupt requests. 

Parameters:

base – The LPI2C peripheral base address. 


Returns:
A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)

Enables or disables the LPI2C slave peripheral DMA requests. 

Parameters:

base – The LPI2C peripheral base address. 
enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request. 
enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable. 
enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable. 







static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle. 
Requires the slave mode to be enabled.

Parameters:

base – The LPI2C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)

Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. 
Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.

Parameters:

base – The LPI2C peripheral base address. 
ackOrNack – Pass true for an ACK or false for a NAK. 







static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)

Enables or disables ACKSTALL. 
When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.

Parameters:

base – The LPI2C peripheral base address. 
enable – True will enable ACKSTALL,false will disable ACKSTALL. 







static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)

Returns the slave address sent by the I2C master. 
This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.

Parameters:

base – The LPI2C peripheral base address. 


Returns:
The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits. 






status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)

Performs a polling send transfer on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 
actualTxSize – [out] 


Returns:
Error or success status returned by API. 






status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)

Performs a polling receive transfer on the I2C bus. 

Parameters:

base – The LPI2C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 
actualRxSize – [out] 


Returns:
Error or success status returned by API. 






void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C slave non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The LPI2C peripheral base address. 
handle – [out] Pointer to the LPI2C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers. 
Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state. 
eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.


Return values:

kStatus_Success – Slave transfers were successfully started. 
kStatus_LPI2C_Busy – Slave transfers have already been started on this handle. 







status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer. 

Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to i2c_slave_handle_t structure. 
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – 







void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Aborts the slave non-blocking transfers. 

Note
This API could be called at any time to stop slave for handling the bus events. 


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state. 







void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The LPI2C peripheral base address. 
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state. 







enum _lpi2c_slave_flags

LPI2C slave peripheral flags. 
The following status register flags can be cleared:

kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag


All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Note
These enumerations are meant to be OR’d together to form a bit mask. 

Values:


enumerator kLPI2C_SlaveTxReadyFlag

Transmit data flag 




enumerator kLPI2C_SlaveRxReadyFlag

Receive data flag 




enumerator kLPI2C_SlaveAddressValidFlag

Address valid flag 




enumerator kLPI2C_SlaveTransmitAckFlag

Transmit ACK flag 




enumerator kLPI2C_SlaveRepeatedStartDetectFlag

Repeated start detect flag 




enumerator kLPI2C_SlaveStopDetectFlag

Stop detect flag 




enumerator kLPI2C_SlaveBitErrFlag

Bit error flag 




enumerator kLPI2C_SlaveFifoErrFlag

FIFO error flag 




enumerator kLPI2C_SlaveAddressMatch0Flag

Address match 0 flag 




enumerator kLPI2C_SlaveAddressMatch1Flag

Address match 1 flag 




enumerator kLPI2C_SlaveGeneralCallFlag

General call flag 




enumerator kLPI2C_SlaveBusyFlag

Master busy flag 




enumerator kLPI2C_SlaveBusBusyFlag

Bus busy flag 




enumerator kLPI2C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer. 




enumerator kLPI2C_SlaveIrqFlags

IRQ sources enabled by the non-blocking transactional API. 




enumerator kLPI2C_SlaveErrorFlags

Errors to check for. 






enum _lpi2c_slave_address_match

LPI2C slave address match options. 
Values:


enumerator kLPI2C_MatchAddress0

Match only address 0. 




enumerator kLPI2C_MatchAddress0OrAddress1

Match either address 0 or address 1. 




enumerator kLPI2C_MatchAddress0ThroughAddress1

Match a range of slave addresses from address 0 through address 1. 






enum _lpi2c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 

Values:


enumerator kLPI2C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start. 




enumerator kLPI2C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role). 




enumerator kLPI2C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kLPI2C_SlaveTransmitAckEvent

Callback needs to either transmit an ACK or NACK. 




enumerator kLPI2C_SlaveRepeatedStartEvent

A repeated start was detected. 




enumerator kLPI2C_SlaveCompletionEvent

A stop was detected, completing the transfer. 




enumerator kLPI2C_SlaveAllEvents

Bit mask of all available events. 






typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t

LPI2C slave address match options. 




typedef struct _lpi2c_slave_config lpi2c_slave_config_t

Structure with settings to initialize the LPI2C slave module. 
This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 





typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t

LPI2C slave transfer structure. 




typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t

LPI2C slave handle structure. 




typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type. 
This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.

Param base:
Base address for the LPI2C instance on which the event occurred. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _lpi2c_slave_config


#include <fsl_lpi2c.h>
Structure with settings to initialize the LPI2C slave module. 
This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableSlave

Enable slave mode. 




uint8_t address0

Slave’s 7-bit address. 




uint8_t address1

Alternate slave 7-bit address. 




lpi2c_slave_address_match_t addressMatchMode

Address matching options. 




bool filterDozeEnable

Enable digital glitch filter in doze mode. 




bool filterEnable

Enable digital glitch filter. 




bool enableGeneralCall

Enable general call address matching. 




struct _lpi2c_slave_config sclStall

SCL stall enable options. 




bool ignoreAck

Continue transfers after a NACK is detected. 




bool enableReceivedAddressRead

Enable reading the address received address as the first byte of data. 




uint32_t sdaGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable. 




uint32_t sclGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable. 




uint32_t dataValidDelay_ns

Width in nanoseconds of the data valid delay. 




uint32_t clockHoldTime_ns

Width in nanoseconds of the clock hold time. 







struct _lpi2c_slave_transfer


#include <fsl_lpi2c.h>
LPI2C slave transfer structure. 

Public Members


lpi2c_slave_transfer_event_t event

Reason the callback is being invoked. 




uint8_t receivedAddress

Matching address send by master. 




uint8_t *data

Transfer buffer 




size_t dataSize

Transfer size 




status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent. 




size_t transferredCount

Number of bytes actually transferred since start or last repeated start. 







struct _lpi2c_slave_handle


#include <fsl_lpi2c.h>
LPI2C slave handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


lpi2c_slave_transfer_t transfer

LPI2C slave transfer copy. 




bool isBusy

Whether transfer is busy. 




bool wasTransmit

Whether the last transfer was a transmit. 




uint32_t eventMask

Mask of enabled events. 




uint32_t transferredCount

Count of bytes transferred. 




lpi2c_slave_transfer_callback_t callback

Callback function called at transfer event. 




void *userData

Callback parameter passed to callback. 







struct sclStall


Public Members


bool enableAck

Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall. 




bool enableTx

Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer. 




bool enableRx

Enables SCL clock stretching when receive data flag is set during a slave-receive transfer. 




bool enableAddress

Enables SCL clock stretching when the address valid flag is asserted. 







LPIT: Low-Power Interrupt Timer#


void LPIT_Init(LPIT_Type *base, const lpit_config_t *config)

Ungates the LPIT clock and configures the peripheral for a basic operation. 
This function issues a software reset to reset all channels and registers except the Module Control register.

Note
This API should be called at the beginning of the application using the LPIT driver.


Parameters:

base – LPIT peripheral base address. 
config – Pointer to the user configuration structure. 







void LPIT_Deinit(LPIT_Type *base)

Disables the module and gates the LPIT clock. 

Parameters:

base – LPIT peripheral base address. 







void LPIT_GetDefaultConfig(lpit_config_t *config)

Fills in the LPIT configuration structure with default settings. 
The default values are: 
config->enableRunInDebug = false;
config->enableRunInDoze = false;


 

Parameters:

config – Pointer to the user configuration structure. 







status_t LPIT_SetupChannel(LPIT_Type *base, lpit_chnl_t channel, const lpit_chnl_params_t *chnlSetup)

Sets up an LPIT channel based on the user’s preference. 
This function sets up the operation mode to one of the options available in the enumeration lpit_timer_modes_t. It sets the trigger source as either internal or external, trigger selection and the timers behaviour when a timeout occurs. It also chains the timer if a prior timer if requested by the user.

Parameters:

base – LPIT peripheral base address. 
channel – Channel that is being configured. 
chnlSetup – Configuration parameters. 







static inline void LPIT_EnableInterrupts(LPIT_Type *base, uint32_t mask)

Enables the selected PIT interrupts. 

Parameters:

base – LPIT peripheral base address. 
mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t







static inline void LPIT_DisableInterrupts(LPIT_Type *base, uint32_t mask)

Disables the selected PIT interrupts. 

Parameters:

base – LPIT peripheral base address. 
mask – The interrupts to enable. This is a logical OR of members of the enumeration lpit_interrupt_enable_t







static inline uint32_t LPIT_GetEnabledInterrupts(LPIT_Type *base)

Gets the enabled LPIT interrupts. 

Parameters:

base – LPIT peripheral base address.


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration lpit_interrupt_enable_t






static inline uint32_t LPIT_GetStatusFlags(LPIT_Type *base)

Gets the LPIT status flags. 

Parameters:

base – LPIT peripheral base address.


Returns:
The status flags. This is the logical OR of members of the enumeration lpit_status_flags_t






static inline void LPIT_ClearStatusFlags(LPIT_Type *base, uint32_t mask)

Clears the LPIT status flags. 

Parameters:

base – LPIT peripheral base address. 
mask – The status flags to clear. This is a logical OR of members of the enumeration lpit_status_flags_t







static inline void LPIT_SetTimerPeriod(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)

Sets the timer period in units of count. 
Timers begin counting down from the value set by this function until it reaches 0, at which point it generates an interrupt and loads this register value again. Writing a new value to this register does not restart the timer. Instead, the value is loaded after the timer expires.

Note
User can call the utility macros provided in fsl_common.h to convert to ticks.


Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 
ticks – Timer period in units of ticks. 







static inline void LPIT_SetTimerValue(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks)

Sets the timer period in units of count. 
In the Dual 16-bit Periodic Counter mode, the counter will load and then the lower 16-bits will decrement down to zero, which will assert the output pre-trigger. The upper 16-bits will then decrement down to zero, which will negate the output pre-trigger and set the timer interrupt flag.

Note
Set TVAL register to 0 or 1 is invalid in compare mode.


Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 
ticks – Timer period in units of ticks. 







static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type *base, lpit_chnl_t channel)

Reads the current timer counting value. 
This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note
User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds.


Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number.


Returns:
Current timer counting value in ticks. 






static inline void LPIT_StartTimer(LPIT_Type *base, lpit_chnl_t channel)

Starts the timer counting. 
After calling this function, timers load the period value and count down to 0. When the timer reaches 0, it generates a trigger pulse and sets the timeout interrupt flag.

Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 







static inline void LPIT_StopTimer(LPIT_Type *base, lpit_chnl_t channel)

Stops the timer counting. 

Parameters:

base – LPIT peripheral base address. 
channel – Timer channel number. 







FSL_LPIT_DRIVER_VERSION

Version 2.1.3 




enum _lpit_chnl

List of LPIT channels. 

Note
Actual number of available channels is SoC-dependent 

Values:


enumerator kLPIT_Chnl_0

LPIT channel number 0 




enumerator kLPIT_Chnl_1

LPIT channel number 1 




enumerator kLPIT_Chnl_2

LPIT channel number 2 




enumerator kLPIT_Chnl_3

LPIT channel number 3 






enum _lpit_timer_modes

Mode options available for the LPIT timer. 
Values:


enumerator kLPIT_PeriodicCounter

Use the all 32-bits, counter loads and decrements to zero 




enumerator kLPIT_DualPeriodicCounter

Counter loads, lower 16-bits decrement to zero, then upper 16-bits decrement 




enumerator kLPIT_TriggerAccumulator

Counter loads on first trigger and decrements on each trigger 




enumerator kLPIT_InputCapture

Counter loads with 0xFFFFFFFF, decrements to zero. It stores the inverse of the current value when a input trigger is detected 






enum _lpit_trigger_select

Trigger options available. 
This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual. 
Values:


enumerator kLPIT_Trigger_TimerChn0

Channel 0 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn1

Channel 1 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn2

Channel 2 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn3

Channel 3 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn4

Channel 4 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn5

Channel 5 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn6

Channel 6 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn7

Channel 7 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn8

Channel 8 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn9

Channel 9 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn10

Channel 10 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn11

Channel 11 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn12

Channel 12 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn13

Channel 13 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn14

Channel 14 is selected as a trigger source 




enumerator kLPIT_Trigger_TimerChn15

Channel 15 is selected as a trigger source 






enum _lpit_trigger_source

Trigger source options available. 
Values:


enumerator kLPIT_TriggerSource_External

Use external trigger input 




enumerator kLPIT_TriggerSource_Internal

Use internal trigger 






enum _lpit_interrupt_enable

List of LPIT interrupts. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 

Values:


enumerator kLPIT_Channel0TimerInterruptEnable

Channel 0 Timer interrupt 




enumerator kLPIT_Channel1TimerInterruptEnable

Channel 1 Timer interrupt 




enumerator kLPIT_Channel2TimerInterruptEnable

Channel 2 Timer interrupt 




enumerator kLPIT_Channel3TimerInterruptEnable

Channel 3 Timer interrupt 






enum _lpit_status_flags

List of LPIT status flags. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 

Values:


enumerator kLPIT_Channel0TimerFlag

Channel 0 Timer interrupt flag 




enumerator kLPIT_Channel1TimerFlag

Channel 1 Timer interrupt flag 




enumerator kLPIT_Channel2TimerFlag

Channel 2 Timer interrupt flag 




enumerator kLPIT_Channel3TimerFlag

Channel 3 Timer interrupt flag 






typedef enum _lpit_chnl lpit_chnl_t

List of LPIT channels. 

Note
Actual number of available channels is SoC-dependent 





typedef enum _lpit_timer_modes lpit_timer_modes_t

Mode options available for the LPIT timer. 




typedef enum _lpit_trigger_select lpit_trigger_select_t

Trigger options available. 
This is used for both internal and external trigger sources. The actual trigger options available is SoC-specific, user should refer to the reference manual. 




typedef enum _lpit_trigger_source lpit_trigger_source_t

Trigger source options available. 




typedef enum _lpit_interrupt_enable lpit_interrupt_enable_t

List of LPIT interrupts. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 





typedef enum _lpit_status_flags lpit_status_flags_t

List of LPIT status flags. 

Note
Number of timer channels are SoC-specific. See the SoC Reference Manual. 





typedef struct _lpit_chnl_params lpit_chnl_params_t

Structure to configure the channel timer. 




typedef struct _lpit_config lpit_config_t

LPIT configuration structure. 
This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.
The configuration structure can be made constant so as to reside in flash. 




static void LPIT_ResetStateDelay(void)

Short wait for LPIT state reset. 
After clear or set LPIT_EN, there should be delay longer than 4 LPIT functional clock. 




static inline void LPIT_Reset(LPIT_Type *base)

Performs a software reset on the LPIT module. 
This resets all channels and registers except the Module Control Register.

Parameters:

base – LPIT peripheral base address. 







LPIT_RESET_STATE_DELAY

Delay used in LPIT_Reset. 
The macro value should be larger than 4 * core clock / LPIT peripheral clock. 




struct _lpit_chnl_params


#include <fsl_lpit.h>
Structure to configure the channel timer. 

Public Members


bool chainChannel

true: Timer chained to previous timer; false: Timer not chained 




lpit_timer_modes_t timerMode

Timers mode of operation. 




lpit_trigger_select_t triggerSelect

Trigger selection for the timer 




lpit_trigger_source_t triggerSource

Decides if we use external or internal trigger. 




bool enableReloadOnTrigger

true: Timer reloads when a trigger is detected; false: No effect 




bool enableStopOnTimeout

true: Timer will stop after timeout; false: does not stop after timeout 




bool enableStartOnTrigger

true: Timer starts when a trigger is detected; false: decrement immediately 







struct _lpit_config


#include <fsl_lpit.h>
LPIT configuration structure. 
This structure holds the configuration settings for the LPIT peripheral. To initialize this structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.
The configuration structure can be made constant so as to reside in flash. 

Public Members


bool enableRunInDebug

true: Timers run in debug mode; false: Timers stop in debug mode 




bool enableRunInDoze

true: Timers run in doze mode; false: Timers stop in doze mode 







LPSPI: Low Power Serial Peripheral Interface#


LPSPI Peripheral driver#


void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the LPSPI master. 

Parameters:

base – LPSPI peripheral address. 
masterConfig – Pointer to structure lpspi_master_config_t. 
srcClock_Hz – Module source input clock in Hertz 







void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)

Sets the lpspi_master_config_t structure to default values. 
This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example: 
lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);


 

Parameters:

masterConfig – pointer to lpspi_master_config_t structure 







void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)

LPSPI slave configuration. 

Parameters:

base – LPSPI peripheral address. 
slaveConfig – Pointer to a structure lpspi_slave_config_t. 







void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)

Sets the lpspi_slave_config_t structure to default values. 
This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example: 
lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);


 

Parameters:

slaveConfig – pointer to lpspi_slave_config_t structure. 







void LPSPI_Deinit(LPSPI_Type *base)

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. 

Parameters:

base – LPSPI peripheral address. 







void LPSPI_Reset(LPSPI_Type *base)

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API. 

Parameters:

base – LPSPI peripheral address. 







uint32_t LPSPI_GetInstance(LPSPI_Type *base)

Get the LPSPI instance from peripheral base address. 

Parameters:

base – LPSPI peripheral base address. 


Returns:
LPSPI instance. 






static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)

Enables the LPSPI peripheral and sets the MCR MDIS to 0. 

Parameters:

base – LPSPI peripheral address. 
enable – Pass true to enable module, false to disable module. 







static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)

Gets the LPSPI status flag state. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI status(in SR register). 






static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)

Gets the LPSPI Tx FIFO size. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Tx FIFO size. 






static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)

Gets the LPSPI Rx FIFO size. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Rx FIFO size. 






static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)

Gets the LPSPI Tx FIFO count. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The number of words in the transmit FIFO. 






static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)

Gets the LPSPI Rx FIFO count. 

Parameters:

base – LPSPI peripheral address. 


Returns:
The number of words in the receive FIFO. 






static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)

Clears the LPSPI status flag. 
This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage: 
LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);




Parameters:

base – LPSPI peripheral address. 
statusFlags – The status flag used from type _lpspi_flags. 







static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)





static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI interrupts. 
This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );



Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable. 







static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI interrupts. 
LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );



Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable. 







static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI DMA request. 
This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. 
LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);




Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_dma_enable. 







static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI DMA request. 
This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. 
SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);




Parameters:

base – LPSPI peripheral address. 
mask – The interrupt mask; Use the enum _lpspi_dma_enable. 







static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Transmit Data Register address for a DMA operation. 
This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Transmit Data Register address. 






static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Receive Data Register address for a DMA operation. 
This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address. 


Returns:
The LPSPI Receive Data Register address. 






bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)

Check the argument for transfer . 

Parameters:

base – LPSPI peripheral address. 
transfer – the transfer struct to be used. 
isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer 


Returns:
Return true for right and false for wrong. 






static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)

Configures the LPSPI for either master or slave. 
Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters:

base – LPSPI peripheral address. 
mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t. 







static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)

Configures the peripheral chip select used for the transfer. 

Parameters:

base – LPSPI peripheral address. 
select – LPSPI Peripheral Chip Select (PCS) configuration. 







static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)

Set the PCS signal to continuous or uncontinuous mode. 

Note
In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).


Parameters:

base – LPSPI peripheral address. 
IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. 







static inline bool LPSPI_IsMaster(LPSPI_Type *base)

Returns whether the LPSPI module is in master mode. 

Parameters:

base – LPSPI peripheral address. 


Returns:
Returns true if the module is in master mode or false if the module is in slave mode. 






static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)

Flushes the LPSPI FIFOs. 

Parameters:

base – LPSPI peripheral address. 
flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. 
flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. 







static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)

Sets the transmit and receive FIFO watermark values. 
This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters:

base – LPSPI peripheral address. 
txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. 
rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. 







static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)

Configures all LPSPI peripheral chip select polarities simultaneously. 
Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific. 
LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);




Parameters:

base – LPSPI peripheral address. 
mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity. 







static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)

Configures the frame size. 
The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.
Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters:

base – LPSPI peripheral address. 
frameSize – The frame size in number of bits. 







uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)

Sets the LPSPI baud rate in bits per second. 
This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address. 
baudRate_Bps – The desired baud rate in bits per second. 
srcClock_Hz – Module source input clock in Hertz. 
tcrPrescaleValue – The TCR prescale value needed to program the TCR. 


Returns:
The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled. 






void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values). 
This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.
The delay names are available in type lpspi_delay_type_t.
The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.
Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address. 
scaler – The 8-bit delay value 0x00 to 0xFF (255). 
whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t. 







uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values). 
This function calculates the values for the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.
The delay names are available in type lpspi_delay_type_t.
The user passes the desired delay and the desired delay value in nano-seconds. The function calculates the value needed for the desired delay parameter and returns the actual calculated delay because an exact delay match may not be possible. In this case, the closest match is calculated without going below the desired delay value input. It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum supported delay is returned. It is up to the higher level peripheral driver to alert the user of an out of range delay input.
Note that the LPSPI module must be configured for master mode before configuring this. And note that the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).

Parameters:

base – LPSPI peripheral address. 
delayTimeInNanoSec – The desired delay value in nano-seconds. 
whichDelay – The desired delay to configuration, which must be of type lpspi_delay_type_t. 
srcClock_Hz – Module source input clock in Hertz. 


Returns:
actual Calculated delay value in nano-seconds. 






static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)

Writes data into the transmit data buffer. 
This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters:

base – LPSPI peripheral address. 
data – The data word to be sent. 







static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)

Reads data from the data buffer. 
This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address. 


Returns:
The data read from the data buffer. 






void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)

Set up the dummy data. 

Parameters:

base – LPSPI peripheral address. 
dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated. 







void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)

Initializes the LPSPI master handle. 
This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

base – LPSPI peripheral address. 
handle – LPSPI handle pointer to lpspi_master_handle_t. 
callback – DSPI callback. 
userData – callback function parameter. 







status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)

LPSPI master transfer data using a polling method. 
This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using an interrupt method. 
This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)

Gets the master transfer remaining bytes. 
This function gets the master transfer remaining bytes.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the non-blocking transaction. 


Returns:
status of status_t. 






void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI master abort transfer which uses an interrupt method. 
This function aborts a transfer which uses an interrupt method.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 







void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI Master IRQ handler function. 
This function processes the LPSPI transmit and receive IRQ.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_master_handle_t structure which stores the transfer state. 







void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)

Initializes the LPSPI slave handle. 
This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

base – LPSPI peripheral address. 
handle – LPSPI handle pointer to lpspi_slave_handle_t. 
callback – DSPI callback. 
userData – callback function parameter. 







status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfer data using an interrupt method. 
This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)

Gets the slave transfer remaining bytes. 
This function gets the slave transfer remaining bytes.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the non-blocking transaction. 


Returns:
status of status_t. 






void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI slave aborts a transfer which uses an interrupt method. 
This function aborts a transfer which uses an interrupt method.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 







void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI Slave IRQ handler function. 
This function processes the LPSPI transmit and receives an IRQ.

Parameters:

base – LPSPI peripheral address. 
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state. 







bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)

Wait for tx FIFO to be empty. 
This function wait the tx fifo empty

Parameters:

base – LPSPI peripheral address. 


Returns:
true for the tx FIFO is ready, false is not. 






void LPSPI_DriverIRQHandler(uint32_t instance)

LPSPI driver IRQ handler common entry. 
This function provides the common IRQ request entry for LPSPI.

Parameters:

instance – LPSPI instance. 







FSL_LPSPI_DRIVER_VERSION

LPSPI driver version. 





Status for the LPSPI driver. 
Values:


enumerator kStatus_LPSPI_Busy

LPSPI transfer is busy. 




enumerator kStatus_LPSPI_Error

LPSPI driver error. 




enumerator kStatus_LPSPI_Idle

LPSPI is idle. 




enumerator kStatus_LPSPI_OutOfRange

LPSPI transfer out Of range. 




enumerator kStatus_LPSPI_Timeout

LPSPI timeout polling status flags. 






enum _lpspi_flags

LPSPI status flags in SPIx_SR register. 
Values:


enumerator kLPSPI_TxDataRequestFlag

Transmit data flag 




enumerator kLPSPI_RxDataReadyFlag

Receive data flag 




enumerator kLPSPI_WordCompleteFlag

Word Complete flag 




enumerator kLPSPI_FrameCompleteFlag

Frame Complete flag 




enumerator kLPSPI_TransferCompleteFlag

Transfer Complete flag 




enumerator kLPSPI_TransmitErrorFlag

Transmit Error flag (FIFO underrun) 




enumerator kLPSPI_ReceiveErrorFlag

Receive Error flag (FIFO overrun) 




enumerator kLPSPI_DataMatchFlag

Data Match flag 




enumerator kLPSPI_ModuleBusyFlag

Module Busy flag 




enumerator kLPSPI_AllStatusFlag

Used for clearing all w1c status flags 






enum _lpspi_interrupt_enable

LPSPI interrupt source. 
Values:


enumerator kLPSPI_TxInterruptEnable

Transmit data interrupt enable 




enumerator kLPSPI_RxInterruptEnable

Receive data interrupt enable 




enumerator kLPSPI_WordCompleteInterruptEnable

Word complete interrupt enable 




enumerator kLPSPI_FrameCompleteInterruptEnable

Frame complete interrupt enable 




enumerator kLPSPI_TransferCompleteInterruptEnable

Transfer complete interrupt enable 




enumerator kLPSPI_TransmitErrorInterruptEnable

Transmit error interrupt enable(FIFO underrun) 




enumerator kLPSPI_ReceiveErrorInterruptEnable

Receive Error interrupt enable (FIFO overrun) 




enumerator kLPSPI_DataMatchInterruptEnable

Data Match interrupt enable 




enumerator kLPSPI_AllInterruptEnable

All above interrupts enable. 






enum _lpspi_dma_enable

LPSPI DMA source. 
Values:


enumerator kLPSPI_TxDmaEnable

Transmit data DMA enable 




enumerator kLPSPI_RxDmaEnable

Receive data DMA enable 






enum _lpspi_master_slave_mode

LPSPI master or slave mode configuration. 
Values:


enumerator kLPSPI_Master

LPSPI peripheral operates in master mode. 




enumerator kLPSPI_Slave

LPSPI peripheral operates in slave mode. 






enum _lpspi_which_pcs_config

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure). 
Values:


enumerator kLPSPI_Pcs0

PCS[0] 




enumerator kLPSPI_Pcs1

PCS[1] 




enumerator kLPSPI_Pcs2

PCS[2] 




enumerator kLPSPI_Pcs3

PCS[3] 






enum _lpspi_pcs_polarity_config

LPSPI Peripheral Chip Select (PCS) Polarity configuration. 
Values:


enumerator kLPSPI_PcsActiveHigh

PCS Active High (idles low) 




enumerator kLPSPI_PcsActiveLow

PCS Active Low (idles high) 






enum _lpspi_pcs_polarity

LPSPI Peripheral Chip Select (PCS) Polarity. 
Values:


enumerator kLPSPI_Pcs0ActiveLow

Pcs0 Active Low (idles high). 




enumerator kLPSPI_Pcs1ActiveLow

Pcs1 Active Low (idles high). 




enumerator kLPSPI_Pcs2ActiveLow

Pcs2 Active Low (idles high). 




enumerator kLPSPI_Pcs3ActiveLow

Pcs3 Active Low (idles high). 




enumerator kLPSPI_PcsAllActiveLow

Pcs0 to Pcs5 Active Low (idles high). 






enum _lpspi_clock_polarity

LPSPI clock polarity configuration. 
Values:


enumerator kLPSPI_ClockPolarityActiveHigh

CPOL=0. Active-high LPSPI clock (idles low) 




enumerator kLPSPI_ClockPolarityActiveLow

CPOL=1. Active-low LPSPI clock (idles high) 






enum _lpspi_clock_phase

LPSPI clock phase configuration. 
Values:


enumerator kLPSPI_ClockPhaseFirstEdge

CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge. 




enumerator kLPSPI_ClockPhaseSecondEdge

CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge. 






enum _lpspi_shift_direction

LPSPI data shifter direction options. 
Values:


enumerator kLPSPI_MsbFirst

Data transfers start with most significant bit. 




enumerator kLPSPI_LsbFirst

Data transfers start with least significant bit. 






enum _lpspi_host_request_select

LPSPI Host Request select configuration. 
Values:


enumerator kLPSPI_HostReqExtPin

Host Request is an ext pin. 




enumerator kLPSPI_HostReqInternalTrigger

Host Request is an internal trigger. 






enum _lpspi_match_config

LPSPI Match configuration options. 
Values:


enumerator kLPSI_MatchDisabled

LPSPI Match Disabled. 




enumerator kLPSI_1stWordEqualsM0orM1

LPSPI Match Enabled. 




enumerator kLPSI_AnyWordEqualsM0orM1

LPSPI Match Enabled. 




enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1

LPSPI Match Enabled. 




enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1

LPSPI Match Enabled. 




enumerator kLPSI_1stWordAndM1EqualsM0andM1

LPSPI Match Enabled. 




enumerator kLPSI_AnyWordAndM1EqualsM0andM1

LPSPI Match Enabled. 






enum _lpspi_pin_config

LPSPI pin (SDO and SDI) configuration. 
Values:


enumerator kLPSPI_SdiInSdoOut

LPSPI SDI input, SDO output. 




enumerator kLPSPI_SdiInSdiOut

LPSPI SDI input, SDI output. 




enumerator kLPSPI_SdoInSdoOut

LPSPI SDO input, SDO output. 




enumerator kLPSPI_SdoInSdiOut

LPSPI SDO input, SDI output. 






enum _lpspi_data_out_config

LPSPI data output configuration. 
Values:


enumerator kLpspiDataOutRetained

Data out retains last value when chip select is de-asserted 




enumerator kLpspiDataOutTristate

Data out is tristated when chip select is de-asserted 






enum _lpspi_transfer_width

LPSPI transfer width configuration. 
Values:


enumerator kLPSPI_SingleBitXfer

1-bit shift at a time, data out on SDO, in on SDI (normal mode) 




enumerator kLPSPI_TwoBitXfer

2-bits shift out on SDO/SDI and in on SDO/SDI 




enumerator kLPSPI_FourBitXfer

4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] 






enum _lpspi_delay_type

LPSPI delay type selection. 
Values:


enumerator kLPSPI_PcsToSck

PCS-to-SCK delay. 




enumerator kLPSPI_LastSckToPcs

Last SCK edge to PCS delay. 




enumerator kLPSPI_BetweenTransfer

Delay between transfers. 






enum _lpspi_transfer_config_flag_for_master

Use this enumeration for LPSPI master transfer configFlags. 
Values:


enumerator kLPSPI_MasterPcs0

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal 




enumerator kLPSPI_MasterPcs1

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal 




enumerator kLPSPI_MasterPcs2

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal 




enumerator kLPSPI_MasterPcs3

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal 




enumerator kLPSPI_MasterPcsContinuous

Is PCS signal continuous 




enumerator kLPSPI_MasterByteSwap

Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. 








enum _lpspi_transfer_config_flag_for_slave

Use this enumeration for LPSPI slave transfer configFlags. 
Values:


enumerator kLPSPI_SlavePcs0

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal 




enumerator kLPSPI_SlavePcs1

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal 




enumerator kLPSPI_SlavePcs2

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal 




enumerator kLPSPI_SlavePcs3

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal 




enumerator kLPSPI_SlaveByteSwap

Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. 








enum _lpspi_transfer_state

LPSPI transfer state, which is used for LPSPI transactional API state machine. 
Values:


enumerator kLPSPI_Idle

Nothing in the transmitter/receiver. 




enumerator kLPSPI_Busy

Transfer queue is not finished. 




enumerator kLPSPI_Error

Transfer error. 






typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t

LPSPI master or slave mode configuration. 




typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure). 




typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t

LPSPI Peripheral Chip Select (PCS) Polarity configuration. 




typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t

LPSPI clock polarity configuration. 




typedef enum _lpspi_clock_phase lpspi_clock_phase_t

LPSPI clock phase configuration. 




typedef enum _lpspi_shift_direction lpspi_shift_direction_t

LPSPI data shifter direction options. 




typedef enum _lpspi_host_request_select lpspi_host_request_select_t

LPSPI Host Request select configuration. 




typedef enum _lpspi_match_config lpspi_match_config_t

LPSPI Match configuration options. 




typedef enum _lpspi_pin_config lpspi_pin_config_t

LPSPI pin (SDO and SDI) configuration. 




typedef enum _lpspi_data_out_config lpspi_data_out_config_t

LPSPI data output configuration. 




typedef enum _lpspi_transfer_width lpspi_transfer_width_t

LPSPI transfer width configuration. 




typedef enum _lpspi_delay_type lpspi_delay_type_t

LPSPI delay type selection. 




typedef struct _lpspi_master_config lpspi_master_config_t

LPSPI master configuration structure. 




typedef struct _lpspi_slave_config lpspi_slave_config_t

LPSPI slave configuration structure. 




typedef struct _lpspi_master_handle lpspi_master_handle_t

Forward declaration of the _lpspi_master_handle typedefs. 




typedef struct _lpspi_slave_handle lpspi_slave_handle_t

Forward declaration of the _lpspi_slave_handle typedefs. 




typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)

Master completion callback function pointer type. 

Param base:
LPSPI peripheral address. 

Param handle:
Pointer to the handle for the LPSPI master. 

Param status:
Success or error code describing whether the transfer is completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)

Slave completion callback function pointer type. 

Param base:
LPSPI peripheral address. 

Param handle:
Pointer to the handle for the LPSPI slave. 

Param status:
Success or error code describing whether the transfer is completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






typedef struct _lpspi_transfer lpspi_transfer_t

LPSPI master/slave transfer structure. 




volatile uint8_t g_lpspiDummyData[]

Global variable for dummy data value setting. 




LPSPI_DUMMY_DATA

LPSPI dummy data if no Tx data. 
Dummy data used for tx if there is not txData. 




SPI_RETRY_TIMES

Retry times for waiting flag. 




LPSPI_MASTER_PCS_SHIFT

LPSPI master PCS shift macro , internal used. 




LPSPI_MASTER_PCS_MASK

LPSPI master PCS shift macro , internal used. 




LPSPI_SLAVE_PCS_SHIFT

LPSPI slave PCS shift macro , internal used. 




LPSPI_SLAVE_PCS_MASK

LPSPI slave PCS shift macro , internal used. 




struct _lpspi_master_config


#include <fsl_lpspi.h>
LPSPI master configuration structure. 

Public Members


uint32_t baudRate

Baud Rate for LPSPI. 




uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096. 




lpspi_clock_polarity_t cpol

Clock polarity. 




lpspi_clock_phase_t cpha

Clock phase. 




lpspi_shift_direction_t direction

MSB or LSB data shift direction. 




uint32_t pcsToSckDelayInNanoSec

PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range. 




uint32_t lastSckToPcsDelayInNanoSec

Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range. 




uint32_t betweenTransferDelayInNanoSec

After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range. 




lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (PCS). 




lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low 




lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers. 




lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated). 




bool enableInputDelay

Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length. 







struct _lpspi_slave_config


#include <fsl_lpspi.h>
LPSPI slave configuration structure. 

Public Members


uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096. 




lpspi_clock_polarity_t cpol

Clock polarity. 




lpspi_clock_phase_t cpha

Clock phase. 




lpspi_shift_direction_t direction

MSB or LSB data shift direction. 




lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (pcs) 




lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low 




lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers. 




lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated). 







struct _lpspi_transfer


#include <fsl_lpspi.h>
LPSPI master/slave transfer structure. 

Public Members


const uint8_t *txData

Send buffer. 




uint8_t *rxData

Receive buffer. 




volatile size_t dataSize

Transfer bytes. 




uint32_t configFlags

Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave. 







struct _lpspi_master_handle


#include <fsl_lpspi.h>
LPSPI master transfer handle structure used for transactional API. 

Public Members


volatile bool isPcsContinuous

Is PCS continuous in transfer. 




volatile bool writeTcrInIsr

A flag that whether should write TCR in ISR. 




volatile bool isByteSwap

A flag that whether should byte swap. 




volatile bool isTxMask

A flag that whether TCR[TXMSK] is set. 




volatile uint16_t bytesPerFrame

Number of bytes in each frame 




volatile uint16_t frameSize

Backup of TCR[FRAMESZ] 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




uint32_t txBuffIfNull

Used if the txData is NULL. 




volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state. 




lpspi_master_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 







struct _lpspi_slave_handle


#include <fsl_lpspi.h>
LPSPI slave transfer handle structure used for transactional API. 

Public Members


volatile bool isByteSwap

A flag that whether should byte swap. 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state. 




volatile uint32_t errorCount

Error count for slave transfer. 




lpspi_slave_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 







LPSPI eDMA Driver#


FSL_LPSPI_EDMA_DRIVER_VERSION

LPSPI EDMA driver version. 




DMA_MAX_TRANSFER_COUNT

DMA max transfer size. 




typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t

Forward declaration of the _lpspi_master_edma_handle typedefs. 




typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t

Forward declaration of the _lpspi_slave_edma_handle typedefs. 




typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type. 

Param base:
LPSPI peripheral base address. 

Param handle:
Pointer to the handle for the LPSPI master. 

Param status:
Success or error code describing whether the transfer completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type. 

Param base:
LPSPI peripheral base address. 

Param handle:
Pointer to the handle for the LPSPI slave. 

Param status:
Success or error code describing whether the transfer completed. 

Param userData:
Arbitrary pointer-dataSized value passed from the application. 






void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI master eDMA handle. 
This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.

Parameters:

base – LPSPI peripheral base address. 
handle – LPSPI handle pointer to lpspi_master_edma_handle_t. 
callback – LPSPI callback. 
userData – callback function parameter. 
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t. 
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t. 







status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA. 
This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)

LPSPI master config transfer parameter while using eDMA. 
This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master. 


Return values:

kStatus_Success – Execution successfully. 
kStatus_LPSPI_Busy – The LPSPI device is busy. 


Returns:
Indicates whether LPSPI master transfer was successful or not. 






status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA without configs. 
This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.
Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure, config field is not uesed. 


Return values:

kStatus_Success – Execution successfully. 
kStatus_LPSPI_Busy – The LPSPI device is busy. 
kStatus_InvalidArgument – The transfer structure is invalid. 


Returns:
Indicates whether LPSPI master transfer was successful or not. 






void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)

LPSPI master aborts a transfer which is using eDMA. 
This function aborts a transfer which is using eDMA.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 







status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)

Gets the master eDMA transfer remaining bytes. 
This function gets the master eDMA transfer remaining bytes.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the EDMA transaction. 


Returns:
status of status_t. 






void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI slave eDMA handle. 
This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.
Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.
(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .

Parameters:

base – LPSPI peripheral base address. 
handle – LPSPI handle pointer to lpspi_slave_edma_handle_t. 
callback – LPSPI callback. 
userData – callback function parameter. 
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t. 
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t. 







status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfers data using eDMA. 
This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.
Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. 
transfer – pointer to lpspi_transfer_t structure. 


Returns:
status of status_t. 






void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)

LPSPI slave aborts a transfer which is using eDMA. 
This function aborts a transfer which is using eDMA.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. 







status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)

Gets the slave eDMA transfer remaining bytes. 
This function gets the slave eDMA transfer remaining bytes.

Parameters:

base – LPSPI peripheral base address. 
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. 
count – Number of bytes transferred so far by the eDMA transaction. 


Returns:
status of status_t. 






struct _lpspi_master_edma_handle


#include <fsl_lpspi_edma.h>
LPSPI master eDMA transfer handle structure used for transactional API. 

Public Members


volatile bool isPcsContinuous

Is PCS continuous in transfer. 




volatile bool isByteSwap

A flag that whether should byte swap. 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




volatile uint8_t bytesLastRead

Bytes for last read RDR. 




volatile bool isThereExtraRxBytes

Is there extra RX byte. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




edma_tcd_t *lastTimeTCD

Pointer to the lastTime TCD 




bool isMultiDMATransmit

Is there multi DMA transmit 




volatile uint8_t dmaTransmitTime

DMA Transfer times. 




uint32_t lastTimeDataBytes

DMA transmit last Time data Bytes 




uint32_t dataBytesEveryTime

Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT 




edma_transfer_config_t transferConfigRx

Config of DMA rx channel. 




edma_transfer_config_t transferConfigTx

Config of DMA tx channel. 




uint32_t txBuffIfNull

Used if there is not txData for DMA purpose. 




uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose. 




uint32_t transmitCommand

Used to write TCR for DMA purpose. 




volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




lpspi_master_edma_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 




edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff 




edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg buff 




edma_tcd_t lpspiSoftwareTCD[3]

SoftwareTCD, internal used 







struct _lpspi_slave_edma_handle


#include <fsl_lpspi_edma.h>
LPSPI slave eDMA transfer handle structure used for transactional API. 

Public Members


volatile bool isByteSwap

A flag that whether should byte swap. 




volatile uint8_t fifoSize

FIFO dataSize. 




volatile uint8_t rxWatermark

Rx watermark. 




volatile uint8_t bytesEachWrite

Bytes for each write TDR. 




volatile uint8_t bytesEachRead

Bytes for each read RDR. 




volatile uint8_t bytesLastRead

Bytes for last read RDR. 




volatile bool isThereExtraRxBytes

Is there extra RX byte. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




const uint8_t *volatile txData

Send buffer. 




uint8_t *volatile rxData

Receive buffer. 




volatile size_t txRemainingByteCount

Number of bytes remaining to send. 




volatile size_t rxRemainingByteCount

Number of bytes remaining to receive. 




volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times. 




volatile uint32_t readRegRemainingTimes

Read RDR register remaining times. 




uint32_t totalByteCount

Number of transfer bytes 




uint32_t txBuffIfNull

Used if there is not txData for DMA purpose. 




uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose. 




volatile uint8_t state

LPSPI transfer state. 




uint32_t errorCount

Error count for slave transfer. 




lpspi_slave_edma_transfer_callback_t callback

Completion callback. 




void *userData

Callback user data. 




edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff 




edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg 




edma_tcd_t lpspiSoftwareTCD[2]

SoftwareTCD, internal used 







LPTMR: Low-Power Timer#


void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)

Ungates the LPTMR clock and configures the peripheral for a basic operation. 

Note
This API should be called at the beginning of the application using the LPTMR driver.


Parameters:

base – LPTMR peripheral base address 
config – A pointer to the LPTMR configuration structure. 







void LPTMR_Deinit(LPTMR_Type *base)

Gates the LPTMR clock. 

Parameters:

base – LPTMR peripheral base address 







void LPTMR_GetDefaultConfig(lptmr_config_t *config)

Fills in the LPTMR configuration structure with default settings. 
The default values are as follows. 
config->timerMode = kLPTMR_TimerModeTimeCounter;
config->pinSelect = kLPTMR_PinSelectInput_0;
config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
config->enableFreeRunning = false;
config->bypassPrescaler = true;
config->prescalerClockSource = kLPTMR_PrescalerClock_1;
config->value = kLPTMR_Prescale_Glitch_0;


 

Parameters:

config – A pointer to the LPTMR configuration structure. 







static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)

Enables the selected LPTMR interrupts. 

Parameters:

base – LPTMR peripheral base address 
mask – The interrupts to enable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t







static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)

Disables the selected LPTMR interrupts. 

Parameters:

base – LPTMR peripheral base address 
mask – The interrupts to disable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t. 







static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)

Gets the enabled LPTMR interrupts. 

Parameters:

base – LPTMR peripheral base address


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration lptmr_interrupt_enable_t






static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)

Gets the LPTMR status flags. 

Parameters:

base – LPTMR peripheral base address


Returns:
The status flags. This is the logical OR of members of the enumeration lptmr_status_flags_t






static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)

Clears the LPTMR status flags. 

Parameters:

base – LPTMR peripheral base address 
mask – The status flags to clear. This is a logical OR of members of the enumeration lptmr_status_flags_t. 







static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)

Sets the timer period in units of count. 
Timers counts from 0 until it equals the count value set here. The count value is written to the CMR register.

Note

The TCF flag is set with the CNR equals the count provided here and then increments.
Call the utility macros provided in the fsl_common.h to convert to ticks.




Parameters:

base – LPTMR peripheral base address 
ticks – A timer period in units of ticks 







static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)

Reads the current timer counting value. 
This function returns the real-time timer counting value in a range from 0 to a timer period.

Note
Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.


Parameters:

base – LPTMR peripheral base address


Returns:
The current counter value in ticks 






static inline void LPTMR_StartTimer(LPTMR_Type *base)

Starts the timer. 
After calling this function, the timer counts up to the CMR register value. Each time the timer reaches the CMR value and then increments, it generates a trigger pulse and sets the timeout interrupt flag. An interrupt is also triggered if the timer interrupt is enabled.

Parameters:

base – LPTMR peripheral base address 







static inline void LPTMR_StopTimer(LPTMR_Type *base)

Stops the timer. 
This function stops the timer and resets the timer’s counter register.

Parameters:

base – LPTMR peripheral base address 







FSL_LPTMR_DRIVER_VERSION

Driver Version 




enum _lptmr_pin_select

LPTMR pin selection used in pulse counter mode. 
Values:


enumerator kLPTMR_PinSelectInput_0

Pulse counter input 0 is selected 




enumerator kLPTMR_PinSelectInput_1

Pulse counter input 1 is selected 




enumerator kLPTMR_PinSelectInput_2

Pulse counter input 2 is selected 




enumerator kLPTMR_PinSelectInput_3

Pulse counter input 3 is selected 






enum _lptmr_pin_polarity

LPTMR pin polarity used in pulse counter mode. 
Values:


enumerator kLPTMR_PinPolarityActiveHigh

Pulse Counter input source is active-high 




enumerator kLPTMR_PinPolarityActiveLow

Pulse Counter input source is active-low 






enum _lptmr_timer_mode

LPTMR timer mode selection. 
Values:


enumerator kLPTMR_TimerModeTimeCounter

Time Counter mode 




enumerator kLPTMR_TimerModePulseCounter

Pulse Counter mode 






enum _lptmr_prescaler_glitch_value

LPTMR prescaler/glitch filter values. 
Values:


enumerator kLPTMR_Prescale_Glitch_0

Prescaler divide 2, glitch filter does not support this setting 




enumerator kLPTMR_Prescale_Glitch_1

Prescaler divide 4, glitch filter 2 




enumerator kLPTMR_Prescale_Glitch_2

Prescaler divide 8, glitch filter 4 




enumerator kLPTMR_Prescale_Glitch_3

Prescaler divide 16, glitch filter 8 




enumerator kLPTMR_Prescale_Glitch_4

Prescaler divide 32, glitch filter 16 




enumerator kLPTMR_Prescale_Glitch_5

Prescaler divide 64, glitch filter 32 




enumerator kLPTMR_Prescale_Glitch_6

Prescaler divide 128, glitch filter 64 




enumerator kLPTMR_Prescale_Glitch_7

Prescaler divide 256, glitch filter 128 




enumerator kLPTMR_Prescale_Glitch_8

Prescaler divide 512, glitch filter 256 




enumerator kLPTMR_Prescale_Glitch_9

Prescaler divide 1024, glitch filter 512 




enumerator kLPTMR_Prescale_Glitch_10

Prescaler divide 2048 glitch filter 1024 




enumerator kLPTMR_Prescale_Glitch_11

Prescaler divide 4096, glitch filter 2048 




enumerator kLPTMR_Prescale_Glitch_12

Prescaler divide 8192, glitch filter 4096 




enumerator kLPTMR_Prescale_Glitch_13

Prescaler divide 16384, glitch filter 8192 




enumerator kLPTMR_Prescale_Glitch_14

Prescaler divide 32768, glitch filter 16384 




enumerator kLPTMR_Prescale_Glitch_15

Prescaler divide 65536, glitch filter 32768 






enum _lptmr_prescaler_clock_select

LPTMR prescaler/glitch filter clock select. 

Note
Clock connections are SoC-specific 

Values:




enum _lptmr_interrupt_enable

List of the LPTMR interrupts. 
Values:


enumerator kLPTMR_TimerInterruptEnable

Timer interrupt enable 






enum _lptmr_status_flags

List of the LPTMR status flags. 
Values:


enumerator kLPTMR_TimerCompareFlag

Timer compare flag 






typedef enum _lptmr_pin_select lptmr_pin_select_t

LPTMR pin selection used in pulse counter mode. 




typedef enum _lptmr_pin_polarity lptmr_pin_polarity_t

LPTMR pin polarity used in pulse counter mode. 




typedef enum _lptmr_timer_mode lptmr_timer_mode_t

LPTMR timer mode selection. 




typedef enum _lptmr_prescaler_glitch_value lptmr_prescaler_glitch_value_t

LPTMR prescaler/glitch filter values. 




typedef enum _lptmr_prescaler_clock_select lptmr_prescaler_clock_select_t

LPTMR prescaler/glitch filter clock select. 

Note
Clock connections are SoC-specific 





typedef enum _lptmr_interrupt_enable lptmr_interrupt_enable_t

List of the LPTMR interrupts. 




typedef enum _lptmr_status_flags lptmr_status_flags_t

List of the LPTMR status flags. 




typedef struct _lptmr_config lptmr_config_t

LPTMR config structure. 
This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration struct can be made constant so it resides in flash. 




static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)

Enable or disable timer DMA request. 

Parameters:

base – base LPTMR peripheral base address 
enable – Switcher of timer DMA feature. “true” means to enable, “false” means to disable. 







struct _lptmr_config


#include <fsl_lptmr.h>
LPTMR config structure. 
This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration struct can be made constant so it resides in flash. 

Public Members


lptmr_timer_mode_t timerMode

Time counter mode or pulse counter mode 




lptmr_pin_select_t pinSelect

LPTMR pulse input pin select; used only in pulse counter mode 




lptmr_pin_polarity_t pinPolarity

LPTMR pulse input pin polarity; used only in pulse counter mode 




bool enableFreeRunning

True: enable free running, counter is reset on overflow False: counter is reset when the compare flag is set 




bool bypassPrescaler

True: bypass prescaler; false: use clock from prescaler 




lptmr_prescaler_clock_select_t prescalerClockSource

LPTMR clock source 




lptmr_prescaler_glitch_value_t value

Prescaler or glitch filter value 







LPUART:  Low Power Universal Asynchronous Receiver/Transmitter Driver#


LPUART Driver#


static inline void LPUART_SoftwareReset(LPUART_Type *base)

Resets the LPUART using software. 
This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.

Parameters:

base – LPUART peripheral base address. 







status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)

Initializes an LPUART instance with the user configuration structure and the peripheral clock. 
This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART. 
lpuart_config_t lpuartConfig;
lpuartConfig.baudRate_Bps = 115200U;
lpuartConfig.parityMode = kLPUART_ParityDisabled;
lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
lpuartConfig.isMsb = false;
lpuartConfig.stopBitCount = kLPUART_OneStopBit;
lpuartConfig.txFifoWatermark = 0;
lpuartConfig.rxFifoWatermark = 1;
LPUART_Init(LPUART1, &lpuartConfig, 20000000U);




Parameters:

base – LPUART peripheral base address. 
config – Pointer to a user-defined configuration structure. 
srcClock_Hz – LPUART clock source frequency in HZ. 


Return values:

kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source. 
kStatus_Success – LPUART initialize succeed 







status_t LPUART_Deinit(LPUART_Type *base)

Deinitializes a LPUART instance. 
This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.

Parameters:

base – LPUART peripheral base address. 


Return values:

kStatus_Success – Deinit is success. 
kStatus_LPUART_Timeout – Timeout during deinit. 







void LPUART_GetDefaultConfig(lpuart_config_t *config)

Gets the default configuration structure. 
This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;

Parameters:

config – Pointer to a configuration structure. 







status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the LPUART instance baudrate. 
This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. 
LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);




Parameters:

base – LPUART peripheral base address. 
baudRate_Bps – LPUART baudrate to be set. 
srcClock_Hz – LPUART clock source frequency in HZ. 


Return values:

kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source. 
kStatus_Success – Set baudrate succeeded. 







void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)

Enable 9-bit data mode for LPUART. 
This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.

Parameters:

base – LPUART peripheral base address. 
enable – true to enable, flase to disable. 







static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)

Set the LPUART address. 
This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.

Note
Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.


Parameters:

base – LPUART peripheral base address. 
address1 – LPUART slave address1. 
address2 – LPUART slave address2. 







static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)

Enable the LPUART match address feature. 

Parameters:

base – LPUART peripheral base address. 
match1 – true to enable match address1, false to disable. 
match2 – true to enable match address2, false to disable. 







static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the rx FIFO watermark. 

Parameters:

base – LPUART peripheral base address. 
water – Rx FIFO watermark. 







static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the tx FIFO watermark. 

Parameters:

base – LPUART peripheral base address. 
water – Tx FIFO watermark. 







static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)

Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. 
This function Enable 16bit Data transmit in lpuart_handle_t.

Parameters:

handle – LPUART handle pointer. 
enable – true to enable, false to disable. 







uint32_t LPUART_GetStatusFlags(LPUART_Type *base)

Gets LPUART status flags. 
This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty: 
if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
{
    ...
}




Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART status flags which are ORed by the enumerators in the _lpuart_flags. 






status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)

Clears status flags with a provided mask. 
This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.

Parameters:

base – LPUART peripheral base address. 
mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask. 


Return values:

kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware. 
kStatus_Success – Status in the mask are cleared. 


Returns:
0 succeed, others failed. 






void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)

Enables LPUART interrupts according to a provided mask. 
This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt: 
LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);




Parameters:

base – LPUART peripheral base address. 
mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable. 







void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)

Disables LPUART interrupts according to a provided mask. 
This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt: 
LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);




Parameters:

base – LPUART peripheral base address. 
mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable. 







uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)

Gets enabled LPUART interrupts. 
This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled: 
uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);

if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
{
    ...
}




Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable. 






static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)

Gets the LPUART data register address. 
This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.

Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART data register addresses which are used both by the transmitter and receiver. 






static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter DMA request. 
This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver DMA. 
This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







uint32_t LPUART_GetInstance(LPUART_Type *base)

Get the LPUART instance from peripheral base address. 

Parameters:

base – LPUART peripheral base address. 


Returns:
LPUART instance. 






static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter. 
This function enables or disables the LPUART transmitter.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver. 
This function enables or disables the LPUART receiver.

Parameters:

base – LPUART peripheral base address. 
enable – True to enable, false to disable. 







static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)

Writes to the transmitter register. 
This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

base – LPUART peripheral base address. 
data – Data write to the TX register. 







static inline uint8_t LPUART_ReadByte(LPUART_Type *base)

Reads the receiver register. 
This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

base – LPUART peripheral base address. 


Returns:
Data read from data register. 






static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)

Gets the rx FIFO data count. 

Parameters:

base – LPUART peripheral base address. 


Returns:
rx FIFO data count. 






static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)

Gets the tx FIFO data count. 

Parameters:

base – LPUART peripheral base address. 


Returns:
tx FIFO data count. 






void LPUART_SendAddress(LPUART_Type *base, uint8_t address)

Transmit an address frame in 9-bit data mode. 

Parameters:

base – LPUART peripheral base address. 
address – LPUART slave address. 







status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)

Writes to the transmitter register using a blocking method. 
This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.

Parameters:

base – LPUART peripheral base address. 
data – Start address of the data to write. 
length – Size of the data to write. 


Return values:

kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully wrote all data. 







status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)

Writes to the transmitter register using a blocking method in 9bit or 10bit mode. 

Note
This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.


Parameters:

base – LPUART peripheral base address. 
data – Start address of the data to write. 
length – Size of the data to write. 


Return values:

kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully wrote all data. 







status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)

Reads the receiver data register using a blocking method. 
This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.

Parameters:

base – LPUART peripheral base address. 
data – Start address of the buffer to store the received data. 
length – Size of the buffer. 


Return values:

kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data. 
kStatus_LPUART_NoiseError – Noise error happened while receiving data. 
kStatus_LPUART_FramingError – Framing error happened while receiving data. 
kStatus_LPUART_ParityError – Parity error happened while receiving data. 
kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully received all data. 







status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)

Reads the receiver data register in 9bit or 10bit mode. 

Note
This function only support 9bit or 10bit transfer.


Parameters:

base – LPUART peripheral base address. 
data – Start address of the buffer to store the received data by 16bit, only 10bit is valid. 
length – Size of the buffer. 


Return values:

kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data. 
kStatus_LPUART_NoiseError – Noise error happened while receiving data. 
kStatus_LPUART_FramingError – Framing error happened while receiving data. 
kStatus_LPUART_ParityError – Parity error happened while receiving data. 
kStatus_LPUART_Timeout – Transmission timed out and was aborted. 
kStatus_Success – Successfully received all data. 







void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)

Initializes the LPUART handle. 
This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.
The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
callback – Callback function. 
userData – User data. 







status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method. 
This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.

Note
The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.


Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
xfer – LPUART transfer structure, see lpuart_transfer_t. 


Return values:

kStatus_Success – Successfully start the data transmission. 
kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register. 
kStatus_InvalidArgument – Invalid argument. 







void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer. 
This function sets up the RX ring buffer to a specific UART handle.
When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.

Note
When using RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, then only 31 bytes are used for saving data.


Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. 
ringBufferSize – size of the ring buffer. 







void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer. 
This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 







size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)

Get the length of received data in RX ring buffer. 

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 


Returns:
Length of received data in RX ring buffer. 






void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data transmit. 
This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 







status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been sent out to bus. 
This function gets the number of bytes that have been sent out to bus by an interrupt method.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Send bytes count. 


Return values:

kStatus_NoTransferInProgress – No send in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method. 
This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameter receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
xfer – LPUART transfer structure, see uart_transfer_t. 
receivedBytes – Bytes received from the ring buffer directly. 


Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue. 
kStatus_LPUART_RxBusy – Previous receive request is not finished. 
kStatus_InvalidArgument – Invalid argument. 







void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data receiving. 
This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 







status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been received. 
This function gets the number of bytes that have been received.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Receive bytes count. 


Return values:

kStatus_NoTransferInProgress – No receive in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)

LPUART IRQ handle function. 
This function handles the LPUART transmit and receive IRQ request.

Parameters:

base – LPUART peripheral base address. 
irqHandle – LPUART handle pointer. 







void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)

LPUART Error IRQ handle function. 
This function handles the LPUART error IRQ request.

Parameters:

base – LPUART peripheral base address. 
irqHandle – LPUART handle pointer. 







void LPUART_DriverIRQHandler(uint32_t instance)

LPUART driver IRQ handler common entry. 
This function provides the common IRQ request entry for LPUART.

Parameters:

instance – LPUART instance. 







FSL_LPUART_DRIVER_VERSION

LPUART driver version. 





Error codes for the LPUART driver. 
Values:


enumerator kStatus_LPUART_TxBusy

TX busy 




enumerator kStatus_LPUART_RxBusy

RX busy 




enumerator kStatus_LPUART_TxIdle

LPUART transmitter is idle. 




enumerator kStatus_LPUART_RxIdle

LPUART receiver is idle. 




enumerator kStatus_LPUART_TxWatermarkTooLarge

TX FIFO watermark too large 




enumerator kStatus_LPUART_RxWatermarkTooLarge

RX FIFO watermark too large 




enumerator kStatus_LPUART_FlagCannotClearManually

Some flag can’t manually clear 




enumerator kStatus_LPUART_Error

Error happens on LPUART. 




enumerator kStatus_LPUART_RxRingBufferOverrun

LPUART RX software ring buffer overrun. 




enumerator kStatus_LPUART_RxHardwareOverrun

LPUART RX receiver overrun. 




enumerator kStatus_LPUART_NoiseError

LPUART noise error. 




enumerator kStatus_LPUART_FramingError

LPUART framing error. 




enumerator kStatus_LPUART_ParityError

LPUART parity error. 




enumerator kStatus_LPUART_BaudrateNotSupport

Baudrate is not support in current clock source 




enumerator kStatus_LPUART_IdleLineDetected

IDLE flag. 




enumerator kStatus_LPUART_Timeout

LPUART times out. 






enum _lpuart_parity_mode

LPUART parity mode. 
Values:


enumerator kLPUART_ParityDisabled

Parity disabled 




enumerator kLPUART_ParityEven

Parity enabled, type even, bit setting: PE|PT = 10 




enumerator kLPUART_ParityOdd

Parity enabled, type odd, bit setting: PE|PT = 11 






enum _lpuart_data_bits

LPUART data bits count. 
Values:


enumerator kLPUART_EightDataBits

Eight data bit 




enumerator kLPUART_SevenDataBits

Seven data bit 






enum _lpuart_stop_bit_count

LPUART stop bit count. 
Values:


enumerator kLPUART_OneStopBit

One stop bit 




enumerator kLPUART_TwoStopBit

Two stop bits 






enum _lpuart_transmit_cts_source

LPUART transmit CTS source. 
Values:


enumerator kLPUART_CtsSourcePin

CTS resource is the LPUART_CTS pin. 




enumerator kLPUART_CtsSourceMatchResult

CTS resource is the match result. 






enum _lpuart_transmit_cts_config

LPUART transmit CTS configure. 
Values:


enumerator kLPUART_CtsSampleAtStart

CTS input is sampled at the start of each character. 




enumerator kLPUART_CtsSampleAtIdle

CTS input is sampled when the transmitter is idle 






enum _lpuart_idle_type_select

LPUART idle flag type defines when the receiver starts counting. 
Values:


enumerator kLPUART_IdleTypeStartBit

Start counting after a valid start bit. 




enumerator kLPUART_IdleTypeStopBit

Start counting after a stop bit. 






enum _lpuart_idle_config

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set. 
Values:


enumerator kLPUART_IdleCharacter1

the number of idle characters. 




enumerator kLPUART_IdleCharacter2

the number of idle characters. 




enumerator kLPUART_IdleCharacter4

the number of idle characters. 




enumerator kLPUART_IdleCharacter8

the number of idle characters. 




enumerator kLPUART_IdleCharacter16

the number of idle characters. 




enumerator kLPUART_IdleCharacter32

the number of idle characters. 




enumerator kLPUART_IdleCharacter64

the number of idle characters. 




enumerator kLPUART_IdleCharacter128

the number of idle characters. 






enum _lpuart_interrupt_enable

LPUART interrupt configuration structure, default settings all disabled. 
This structure contains the settings for all LPUART interrupt configurations. 
Values:


enumerator kLPUART_LinBreakInterruptEnable

LIN break detect. bit 7 




enumerator kLPUART_RxActiveEdgeInterruptEnable

Receive Active Edge. bit 6 




enumerator kLPUART_TxDataRegEmptyInterruptEnable

Transmit data register empty. bit 23 




enumerator kLPUART_TransmissionCompleteInterruptEnable

Transmission complete. bit 22 




enumerator kLPUART_RxDataRegFullInterruptEnable

Receiver data register full. bit 21 




enumerator kLPUART_IdleLineInterruptEnable

Idle line. bit 20 




enumerator kLPUART_RxOverrunInterruptEnable

Receiver Overrun. bit 27 




enumerator kLPUART_NoiseErrorInterruptEnable

Noise error flag. bit 26 




enumerator kLPUART_FramingErrorInterruptEnable

Framing error flag. bit 25 




enumerator kLPUART_ParityErrorInterruptEnable

Parity error flag. bit 24 




enumerator kLPUART_Match1InterruptEnable

Parity error flag. bit 15 




enumerator kLPUART_Match2InterruptEnable

Parity error flag. bit 14 




enumerator kLPUART_TxFifoOverflowInterruptEnable

Transmit FIFO Overflow. bit 9 




enumerator kLPUART_RxFifoUnderflowInterruptEnable

Receive FIFO Underflow. bit 8 




enumerator kLPUART_AllInterruptEnable







enum _lpuart_flags

LPUART status flags. 
This provides constants for the LPUART status flags for use in the LPUART functions. 
Values:


enumerator kLPUART_TxDataRegEmptyFlag

Transmit data register empty flag, sets when transmit buffer is empty. bit 23 




enumerator kLPUART_TransmissionCompleteFlag

Transmission complete flag, sets when transmission activity complete. bit 22 




enumerator kLPUART_RxDataRegFullFlag

Receive data register full flag, sets when the receive data buffer is full. bit 21 




enumerator kLPUART_IdleLineFlag

Idle line detect flag, sets when idle line detected. bit 20 




enumerator kLPUART_RxOverrunFlag

Receive Overrun, sets when new data is received before data is read from receive register. bit 19 




enumerator kLPUART_NoiseErrorFlag

Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18 




enumerator kLPUART_FramingErrorFlag

Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 




enumerator kLPUART_ParityErrorFlag

If parity enabled, sets upon parity error detection. bit 16 




enumerator kLPUART_LinBreakFlag

LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31 




enumerator kLPUART_RxActiveEdgeFlag

Receive pin active edge interrupt flag, sets when active edge detected. bit 30 




enumerator kLPUART_RxActiveFlag

Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 




enumerator kLPUART_DataMatch1Flag

The next character to be read from LPUART_DATA matches MA1. bit 15 




enumerator kLPUART_DataMatch2Flag

The next character to be read from LPUART_DATA matches MA2. bit 14 




enumerator kLPUART_TxFifoEmptyFlag

TXEMPT bit, sets if transmit buffer is empty. bit 7 




enumerator kLPUART_RxFifoEmptyFlag

RXEMPT bit, sets if receive buffer is empty. bit 6 




enumerator kLPUART_TxFifoOverflowFlag

TXOF bit, sets if transmit buffer overflow occurred. bit 1 




enumerator kLPUART_RxFifoUnderflowFlag

RXUF bit, sets if receive buffer underflow occurred. bit 0 




enumerator kLPUART_AllClearFlags





enumerator kLPUART_AllFlags







typedef enum _lpuart_parity_mode lpuart_parity_mode_t

LPUART parity mode. 




typedef enum _lpuart_data_bits lpuart_data_bits_t

LPUART data bits count. 




typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t

LPUART stop bit count. 




typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t

LPUART transmit CTS source. 




typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t

LPUART transmit CTS configure. 




typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t

LPUART idle flag type defines when the receiver starts counting. 




typedef enum _lpuart_idle_config lpuart_idle_config_t

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set. 




typedef struct _lpuart_config lpuart_config_t

LPUART configuration structure. 




typedef struct _lpuart_transfer lpuart_transfer_t

LPUART transfer structure. 




typedef struct _lpuart_handle lpuart_handle_t





typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function. 




typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)





void *s_lpuartHandle[]





const IRQn_Type s_lpuartTxIRQ[]





lpuart_isr_t s_lpuartIsr[]





UART_RETRY_TIMES

Retry times for waiting flag. 




struct _lpuart_config


#include <fsl_lpuart.h>
LPUART configuration structure. 

Public Members


uint32_t baudRate_Bps

LPUART baud rate 




lpuart_parity_mode_t parityMode

Parity mode, disabled (default), even, odd 




lpuart_data_bits_t dataBitsCount

Data bits count, eight (default), seven 




bool isMsb

Data bits order, LSB (default), MSB 




lpuart_stop_bit_count_t stopBitCount

Number of stop bits, 1 stop bit (default) or 2 stop bits 




uint8_t txFifoWatermark

TX FIFO watermark 




uint8_t rxFifoWatermark

RX FIFO watermark 




bool enableRxRTS

RX RTS enable 




bool enableTxCTS

TX CTS enable 




lpuart_transmit_cts_source_t txCtsSource

TX CTS source 




lpuart_transmit_cts_config_t txCtsConfig

TX CTS configure 




uint8_t rtsWatermark

RTS watermark 




lpuart_idle_type_select_t rxIdleType

RX IDLE type. 




lpuart_idle_config_t rxIdleConfig

RX IDLE configuration. 




bool enableTx

Enable TX 




bool enableRx

Enable RX 




bool swapTxdRxd

Swap TXD and RXD pins 







struct _lpuart_transfer


#include <fsl_lpuart.h>
LPUART transfer structure. 

Public Members


size_t dataSize

The byte count to be transfer. 







struct _lpuart_handle


#include <fsl_lpuart.h>
LPUART handle structure. 

Public Members


volatile size_t txDataSize

Size of the remaining data to send. 




size_t txDataSizeAll

Size of the data to send out. 




volatile size_t rxDataSize

Size of the remaining data to receive. 




size_t rxDataSizeAll

Size of the data to receive. 




size_t rxRingBufferSize

Size of the ring buffer. 




volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer. 




volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer. 




lpuart_transfer_callback_t callback

Callback function. 




void *userData

LPUART callback function parameter. 




volatile uint8_t txState

TX transfer state. 




volatile uint8_t rxState

RX transfer state. 




bool isSevenDataBits

Seven data bits flag. 




bool is16bitData

16bit data bits flag, only used for 9bit or 10bit data 







union __unnamed65__


Public Members


uint8_t *data

The buffer of data to be transfer. 




uint8_t *rxData

The buffer to receive data. 




uint16_t *rxData16

The buffer to receive data. 




const uint8_t *txData

The buffer of data to be sent. 




const uint16_t *txData16

The buffer of data to be sent. 







union __unnamed67__


Public Members


const uint8_t *volatile txData

Address of remaining data to send. 




const uint16_t *volatile txData16

Address of remaining data to send. 







union __unnamed69__


Public Members


uint8_t *volatile rxData

Address of remaining data to receive. 




uint16_t *volatile rxData16

Address of remaining data to receive. 







union __unnamed71__


Public Members


uint8_t *rxRingBuffer

Start address of the receiver ring buffer. 




uint16_t *rxRingBuffer16

Start address of the receiver ring buffer. 







LPUART eDMA Driver#


void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the LPUART handle which is used in transactional functions. 

Note
This function disables all LPUART interrupts.


Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 
callback – Callback function. 
userData – User data. 
txEdmaHandle – User requested DMA handle for TX DMA transfer. 
rxEdmaHandle – User requested DMA handle for RX DMA transfer. 







status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Sends data using eDMA. 
This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
xfer – LPUART eDMA transfer structure. See lpuart_transfer_t. 


Return values:

kStatus_Success – if succeed, others failed. 
kStatus_LPUART_TxBusy – Previous transfer on going. 
kStatus_InvalidArgument – Invalid argument. 







status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Receives data using eDMA. 
This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 
xfer – LPUART eDMA transfer structure, see lpuart_transfer_t. 


Return values:

kStatus_Success – if succeed, others fail. 
kStatus_LPUART_RxBusy – Previous transfer ongoing. 
kStatus_InvalidArgument – Invalid argument. 







void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the sent data using eDMA. 
This function aborts the sent data using eDMA.

Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 







void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the received data using eDMA. 
This function aborts the received data using eDMA.

Parameters:

base – LPUART peripheral base address. 
handle – Pointer to lpuart_edma_handle_t structure. 







status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of bytes written to the LPUART TX register. 
This function gets the number of bytes written to the LPUART TX register by DMA.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Send bytes count. 


Return values:

kStatus_NoTransferInProgress – No send in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of received bytes. 
This function gets the number of received bytes.

Parameters:

base – LPUART peripheral base address. 
handle – LPUART handle pointer. 
count – Receive bytes count. 


Return values:

kStatus_NoTransferInProgress – No receive in progress. 
kStatus_InvalidArgument – Parameter is invalid. 
kStatus_Success – Get successfully through the parameter count; 







void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)

LPUART eDMA IRQ handle function. 
This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application. 

Note
This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.


Parameters:

base – LPUART peripheral base address. 
lpuartEdmaHandle – LPUART handle pointer. 







FSL_LPUART_EDMA_DRIVER_VERSION

LPUART EDMA driver version. 




typedef struct _lpuart_edma_handle lpuart_edma_handle_t





typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function. 




struct _lpuart_edma_handle


#include <fsl_lpuart_edma.h>
LPUART eDMA handle. 

Public Members


lpuart_edma_transfer_callback_t callback

Callback function. 




void *userData

LPUART callback function parameter. 




size_t rxDataSizeAll

Size of the data to receive. 




size_t txDataSizeAll

Size of the data to send out. 




edma_handle_t *txEdmaHandle

The eDMA TX channel used. 




edma_handle_t *rxEdmaHandle

The eDMA RX channel used. 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




volatile uint8_t txState

TX transfer state. 




volatile uint8_t rxState

RX transfer state 







MCM: Miscellaneous Control Module#


FSL_MCM_DRIVER_VERSION

MCM driver version. 





Enum _mcm_interrupt_flag. Interrupt status flag mask. . 
Values:


enumerator kMCM_CacheWriteBuffer

Cache Write Buffer Error Enable. 




enumerator kMCM_ParityError

Cache Parity Error Enable. 




enumerator kMCM_FPUInvalidOperation

FPU Invalid Operation Interrupt Enable. 




enumerator kMCM_FPUDivideByZero

FPU Divide-by-zero Interrupt Enable. 




enumerator kMCM_FPUOverflow

FPU Overflow Interrupt Enable. 




enumerator kMCM_FPUUnderflow

FPU Underflow Interrupt Enable. 




enumerator kMCM_FPUInexact

FPU Inexact Interrupt Enable. 




enumerator kMCM_FPUInputDenormalInterrupt

FPU Input Denormal Interrupt Enable. 






typedef union _mcm_buffer_fault_attribute mcm_buffer_fault_attribute_t

The union of buffer fault attribute. 




typedef union _mcm_lmem_fault_attribute mcm_lmem_fault_attribute_t

The union of LMEM fault attribute. 




static inline void MCM_EnableCrossbarRoundRobin(MCM_Type *base, bool enable)

Enables/Disables crossbar round robin. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable crossbar round robin.

true Enable crossbar round robin.
false disable crossbar round robin. 









static inline void MCM_EnableInterruptStatus(MCM_Type *base, uint32_t mask)

Enables the interrupt. 

Parameters:

base – MCM peripheral base address. 
mask – Interrupt status flags mask(_mcm_interrupt_flag). 







static inline void MCM_DisableInterruptStatus(MCM_Type *base, uint32_t mask)

Disables the interrupt. 

Parameters:

base – MCM peripheral base address. 
mask – Interrupt status flags mask(_mcm_interrupt_flag). 







static inline uint16_t MCM_GetInterruptStatus(MCM_Type *base)

Gets the Interrupt status . 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_ClearCacheWriteBufferErroStatus(MCM_Type *base)

Clears the Interrupt status . 

Parameters:

base – MCM peripheral base address. 







static inline uint32_t MCM_GetBufferFaultAddress(MCM_Type *base)

Gets buffer fault address. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_GetBufferFaultAttribute(MCM_Type *base, mcm_buffer_fault_attribute_t *bufferfault)

Gets buffer fault attributes. 

Parameters:

base – MCM peripheral base address. 
bufferfault – Structure to store the result. 







static inline uint32_t MCM_GetBufferFaultData(MCM_Type *base)

Gets buffer fault data. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_LimitCodeCachePeripheralWriteBuffering(MCM_Type *base, bool enable)

Limit code cache peripheral write buffering. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable limit code cache peripheral write buffering.

true Enable limit code cache peripheral write buffering.
false disable limit code cache peripheral write buffering. 









static inline void MCM_BypassFixedCodeCacheMap(MCM_Type *base, bool enable)

Bypass fixed code cache map. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable bypass fixed code cache map.

true Enable bypass fixed code cache map.
false disable bypass fixed code cache map. 









static inline void MCM_EnableCodeBusCache(MCM_Type *base, bool enable)

Enables/Disables code bus cache. 

Parameters:

base – MCM peripheral base address. 
enable – Used to disable/enable code bus cache.

true Enable code bus cache.
false disable code bus cache. 









static inline void MCM_ForceCodeCacheToNoAllocation(MCM_Type *base, bool enable)

Force code cache to no allocation. 

Parameters:

base – MCM peripheral base address. 
enable – Used to force code cache to allocation or no allocation.

true Force code cache to no allocation.
false Force code cache to allocation. 









static inline void MCM_EnableCodeCacheWriteBuffer(MCM_Type *base, bool enable)

Enables/Disables code cache write buffer. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable code cache write buffer.

true Enable code cache write buffer.
false Disable code cache write buffer. 









static inline void MCM_ClearCodeBusCache(MCM_Type *base)

Clear code bus cache. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_EnablePcParityFaultReport(MCM_Type *base, bool enable)

Enables/Disables PC Parity Fault Report. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable PC Parity Fault Report.

true Enable PC Parity Fault Report.
false disable PC Parity Fault Report. 









static inline void MCM_EnablePcParity(MCM_Type *base, bool enable)

Enables/Disables PC Parity. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable PC Parity.

true Enable PC Parity.
false disable PC Parity. 









static inline void MCM_LockConfigState(MCM_Type *base)

Lock the configuration state. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_EnableCacheParityReporting(MCM_Type *base, bool enable)

Enables/Disables cache parity reporting. 

Parameters:

base – MCM peripheral base address. 
enable – Used to enable/disable cache parity reporting.

true Enable cache parity reporting.
false disable cache parity reporting. 









static inline uint32_t MCM_GetLmemFaultAddress(MCM_Type *base)

Gets LMEM fault address. 

Parameters:

base – MCM peripheral base address. 







static inline void MCM_GetLmemFaultAttribute(MCM_Type *base, mcm_lmem_fault_attribute_t *lmemFault)

Get LMEM fault attributes. 

Parameters:

base – MCM peripheral base address. 
lmemFault – Structure to store the result. 







static inline uint64_t MCM_GetLmemFaultData(MCM_Type *base)

Gets LMEM fault data. 

Parameters:

base – MCM peripheral base address. 







MCM_LMFATR_TYPE_MASK





MCM_LMFATR_MODE_MASK





MCM_LMFATR_BUFF_MASK





MCM_LMFATR_CACH_MASK





MCM_ISCR_STAT_MASK





FSL_COMPONENT_ID





union _mcm_buffer_fault_attribute


#include <fsl_mcm.h>
The union of buffer fault attribute. 

Public Members


uint32_t attribute

Indicates the faulting attributes, when a properly-enabled cache write buffer error interrupt event is detected. 




struct _mcm_buffer_fault_attribute._mcm_buffer_fault_attribut attribute_memory






struct _mcm_buffer_fault_attribut


Public Members


uint32_t busErrorDataAccessType

Indicates the type of cache write buffer access. 




uint32_t busErrorPrivilegeLevel

Indicates the privilege level of the cache write buffer access. 




uint32_t busErrorSize

Indicates the size of the cache write buffer access. 




uint32_t busErrorAccess

Indicates the type of system bus access. 




uint32_t busErrorMasterID

Indicates the crossbar switch bus master number of the captured cache write buffer bus error. 




uint32_t busErrorOverrun

Indicates if another cache write buffer bus error is detected. 









union _mcm_lmem_fault_attribute


#include <fsl_mcm.h>
The union of LMEM fault attribute. 

Public Members


uint32_t attribute

Indicates the attributes of the LMEM fault detected. 




struct _mcm_lmem_fault_attribute._mcm_lmem_fault_attribut attribute_memory






struct _mcm_lmem_fault_attribut


Public Members


uint32_t parityFaultProtectionSignal

Indicates the features of parity fault protection signal. 




uint32_t parityFaultMasterSize

Indicates the parity fault master size. 




uint32_t parityFaultWrite

Indicates the parity fault is caused by read or write. 




uint32_t backdoorAccess

Indicates the LMEM access fault is initiated by core access or backdoor access. 




uint32_t parityFaultSyndrome

Indicates the parity fault syndrome. 




uint32_t overrun

Indicates the number of faultss. 









Mipi_dsi#


void DSI_Init(MIPI_DSI_Type *base, dsi_config_t *config)

Initializes the MIPI DSI host with the user configuration. 
This function initializes the MIPI DSI host with the configuration, it should be called before other MIPI DSI driver functions.

Parameters:

base – MIPI DSI host peripheral base address. 
config – Pointer to the user configuration structure. 







void DSI_Deinit(MIPI_DSI_Type *base)

Deinitializes an MIPI DSI host. 
This function should be called after all bother MIPI DSI driver functions.

Parameters:

base – MIPI DSI host peripheral base address. 







void DSI_GetDefaultConfig(dsi_config_t *config)

Gets the default configuration to initialize the MIPI DSI host. 
The default value is: 
config->mode = kDSI_CommandMode;
config->packageFlags = kDSI_DpiEnableAll;
config->enableNoncontinuousClk = true;
config->HsRxDeviceReady_ByteClk = 0U;
config->lpRxDeviceReady_ByteClk = 0U;
config->HsTxDeviceReady_ByteClk = 0U;
config->lpTxDeviceReady_ByteClk = 0U;




Parameters:

config – Pointer to a user-defined configuration structure. 







uint32_t DSI_DphyGetPllDivider(uint32_t *m, uint32_t *n, uint32_t refClkFreq_Hz, uint32_t desiredOutFreq_Hz)

Calculates the D-PHY PLL dividers to generate the desired output frequency. 
The phy byte clock frequency(byte count per second) is generated by multiplying the refClkFreq_Hz, the formula is as follows, m & n is configured by mediamix control block.
desiredOutFreq_Hz = refClkFreq_Hz * (M + 2) / (N + 1). M: 62 ~ 625 N: 0 ~ 15

Parameters:

m – Control of the feedback multiplication ratio. 
n – Control of the input frequency division ratio. 
refClkFreq_Hz – The D-PHY input reference clock frequency (REF_CLK). 
desiredOutFreq_Hz – Desired PLL output frequency. 


Returns:
The actually output frequency using the returned dividers. If can not find suitable dividers, return 0. 






status_t DSI_PowerUp(MIPI_DSI_Type *base)

Power up the DSI. 

Parameters:

base – MIPI DSI host peripheral base address. 


Return values:

kStatus_Success – Data transfer finished with no error. 
kStatus_Timeout – Transfer failed because of timeout. 







static inline void DSI_PowerDown(MIPI_DSI_Type *base)

Power down the DSI. 

Parameters:

base – MIPI DSI host peripheral base address. 







static inline void DSI_EnableInterrupts(MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)

Enable the interrupts. 
The interrupts to enable are passed in as OR’ed mask value of _dsi_interrupt.

Parameters:

base – MIPI DSI host peripheral base address. 
intGroup1 – Interrupts to enable in group 1. 
intGroup2 – Interrupts to enable in group 2. 







static inline void DSI_DisableInterrupts(MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)

Disable the interrupts. 
The interrupts to disable are passed in as OR’ed mask value of _dsi_interrupt.

Parameters:

base – MIPI DSI host peripheral base address. 
intGroup1 – Interrupts to disable in group 1. 
intGroup2 – Interrupts to disable in group 2. 







static inline void DSI_GetAndClearInterruptStatus(MIPI_DSI_Type *base, uint32_t *intGroup1, uint32_t *intGroup2)

Get and clear the interrupt status. 

Parameters:

base – MIPI DSI host peripheral base address. 
intGroup1 – Group 1 interrupt status. 
intGroup2 – Group 2 interrupt status. 







void DSI_SetDpiConfig(MIPI_DSI_Type *base, const dsi_dpi_config_t *config, uint8_t laneNum)

Configure the DPI interface. 
This function sets the DPI interface configuration, it should be used in video mode.

Parameters:

base – MIPI DSI host peripheral base address. 
config – Pointer to the DPI interface configuration. 
laneNum – How may lanes in use. 







void DSI_SetCommandModeConfig(MIPI_DSI_Type *base, const dsi_command_config_t *config, uint32_t phyByteClkFreq_Hz)

Configures the command mode configuration. 
This function configures the timeout values for DSI command mode.

Parameters:

base – MIPI DSI host peripheral base address. 
config – Pointer to the command mode configuration structure. 
phyByteClkFreq_Hz – Byte clock frequency in each lane. 







static inline void DSI_EnableCommandMode(MIPI_DSI_Type *base, bool enable)

Enables the command mode. 
This function configures the timeout values for DSI command mode.

Parameters:

base – MIPI DSI host peripheral base address. 
enable – true to enable command mode and disable video mode, vise versa. 







static inline void DSI_EnableVpgEnMode(MIPI_DSI_Type *base, bool enable)

Enables the VPG mode. 
This function configures video mode pattern generator.

Parameters:

base – MIPI DSI host peripheral base address. 
enable – true to enable video mode pattern generator. 







void DSI_GetDefaultDphyConfig(dsi_dphy_config_t *config, uint32_t phyByteClkFreq_Hz, uint8_t laneNum)

Gets the default D-PHY configuration. 
Gets the default D-PHY configuration, the timing parameters are set according to D-PHY specification. User can use the configuration directly, or change the parameters according device specific requirements.

Parameters:

config – Pointer to the D-PHY configuration. 
phyByteClkFreq_Hz – Byte clock frequency in each lane. 
laneNum – How may lanes in use. 







void DSI_InitDphy(MIPI_DSI_Type *base, const dsi_dphy_config_t *config)

Initializes the D-PHY. 
This function configures the D-PHY timing and setups the D-PHY PLL based on user configuration. The default configuration can be obtained by calling the function DSI_GetDefaultDphyConfig.

Parameters:

base – MIPI DSI host peripheral base address. 
config – Pointer to the D-PHY configuration. 







void DSI_SetPacketControl(MIPI_DSI_Type *base, uint8_t flags)

Configures the APB packet to send. 
This function configures the next APB packet transfer feature. After configuration, user can write the payload by calling DSI_WriteTxPayload then call DSI_WriteTxHeader to start the tranasfer or just call DSI_WriteTxHeader alone if it is a short packet.

Parameters:

base – MIPI DSI host peripheral base address. 
flags – The transfer control flags, see ref _dsi_transfer_flags. 







void DSI_WriteTxHeader(MIPI_DSI_Type *base, uint16_t wordCount, uint8_t virtualChannel, dsi_tx_data_type_t dataType)

Writes tx header to command FIFO. This will trigger the packet transfer. 

Parameters:

base – MIPI DSI host peripheral base address. 
wordCount – For long packet, this is the byte count of the payload. For short packet, this is (data1 << 8) | data0. 
virtualChannel – Virtual channel. 
dataType – The packet data type, (DI). 







void DSI_WriteTxPayload(MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize)

Fills the long APB packet payload. 
Write the long packet payload to TX FIFO.

Parameters:

base – MIPI DSI host peripheral base address. 
payload – Pointer to the payload. 
payloadSize – Payload size in byte. 







void DSI_WriteTxPayloadExt(MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDcsCmd, uint8_t dcsCmd)

Writes payload data to generic payload FIFO. 
Write the long packet payload to TX FIFO. This function could be used in two ways

Include the DCS command in the 1st byte of payload. In this case, the DCS command is the first byte of payload. The parameter sendDcsCmd is set to false, the dcsCmd is not used. This function is the same as DSI_WriteTxPayload when used in this way.
The DCS command in not in payload, but specified by parameter dcsCmd. In this case, the parameter sendDcsCmd is set to true, the dcsCmd is the DCS command to send. The payload is sent after dcsCmd.



Parameters:

base – MIPI DSI host peripheral base address. 
payload – Pointer to the payload. 
payloadSize – Payload size in byte. 
sendDcsCmd – If set to true, the DCS command is specified by dcsCmd, otherwise the DCS command is included in the payload. 
dcsCmd – The DCS command to send, only used when sendDCSCmd is true. 







void DSI_ReadRxData(MIPI_DSI_Type *base, uint8_t *payload, uint16_t payloadSize)

Reads the long APB packet payload. 
Read the long packet payload from RX FIFO. This function reads directly from RX FIFO status. Upper layer should make sure the whole rx packet has been received.

Parameters:

base – MIPI DSI host peripheral base address. 
payload – Pointer to the payload buffer. 
payloadSize – Payload size in byte. 







status_t DSI_TransferBlocking(MIPI_DSI_Type *base, dsi_transfer_t *xfer)

APB data transfer using blocking method. 
Perform APB data transfer using blocking method. This function waits until all data send or received, or timeout happens.

Parameters:

base – MIPI DSI host peripheral base address. 
xfer – Pointer to the transfer structure. 


Return values:

kStatus_Success – Data transfer finished with no error. 
kStatus_Timeout – Transfer failed because of timeout. 
kStatus_DSI_RxDataError – RX data error, user could use ref DSI_GetRxErrorStatus to check the error details. 
kStatus_DSI_PhyError – PHY error detected during transfer. 
kStatus_DSI_ErrorReportReceived – Error Report packet received, user could use ref DSI_GetAndClearHostStatus to check the error report status. 
kStatus_DSI_NotSupported – Transfer format not supported. 
kStatus_DSI_Fail – Transfer failed for other reasons. 







uint16_t Pll_Set_Hs_Freqrange(uint32_t bnd_width)

Lookup table method to obtain HS frequency range of operation selection override. 

Parameters:

bnd_width – band width frequncy in Hz 


Returns:
the hsfreqrange_ovr[6:0] value based on band width frequncy in hz. 






uint16_t Pll_Set_Pll_Prop_Param(uint32_t pll_freq_sel)

Lookup table method to obtain PLL Proportional Charge Pump control. 

Parameters:

pll_freq_sel – PLL frequency in Mhz 


Returns:
the pll_prop_cntrl_rw[5:0] value based on video Pll frequency in Mhz. 






uint16_t Pll_Set_Sr_Osc_Freq_Target(uint32_t pll_freq_sel)

Lookup table method to obtain DDL target oscillation frequency. 

Parameters:

pll_freq_sel – PLL frequency in Mhz 


Returns:
the sr_osc_freq_target[11:0] value based on video Pll frequency in Mhz. 






uint32_t Pll_Set_Pll_Vco_Freq(uint32_t pll_freq_sel)

calculate VCO frequency. 

Parameters:

pll_freq_sel – PLL frequency in Hz 


Returns:
the vco_freq_clk value 






uint16_t Pll_Set_Pll_Vco_Param(uint32_t pll_freq_sel)

Lookup table method to obtain VCO parameter. 

Parameters:

pll_freq_sel – PLL frequency in Mhz 


Returns:
the pll_vco_cntrl_ovr_rw[5:0] value based on video Pll frequency in Mhz. If can not find suitable value, return default value 63. 






void DSI_ConfigDphy(MIPI_DSI_Type *base, uint32_t phyRefClkFreq_Hz, uint32_t dataRateFreq_Hz)

config to set Dphy. 

Parameters:

phyRefClkFreq_Hz – Dphy reference clock frequency in Hz 
dataRateFreq_Hz – line rate clock frequency. 







FSL_MIPI_DSI_DRIVER_VERSION






Error codes for the MIPI DSI driver. 
Values:


enumerator kStatus_DSI_Busy

DSI is busy. 




enumerator kStatus_DSI_EccMultiBitError

Multibit ECC error detected in rx packet. 




enumerator kStatus_DSI_CrcError

CRC error detected in rx packet. 




enumerator kStatus_DSI_PacketSizeError

Rx packet size error. 




enumerator kStatus_DSI_EotMissingError

Received transmission does not end with an EoT packet. 




enumerator kStatus_DSI_ErrorReportReceived

Error report package received. 




enumerator kStatus_DSI_NotSupported

The transfer type not supported. 




enumerator kStatus_DSI_PhyError

Physical layer error. 







Status and interrupt mask of acknowledge error sent by device caused by host, belongs to interrupt group1. INT_ST0 bit0-bit15. 
Values:


enumerator kDSI_ErrorReportSot

SoT error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportSotSync

SoT Sync error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportEotSync

EoT Sync error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportEscEntryCmd

Escape Mode Entry Command error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportLpSync

Low-power Transmit Sync error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportPeriphTo

Peripheral Timeout error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportFalseControl

False Control error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportDeviceSpecific1

The deice specific error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportEccOneBit

Single-bit ECC error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportEccMultiBit

Muiti-bit ECC error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportChecksum

Checksum error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportDataTypeUnrecognized

DSI data type not recognized error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportVcIdInvalid

Virtual channel ID invalid error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportTxLengthInvalid

Invalid transmission length error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportDeviceSpecific2

The deice specific error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportProtocolViolation

Protocol violation error detected in device’s acknowledge error report. 




enumerator kDSI_ErrorReportAll








Status and interrupt mask of error in phy layer, belongs to interrupt group1. INT_ST0 bit16-bit20. 
Values:


enumerator kDSI_PhyErrorEscEntry

Escape entry error from Lane 0. 




enumerator kDSI_PhyErrorLpSync

Low-power data transmission synchronization error from Lane 0. 




enumerator kDSI_PhyErrorControl

Control error from Lane 0. 




enumerator kDSI_PhyErrorLp0Connection

LP0 connection error from Lane 0. 




enumerator kDSI_PhyErrorLp1Connection

LP1 connection error from Lane 0. 




enumerator kDSI_PhyErrorAll








Timeout error interrupt and status, belongs to interrupt group2. INT_ST1 bit0-bit6. 
Values:


enumerator kDSI_TimeoutErrorHtx

High Speed forward TX timeout detected. 




enumerator kDSI_TimeoutErrorLrx

Reverse Low power data receive timeout detected. 







Host receive packet error status, belongs to interrupt group2. INT_ST1 bit0-bit6. 
Values:


enumerator kDSI_RxErrorEccOneBit

ECC single bit error detected. 




enumerator kDSI_RxErrorEccMultiBit

ECC multi bit error detected. 




enumerator kDSI_RxErrorCrc

CRC error detected. 




enumerator kDSI_RxErrorPacketSize

Packet size error detected. 




enumerator kDSI_RxErrorEotMissing

Host receives a transmission that does not end with an EoT packet. 




enumerator kDSI_RxErrorAll








Host receive error status, belongs to interrupt group2. INT_ST1 bit7-bit12 bit19? 
Values:


enumerator kDSI_DpiPayloadFifoOverflow

During a DPI pixel line storage, the payload FIFO overflow occurs. 




enumerator kDSI_GenericCommandFifoOverflow

System writes a command through the Generic interface while FIFO is full causing overflow. 




enumerator kDSI_GenericPayloadFifoOverflow

System writes a payload data through the Generic interface while FIFO is full causing payload FIFO overflow. 




enumerator kDSI_GenericPayloadFifoUnderflow

System writes the packet header before the packet payload is completed loaded into the payload FIFO during a packet build causing payload FIFO underflow. 




enumerator kDSI_GenericReadFifoUnderflow

System requests data before it is fully received causing underflow. 




enumerator kDSI_GenericReadFifoOverflow

The Read FIFO size is not correctly dimensioned for the max rx packet size causing generic read FIFO overflow. 







_dsi_dpi_package_flag Flags for DPI package composition. 
Values:


enumerator kDSI_DpiEnableEotpTxHs

Enables the EoTp transmission in high-speed. 




enumerator kDSI_DpiEnableEotpRx

Enables the EoTp reception. 




enumerator kDSI_DpiEnableBta

Enables the Bus Turn-Around (BTA) request. 




enumerator kDSI_DpiEnableEcc

Enables the ECC reception, error correction, and reporting. 




enumerator kDSI_DpiEnableCrc

Enables the CRC reception and error reporting. 




enumerator kDSI_DpiEnableEotpTxLp

Enables the EoTp transmission in low-power. 




enumerator kDSI_DpiEnableAll







enum _dsi_operation_mode

MIPI DSI operation mode. 
Values:


enumerator kDSI_VideoMode

Video mode. 




enumerator kDSI_CommandMode

Command mode. 






enum _dsi_dpi_color_coding

MIPI DPI interface color coding. 
Values:


enumerator kDSI_DpiRGB16Bit

16-bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB. 




enumerator kDSI_DpiRGB16BitLoose0

16-bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB. 




enumerator kDSI_DpiRGB16BitLoose1

16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX. 




enumerator kDSI_DpiRGB18Bit

18-bit configuration 1. RGB666: XXXXXXRR_RRRRGGGG_GGBBBBBB. 




enumerator kDSI_DpiRGB18BitLoose

18-bit configuration 2. RGB666: XXRRRRRR_XXGGGGGG_XXBBBBBB. 




enumerator kDSI_DpiRGB24Bit

24-bit configuration. RGB888: RRRRRRRR_GGGGGGGG_BBBBBBBB. 




enumerator kDSI_DpiYCbCr20Bit

20-bit configuration. YCbCr422 loosely packed. CyCle1: YYYYYYYY_YYXXCbCbCbCb_CbCbCbCbCbCbXX, Cycle2: YYYYYYYY_YYXXCrCrCrCr_CrCrCrCrCrCrXX. 




enumerator kDSI_DpiYCbCr24Bit

24-bit configuration. YCbCr422: CyCle1: YYYYYYYY_YYYYCbCbCbCb_CbCbCbCbCbCbCbCb, Cycle2: YYYYYYYY_YYYYCrCrCrCr_CrCrCrCrCrCrCrCr. 




enumerator kDSI_DpiYCbCr16Bit

16-bit configuration. YCbCr422 loosely packed. CyCle1: YYYYYYYY_YYXXCbCbCbCb_CbCbCbCbCbCbXX, Cycle2: YYYYYYYY_XXXXCrCrCrCr_CrCrCrCrXXXX. 




enumerator kDSI_DpiRGB30Bit

30-bit configuration. RGB10.10.10: XXRRRRRR_RRRRGGGG_GGGGGGBB_BBBBBBBB. 




enumerator kDSI_DpiRGB36Bit

36-bit configuration. RGB12.12.12. CyCle1: XXXXXXRR_RRRRRRRR_RRGGGGGG, Cycle2: XXXXXXGG_GGGGBBBB_BBBBBBBB. 




enumerator kDSI_DpiYCbCr12Bit

12-bit configuration. YCbCr420: CyCle1: Y1Y1Y1Y1Y1Y1Y1Y1_Y0Y0Y0Y0Y0Y0Y0Y0_CbCbCbCbCbCbCbCb, Cycle2: Y1Y1Y1Y1Y1Y1Y1Y1_Y0Y0Y0Y0Y0Y0Y0Y0_CrCrCrCrCrCrCrCr. 




enumerator kDSI_DpiDcs24Bit

24-bit configuration with no specific coding. 







_dsi_dpi_polarity_flag Flags for DPI signal polarity. 
Values:


enumerator kDSI_DpiDataEnableActiveHigh

Data enable pin active high. 




enumerator kDSI_DpiVsyncActiveHigh

VSYNC active high. 




enumerator kDSI_DpiHsyncActiveHigh

HSYNC active high. 




enumerator kDSI_DpiShutDownActiveHigh

Shutdown pin active high. 




enumerator kDSI_DpiColorModeActiveHigh

Color mode pin active high. 




enumerator kDSI_DpiDataEnableActiveLow

Data enable pin active low. 




enumerator kDSI_DpiVsyncActiveLow

VSYNC active low. 




enumerator kDSI_DpiHsyncActiveLow

HSYNC active low. 




enumerator kDSI_DpiShutDownActiveLow

Shutdown pin active low. 




enumerator kDSI_DpiColorModeActiveLow

Color mode pin active low. 






enum _dsi_video_mode

DSI video mode. 
Values:


enumerator kDSI_DpiNonBurstWithSyncPulse

Non-Burst mode with Sync Pulses. 




enumerator kDSI_DpiNonBurstWithSyncEvent

Non-Burst mode with Sync Events. 




enumerator kDSI_DpiBurst

Burst mode. 






enum _dsi_video_pattern

Values:


enumerator kDSI_PatternDisable

Color bar pattern mode disabled. 




enumerator kDSI_PatternVertical

Color bar pattern mode displayed vertically. 




enumerator kDSI_PatternHorizontal

Color bar pattern mode displayed horizontally. 






enum _dsi_tx_data_type

DSI TX data type. 
Values:


enumerator kDSI_TxDataVsyncStart

V Sync start. 




enumerator kDSI_TxDataVsyncEnd

V Sync end. 




enumerator kDSI_TxDataHsyncStart

H Sync start. 




enumerator kDSI_TxDataHsyncEnd

H Sync end. 




enumerator kDSI_TxDataEoTp

End of transmission packet. 




enumerator kDSI_TxDataCmOff

Color mode off. 




enumerator kDSI_TxDataCmOn

Color mode on. 




enumerator kDSI_TxDataShutDownPeriph

Shut down peripheral. 




enumerator kDSI_TxDataTurnOnPeriph

Turn on peripheral. 




enumerator kDSI_TxDataGenShortWrNoParam

Generic Short WRITE, no parameters. 




enumerator kDSI_TxDataGenShortWrOneParam

Generic Short WRITE, one parameter. 




enumerator kDSI_TxDataGenShortWrTwoParam

Generic Short WRITE, two parameter. 




enumerator kDSI_TxDataGenShortRdNoParam

Generic Short READ, no parameters. 




enumerator kDSI_TxDataGenShortRdOneParam

Generic Short READ, one parameter. 




enumerator kDSI_TxDataGenShortRdTwoParam

Generic Short READ, two parameter. 




enumerator kDSI_TxDataDcsShortWrNoParam

DCS Short WRITE, no parameters. 




enumerator kDSI_TxDataDcsShortWrOneParam

DCS Short WRITE, one parameter. 




enumerator kDSI_TxDataDcsShortRdNoParam

DCS Short READ, no parameters. 




enumerator kDSI_TxDataSetMaxReturnPktSize

Set the Maximum Return Packet Size. 




enumerator kDSI_TxDataNull

Null Packet, no data. 




enumerator kDSI_TxDataBlanking

Blanking Packet, no data. 




enumerator kDSI_TxDataGenLongWr

Generic long write. 




enumerator kDSI_TxDataDcsLongWr

DCS Long Write/write_LUT Command Packet. 




enumerator kDSI_TxDataLooselyPackedPixel20BitYCbCr

Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 Format. 




enumerator kDSI_TxDataPackedPixel24BitYCbCr

Packed Pixel Stream, 24-bit YCbCr, 4:2:2 Format. 




enumerator kDSI_TxDataPackedPixel16BitYCbCr

Packed Pixel Stream, 16-bit YCbCr, 4:2:2 Format. 




enumerator kDSI_TxDataPackedPixel30BitRGB

Packed Pixel Stream, 30-bit RGB, 10-10-10 Format. 




enumerator kDSI_TxDataPackedPixel36BitRGB

Packed Pixel Stream, 36-bit RGB, 12-12-12 Format. 




enumerator kDSI_TxDataPackedPixel12BitYCrCb

Packed Pixel Stream, 12-bit YCbCr, 4:2:0 Format. 




enumerator kDSI_TxDataPackedPixel16BitRGB

Packed Pixel Stream, 16-bit RGB, 5-6-5 Format. 




enumerator kDSI_TxDataPackedPixel18BitRGB

Packed Pixel Stream, 18-bit RGB, 6-6-6 Format. 




enumerator kDSI_TxDataLooselyPackedPixel18BitRGB

Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format. 




enumerator kDSI_TxDataPackedPixel24BitRGB

Packed Pixel Stream, 24-bit RGB, 8-8-8 Format. 






enum _dsi_rx_data_type

DSI RX data type. 
Values:


enumerator kDSI_RxDataAckAndErrorReport

Acknowledge and Error Report 




enumerator kDSI_RxDataEoTp

End of Transmission packet. 




enumerator kDSI_RxDataGenShortRdResponseOneByte

Generic Short READ Response, 1 byte returned. 




enumerator kDSI_RxDataGenShortRdResponseTwoByte

Generic Short READ Response, 2 byte returned. 




enumerator kDSI_RxDataGenLongRdResponse

Generic Long READ Response. 




enumerator kDSI_RxDataDcsLongRdResponse

DCS Long READ Response. 




enumerator kDSI_RxDataDcsShortRdResponseOneByte

DCS Short READ Response, 1 byte returned. 




enumerator kDSI_RxDataDcsShortRdResponseTwoByte

DCS Short READ Response, 2 byte returned. 







_dsi_transfer_flags DSI transfer control flags. 
Values:


enumerator kDSI_TransferUseLowPower

Use low power or not. 




enumerator kDSI_TransferPerformBTA

Perform BTA or not at the end of a frame. 






typedef enum _dsi_operation_mode dsi_operation_mode_t

MIPI DSI operation mode. 




typedef struct _dsi_config dsi_config_t

MIPI DSI controller configuration. 




typedef enum _dsi_dpi_color_coding dsi_dpi_color_coding_t

MIPI DPI interface color coding. 




typedef enum _dsi_video_mode dsi_video_mode_t

DSI video mode. 




typedef enum _dsi_video_pattern dsi_video_pattern_t





typedef struct _dsi_dpi_config dsi_dpi_config_t

MIPI DSI controller DPI interface configuration. 




typedef struct _dsi_command_config dsi_command_config_t

MIPI DSI command mode configuration. 




typedef struct _dsi_dphy_config dsi_dphy_config_t

MIPI DSI D-PHY configuration. 




typedef enum _dsi_tx_data_type dsi_tx_data_type_t

DSI TX data type. 




typedef enum _dsi_rx_data_type dsi_rx_data_type_t

DSI RX data type. 




typedef struct _dsi_transfer dsi_transfer_t

Structure for the data transfer. 




uint32_t DSI_GetInstance(MIPI_DSI_Type *base)

Gets the MIPI DSI host controller instance from peripheral base address. 

Parameters:

base – MIPI DSI peripheral base address. 


Returns:
MIPI DSI instance. 






TX_DPHY_TX_PLL_1





TX_DPHY_TX_PLL_5





TX_DPHY_TX_PLL_9





TX_DPHY_TX_PLL_13





TX_DPHY_TX_PLL_17





TX_DPHY_TX_PLL_22





TX_DPHY_TX_PLL_23





TX_DPHY_TX_PLL_24





TX_DPHY_TX_PLL_25





TX_DPHY_TX_PLL_27





TX_DPHY_TX_PLL_28





TX_DPHY_TX_PLL_29





TX_DPHY_TX_PLL_30





TX_DPHY_TX_PLL_31





TX_DPHY_TX_CB_0





TX_DPHY_TX_CB_1





TX_DPHY_TX_CB_2





TX_DPHY_TX_SLEW_5





TX_DPHY_TX_SLEW_6





TX_DPHY_TX_SLEW_7





TX_DPHY_TX_CLK_TERMLOWCAP





struct _dsi_config


#include <fsl_mipi_dsi.h>
MIPI DSI controller configuration. 

Public Members


dsi_operation_mode_t mode

DSI operation mode. MODE_CFG[cmd_video_mode] 




uint8_t packageFlags

OR’ed value of _dsi_dpi_package_flag that controls DPI package composition. PCKHDL_CFG 




bool enableNoncontinuousClk

Enables the automatic mechanism to stop providing clock in the clock lane when time allows. LPCLK_CTRL[auto_clklane_ctrl] 




uint16_t HsRxDeviceReady_ByteClk

The min time the display device takes to process high-speed read from master before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measured in lane byte clock. HS_RD_TO_CNT[hs_rd_to_cnt] 




uint16_t lpRxDeviceReady_ByteClk

The min time the display device takes to process low-power read from master before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measured in lane byte clock. LP_RD_TO_CNT[lp_rd_to_cnt] 




uint16_t HsTxDeviceReady_ByteClk

The min time the display device takes to process high-speed write from master before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measured in lane byte clock. HS_WR_TO_CNT[hs_wr_to_cnt] 




uint16_t lpTxDeviceReady_ByteClk

The min time the display device takes to process low-power write from master before it can continue doing other stuff. The timer starts when D-PHY enters stop state and measured in lane byte clock. LP_WR_TO_CNT[lp_wr_to_cnt] 







struct _dsi_dpi_config


#include <fsl_mipi_dsi.h>
MIPI DSI controller DPI interface configuration. 

Public Members


uint8_t virtualChannel

Virtual channel. DPI_VCID[dpi_vcid] 




dsi_dpi_color_coding_t colorCoding

DPI color coding. DPI_COLOR_CODING 




uint8_t polarityFlags

OR’ed value of _dsi_dpi_polarity_flag that controls signal polarity. DPI_CFG_POL 




bool enablelpSwitch

Enable return to low-power inside the VSA/VBP/VFP/VACT/HBP/HFP period when timing allows. VID_MODE_CFG[bit8-13] 




bool enableAck

Enable the request for an acknowledge response at the end of a frame. VID_MODE_CFG[frame_bta_ack_en] 




dsi_video_mode_t videoMode

Video mode. VID_MODE_CFG[vid_mode_type] 




uint16_t pixelPayloadSize

Color bar pattern. VID_MODE_CFG[vpg_orientation][vpg_en][vpg_mode=0] The number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4, for YCbCr data types, it must be a multiple of 2. Recommended to set to the line size (in pixels). VID_PKT_SIZE 




uint16_t vsw

Number of lines in vertical sync width. VID_VSA_LINES 




uint16_t vbp

Number of lines in vertical back porch. VID_VBP_LINES 




uint16_t vfp

Number of lines in vertical front porch. VID_VFP_LINES 




uint16_t panelHeight

Number of lines in vertical active area. VID_VACTIVE_LINES 




uint16_t hsw

Horizontal sync width, in dpi pixel clock. VID_HSA_TIME 




uint16_t hbp

Horizontal back porch, in dpi pixel clock. VID_HBP_TIME 




uint16_t hfp

Horizontal front porch, in dpi pixel clock. VID_HLINE_TIME = (hsw+hbp+hfp+width) 







struct _dsi_command_config


#include <fsl_mipi_dsi.h>
MIPI DSI command mode configuration. 

Public Members


uint32_t escClkFreq_Hz

Escape clock frequencey in Hz. 




uint16_t lpRxTo_Ns

Timeout value that triggers a low-power reception timeout contention detection. TO_CNT_CFG[lprx_to_cnt] 




uint16_t hsTxTo_Ns

Timeout value that triggers a high-speed transmission timeout contention detection. In non-burst mode, the time should be larger than 1.1 times of one frame data transmission time, in burst mode it should be one line. TO_CNT_CFG[hstx_to_cnt] 




uint16_t btaTo_Ns

The time period for which MIPI DSI host keeps the link still after completing a Bus Turnaround. BTA_TO_CNT[bta_to_cnt] 







struct _dsi_dphy_config


#include <fsl_mipi_dsi.h>
MIPI DSI D-PHY configuration. 

Public Members


uint8_t numLanes

Number of lanes. The value range is from 1-4, lane 0-3. PHY_IF_CFG[n_lanes] 




uint8_t tStopState_ByteClk

Minimum time that the PHY controller stays in stop state before a HS transmission. TODO in what unit? PHY_IF_CFG[phy_stop_wait_time] 




uint16_t tClkHs2Lp_ByteClk

Maximum time that the D-PHY clock lane takes to go from high-speed to low-power in lane byte clock. PHY_TMR_LPCLK_CFG[phy_clkhs2lp_time] 




uint16_t tClkLp2Hs_ByteClk

Maximum time that the D-PHY clock lane takes to go from low-power to high-speed in lane byte clock. PHY_TMR_LPCLK_CFG[phy_clklp2hs_time] 




uint16_t tDataHs2Lp_ByteClk

Maximum time that the D-PHY data lane takes to go from high-speed to low-power in lane byte clock. PHY_TMR_CFG[phy_hs2lp_time] 




uint16_t tDataLp2Hs_ByteClk

Maximum time that the D-PHY data lane takes to go from low-power to high-speed in lane byte clock. PHY_TMR_CFG[phy_lp2hs_time] 




uint16_t maxRead_ByteClk

Maximum time required to perform a read command in lane byte clock. PHY_TMR_RD_CFG[max_rd_time] 







struct _dsi_transfer


#include <fsl_mipi_dsi.h>
Structure for the data transfer. 

Public Members


uint8_t virtualChannel

Virtual channel. 




dsi_tx_data_type_t txDataType

TX data type. 




uint8_t flags

Flags to control the transfer, see _dsi_transfer_flags. 




const uint8_t *txData

The TX data buffer. 




uint8_t *rxData

The TX data buffer. 




uint16_t txDataSize

Size of the TX data. 




uint16_t rxDataSize

Size of the RX data. 




bool sendDcsCmd

If set to true, the DCS command is specified by dcsCmd, otherwise the DCS command is included in the txData. 




uint8_t dcsCmd

The DCS command to send, only valid when sendDcsCmd is true. 







MIPI_DSI: MIPI DSI Host Controller#


MU: Messaging Unit#


uint32_t MU_GetInstance(MU_Type *base)

Get the MU instance index. 

Parameters:

base – MU peripheral base address. 


Returns:
MU instance index. 






void MU_Init(MU_Type *base)

Initializes the MU module. 
This function enables the MU clock only.

Parameters:

base – MU peripheral base address. 







void MU_Deinit(MU_Type *base)

De-initializes the MU module. 
This function disables the MU clock only.

Parameters:

base – MU peripheral base address. 







static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)

Writes a message to the TX register. 
This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.
while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.



Parameters:

base – MU peripheral base address. 
regIndex – TX register index, see mu_msg_reg_index_t. 
msg – Message to send. 







status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)

Blocks to send a message. 
This function waits until the TX register is empty and sends the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and returns kStatus_Timeout.

Parameters:

base – MU peripheral base address. 
regIndex – MU message register, see mu_msg_reg_index_t. 
msg – Message to send.


Return values:

kStatus_Success – Message sent successfully. 
kStatus_Timeout – Timeout occurred while waiting for TX register to be empty. 


Returns:
status_t 






static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)

Reads a message from the RX register. 
This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.
uint32_t msg;
while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
{
}  Wait for the RX0 register full.

msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.



Parameters:

base – MU peripheral base address. 
regIndex – RX register index, see mu_msg_reg_index_t. 


Returns:
The received message. 






status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue)

Blocks to receive a message with timeout protection. 
This function waits until the RX register is full and receives the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.
This function provides the same blocking behavior as MU_ReceiveMsg() but with additional timeout protection to prevent system hangs if the other core becomes unresponsive or if hardware issues occur.

Note
Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that this function includes timeout protection while MU_ReceiveMsg() waits indefinitely.


Parameters:

base – MU peripheral base address. 
regIndex – RX register index, see mu_msg_reg_index_t. 
readValue – Pointer to store the received message.


Return values:

kStatus_Success – Message received successfully. 
kStatus_InvalidArgument – Invalid readValue pointer. 
kStatus_Timeout – Timeout occurred while waiting for RX register to be full. 


Returns:
status_t 






uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)

Blocks to receive a message (infinite wait, no timeout protection). 
This function waits until the RX register is full and receives the message. This function will wait indefinitely until a message is received.

Note
Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that MU_ReceiveMsgTimeout() includes timeout protection while this function waits indefinitely.


Warning
This function does not include timeout protection and may cause system hangs if the other core becomes unresponsive. For applications requiring timeout protection, use MU_ReceiveMsgTimeout() instead.


Parameters:

base – MU peripheral base address. 
regIndex – RX register index, see mu_msg_reg_index_t. 


Returns:
The received message. 






static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)

Sets the 3-bit MU flags reflect on the other MU side. 
This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.
while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
{
}  Wait for previous MU flags updating.

MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.



Parameters:

base – MU peripheral base address. 
flags – The 3-bit MU flags to set. 







status_t MU_SetFlags(MU_Type *base, uint32_t flags)

brief Blocks setting the 3-bit MU flags reflect on the other MU side.
This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.
If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

return status_t retval kStatus_Success Flags were set successfully. retval kStatus_Timeout Timeout occurred while waiting for flags to update. 

Parameters:

base – MU peripheral base address. 
flags – The 3-bit MU flags to set.







static inline uint32_t MU_GetFlags(MU_Type *base)

Gets the current value of the 3-bit MU flags set by the other side. 
This function gets the current 3-bit MU flags on the current side.

Parameters:

base – MU peripheral base address. 


Returns:
flags Current value of the 3-bit flags. 






uint32_t MU_GetStatusFlags(MU_Type *base)

Gets the MU status flags. 
This function returns the bit mask of the MU status flags. See _mu_status_flags.
uint32_t flags;
flags = MU_GetStatusFlags(base);  Get all status flags.
if (kMU_Tx0EmptyFlag & flags)
{
    The TX0 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
}
if (kMU_Tx1EmptyFlag & flags)
{
    The TX1 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
}


If there are more than 4 general purpose interrupts, use MU_GetGeneralPurposeStatusFlags.

Parameters:

base – MU peripheral base address. 


Returns:
Bit mask of the MU status flags, see _mu_status_flags. 






static inline uint32_t MU_GetInterruptsPending(MU_Type *base)

Gets the MU IRQ pending status of enabled interrupts. 
This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag

Parameters:

base – MU peripheral base address. 


Returns:
Bit mask of the MU IRQs pending. 






static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t flags)

Clears the specific MU status flags. 
This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.
Clear general interrupt 0 and general interrupt 1 pending flags.
MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);


If there are more than 4 general purpose interrupts, use MU_ClearGeneralPurposeStatusFlags.

Parameters:

base – MU peripheral base address. 
flags – Bit mask of the MU status flags. See _mu_status_flags. Only the following flags can be cleared by software (if applicable for particular device), other flags are cleared by hardware:

kMU_GenInt0Flag
kMU_GenInt1Flag
kMU_GenInt2Flag
kMU_GenInt3Flag
kMU_MuResetInterruptFlag
kMU_OtherSideEnterRunInterruptFlag
kMU_OtherSideEnterHaltInterruptFlag
kMU_OtherSideEnterWaitInterruptFlag
kMU_OtherSideEnterStopInterruptFlag
kMU_OtherSideEnterPowerDownInterruptFlag
kMU_ResetAssertInterruptFlag
kMU_HardwareResetInterruptFlag 









static inline void MU_EnableInterrupts(MU_Type *base, uint32_t interrupts)

Enables the specific MU interrupts. 
This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.
   Enable general interrupt 0 and TX0 empty interrupt.
MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);


If there are more than 4 general purpose interrupts, use MU_EnableGeneralPurposeInterrupts.

Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable. 







static inline void MU_DisableInterrupts(MU_Type *base, uint32_t interrupts)

Disables the specific MU interrupts. 
This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.
   Disable general interrupt 0 and TX0 empty interrupt.
MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);


If there are more than 4 general purpose interrupts, use MU_DisableGeneralPurposeInterrupts.

Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable. 







status_t MU_TriggerInterrupts(MU_Type *base, uint32_t interrupts)

Triggers interrupts to the other core. 
This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.
if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}


If there are more than 4 general purpose interrupts, use MU_TriggerGeneralPurposeInterrupts.

Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. 


Return values:

kStatus_Success – Interrupts have been triggered successfully. 
kStatus_Fail – Previous interrupts have not been accepted. 







static inline void MU_EnableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Enables the MU general purpose interrupts. 
This function enables the MU general purpose interrupts. The interrupts to enable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_EnableInterrupts only support general interrupt 0~3, this function supports all general interrupts.
For example, to enable general purpose interrupt 0 and 3, use like this: 
MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);




Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU general purpose interrupts, see mu_general_purpose_interrupt_t. 







static inline void MU_DisableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Disables the MU general purpose interrupts. 
This function disables the MU general purpose interrupts. The interrupts to disable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_DisableInterrupts only support general interrupt 0~3, this function supports all general interrupts.
For example, to disable general purpose interrupt 0 and 3, use like this: 
MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);




Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the MU general purpose interrupts. see mu_general_purpose_interrupt_t. 







static inline uint32_t MU_GetGeneralPurposeStatusFlags(MU_Type *base)

Gets the MU general purpose interrupt status flags. 
This function returns the bit mask of the MU general purpose interrupt status flags. MU_GetStatusFlags can only get general purpose interrupt status 0~3, this function can get all general purpose interrupts status.
This example shows to check whether general purpose interrupt 0 and 3 happened.
uint32_t flags;
flags = MU_GetGeneralPurposeStatusFlags(base);
if (kMU_GeneralPurposeInterrupt0 & flags)
{
}
if (kMU_GeneralPurposeInterrupt3 & flags)
{
}



Parameters:

base – MU peripheral base address. 


Returns:
Bit mask of the MU general purpose interrupt status flags. 






static inline void MU_ClearGeneralPurposeStatusFlags(MU_Type *base, uint32_t flags)

Clear the MU general purpose interrupt status flags. 
This function clears the specific MU general purpose interrupt status flags. The flags to clear should be passed in as bit mask. mu_general_purpose_interrupt_t_mu_status_flags.
Example to clear general purpose interrupt 0 and general interrupt 1 pending flags. 
MU_ClearGeneralPurposeStatusFlags(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt1);




Parameters:

base – MU peripheral base address. 
flags – Bit mask of the MU general purpose interrupt status flags. See mu_general_purpose_interrupt_t. 







static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)

Return the RX status flags in reverse numerical order. 
This function return the RX status flags in reverse order. Note: RFn bits of SR[3-0](mu status register) are mapped in ascending numerical order: RF0 -> SR[0] RF1 -> SR[1] RF2 -> SR[2] RF3 -> SR[3] This function will return these bits in reverse numerical order(RF3->RF1) to comply with MU_GetRxStatusFlags() of mu driver. See MU_GetRxStatusFlags() from drivers/mu/fsl_mu.h
status_reg = MU_GetRxStatusFlags(base);



Parameters:

base – MU peripheral base address. 


Returns:
MU RX status flags in reverse order 






status_t MU_TriggerGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Triggers general purpose interrupts to the other core. 
This function triggers the specific general purpose interrupts to the other core. The interrupts to trigger are passed in as bit mask. See mu_general_purpose_interrupt_t. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.
status_t status;
status = MU_TriggerGeneralPurposeInterrupts(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt2);

if (kStatus_Success != status)
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}



Parameters:

base – MU peripheral base address. 
interrupts – Bit mask of the interrupts to trigger. See mu_general_purpose_interrupt_t. 


Return values:

kStatus_Success – Interrupts have been triggered successfully. 
kStatus_Fail – Previous interrupts have not been accepted. 







void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode)

Boots the other core. 
This function boots the other core with a boot configuration.

Parameters:

base – MU peripheral base address. 
mode – The other core boot mode. 







void MU_HoldOtherCoreReset(MU_Type *base)

Holds the other core reset. 
This function causes the other core to be held in reset following any reset event.

Parameters:

base – MU peripheral base address. 







static inline status_t MU_ResetBothSides(MU_Type *base)

Resets the MU for both A side and B side. 
This function resets the MU for both A side and B side. Before reset, it is recommended to interrupt processor B, because this function may affect the ongoing processor B programs.
If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations if waiting for the other side to come out of reset takes too long.

Note
For some platforms, only MU side A could use this function, check reference manual for details. 


Parameters:

base – MU peripheral base address. 


Return values:

kStatus_Success – The MU was reset successfully. 
kStatus_Timeout – Timeout occurred while waiting for the other side to come out of reset.


Returns:
status_t 






status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)

Hardware reset the other core. 
This function resets the other core, the other core could mask the hardware reset by calling MU_MaskHardwareReset. The hardware reset mask feature is only available for some platforms. This function could be used together with MU_BootOtherCore to control the other core reset workflow.
If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout if waiting for the other core to enter or exit reset takes too long.
Example 1: Reset the other core, and no hold reset 
MU_HardwareResetOtherCore(MU_A, true, false, bootMode);


 In this example, the core at MU side B will reset with the specified boot mode.
Example 2: Reset the other core and hold it, then boot the other core later. Here the other core enters reset, and the reset is hold 
MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);


 Current core boot the other core when necessary. MU_BootOtherCore(MU_A, bootMode);




Note
The feature waitReset, holdReset, and bootMode might be not supported for some platforms. waitReset is only available for platforms that FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0. bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not defined as 0.


Parameters:

base – MU peripheral base address. 
waitReset – Wait the other core enters reset. Only work when there is CSSR0[RAIP].

true: Wait until the other core enters reset, if the other core has masked the hardware reset, then this function will be blocked.
false: Don’t wait the reset. 


holdReset – Hold the other core reset or not. Only work when there is CCR0[RSTH].

true: Hold the other core in reset, this function returns directly when the other core enters reset.
false: Don’t hold the other core in reset, this function waits until the other core out of reset. 


bootMode – Boot mode of the other core, if holdReset is true, this parameter is useless.


Return values:

kStatus_Success – The other core was reset successfully. 
kStatus_Timeout – Timeout occurred while waiting for the other core to enter or exit reset. 


Returns:
status_t 






FSL_MU_DRIVER_VERSION

MU driver version. 




enum _mu_status_flags

MU status flags. 
Values:


enumerator kMU_Tx0EmptyFlag

TX0 empty. 




enumerator kMU_Tx1EmptyFlag

TX1 empty. 




enumerator kMU_Tx2EmptyFlag

TX2 empty. 




enumerator kMU_Tx3EmptyFlag

TX3 empty. 




enumerator kMU_Rx0FullFlag

RX0 full. 




enumerator kMU_Rx1FullFlag

RX1 full. 




enumerator kMU_Rx2FullFlag

RX2 full. 




enumerator kMU_Rx3FullFlag

RX3 full. 




enumerator kMU_GenInt0Flag

General purpose interrupt 0 pending. 




enumerator kMU_GenInt1Flag

General purpose interrupt 1 pending. 




enumerator kMU_GenInt2Flag

General purpose interrupt 2 pending. 




enumerator kMU_GenInt3Flag

General purpose interrupt 3 pending. 




enumerator kMU_RxFullPendingFlag

Any RX full flag is pending. 




enumerator kMU_TxEmptyPendingFlag

Any TX empty flag is pending. 




enumerator kMU_GenIntPendingFlag

Any general interrupt flag is pending. 




enumerator kMU_EventPendingFlag

MU event pending. 




enumerator kMU_FlagsUpdatingFlag

MU flags update is on-going. 




enumerator kMU_MuInResetFlag

MU of any side is in reset. 




enumerator kMU_MuResetInterruptFlag

The other side initializes MU reset. 






enum _mu_interrupt_enable

MU interrupt source to enable. 
Values:


enumerator kMU_Tx0EmptyInterruptEnable

TX0 empty. 




enumerator kMU_Tx1EmptyInterruptEnable

TX1 empty. 




enumerator kMU_Tx2EmptyInterruptEnable

TX2 empty. 




enumerator kMU_Tx3EmptyInterruptEnable

TX3 empty. 




enumerator kMU_Rx0FullInterruptEnable

RX0 full. 




enumerator kMU_Rx1FullInterruptEnable

RX1 full. 




enumerator kMU_Rx2FullInterruptEnable

RX2 full. 




enumerator kMU_Rx3FullInterruptEnable

RX3 full. 




enumerator kMU_GenInt0InterruptEnable

General purpose interrupt 0. 




enumerator kMU_GenInt1InterruptEnable

General purpose interrupt 1. 




enumerator kMU_GenInt2InterruptEnable

General purpose interrupt 2. 




enumerator kMU_GenInt3InterruptEnable

General purpose interrupt 3. 




enumerator kMU_MuResetInterruptEnable

The other side initializes MU reset. 






enum _mu_interrupt_trigger

MU interrupt that could be triggered to the other core. 
Values:


enumerator kMU_GenInt0InterruptTrigger

General purpose interrupt 0. 




enumerator kMU_GenInt1InterruptTrigger

General purpose interrupt 1. 




enumerator kMU_GenInt2InterruptTrigger

General purpose interrupt 2. 




enumerator kMU_GenInt3InterruptTrigger

General purpose interrupt 3. 






enum _mu_msg_reg_index

MU message register index. 
Values:


enumerator kMU_MsgReg0

Message register 0. 




enumerator kMU_MsgReg1

Message register 1. 




enumerator kMU_MsgReg2

Message register 2. 




enumerator kMU_MsgReg3

Message register 3. 






enum _mu_general_purpose_interrupt

MU general purpose interrupts. 
Values:


enumerator kMU_GeneralPurposeInterrupt0

General purpose interrupt 0 




enumerator kMU_GeneralPurposeInterrupt1

General purpose interrupt 1 




enumerator kMU_GeneralPurposeInterrupt2

General purpose interrupt 2 




enumerator kMU_GeneralPurposeInterrupt3

General purpose interrupt 3 






typedef enum _mu_msg_reg_index mu_msg_reg_index_t

MU message register index. 




typedef enum _mu_general_purpose_interrupt mu_general_purpose_interrupt_t

MU general purpose interrupts. 




MU_CORE_INTR(intr)





MU_MISC_INTR(intr)





MU_TX_INTR(intr)





MU_RX_INTR(intr)





MU_GI_INTR(intr)





MU_GET_CORE_INTR(intrs)





MU_GET_TX_INTR(intrs)





MU_GET_RX_INTR(intrs)





MU_GET_GI_INTR(intrs)





MU_CORE_FLAG(flag)





MU_STAT_FLAG(flag)





MU_TX_FLAG(flag)





MU_RX_FLAG(flag)





MU_GI_FLAG(flag)





MU_GET_CORE_FLAG(flags)





MU_GET_STAT_FLAG(flags)





MU_GET_TX_FLAG(flags)





MU_GET_RX_FLAG(flags)





MU_GET_GI_FLAG(flags)





MU1_BUSY_POLL_COUNT

Maximum polling iterations for MU waiting loops. 
This parameter defines the maximum number of iterations for any polling loop in the MU code before timing out and returning an error.
It applies to all waiting loops in MU driver, such as waiting for TX register to be empty or waiting for RX register to be full.
This is a count of loop iterations, not a time-based value.
If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if a core becomes unresponsive. 




OTFAD: On The Fly AES-128 Decryption Driver#


void OTFAD_GetDefaultConfig(otfad_config_t *config)

OTFAD module initialization function. 

Parameters:

config – OTFAD configuration. 







void OTFAD_Init(OTFAD_Type *base, const otfad_config_t *config)

OTFAD module initialization function. 

Parameters:

base – OTFAD base address. 
config – OTFAD configuration. 







void OTFAD_Deinit(OTFAD_Type *base)

Deinitializes the OTFAD. 




static inline uint32_t OTFAD_GetOperateMode(OTFAD_Type *base)

OTFAD module get operate mode. 

Parameters:

base – OTFAD base address. 







static inline uint32_t OTFAD_GetStatus(OTFAD_Type *base)

OTFAD module get status. 

Parameters:

base – OTFAD base address. 







status_t OTFAD_SetEncryptionConfig(OTFAD_Type *base, const otfad_encryption_config_t *config)

OTFAD module set encryption configuration. 

Note: if enable keyblob process, the first 256 bytes external memory is use for keyblob data, so this region shouldn’t be in OTFAD region. 

Parameters:

base – OTFAD base address. 
config – encryption configuration.







status_t OTFAD_GetEncryptionConfig(OTFAD_Type *base, otfad_encryption_config_t *config)

OTFAD module get encryption configuration. 

Note: if enable keyblob process, the first 256 bytes external memory is use for keyblob data, so this region shouldn’t be in OTFAD region. 

Parameters:

base – OTFAD base address. 
config – encryption configuration.







status_t OTFAD_HitDetermination(OTFAD_Type *base, uint32_t address, uint8_t *contextIndex)

OTFAD module do hit determination. 

Parameters:

base – OTFAD base address. 
address – the physical address space assigned to the QuadSPI(FlexSPI) module. 
contextIndex – hitted context region index. 


Returns:
status, such as kStatus_Success or kStatus_OTFAD_ResRegAccessMode. 






FSL_OTFAD_DRIVER_VERSION

Driver version. 





Status codes for the OTFAD driver. 
Values:


enumerator kStatus_OTFAD_ResRegAccessMode

Restricted register mode 




enumerator kStatus_OTFAD_AddressError

End address less than start address 




enumerator kStatus_OTFAD_RegionOverlap

the OTFAD does not support any form of memory region overlap, for system accesses that hit in multiple contexts or no contexts, the fetched data is simply bypassed 




enumerator kStatus_OTFAD_RegionMiss

For accesses that hit in a single context, but not the selected one 







OTFAD context type. 
Values:


enumerator kOTFAD_Context_0

context 0 




enumerator kOTFAD_Context_1

context 1 




enumerator kOTFAD_Context_2

context 2 




enumerator kOTFAD_Context_3

context 3 







OTFAD operate mode. 
Values:


enumerator kOTFAD_NRM

Normal Mode 




enumerator kOTFAD_SVM

Security Violation Mode 




enumerator kOTFAD_LDM

Logically Disabled Mode 






typedef struct _otfad_encryption_config otfad_encryption_config_t

OTFAD encryption configuration structure. 




typedef struct _otfad_config otfad_config_t

OTFAD configuration structure. 




struct _otfad_encryption_config


#include <fsl_otfad.h>
OTFAD encryption configuration structure. 

Public Members


bool valid

The context is valid or not 




bool AESdecryption

AES decryption enable 




uint8_t readOnly

read write attribute for the entire set of context registers 




uint8_t contextIndex

OTFAD context index 




uint32_t startAddr

Start address 




uint32_t endAddr

End address 




uint32_t key[4]

Encryption key 




uint32_t counter[2]

Encryption counter 







struct _otfad_config


#include <fsl_otfad.h>
OTFAD configuration structure. 

Public Members


bool forceSVM

Force entry into SVM after a write 




bool forceLDM

Force entry into LDM after a write 




bool restrictedRegAccess

Restricted register access enable 




bool enableOTFAD

OTFAD has decryption enabled 







PDM: Microphone Interface#


PDM Driver#


void PDM_Init(PDM_Type *base, const pdm_config_t *config)

Initializes the PDM peripheral. 
Ungates the PDM clock, resets the module, and configures PDM with a configuration structure. The configuration structure can be custom filled or set with default values by PDM_GetDefaultConfig().

Note
This API should be called at the beginning of the application to use the PDM driver. Otherwise, accessing the PDM module can cause a hard fault because the clock is not enabled.


Parameters:

base – PDM base pointer 
config – PDM configuration structure. 







void PDM_Deinit(PDM_Type *base)

De-initializes the PDM peripheral. 
This API gates the PDM clock. The PDM module can’t operate unless PDM_Init is called to enable the clock.

Parameters:

base – PDM base pointer 







static inline void PDM_Reset(PDM_Type *base)

Resets the PDM module. 

Parameters:

base – PDM base pointer 







static inline void PDM_Enable(PDM_Type *base, bool enable)

Enables/disables PDM interface. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface is enabled, false means PDM interface is disabled. 







static inline void PDM_EnableDebugMode(PDM_Type *base, bool enable)

Enables/disables debug mode for PDM. The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface enter debug mode, false means PDM interface in normal mode. 







static inline void PDM_EnableInDebugMode(PDM_Type *base, bool enable)

Enables/disables PDM interface in debug mode. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface is enabled debug mode, false means PDM interface is disabled after after completing the current frame in debug mode. 







static inline void PDM_EnterLowLeakageMode(PDM_Type *base, bool enable)

Enables/disables PDM interface disable/Low Leakage mode. 

Parameters:

base – PDM base pointer 
enable – True means PDM interface is in disable/low leakage mode, False means PDM interface is in normal mode. 







static inline void PDM_EnableChannel(PDM_Type *base, uint8_t channel, bool enable)

Enables/disables the PDM channel. 

Parameters:

base – PDM base pointer 
channel – PDM channel number need to enable or disable. 
enable – True means enable PDM channel, false means disable. 







void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config)

PDM one channel configurations. 

Parameters:

base – PDM base pointer 
config – PDM channel configurations. 
channel – channel number. after completing the current frame in debug mode. 







status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ)

PDM set sample rate. 

Note
This function is depend on the configuration of the PDM and PDM channel, so the correct call sequence is 
PDM_Init(base, pdmConfig)
PDM_SetChannelConfig(base, channel, &channelConfig)
PDM_SetSampleRateConfig(base, source, sampleRate)





Parameters:

base – PDM base pointer 
sourceClock_HZ – PDM source clock frequency. 
sampleRate_HZ – PDM sample rate. 







status_t PDM_SetSampleRate(PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv)

PDM set sample rate. 


Deprecated:
Do not use this function. It has been superceded by PDM_SetSampleRateConfig




Parameters:

base – PDM base pointer 
enableChannelMask – PDM channel enable mask. 
qualityMode – quality mode. 
osr – cic oversample rate 
clkDiv – clock divider 







uint32_t PDM_GetInstance(PDM_Type *base)

Get the instance number for PDM. 

Parameters:

base – PDM base pointer. 







static inline uint32_t PDM_GetStatus(PDM_Type *base)

Gets the PDM internal status flag. Use the Status Mask in _pdm_internal_status to get the status value needed. 

Parameters:

base – PDM base pointer 


Returns:
PDM status flag value. 






static inline uint32_t PDM_GetFifoStatus(PDM_Type *base)

Gets the PDM FIFO status flag. Use the Status Mask in _pdm_fifo_status to get the status value needed. 

Parameters:

base – PDM base pointer 


Returns:
FIFO status. 






static inline uint32_t PDM_GetRangeStatus(PDM_Type *base)

Gets the PDM Range status flag. Use the Status Mask in _pdm_range_status to get the status value needed. 

Parameters:

base – PDM base pointer 


Returns:
output status. 






static inline void PDM_ClearStatus(PDM_Type *base, uint32_t mask)

Clears the PDM Tx status. 

Parameters:

base – PDM base pointer 
mask – State mask. It can be a combination of the status between kPDM_StatusFrequencyLow and kPDM_StatusCh7FifoDataAvaliable. 







static inline void PDM_ClearFIFOStatus(PDM_Type *base, uint32_t mask)

Clears the PDM Tx status. 

Parameters:

base – PDM base pointer 
mask – State mask.It can be a combination of the status in _pdm_fifo_status. 







static inline void PDM_ClearRangeStatus(PDM_Type *base, uint32_t mask)

Clears the PDM range status. 

Parameters:

base – PDM base pointer 
mask – State mask. It can be a combination of the status in _pdm_range_status. 







void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask)

Enables the PDM interrupt requests. 

Parameters:

base – PDM base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kPDM_ErrorInterruptEnable 
kPDM_FIFOInterruptEnable 









static inline void PDM_DisableInterrupts(PDM_Type *base, uint32_t mask)

Disables the PDM interrupt requests. 

Parameters:

base – PDM base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kPDM_ErrorInterruptEnable 
kPDM_FIFOInterruptEnable 









static inline void PDM_EnableDMA(PDM_Type *base, bool enable)

Enables/disables the PDM DMA requests. 

Parameters:

base – PDM base pointer 
enable – True means enable DMA, false means disable DMA. 







static inline uint32_t PDM_GetDataRegisterAddress(PDM_Type *base, uint32_t channel)

Gets the PDM data register address. 
This API is used to provide a transfer address for the PDM DMA transfer configuration.

Parameters:

base – PDM base pointer. 
channel – Which data channel used. 


Returns:
data register address. 






void PDM_ReadFifo(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth)

PDM read fifo. 

Note
: This function support 16 bit only for IP version that only supports 16bit.


Parameters:

base – PDM base pointer. 
startChannel – start channel number. 
channelNums – total enabled channelnums. 
buffer – received buffer address. 
size – number of samples to read. 
dataWidth – sample width. 







void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain)

Set the PDM channel gain. 
Please note for different quality mode, the valid gain value is different, reference RM for detail. 

Parameters:

base – PDM base pointer. 
channel – PDM channel index. 
gain – channel gain, the register gain value range is 0 - 15. 







void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData)

Initializes the PDM handle. 
This function initializes the handle for the PDM transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – PDM base pointer. 
handle – PDM handle pointer. 
callback – Pointer to the user callback function. 
userData – User parameter passed to the callback function. 







status_t PDM_TransferSetChannelConfig(PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format)

PDM set channel transfer config. 

Parameters:

base – PDM base pointer. 
handle – PDM handle pointer. 
channel – PDM channel. 
config – channel config. 
format – data format, support data width configurations,_pdm_data_width. 


Return values:
kStatus_PDM_ChannelConfig_Failed – or kStatus_Success. 






status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on PDM. 

Note
This API returns immediately after the transfer initiates. Call the PDM_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_PDM_Busy, the transfer is finished.


Parameters:

base – PDM base pointer 
handle – Pointer to the pdm_handle_t structure which stores the transfer state. 
xfer – Pointer to the pdm_transfer_t structure. 


Return values:

kStatus_Success – Successfully started the data receive. 
kStatus_PDM_Busy – Previous receive still not finished. 







void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle)

Aborts the current IRQ receive. 

Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – PDM base pointer 
handle – Pointer to the pdm_handle_t structure which stores the transfer state. 







void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle)

Tx interrupt handler. 

Parameters:

base – PDM base pointer. 
handle – Pointer to the pdm_handle_t structure. 







FSL_PDM_DRIVER_VERSION

Version 2.9.4 





PDM return status. 
Values:


enumerator kStatus_PDM_Busy

PDM is busy. 




enumerator kStatus_PDM_CLK_LOW

PDM clock frequency low 




enumerator kStatus_PDM_FIFO_ERROR

PDM FIFO underrun or overflow 




enumerator kStatus_PDM_QueueFull

PDM FIFO underrun or overflow 




enumerator kStatus_PDM_Idle

PDM is idle 




enumerator kStatus_PDM_Output_ERROR

PDM is output error 




enumerator kStatus_PDM_ChannelConfig_Failed

PDM channel config failed 






enum _pdm_interrupt_enable

The PDM interrupt enable flag. 
Values:


enumerator kPDM_ErrorInterruptEnable

PDM channel error interrupt enable. 




enumerator kPDM_FIFOInterruptEnable

PDM channel FIFO interrupt 






enum _pdm_internal_status

The PDM status. 
Values:


enumerator kPDM_StatusDfBusyFlag

Decimation filter is busy processing data 




enumerator kPDM_StatusFrequencyLow

Mic app clock frequency not high enough 




enumerator kPDM_StatusCh0FifoDataAvaliable

channel 0 fifo data reached watermark level 




enumerator kPDM_StatusCh1FifoDataAvaliable

channel 1 fifo data reached watermark level 




enumerator kPDM_StatusCh2FifoDataAvaliable

channel 2 fifo data reached watermark level 




enumerator kPDM_StatusCh3FifoDataAvaliable

channel 3 fifo data reached watermark level 






enum _pdm_channel_enable_mask

PDM channel enable mask. 
Values:


enumerator kPDM_EnableChannel0

channgel 0 enable mask 




enumerator kPDM_EnableChannel1

channgel 1 enable mask 




enumerator kPDM_EnableChannel2

channgel 2 enable mask 




enumerator kPDM_EnableChannel3

channgel 3 enable mask 




enumerator kPDM_EnableChannelAll







enum _pdm_fifo_status

The PDM fifo status. 
Values:


enumerator kPDM_FifoStatusUnderflowCh0

channel0 fifo status underflow 




enumerator kPDM_FifoStatusUnderflowCh1

channel1 fifo status underflow 




enumerator kPDM_FifoStatusUnderflowCh2

channel2 fifo status underflow 




enumerator kPDM_FifoStatusUnderflowCh3

channel3 fifo status underflow 




enumerator kPDM_FifoStatusOverflowCh0

channel0 fifo status overflow 




enumerator kPDM_FifoStatusOverflowCh1

channel1 fifo status overflow 




enumerator kPDM_FifoStatusOverflowCh2

channel2 fifo status overflow 




enumerator kPDM_FifoStatusOverflowCh3

channel3 fifo status overflow 






enum _pdm_range_status

The PDM output status. 
Values:


enumerator kPDM_RangeStatusUnderFlowCh0

channel0 range status underflow 




enumerator kPDM_RangeStatusUnderFlowCh1

channel1 range status underflow 




enumerator kPDM_RangeStatusUnderFlowCh2

channel2 range status underflow 




enumerator kPDM_RangeStatusUnderFlowCh3

channel3 range status underflow 




enumerator kPDM_RangeStatusOverFlowCh0

channel0 range status overflow 




enumerator kPDM_RangeStatusOverFlowCh1

channel1 range status overflow 




enumerator kPDM_RangeStatusOverFlowCh2

channel2 range status overflow 




enumerator kPDM_RangeStatusOverFlowCh3

channel3 range status overflow 






enum _pdm_dc_remover

PDM DC remover configurations. 
Values:


enumerator kPDM_DcRemoverCutOff20Hz

DC remover cut off 20HZ 




enumerator kPDM_DcRemoverCutOff13Hz

DC remover cut off 13.3HZ 




enumerator kPDM_DcRemoverCutOff40Hz

DC remover cut off 40HZ 




enumerator kPDM_DcRemoverBypass

DC remover bypass 






enum _pdm_df_quality_mode

PDM decimation filter quality mode. 
Values:


enumerator kPDM_QualityModeMedium

quality mode memdium 




enumerator kPDM_QualityModeHigh

quality mode high 




enumerator kPDM_QualityModeLow

quality mode low 




enumerator kPDM_QualityModeVeryLow0

quality mode very low0 




enumerator kPDM_QualityModeVeryLow1

quality mode very low1 




enumerator kPDM_QualityModeVeryLow2

quality mode very low2 






enum _pdm_qulaity_mode_k_factor

PDM quality mode K factor. 
Values:


enumerator kPDM_QualityModeHighKFactor

high quality mode K factor = 1 / 2 




enumerator kPDM_QualityModeMediumKFactor

medium/very low0 quality mode K factor = 2 / 2 




enumerator kPDM_QualityModeLowKFactor

low/very low1 quality mode K factor = 4 / 2 




enumerator kPDM_QualityModeVeryLow2KFactor

very low2 quality mode K factor = 8 / 2 






enum _pdm_df_output_gain

PDM decimation filter output gain. 
Values:


enumerator kPDM_DfOutputGain0

Decimation filter output gain 0 




enumerator kPDM_DfOutputGain1

Decimation filter output gain 1 




enumerator kPDM_DfOutputGain2

Decimation filter output gain 2 




enumerator kPDM_DfOutputGain3

Decimation filter output gain 3 




enumerator kPDM_DfOutputGain4

Decimation filter output gain 4 




enumerator kPDM_DfOutputGain5

Decimation filter output gain 5 




enumerator kPDM_DfOutputGain6

Decimation filter output gain 6 




enumerator kPDM_DfOutputGain7

Decimation filter output gain 7 




enumerator kPDM_DfOutputGain8

Decimation filter output gain 8 




enumerator kPDM_DfOutputGain9

Decimation filter output gain 9 




enumerator kPDM_DfOutputGain10

Decimation filter output gain 10 




enumerator kPDM_DfOutputGain11

Decimation filter output gain 11 




enumerator kPDM_DfOutputGain12

Decimation filter output gain 12 




enumerator kPDM_DfOutputGain13

Decimation filter output gain 13 




enumerator kPDM_DfOutputGain14

Decimation filter output gain 14 




enumerator kPDM_DfOutputGain15

Decimation filter output gain 15 






enum _pdm_data_width

PDM data width. 
Values:


enumerator kPDM_DataWwidth24

PDM data width 24bit 




enumerator kPDM_DataWwidth32

PDM data width 32bit 






typedef enum _pdm_dc_remover pdm_dc_remover_t

PDM DC remover configurations. 




typedef enum _pdm_df_quality_mode pdm_df_quality_mode_t

PDM decimation filter quality mode. 




typedef enum _pdm_df_output_gain pdm_df_output_gain_t

PDM decimation filter output gain. 




typedef struct _pdm_channel_config pdm_channel_config_t

PDM channel configurations. 




typedef struct _pdm_config pdm_config_t

PDM user configuration structure. 




typedef struct _pdm_transfer pdm_transfer_t

PDM SDMA transfer structure. 




typedef struct _pdm_handle pdm_handle_t

PDM handle. 




typedef void (*pdm_transfer_callback_t)(PDM_Type *base, pdm_handle_t *handle, status_t status, void *userData)

PDM transfer callback prototype. 




PDM_XFER_QUEUE_SIZE

PDM XFER QUEUE SIZE. 




struct _pdm_channel_config


#include <fsl_pdm.h>
PDM channel configurations. 

Public Members


pdm_dc_remover_t outputCutOffFreq

PDM output DC remover cut off frequency 




pdm_df_output_gain_t gain

Decimation Filter Output Gain 







struct _pdm_config


#include <fsl_pdm.h>
PDM user configuration structure. 

Public Members


bool enableDoze

This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted 




bool enableFilterBypass

Switchable bypass path for the decimation filter 




uint8_t fifoWatermark

Watermark value for FIFO 




pdm_df_quality_mode_t qualityMode

Quality mode 




uint8_t cicOverSampleRate

CIC filter over sampling rate 







struct _pdm_transfer


#include <fsl_pdm.h>
PDM SDMA transfer structure. 

Public Members


volatile uint8_t *data

Data start address to transfer. 




volatile size_t dataSize

Total Transfer bytes size. 







struct _pdm_handle


#include <fsl_pdm.h>
PDM handle structure. 

Public Members


uint32_t state

Transfer status 




pdm_transfer_callback_t callback

Callback function called at transfer event 




void *userData

Callback parameter passed to callback function 




pdm_transfer_t pdmQueue[(4U)]

Transfer queue storing queued transfer 




size_t transferSize[(4U)]

Data bytes need to transfer 




volatile uint8_t queueUser

Index for user to queue transfer 




volatile uint8_t queueDriver

Index for driver to get the transfer data and size 




uint32_t format

data format 




uint8_t watermark

Watermark value 




uint8_t startChannel

end channel 




uint8_t channelNums

Enabled channel number 







PDM EDMA Driver#


void PDM_TransferInstallEDMATCDMemory(pdm_edma_handle_t *handle, void *tcdAddr, size_t tcdNum)

Install EDMA descriptor memory. 

Parameters:

handle – Pointer to EDMA channel transfer handle. 
tcdAddr – EDMA head descriptor address. 
tcdNum – EDMA link descriptor address. 







void PDM_TransferCreateHandleEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)

Initializes the PDM Rx eDMA handle. 
This function initializes the PDM slave DMA handle, which can be used for other PDM master transactional APIs. Usually, for a specified PDM instance, call this API once to get the initialized handle.

Parameters:

base – PDM base pointer. 
handle – PDM eDMA handle pointer. 
callback – Pointer to user callback function. 
userData – User parameter passed to the callback function. 
dmaHandle – eDMA handle pointer, this handle shall be static allocated by users. 







void PDM_TransferSetMultiChannelInterleaveType(pdm_edma_handle_t *handle, pdm_edma_multi_channel_interleave_t multiChannelInterleaveType)

Initializes the multi PDM channel interleave type. 
This function initializes the PDM DMA handle member interleaveType, it shall be called only when application would like to use type kPDM_EDMAMultiChannelInterleavePerChannelBlock, since the default interleaveType is kPDM_EDMAMultiChannelInterleavePerChannelSample always

Parameters:

handle – PDM eDMA handle pointer. 
multiChannelInterleaveType – Multi channel interleave type. 







void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, pdm_edma_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config)

Configures the PDM channel. 

Parameters:

base – PDM base pointer. 
handle – PDM eDMA handle pointer. 
channel – channel index. 
config – pdm channel configurations. 







status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_transfer_t *xfer)

Performs a non-blocking PDM receive using eDMA. 

Mcaro MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL can control whether PDM is enabled internally or externally.

Scatter gather case: This functio support dynamic scatter gather and staic scatter gather, a. for the dynamic scatter gather case: Application should call PDM_TransferReceiveEDMA function continuously to make sure new receive request is submit before the previous one finish. b. for the static scatter gather case: Application should use the link transfer feature and make sure a loop link transfer is provided, such as: 
pdm_edma_transfer_t pdmXfer[2] =
 {
     {
     .data  = s_buffer,
     .dataSize = BUFFER_SIZE,
     .linkTransfer = &pdmXfer[1],
     },

     {
     .data  = &s_buffer[BUFFER_SIZE],
     .dataSize = BUFFER_SIZE,
     .linkTransfer = &pdmXfer[0]
     },
 };



Multi channel case: This function support receive multi pdm channel data, for example, if two channel is requested, 
PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_0, &channelConfig);
PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_1, &channelConfig);
PDM_TransferReceiveEDMA(DEMO_PDM, &s_pdmRxHandle_0, pdmXfer);


 The output data will be formatted as below if handle->interleaveType = 



Note
This interface returns immediately after the transfer initiates. Call the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished.





void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)

Terminate all PDM receive. 
This function will clear all transfer slots buffered in the pdm queue. If users only want to abort the current transfer slot, please call PDM_TransferAbortReceiveEDMA.

Parameters:

base – PDM base pointer. 
handle – PDM eDMA handle pointer. 







void PDM_TransferAbortReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle)

Aborts a PDM receive using eDMA. 
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call PDM_TransferTerminateReceiveEDMA.

Parameters:

base – PDM base pointer 
handle – PDM eDMA handle pointer. 







status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count)

Gets byte count received by PDM. 

Parameters:

base – PDM base pointer 
handle – PDM eDMA handle pointer. 
count – Bytes count received by PDM. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress. 







FSL_PDM_EDMA_DRIVER_VERSION

Version 2.6.5 




enum _pdm_edma_multi_channel_interleave

pdm multi channel interleave type 
Values:


enumerator kPDM_EDMAMultiChannelInterleavePerChannelSample





enumerator kPDM_EDMAMultiChannelInterleavePerChannelBlock







typedef struct _pdm_edma_handle pdm_edma_handle_t

PDM edma handler. 




typedef enum _pdm_edma_multi_channel_interleave pdm_edma_multi_channel_interleave_t

pdm multi channel interleave type 




typedef struct _pdm_edma_transfer pdm_edma_transfer_t

PDM edma transfer. 




typedef void (*pdm_edma_callback_t)(PDM_Type *base, pdm_edma_handle_t *handle, status_t status, void *userData)

PDM eDMA transfer callback function for finish and error. 




MCUX_SDK_PDM_EDMA_PDM_ENABLE_INTERNAL

the PDM enable position When calling PDM_TransferReceiveEDMA 




struct _pdm_edma_transfer


#include <fsl_pdm_edma.h>
PDM edma transfer. 

Public Members


volatile uint8_t *data

Data start address to transfer. 




volatile size_t dataSize

Total Transfer bytes size. 




struct _pdm_edma_transfer *linkTransfer

linked transfer configurations 







struct _pdm_edma_handle


#include <fsl_pdm_edma.h>
PDM DMA transfer handle, users should not touch the content of the handle. 

Public Members


edma_handle_t *dmaHandle

DMA handler for PDM send 




uint8_t count

The transfer data count in a DMA request 




uint32_t receivedBytes

total transfer count 




uint32_t state

Internal state for PDM eDMA transfer 




pdm_edma_callback_t callback

Callback for users while transfer finish or error occurs 




bool isLoopTransfer

loop transfer 




void *userData

User callback parameter 




edma_tcd_t *tcd

TCD pool for eDMA transfer. 




uint32_t tcdNum

TCD number 




uint32_t tcdUser

Index for user to queue transfer. 




uint32_t tcdDriver

Index for driver to get the transfer data and size 




volatile uint32_t tcdUsedNum

Index for user to queue transfer. 




pdm_edma_multi_channel_interleave_t interleaveType

multi channel transfer interleave type 




uint8_t endChannel

The last enabled channel 




uint8_t channelNums

total channel numbers 







RGPIO: Rapid General-Purpose Input/Output Driver#


FSL_RGPIO_DRIVER_VERSION

RGPIO driver version 2.2.0. 




enum _rgpio_pin_direction

RGPIO direction definition. 
Values:


enumerator kRGPIO_DigitalInput

Set current pin as digital input 




enumerator kRGPIO_DigitalOutput

Set current pin as digital output 






enum _rgpio_checker_attribute

RGPIO checker attribute. 
Values:


enumerator kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW

User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW

User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW

User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW

User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW

User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW

User nonsecure:None; User Secure:None; Privileged Secure:Read+Write 




enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR

User nonsecure:None; User Secure:None; Privileged Secure:Read 




enumerator kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN

User nonsecure:None; User Secure:None; Privileged Secure:None 




enumerator kRGPIO_IgnoreAttributeCheck

Ignores the attribute check 






enum _rgpio_interrupt_sel

Configures the interrupt generation condition. 
Values:


enumerator kRGPIO_InterruptOutput0

Interrupt/DMA request/trigger output 0. 




enumerator kRGPIO_InterruptOutput1

Interrupt/DMA request/trigger output 1. 




enumerator kRGPIO_InterruptOutput2

Interrupt/DMA request/trigger output 2. 




enumerator kRGPIO_InterruptOutput3

Interrupt/DMA request/trigger output 3. 






enum _rgpio_interrupt_config

Configures the interrupt generation condition. 
Values:


enumerator kRGPIO_InterruptOrDMADisabled

Interrupt/DMA request is disabled. 




enumerator kRGPIO_DMARisingEdge

DMA request on rising edge. 




enumerator kRGPIO_DMAFallingEdge

DMA request on falling edge. 




enumerator kRGPIO_DMAEitherEdge

DMA request on either edge. 




enumerator kRGPIO_FlagRisingEdge

Flag sets on rising edge. 




enumerator kRGPIO_FlagFallingEdge

Flag sets on falling edge. 




enumerator kRGPIO_FlagEitherEdge

Flag sets on either edge. 




enumerator kRGPIO_InterruptLogicZero

Interrupt when logic zero. 




enumerator kRGPIO_InterruptRisingEdge

Interrupt on rising edge. 




enumerator kRGPIO_InterruptFallingEdge

Interrupt on falling edge. 




enumerator kRGPIO_InterruptEitherEdge

Interrupt on either edge. 




enumerator kRGPIO_InterruptLogicOne

Interrupt when logic one. 




enumerator kRGPIO_ActiveHighTriggerOutputEnable

Enable active high-trigger output. 




enumerator kRGPIO_ActiveLowTriggerOutputEnable

Enable active low-trigger output. 






typedef enum _rgpio_pin_direction rgpio_pin_direction_t

RGPIO direction definition. 




typedef enum _rgpio_checker_attribute rgpio_checker_attribute_t

RGPIO checker attribute. 




typedef enum _rgpio_interrupt_sel rgpio_interrupt_sel_t

Configures the interrupt generation condition. 




typedef enum _rgpio_interrupt_config rgpio_interrupt_config_t

Configures the interrupt generation condition. 




typedef struct _rgpio_pin_config rgpio_pin_config_t

The RGPIO pin configuration structure. 
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig(). 




struct _rgpio_pin_config


#include <fsl_rgpio.h>
The RGPIO pin configuration structure. 
Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig(). 

Public Members


rgpio_pin_direction_t pinDirection

RGPIO direction, input or output 




uint8_t outputLogic

Set a default output logic, which has no use in input 







RGPIO Driver#


void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config)

Initializes a RGPIO pin used by the board. 
To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. Then, call the RGPIO_PinInit() function.
This is an example to define an input pin or an output pin configuration. 
 Define a digital input pin configuration,
rgpio_pin_config_t config =
{
  kRGPIO_DigitalInput,
  0,
}
Define a digital output pin configuration,
rgpio_pin_config_t config =
{
  kRGPIO_DigitalOutput,
  0,
}




Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO port pin number 
config – RGPIO pin configuration pointer 







uint32_t RGPIO_GetInstance(RGPIO_Type *base)

Gets the RGPIO instance according to the RGPIO base. 

Parameters:

base – RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) 


Return values:
RGPIO – instance 






static inline rgpio_pin_direction_t RGPIO_GetPinDirection(RGPIO_Type *base, uint32_t pin)

Gets the current direction of a RGPIO pin. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO port pin number 


Return values:
RGPIO – pin direction

kRGPIO_DigitalInput: pin is configured as digital input.
kRGPIO_DigitalOutput: pin is configured as digital output. 








static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the multiple RGPIO pins to the logic 1 or 0. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO pin number 
output – RGPIO pin output logic level.

0: corresponding pin output low-logic level.
1: corresponding pin output high-logic level. 









static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the multiple RGPIO pins to the logic 1 or 0. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PinWrite. 







static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 1. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 1. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PortSet. 







static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 0. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask)

Sets the output level of the multiple RGPIO pins to the logic 0. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PortClear.




Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple RGPIO pins. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple RGPIO pins. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PortToggle. 







static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin)

Reads the current input value of the RGPIO port. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
pin – RGPIO pin number 


Return values:
RGPIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level. 








static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin)

Reads the current input value of the RGPIO port. 


Deprecated:
Do not use this function. It has been superceded by RGPIO_PinRead. 







static inline void RGPIO_EnablePortInput(RGPIO_Type *base, uint32_t mask, bool enable)


Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number mask 
enable – RGPIO digital input enable/disable flag. 







void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute)

The RGPIO module supports a device-specific number of data ports, organized as 32-bit words. Each 32-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro 







static inline void RGPIO_SetPinInterruptConfig(RGPIO_Type *base, uint32_t pin, rgpio_interrupt_sel_t sel, rgpio_interrupt_config_t config)

Configures the gpio pin interrupt/DMA request. 

Parameters:

base – RGPIO peripheral base pointer. 
pin – RGPIO pin number. 
sel – RGPIO pin interrupt selection(0-3). 
config – RGPIO pin interrupt configuration. 







static inline void _SetMultipleInterruptPinsConfig(RGPIO_Type *base, uint32_t mask, rgpio_interrupt_sel_t sel, rgpio_interrupt_config_t config)

Sets the gpio interrupt configuration in ICR register for multiple pins. 

Parameters:

base – RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) 
mask – RGPIO pin number macro. 
sel – RGPIO pin interrupt selection(0-3). 
config – RGPIO pin interrupt configuration. 







static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel)

Reads the whole gpio status flag. 
If a pin is configured to generate the DMA request, the corresponding flag is cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted, the flag is set again immediately.

Parameters:

base – RGPIO peripheral base pointer. 
sel – RGPIO pin interrupt selection(0-3). 


Returns:
Current gpio interrupt status flags, for example, 0x00010001 means the pin 0 and 16 have the interrupt. 






static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, rgpio_interrupt_sel_t sel, uint32_t mask)

Clears the multiple pin interrupt status flag. 

Parameters:

base – RGPIO peripheral base pointer. 
sel – RGPIO pin interrupt selection(0-3). 
mask – RGPIO pin number macro. 







SAI: Serial Audio Interface#


SAI Driver#


void SAI_Init(I2S_Type *base)

Initializes the SAI peripheral. 
This API gates the SAI clock. The SAI module can’t operate unless SAI_Init is called to enable the clock.

Parameters:

base – SAI base pointer. 







void SAI_Deinit(I2S_Type *base)

De-initializes the SAI peripheral. 
This API gates the SAI clock. The SAI module can’t operate unless SAI_TxInit or SAI_RxInit is called to enable the clock.

Parameters:

base – SAI base pointer. 







void SAI_TxReset(I2S_Type *base)

Resets the SAI Tx. 
This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.

Parameters:

base – SAI base pointer 







void SAI_RxReset(I2S_Type *base)

Resets the SAI Rx. 
This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.

Parameters:

base – SAI base pointer 







void SAI_TxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Tx. 

Parameters:

base – SAI base pointer. 
enable – True means enable SAI Tx, false means disable. 







void SAI_RxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Rx. 

Parameters:

base – SAI base pointer. 
enable – True means enable SAI Rx, false means disable. 







static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction. 
Select bit clock direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction. 
Select bit clock direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx frame sync direction. 
Select frame sync direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Tx frame sync direction. 
Select frame sync direction, master or slave.

Parameters:

base – SAI base pointer. 
masterSlave – reference sai_master_slave_t. 







void SAI_TxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Transmitter bit clock rate configurations. 

Parameters:

base – SAI base pointer. 
sourceClockHz – Bit clock source frequency. 
sampleRate – Audio data sample rate. 
bitWidth – Audio data bitWidth. 
channelNumbers – Audio channel numbers. 







void SAI_RxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Receiver bit clock rate configurations. 

Parameters:

base – SAI base pointer. 
sourceClockHz – Bit clock source frequency. 
sampleRate – Audio data sample rate. 
bitWidth – Audio data bitWidth. 
channelNumbers – Audio channel numbers. 







void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Transmitter Bit clock configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – bit clock other configurations, can be NULL in slave mode. 







void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Receiver Bit clock configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – bit clock other configurations, can be NULL in slave mode. 







void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)

Master clock configurations. 

Parameters:

base – SAI base pointer. 
config – master clock configurations. 







void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI transmitter fifo configurations. 

Parameters:

base – SAI base pointer. 
config – fifo configurations. 







void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI receiver fifo configurations. 

Parameters:

base – SAI base pointer. 
config – fifo configurations. 







void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI transmitter Frame sync configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – frame sync configurations, can be NULL in slave mode. 







void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI receiver Frame sync configurations. 

Parameters:

base – SAI base pointer. 
masterSlave – master or slave. 
config – frame sync configurations, can be NULL in slave mode. 







void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI transmitter Serial data configurations. 

Parameters:

base – SAI base pointer. 
config – serial data configurations. 







void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI receiver Serial data configurations. 

Parameters:

base – SAI base pointer. 
config – serial data configurations. 







void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI transmitter configurations. 

Parameters:

base – SAI base pointer. 
config – transmitter configurations. 







void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI receiver configurations. 

Parameters:

base – SAI base pointer. 
config – receiver configurations. 







void SAI_GetClassicI2SConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get classic I2S mode configurations. 

Parameters:

config – transceiver configurations. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get left justified mode configurations. 

Parameters:

config – transceiver configurations. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get right justified mode configurations. 

Parameters:

config – transceiver configurations. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetTDMConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, uint32_t dataWordNum, uint32_t saiChannelMask)

Get TDM mode configurations. 

Parameters:

config – transceiver configurations. 
frameSyncWidth – length of frame sync. 
bitWidth – audio data word width. 
dataWordNum – word number in one frame. 
saiChannelMask – mask value of the channel to be enable. 







void SAI_GetDSPConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get DSP mode configurations. 

DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: 
SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
SAI_TxSetConfig(base, config)




Note
DSP mode is also called PCM mode which support MODE A and MODE B, DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: 
SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
config->frameSync.frameSyncEarly    = true;
SAI_TxSetConfig(base, config)





Parameters:

config – transceiver configurations. 
frameSyncWidth – length of frame sync. 
bitWidth – audio data bitWidth. 
mode – audio data channel. 
saiChannelMask – mask value of the channel to enable. 







static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state. 

Parameters:

base – SAI base pointer 


Returns:
SAI Tx status flag value. Use the Status Mask to get the status value needed. 






static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Tx status flag state. 

Parameters:

base – SAI base pointer 
mask – State mask. It can be a combination of the following source if defined: 

kSAI_WordStartFlag 
kSAI_SyncErrorFlag 
kSAI_FIFOErrorFlag 









static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state. 

Parameters:

base – SAI base pointer 


Returns:
SAI Rx status flag value. Use the Status Mask to get the status value needed. 






static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Rx status flag state. 

Parameters:

base – SAI base pointer 
mask – State mask. It can be a combination of the following sources if defined. 

kSAI_WordStartFlag 
kSAI_SyncErrorFlag 
kSAI_FIFOErrorFlag 









void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset . 
FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like TCR1~TCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

base – SAI base pointer 
resetType – Reset type, FIFO reset or software reset 







void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset . 
FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like RCR1~RCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

base – SAI base pointer 
resetType – Reset type, FIFO reset or software reset 







void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Tx channel FIFO enable mask. 

Parameters:

base – SAI base pointer 
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled. 







void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Rx channel FIFO enable mask. 

Parameters:

base – SAI base pointer 
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled. 







void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Tx data order. 

Parameters:

base – SAI base pointer 
order – Data order MSB or LSB 







void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Rx data order. 

Parameters:

base – SAI base pointer 
order – Data order MSB or LSB 







void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order. 

Parameters:

base – SAI base pointer 
polarity – 







void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Tx FIFO packing feature. 

Parameters:

base – SAI base pointer. 
pack – FIFO pack type. It is element of sai_fifo_packing_t. 







void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Rx FIFO packing feature. 

Parameters:

base – SAI base pointer. 
pack – FIFO pack type. It is element of sai_fifo_packing_t. 







static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Tx FIFO error continue. 
FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in TCSR register.

Parameters:

base – SAI base pointer. 
isEnabled – Is FIFO error continue enabled, true means enable, false means disable. 







static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Rx FIFO error continue. 
FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in RCSR register.

Parameters:

base – SAI base pointer. 
isEnabled – Is FIFO error continue enabled, true means enable, false means disable. 







static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Tx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Rx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Tx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Rx interrupt requests. 

Parameters:

base – SAI base pointer 
mask – interrupt source The parameter can be a combination of the following sources if defined. 

kSAI_WordStartInterruptEnable 
kSAI_SyncErrorInterruptEnable 
kSAI_FIFOWarningInterruptEnable 
kSAI_FIFORequestInterruptEnable 
kSAI_FIFOErrorInterruptEnable 









static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Tx DMA requests. 

Parameters:

base – SAI base pointer 
mask – DMA source The parameter can be combination of the following sources if defined. 

kSAI_FIFOWarningDMAEnable 
kSAI_FIFORequestDMAEnable 


enable – True means enable DMA, false means disable DMA. 







static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Rx DMA requests. 

Parameters:

base – SAI base pointer 
mask – DMA source The parameter can be a combination of the following sources if defined. 

kSAI_FIFOWarningDMAEnable 
kSAI_FIFORequestDMAEnable 


enable – True means enable DMA, false means disable DMA. 







static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Tx data register address. 
This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

base – SAI base pointer. 
channel – Which data channel used. 


Returns:
data register address. 






static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Rx data register address. 
This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

base – SAI base pointer. 
channel – Which data channel used. 


Returns:
data register address. 






void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be written. 
size – Bytes to be written. 







void SAI_WriteMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data to multi channel using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
channelMask – channel mask. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be written. 
size – Bytes to be written. 







static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)

Writes data into SAI FIFO. 

Parameters:

base – SAI base pointer. 
channel – Data channel used. 
data – Data needs to be written. 







void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives data using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be read. 
size – Bytes to be read. 







void SAI_ReadMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives multi channel data using a blocking method. 

Note
This function blocks by polling until data is ready to be sent.


Parameters:

base – SAI base pointer. 
channel – Data channel used. 
channelMask – channel mask. 
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits. 
buffer – Pointer to the data to be read. 
size – Bytes to be read. 







static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)

Reads data from the SAI FIFO. 

Parameters:

base – SAI base pointer. 
channel – Data channel used. 


Returns:
Data in SAI FIFO. 






void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Tx handle. 
This function initializes the Tx handle for the SAI Tx transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – SAI base pointer 
handle – SAI handle pointer. 
callback – Pointer to the user callback function. 
userData – User parameter passed to the callback function 







void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Rx handle. 
This function initializes the Rx handle for the SAI Rx transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – SAI base pointer. 
handle – SAI handle pointer. 
callback – Pointer to the user callback function. 
userData – User parameter passed to the callback function. 







void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI transmitter transfer configurations. 
This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

base – SAI base pointer. 
handle – SAI handle pointer. 
config – tranmitter configurations. 







void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI receiver transfer configurations. 
This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

base – SAI base pointer. 
handle – SAI handle pointer. 
config – receiver configurations. 







status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on SAI. 

Note
This API returns immediately after the transfer initiates. Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.


Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
xfer – Pointer to the sai_transfer_t structure. 


Return values:

kStatus_Success – Successfully started the data receive. 
kStatus_SAI_TxBusy – Previous receive still not finished. 
kStatus_InvalidArgument – The input parameter is invalid. 







status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on SAI. 

Note
This API returns immediately after the transfer initiates. Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.


Parameters:

base – SAI base pointer 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
xfer – Pointer to the sai_transfer_t structure. 


Return values:

kStatus_Success – Successfully started the data receive. 
kStatus_SAI_RxBusy – Previous receive still not finished. 
kStatus_InvalidArgument – The input parameter is invalid. 







status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a set byte count. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
count – Bytes count sent. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a received byte count. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 
count – Bytes count received. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)

Aborts the current send. 

Note
This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 







void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)

Aborts the current IRQ receive. 

Note
This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.


Parameters:

base – SAI base pointer 
handle – Pointer to the sai_handle_t structure which stores the transfer state. 







void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI send. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSend.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI receive. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceive.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure. 







void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler. 

Parameters:

base – SAI base pointer. 
handle – Pointer to the sai_handle_t structure. 







void SAI_DriverIRQHandler(uint32_t instance)

SAI driver IRQ handler common entry. 
This function provides the common IRQ request entry for SAI.

Parameters:

instance – SAI instance. 







FSL_SAI_DRIVER_VERSION

Version 2.4.11 





_sai_status_t, SAI return status. 
Values:


enumerator kStatus_SAI_TxBusy

SAI Tx is busy. 




enumerator kStatus_SAI_RxBusy

SAI Rx is busy. 




enumerator kStatus_SAI_TxError

SAI Tx FIFO error. 




enumerator kStatus_SAI_RxError

SAI Rx FIFO error. 




enumerator kStatus_SAI_QueueFull

SAI transfer queue is full. 




enumerator kStatus_SAI_TxIdle

SAI Tx is idle 




enumerator kStatus_SAI_RxIdle

SAI Rx is idle 







_sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific 
Values:


enumerator kSAI_Channel0Mask

channel 0 mask value 




enumerator kSAI_Channel1Mask

channel 1 mask value 




enumerator kSAI_Channel2Mask

channel 2 mask value 




enumerator kSAI_Channel3Mask

channel 3 mask value 




enumerator kSAI_Channel4Mask

channel 4 mask value 




enumerator kSAI_Channel5Mask

channel 5 mask value 




enumerator kSAI_Channel6Mask

channel 6 mask value 




enumerator kSAI_Channel7Mask

channel 7 mask value 






enum _sai_protocol

Define the SAI bus type. 
Values:


enumerator kSAI_BusLeftJustified

Uses left justified format. 




enumerator kSAI_BusRightJustified

Uses right justified format. 




enumerator kSAI_BusI2S

Uses I2S format. 




enumerator kSAI_BusPCMA

Uses I2S PCM A format. 




enumerator kSAI_BusPCMB

Uses I2S PCM B format. 






enum _sai_master_slave

Master or slave mode. 
Values:


enumerator kSAI_Master

Master mode include bclk and frame sync 




enumerator kSAI_Slave

Slave mode include bclk and frame sync 




enumerator kSAI_Bclk_Master_FrameSync_Slave

bclk in master mode, frame sync in slave mode 




enumerator kSAI_Bclk_Slave_FrameSync_Master

bclk in slave mode, frame sync in master mode 






enum _sai_mono_stereo

Mono or stereo audio format. 
Values:


enumerator kSAI_Stereo

Stereo sound. 




enumerator kSAI_MonoRight

Only Right channel have sound. 




enumerator kSAI_MonoLeft

Only left channel have sound. 






enum _sai_data_order

SAI data order, MSB or LSB. 
Values:


enumerator kSAI_DataLSB

LSB bit transferred first 




enumerator kSAI_DataMSB

MSB bit transferred first 






enum _sai_clock_polarity

SAI clock polarity, active high or low. 
Values:


enumerator kSAI_PolarityActiveHigh

Drive outputs on rising edge 




enumerator kSAI_PolarityActiveLow

Drive outputs on falling edge 




enumerator kSAI_SampleOnFallingEdge

Sample inputs on falling edge 




enumerator kSAI_SampleOnRisingEdge

Sample inputs on rising edge 






enum _sai_sync_mode

Synchronous or asynchronous mode. 
Values:


enumerator kSAI_ModeAsync

Asynchronous mode 




enumerator kSAI_ModeSync

Synchronous mode (with receiver or transmit) 




enumerator kSAI_ModeSyncWithOtherTx

Synchronous with another SAI transmit 




enumerator kSAI_ModeSyncWithOtherRx

Synchronous with another SAI receiver 






enum _sai_bclk_source

Bit clock source. 
Values:


enumerator kSAI_BclkSourceBusclk

Bit clock using bus clock 




enumerator kSAI_BclkSourceMclkOption1

Bit clock MCLK option 1 




enumerator kSAI_BclkSourceMclkOption2

Bit clock MCLK option2 




enumerator kSAI_BclkSourceMclkOption3

Bit clock MCLK option3 




enumerator kSAI_BclkSourceMclkDiv

Bit clock using master clock divider 




enumerator kSAI_BclkSourceOtherSai0

Bit clock from other SAI device 




enumerator kSAI_BclkSourceOtherSai1

Bit clock from other SAI device 







_sai_interrupt_enable_t, The SAI interrupt enable flag 
Values:


enumerator kSAI_WordStartInterruptEnable

Word start flag, means the first word in a frame detected 




enumerator kSAI_SyncErrorInterruptEnable

Sync error flag, means the sync error is detected 




enumerator kSAI_FIFOWarningInterruptEnable

FIFO warning flag, means the FIFO is empty 




enumerator kSAI_FIFOErrorInterruptEnable

FIFO error flag 




enumerator kSAI_FIFORequestInterruptEnable

FIFO request, means reached watermark 







_sai_dma_enable_t, The DMA request sources 
Values:


enumerator kSAI_FIFOWarningDMAEnable

FIFO warning caused by the DMA request 




enumerator kSAI_FIFORequestDMAEnable

FIFO request caused by the DMA request 







_sai_flags, The SAI status flag 
Values:


enumerator kSAI_WordStartFlag

Word start flag, means the first word in a frame detected 




enumerator kSAI_SyncErrorFlag

Sync error flag, means the sync error is detected 




enumerator kSAI_FIFOErrorFlag

FIFO error flag 




enumerator kSAI_FIFORequestFlag

FIFO request flag. 




enumerator kSAI_FIFOWarningFlag

FIFO warning flag 






enum _sai_reset_type

The reset type. 
Values:


enumerator kSAI_ResetTypeSoftware

Software reset, reset the logic state 




enumerator kSAI_ResetTypeFIFO

FIFO reset, reset the FIFO read and write pointer 




enumerator kSAI_ResetAll

All reset. 






enum _sai_fifo_packing

The SAI packing mode The mode includes 8 bit and 16 bit packing. 
Values:


enumerator kSAI_FifoPackingDisabled

Packing disabled 




enumerator kSAI_FifoPacking8bit

8 bit packing enabled 




enumerator kSAI_FifoPacking16bit

16bit packing enabled 






enum _sai_sample_rate

Audio sample rate. 
Values:


enumerator kSAI_SampleRate8KHz

Sample rate 8000 Hz 




enumerator kSAI_SampleRate11025Hz

Sample rate 11025 Hz 




enumerator kSAI_SampleRate12KHz

Sample rate 12000 Hz 




enumerator kSAI_SampleRate16KHz

Sample rate 16000 Hz 




enumerator kSAI_SampleRate22050Hz

Sample rate 22050 Hz 




enumerator kSAI_SampleRate24KHz

Sample rate 24000 Hz 




enumerator kSAI_SampleRate32KHz

Sample rate 32000 Hz 




enumerator kSAI_SampleRate44100Hz

Sample rate 44100 Hz 




enumerator kSAI_SampleRate48KHz

Sample rate 48000 Hz 




enumerator kSAI_SampleRate96KHz

Sample rate 96000 Hz 




enumerator kSAI_SampleRate192KHz

Sample rate 192000 Hz 




enumerator kSAI_SampleRate384KHz

Sample rate 384000 Hz 






enum _sai_word_width

Audio word width. 
Values:


enumerator kSAI_WordWidth8bits

Audio data width 8 bits 




enumerator kSAI_WordWidth16bits

Audio data width 16 bits 




enumerator kSAI_WordWidth24bits

Audio data width 24 bits 




enumerator kSAI_WordWidth32bits

Audio data width 32 bits 






enum _sai_data_pin_state

sai data pin state definition 
Values:


enumerator kSAI_DataPinStateTriState

transmit data pins are tri-stated when slots are masked or channels are disabled 




enumerator kSAI_DataPinStateOutputZero

transmit data pins are never tri-stated and will output zero when slots are masked or channel disabled 






enum _sai_fifo_combine

sai fifo combine mode definition 
Values:


enumerator kSAI_FifoCombineDisabled

sai TX/RX fifo combine mode disabled 




enumerator kSAI_FifoCombineModeEnabledOnRead

sai TX fifo combine mode enabled on FIFO reads 




enumerator kSAI_FifoCombineModeEnabledOnWrite

sai TX fifo combine mode enabled on FIFO write 




enumerator kSAI_RxFifoCombineModeEnabledOnWrite

sai RX fifo combine mode enabled on FIFO write 




enumerator kSAI_RXFifoCombineModeEnabledOnRead

sai RX fifo combine mode enabled on FIFO reads 




enumerator kSAI_FifoCombineModeEnabledOnReadWrite

sai TX/RX fifo combined mode enabled on FIFO read/writes 






enum _sai_transceiver_type

sai transceiver type 
Values:


enumerator kSAI_Transmitter

sai transmitter 




enumerator kSAI_Receiver

sai receiver 






enum _sai_frame_sync_len

sai frame sync len 
Values:


enumerator kSAI_FrameSyncLenOneBitClk

1 bit clock frame sync len for DSP mode 




enumerator kSAI_FrameSyncLenPerWordWidth

Frame sync length decided by word width 






typedef enum _sai_protocol sai_protocol_t

Define the SAI bus type. 




typedef enum _sai_master_slave sai_master_slave_t

Master or slave mode. 




typedef enum _sai_mono_stereo sai_mono_stereo_t

Mono or stereo audio format. 




typedef enum _sai_data_order sai_data_order_t

SAI data order, MSB or LSB. 




typedef enum _sai_clock_polarity sai_clock_polarity_t

SAI clock polarity, active high or low. 




typedef enum _sai_sync_mode sai_sync_mode_t

Synchronous or asynchronous mode. 




typedef enum _sai_bclk_source sai_bclk_source_t

Bit clock source. 




typedef enum _sai_reset_type sai_reset_type_t

The reset type. 




typedef enum _sai_fifo_packing sai_fifo_packing_t

The SAI packing mode The mode includes 8 bit and 16 bit packing. 




typedef struct _sai_config sai_config_t

SAI user configuration structure. 




typedef enum _sai_sample_rate sai_sample_rate_t

Audio sample rate. 




typedef enum _sai_word_width sai_word_width_t

Audio word width. 




typedef enum _sai_data_pin_state sai_data_pin_state_t

sai data pin state definition 




typedef enum _sai_fifo_combine sai_fifo_combine_t

sai fifo combine mode definition 




typedef enum _sai_transceiver_type sai_transceiver_type_t

sai transceiver type 




typedef enum _sai_frame_sync_len sai_frame_sync_len_t

sai frame sync len 




typedef struct _sai_transfer_format sai_transfer_format_t

sai transfer format 




typedef struct _sai_master_clock sai_master_clock_t

master clock configurations 




typedef struct _sai_fifo sai_fifo_t

sai fifo configurations 




typedef struct _sai_bit_clock sai_bit_clock_t

sai bit clock configurations 




typedef struct _sai_frame_sync sai_frame_sync_t

sai frame sync configurations 




typedef struct _sai_serial_data sai_serial_data_t

sai serial data configurations 




typedef struct _sai_transceiver sai_transceiver_t

sai transceiver configurations 




typedef struct _sai_transfer sai_transfer_t

SAI transfer structure. 




typedef struct _sai_handle sai_handle_t





typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData)

SAI transfer callback prototype. 




MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK

Used to control whether SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() allows a NULL FIFO watermark. 
If this macro is set to 0 then SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() will set the watermark to half of the FIFO’s depth if passed a NULL watermark. 




MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG

Disable implicit channel data configuration within SAI_TxSetConfig()/SAI_RxSetConfig(). 
Use this macro to control whether SAI_RxSetConfig()/SAI_TxSetConfig() will attempt to implicitly configure the channel data. By channel data we mean the startChannel, channelMask, endChannel, and channelNums fields from the sai_transciever_t structure. By default, SAI_TxSetConfig()/SAI_RxSetConfig() will attempt to compute these fields, which may not be desired in cases where the user wants to set them before the call to said functions. 




SAI_XFER_QUEUE_SIZE

SAI transfer queue size, user can refine it according to use case. 




FSL_SAI_HAS_FIFO_EXTEND_FEATURE

sai fifo feature 




struct _sai_config


#include <fsl_sai.h>
SAI user configuration structure. 

Public Members


sai_protocol_t protocol

Audio bus protocol in SAI 




sai_sync_mode_t syncMode

SAI sync mode, control Tx/Rx clock sync 




bool mclkOutputEnable

Master clock output enable, true means master clock divider enabled 




sai_bclk_source_t bclkSource

Bit Clock source 




sai_master_slave_t masterSlave

Master or slave 







struct _sai_transfer_format


#include <fsl_sai.h>
sai transfer format 

Public Members


uint32_t sampleRate_Hz

Sample rate of audio data 




uint32_t bitWidth

Data length of audio data, usually 8/16/24/32 bits 




sai_mono_stereo_t stereo

Mono or stereo 




uint32_t masterClockHz

Master clock frequency in Hz 




uint8_t watermark

Watermark value 




uint8_t channel

Transfer start channel 




uint8_t channelMask

enabled channel mask value, reference _sai_channel_mask 




uint8_t endChannel

end channel number 




uint8_t channelNums

Total enabled channel numbers 




sai_protocol_t protocol

Which audio protocol used 




bool isFrameSyncCompact

True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock. 







struct _sai_master_clock


#include <fsl_sai.h>
master clock configurations 

Public Members


bool mclkOutputEnable

master clock output enable 




uint32_t mclkHz

target mclk frequency 




uint32_t mclkSourceClkHz

mclk source frequency 







struct _sai_fifo


#include <fsl_sai.h>
sai fifo configurations 

Public Members


bool fifoContinueOneError

fifo continues when error occur 




sai_fifo_combine_t fifoCombine

fifo combine mode 




sai_fifo_packing_t fifoPacking

fifo packing mode 




uint8_t fifoWatermark

fifo watermark 







struct _sai_bit_clock


#include <fsl_sai.h>
sai bit clock configurations 

Public Members


bool bclkSrcSwap

bit clock source swap 




bool bclkInputDelay

bit clock actually used by the transmitter is delayed by the pad output delay, this has effect of decreasing the data input setup time, but increasing the data output valid time . 




sai_clock_polarity_t bclkPolarity

bit clock polarity 




sai_bclk_source_t bclkSource

bit Clock source 







struct _sai_frame_sync


#include <fsl_sai.h>
sai frame sync configurations 

Public Members


uint8_t frameSyncWidth

frame sync width in number of bit clocks 




bool frameSyncEarly

TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame 




bool frameSyncGenerateOnDemand

internal frame sync is generated when FIFO waring flag is clear 




sai_clock_polarity_t frameSyncPolarity

frame sync polarity 







struct _sai_serial_data


#include <fsl_sai.h>
sai serial data configurations 

Public Members


sai_data_pin_state_t dataMode

sai data pin state when slots masked or channel disabled 




sai_data_order_t dataOrder

configure whether the LSB or MSB is transmitted first 




uint8_t dataWord0Length

configure the number of bits in the first word in each frame 




uint8_t dataWordNLength

configure the number of bits in the each word in each frame, except the first word 




uint8_t dataWordLength

used to record the data length for dma transfer 




uint8_t dataFirstBitShifted

Configure the bit index for the first bit transmitted for each word in the frame 




uint8_t dataWordNum

configure the number of words in each frame 




uint32_t dataMaskedWord

configure whether the transmit word is masked 







struct _sai_transceiver


#include <fsl_sai.h>
sai transceiver configurations 

Public Members


sai_serial_data_t serialData

serial data configurations 




sai_frame_sync_t frameSync

ws configurations 




sai_bit_clock_t bitClock

bit clock configurations 




sai_fifo_t fifo

fifo configurations 




sai_master_slave_t masterSlave

transceiver is master or slave 




sai_sync_mode_t syncMode

transceiver sync mode 




uint8_t startChannel

Transfer start channel 




uint8_t channelMask

enabled channel mask value, reference _sai_channel_mask 




uint8_t endChannel

end channel number 




uint8_t channelNums

Total enabled channel numbers 







struct _sai_transfer


#include <fsl_sai.h>
SAI transfer structure. 

Public Members


uint8_t *data

Data start address to transfer. 




size_t dataSize

Transfer size. 







struct _sai_handle


#include <fsl_sai.h>
SAI handle structure. 

Public Members


I2S_Type *base

base address 




uint32_t state

Transfer status 




sai_transfer_callback_t callback

Callback function called at transfer event 




void *userData

Callback parameter passed to callback function 




uint8_t bitWidth

Bit width for transfer, 8/16/24/32 bits 




uint8_t channel

Transfer start channel 




uint8_t channelMask

enabled channel mask value, refernece _sai_channel_mask 




uint8_t endChannel

end channel number 




uint8_t channelNums

Total enabled channel numbers 




sai_transfer_t saiQueue[(4U)]

Transfer queue storing queued transfer 




size_t transferSize[(4U)]

Data bytes need to transfer 




volatile uint8_t queueUser

Index for user to queue transfer 




volatile uint8_t queueDriver

Index for driver to get the transfer data and size 




uint8_t watermark

Watermark value 







SAI EDMA Driver#


void SAI_TransferTxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle)

Initializes the SAI eDMA handle. 
This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
callback – Pointer to user callback function. 
userData – User parameter passed to the callback function. 
txDmaHandle – eDMA handle pointer, this handle shall be static allocated by users. 







void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle)

Initializes the SAI Rx eDMA handle. 
This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. Usually, for a specified SAI instance, call this API once to get the initialized handle.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
callback – Pointer to user callback function. 
userData – User parameter passed to the callback function. 
rxDmaHandle – eDMA handle pointer, this handle shall be static allocated by users. 







void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType)

Initializes the SAI interleave type. 
This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is kSAI_EDMAInterleavePerChannelSample always

Parameters:

handle – SAI eDMA handle pointer. 
interleaveType – Multi channel interleave type. 







void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)

Configures the SAI Tx. 

Note
SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnWrite to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step. 
sai_transceiver_t config;
SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnWrite;
SAI_TransferTxSetConfigEDMA(I2S0, &edmaHandle, &config);





Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
saiConfig – sai configurations. 







void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig)

Configures the SAI Rx. 

Note
SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. To activate the multi-channel transfer enable SAI channels by filling the channelMask of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine mode by assigning kSAI_FifoCombineModeEnabledOnRead to the fifoCombine member of sai_fifo_combine_t which is a member of sai_transceiver_t. This is an example of multi-channel data transfer configuration step. 
sai_transceiver_t config;
SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask);
config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead;
SAI_TransferRxSetConfigEDMA(I2S0, &edmaHandle, &config);





Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
saiConfig – sai configurations. 







status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)

Performs a non-blocking SAI transfer using DMA. 

This function support multi channel transfer,

for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers
for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.



Note
This interface returns immediately after the transfer initiates. Call SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished.


Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
xfer – Pointer to the DMA transfer structure. 


Return values:

kStatus_Success – Start a SAI eDMA send successfully. 
kStatus_InvalidArgument – The input argument is invalid. 
kStatus_TxBusy – SAI is busy sending data. 







status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)

Performs a non-blocking SAI receive using eDMA. 

This function support multi channel transfer,

for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation on channel numbers
for the sai IP not support fifo combine mode, sai edma provide another solution which using EDMA modulo feature, but support 2 or 4 channels only.



Note
This interface returns immediately after the transfer initiates. Call the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished.


Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 
xfer – Pointer to DMA transfer structure. 


Return values:

kStatus_Success – Start a SAI eDMA receive successfully. 
kStatus_InvalidArgument – The input argument is invalid. 
kStatus_RxBusy – SAI is busy receiving data. 







status_t SAI_TransferSendLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)

Performs a non-blocking SAI loop transfer using eDMA. 

Once the loop transfer start, application can use function SAI_TransferAbortSendEDMA to stop the loop transfer.

Note
This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.


Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). 
loopTransferCount – the counts of xfer array. 


Return values:

kStatus_Success – Start a SAI eDMA send successfully. 
kStatus_InvalidArgument – The input argument is invalid. 







status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount)

Performs a non-blocking SAI loop transfer using eDMA. 

Once the loop transfer start, application can use function SAI_TransferAbortReceiveEDMA to stop the loop transfer.

Note
This function support loop transfer only,such as A->B->…->A, application must be aware of that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. This function support one sai channel only.


Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
xfer – Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). 
loopTransferCount – the counts of xfer array. 


Return values:

kStatus_Success – Start a SAI eDMA receive successfully. 
kStatus_InvalidArgument – The input argument is invalid. 







void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Terminate all SAI send. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSendEDMA.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Terminate all SAI receive. 
This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceiveEDMA.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Aborts a SAI transfer using eDMA. 
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA.

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 







void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Aborts a SAI receive using eDMA. 
This function only aborts the current transfer slots, the other transfer slots’ information still kept in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA.

Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 







status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)

Gets byte count sent by SAI. 

Parameters:

base – SAI base pointer. 
handle – SAI eDMA handle pointer. 
count – Bytes count sent by SAI. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress. 







status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count)

Gets byte count received by SAI. 

Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 
count – Bytes count received by SAI. 


Return values:

kStatus_Success – Succeed get the transfer count. 
kStatus_NoTransferInProgress – There is no non-blocking transaction in progress. 







uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle)

Gets valid transfer slot. 
This function can be used to query the valid transfer request slot that the application can submit. It should be called in the critical section, that means the application could call it in the corresponding callback function or disable IRQ before calling it in the application, otherwise, the returned value may not correct.

Parameters:

base – SAI base pointer 
handle – SAI eDMA handle pointer. 


Return values:
valid – slot count that application submit. 






FSL_SAI_EDMA_DRIVER_VERSION

Version 2.7.4 




enum _sai_edma_interleave

sai interleave type 
Values:


enumerator kSAI_EDMAInterleavePerChannelSample





enumerator kSAI_EDMAInterleavePerChannelBlock







typedef struct sai_edma_handle sai_edma_handle_t





typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData)

SAI eDMA transfer callback function for finish and error. 




typedef enum _sai_edma_interleave sai_edma_interleave_t

sai interleave type 




MCUX_SDK_SAI_EDMA_RX_ENABLE_INTERNAL

the SAI enable position When calling SAI_TransferReceiveEDMA 




MCUX_SDK_SAI_EDMA_TX_ENABLE_INTERNAL

the SAI enable position When calling SAI_TransferSendEDMA 




struct sai_edma_handle


#include <fsl_sai_edma.h>
SAI DMA transfer handle, users should not touch the content of the handle. 

Public Members


edma_handle_t *dmaHandle

DMA handler for SAI send 




uint8_t nbytes

eDMA minor byte transfer count initially configured. 




uint8_t bytesPerFrame

Bytes in a frame 




uint8_t channelMask

Enabled channel mask value, reference _sai_channel_mask 




uint8_t channelNums

total enabled channel nums 




uint8_t channel

Which data channel 




uint8_t count

The transfer data count in a DMA request 




uint32_t state

Internal state for SAI eDMA transfer 




sai_edma_callback_t callback

Callback for users while transfer finish or error occurs 




void *userData

User callback parameter 




uint8_t tcd[((4U) + 1U) * sizeof(edma_tcd_t)]

TCD pool for eDMA transfer. 




sai_transfer_t saiQueue[(4U)]

Transfer queue storing queued transfer. 




size_t transferSize[(4U)]

Data bytes need to transfer 




sai_edma_interleave_t interleaveType

Transfer interleave type 




volatile uint8_t queueUser

Index for user to queue transfer. 




volatile uint8_t queueDriver

Index for driver to get the transfer data and size 







SAR_ADC: SAR_ADC Module#


void ADC_GetDefaultConfig(adc_config_t *config)

This function is used to get available predefined configurations for the ADC initialization. 

Parameters:

config – Pointer to the ADC configuration structure, please refer to adc_config_t for details. 







void ADC_Init(ADC_Type *base, const adc_config_t *config)

This function is used to initialize the ADC. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the ADC configuration structure, please refer to adc_config_t for details. 







void ADC_Deinit(ADC_Type *base)

This function is used to de-initialize the ADC. 

Parameters:

base – ADC peripheral base address. 







static inline void ADC_SetPowerDownMode(ADC_Type *base, bool enable)

This function is used to enter or exit power-down mode. 
After the release of the reset, the ADC analog module will be kept in power-down mode by default. The power-down mode can be set anytime. However, ADC can enter the power-down mode successfully only after completion of an ongoing conversion (if there is one). In scan mode, the ongoing operation should be aborted manually before or after switching mode. If the power-down mode is entered by setting MCR[PWDN], the process running in the previous mode must be restarted manually (by setting the appropriate START bit in the MCR register) after exiting power-down mode.

Note
After setting the ADC mode, it is recommended to use the function ADC_GetAdcState to query whether the ADC has correctly entered the mode.


Parameters:

base – ADC peripheral base address. 
enable – Indicates whether to enter or exit power-down mode.

true Request to enter power-down mode.
false When ADC status is in power-down mode (MSR[ADCSTATUS] = 001b), start ADC transition to IDLE mode. 









static inline void ADC_SetOperatingClock(ADC_Type *base, adc_clock_frequency_t clockSelect)

This function is used to select the ADC operating clock. 

Note
Needs to enter power-down mode before changing the ADC internal operating clock.


Parameters:

base – ADC peripheral base address. 
clockSelect – ADC clock frequency selection, please refer to adc_clock_frequency_t for details. 







static inline adc_state_t ADC_GetAdcState(ADC_Type *base)

This function is used to get the ADC state. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC state, for possible states, please refer to adc_state_t for details. 






static inline bool ADC_CheckAutoClockOffEnabled(ADC_Type *base)

This function is used to check whether the ADC auto clock-off feature has been enabled or not. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC auto clock-off feature status.

true Auto clock-off feature has been enabled.
false Auto clock-off feature has not been enabled. 








static inline uint8_t ADC_GetCurrentConvertedChannelId(ADC_Type *base)

This function is used to get the ID of the channel that is currently being converted. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC channel ID that is currently being converted. 






static inline bool ADC_CheckSelfTestConvInProcess(ADC_Type *base)

This function is used to check whether the self-test conversion is in process or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Self-test conversion status.

true Self-test conversion is in process.
false Self-test conversion is not in process. 








static inline bool ADC_CheckInjectConvInProcess(ADC_Type *base)

This function is used to check whether the inject conversion is in process or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Inject conversion status.

true Inject conversion is in process.
false Inject conversion is not in process. 








static inline bool ADC_CheckInjectConvAborted(ADC_Type *base)

This function is used to check whether the inject conversion has been aborted or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Inject conversion abort status.

true Injected conversion has been aborted.
false Injected conversion has not been aborted. 








static inline bool ADC_CheckNormalConvInProcess(ADC_Type *base)

This function is used to check whether the normal conversion is in process or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Normal conversion status.

true Normal conversion is in process.
false Normal conversion is not in process. 








static inline bool ADC_CheckCalibrationBusy(ADC_Type *base)

This function is used to check whether the ADC is executing calibration or ready for use. 

Parameters:

base – ADC peripheral base address.


Returns:
Calibration process status.

true ADC is busy in a calibration process.
false ADC is ready for use. 








static inline bool ADC_CheckCalibrationFailed(ADC_Type *base)

This function is used to check whether the calibration has failed or passed. 

Note
When the user clears the calibration failed status and then reads the status, it will display the calibration passed. At this time, the calibration may not be successful. The user must read the MSR[CALBUSY] bit by function ADC_CheckCalibrationBusy to perform a double check.


Returns:
Normal conversion status.

true Calibration failed.
false Calibration passed (must be checked with CALBUSY = 0b). 








static inline void ADC_ClearCalibrationFailedFlag(ADC_Type *base)

This function is used to clear the flag of calibration. 

Parameters:

base – ADC peripheral base address. 







static inline bool ADC_CheckCalibrationSuccessful(ADC_Type *base)

This function is used to check whether the calibration is successful or not. 

Parameters:

base – ADC peripheral base address.


Returns:
Normal conversion status.

true Calibrated or calibration successful.
false Uncalibrated or calibration unsuccessful. 








void ADC_SetConvChainConfig(ADC_Type *base, const adc_chain_config_t *config)

This function is used to configure the chain. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the chain configuration structure, please refer to adc_chain_config_t for details. 







static inline void ADC_EnableSpecificChannelNormalConv(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC channel to execute normal conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the normal conversion. 







static inline void ADC_DisableSpecificChannelNormalConv(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC channel to execute the normal conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the normal conversion. 







static inline void ADC_EnableSpecificChannelInjectConv(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC channel to execute the inject conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the inject conversion. 







static inline void ADC_DisableSpecificChannelInjectConv(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC channel to execute the inject conversion. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the inject conversion. 







static inline void ADC_SetConvMode(ADC_Type *base, adc_conv_mode_t convMode)

This function is used to set the ADC conversion mode. 

Note
Before setting the conversion mode, users need to check whether the ADC is in the idle status through the function ADC_GetAdcState.


Parameters:

base – ADC peripheral base address. 
convMode – ADC conversion mode, please refer to adc_conv_mode_t for details. 







static inline void ADC_StartConvChain(ADC_Type *base, adc_conv_mode_t convMode)

This function is used to start the ADC conversion chain to execute the conversion. 

Note
Normal conversion supports two conversion modes, one is one-shot conversion mode, and the other is scan conversion mode. Normal conversion should usually be used to convert analog samples most of the time in an application, unless there is a special need. Inject conversion has a higher priority than normal conversion and it runs in one-shot mode only, it can be started in IDLE condition or when normal conversion is in process.


Parameters:

base – ADC peripheral base address. 
convMode – Pointer to the ADC conversion chain, please refer to adc_conv_mode_t for details. 







static inline void ADC_StopConvChain(ADC_Type *base)

This function is used to stop scan in normal conversion scan operation mode. 

Note
In scan operation mode, the MCR[NSTART] field remains high after setting. Clearing this field in scan operation mode causes the current chain conversion to finish, then stop the scan.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_AbortCurrentConvChain(ADC_Type *base)

This function is used to abort the conversion chain. 
Abort the current chain of conversions by setting MCR[ABORTCHAIN]. In that case, the behavior of the ADC depends on MCR[MODE] (one-shot/scan conversion modes). In one-shot mode, MSR[NSTART] is automatically reset together with MCR[ABORTCHAIN], an end-of-chain interrupt is not generated in the case of an abort chain. In scan mode, a new chain is started. The end-of-conversion interrupt of the current aborted conversion is not generated but an end-of-chain interrupt is generated.

Note
Setting this field in an IDLE state (for example, no normal/inject conversion is in process) has no effect. In this case, the MCR[ABORTCHAIN] field is reset immediately.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_AbortCurrentConv(ADC_Type *base)

This function is used to abort the conversion channel. 
Abort the current conversion and immediately start the conversion of the next channel of the chain. In the case of an abort operation, MSR[NSTART/JSTART] remains set if not in the last channel of the chain, and MCR[ABORT] is reset as soon as the channel is aborted. The end-of-conversion interrupt corresponds to the aborted channel is not generated. This behavior is true for normal or inject conversion modes. If the last channel of a chain is aborted, and the end-of-chain is reported, then an end-of-chain interrupt will be generated.

Note
This conversion can not abort while the self-test channel conversion is in process.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_EnableConvInt(ADC_Type *base, uint32_t mask)

This function is used to enable the ADC end-of-conversion and end-of-chain interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to enable the ADC end-of-conversion and end-of-chain interrupts, please refer to _adc_conv_int_enable for details. 







static inline void ADC_DisableConvInt(ADC_Type *base, uint32_t mask)

This function is used to disable the ADC end-of-conversion and end-of-chain interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to disable the ADC end-of-conversion and end-of-chain interrupts, please refer to _adc_conv_int_enable for details. 







static inline uint32_t ADC_GetConvIntStatus(ADC_Type *base)

This function is used to get the ADC end-of-conversion and end-of-chain interrupts status. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC end-of-conversion and end-of-chain interrupts status mask. 






static inline void ADC_ClearConvIntStatus(ADC_Type *base, uint32_t mask)

This function is used to clear the ADC end-of-conversion and end-of-chain interrupts status. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value for flags to be cleared, please refer to _adc_conv_int_flag for details. 







static inline void ADC_EnableSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC channel end-of-conversion interrupt. 

Note
This function can only turn on the interrupt of a specific channel, if the interrupt occurs, the user also needs to turn on the global end-of-conversion interrupt by using function ADC_EnableConvInt


Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the end-of-conversion interrupt. 







static inline void ADC_DisableSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC channel end-of-conversion interrupt. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the end-of-conversion interrupt. 







static inline bool ADC_CheckSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to check whether the specific conversion channel’s end-of-conversion interrupt has been occured. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to check the end-of-conversion interrupt status.


Returns:
Channel end-of-conversion interrupt status flag of the specific channel.

true Channel end-of-conversion interrupt has been occured.
false Channel end-of-conversion interrupt has not been occured. 








static inline void ADC_ClearSpecificConvChannelInt(ADC_Type *base, uint8_t channelIndex)

This function is used to clear specific channel end-of-conversion interrupt flag. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to clear the end-of-conversion interrupt flag. 







static inline void ADC_EnableDmaTransfer(ADC_Type *base)

This function is used to enable the DMA transfer function. 

Note
This function is a master switch used to control whether the data converted by the ADC is transmitted through DMA. If the user configures DMA to transmit the conversion data of the channel during the chain channel configuration process, then the main switch of the DMA transmission must be turned on, otherwise, data transmission cannot be performed.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_DisableDmaTransfer(ADC_Type *base)

This function is used to disable the DMA transfer function. 

Parameters:

base – ADC peripheral base address. 







static inline void ADC_EnableSpecificConvChannelDmaTransfer(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC conversion channel’s DMA transfer function. 

Note
This function can only turn on the DMA transfer of a specific channel, before using the DMA transfer, the user needs to turn on the global DMA transfer by using the function ADC_EnableDmaTransfer.


Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the DMA transfer function. 







static inline void ADC_DisableSpecificConvChannelDmaTransfer(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC conversion channel’s DMA transfer function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the DMA transfer function. 







static inline void ADC_EnableSpecificConvChannelPresample(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC conversion channel’s pre-sample function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to enable the pre-sample function. 







static inline void ADC_DisableSpecificConvChannelPresample(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC conversion channel’s pre-sample function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to disable the pre-sample function. 







void ADC_SetAnalogWdgConfig(ADC_Type *base, const adc_wdg_config_t *config)

This function is used to configure the analog watchdog. 
The analog watchdogs are used to monitor the conversion result to see if it is within defined limits, specified by a higher and a lower threshold value. After the conversion of the selected channel, a comparison is performed between the converted value and the threshold values. If the converted value is outside the threshold values, then a corresponding threshold violation interrupt is generated.

Parameters:

base – ADC peripheral base address. 
config – Pointer to the analog watchdog configuration structure, please refer to adc_wdg_config_t for details. 







static inline void ADC_EnableSpecificConvChannelAnalogWdg(ADC_Type *base, uint8_t channelIndex)

This function is used to enable the specific ADC conversion channel’s analog watchdog function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Conversion channel index to enable the analog watchdog function. 







static inline void ADC_DisableSpecificConvChannelAnalogWdg(ADC_Type *base, uint8_t channelIndex)

This function is used to disable the specific ADC conversion channel’s analog watchdog function. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Conversion channel index to disable the analog watchdog function. 







static inline bool ADC_CheckSpecificConvChannelOutofRange(ADC_Type *base, uint8_t channelIndex)

This function is used to check whether the specific conversion channel’s converted data is out of range. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to check the converted data out of range status.


Returns:
Converted data out of range status of the specific conversion channel.

true Channel converted data is out of range.
false Channel converted data is in range. 








static inline void ADC_ClearSpecificConvChannelOutofRange(ADC_Type *base, uint8_t channelIndex)

This function is used to clear the specific conversion channel’s converted data out-of-range flag. 

Parameters:

base – ADC peripheral base address. 
channelIndex – Channel index to clear the converted data out of range flag. 







static inline void ADC_EnableWdgThresholdInt(ADC_Type *base, uint32_t mask)

This function is used to enable the analog watchdog threshold low or/and high interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to enable the analog watchdog threshold low or/and high interrupts, please refer to _adc_wdg_threshold_int_enable for details. 







static inline void ADC_DisableWdgThresholdInt(ADC_Type *base, uint32_t mask)

This function is used to disable the analog watchdog threshold low or/and high interrupts. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to disable the analog watchdog threshold low or/and high interrupts, please refer to _adc_wdg_threshold_int_enable for details. 







static inline uint32_t ADC_GetWdgThresholdIntStatus(ADC_Type *base)

This function is used to get the analog watchdog threshold interrupts status. 

Parameters:

base – ADC peripheral base address.


Returns:
Analog watchdog threshold interrupts status mask. 






static inline void ADC_ClearWdgThresholdIntStatus(ADC_Type *base, uint32_t mask)

This function is used to clear the analog watchdog threshold low or/and high interrupts status. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value for flags to be cleared, please refer to _adc_wdg_threshold_int_flag for details. 







bool ADC_DoCalibration(ADC_Type *base, const adc_calibration_config_t *config)

This function is used to do the calibration. 
The calibration is used to reduce or eliminate the various errors. In the calibration process, the calibration values for offset, gain, and capacitor mismatch are obtained. These calibration values (except gain calibration) are used in a result post-processing step to reduce or eliminate the various errors contribution effects. The gain calibration is used during the sample phase to define the additional charge to be loaded in order to compensate for the gain failure. Calibration must be performed after every power-up reset and whenever required in runtime operation. It is also recommended to run calibration if the operating conditions (particularly VrefH) change. Never apply functional reset during the calibration process. If applied, calibration must be rerun after exiting a reset condition; otherwise, the calibration-generated values and conversion results may be unspecified.

Note
This function executes a calibration sequence, it is recommended to run this sequence before using the ADC converter. The maximum clock frequency for the calibration is 40 MHz. Before calling this function, the user needs to ensure that the input clock is within 40MHz. The results of individual steps are also updated in the CALSTAT register (CALSTAT[STAT_n]). The result of the last failed step is dynamically updated in the same register.


Parameters:

base – ADC peripheral base address. 
config – Pointer to the calibration configuration structure, please refer to adc_calibration_config_t for details.


Returns:
Status whether calibration is running passed or failed.

true Calibration successful.
false Calibration unsuccessful. 








void ADC_SetUserOffsetAndGainConfig(ADC_Type *base, const adc_user_offset_gain_config_t *config)

This function is used to configure the user gain and offset. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the user offset and gain configuration structure, please refer to adc_user_offset_gain_config_t for details. 







void ADC_SetSelfTestConfig(ADC_Type *base, const adc_self_test_config_t *config)

This function is used to configure the ADC self-test. 
The self-test is used to check at regular intervals whether ADC is operating correctly. When self-test is enabled, ADC automatically checks its components and flags any errors it finds. The test can be enabled to check the supply voltage (VDD), reference voltage (VrefH), and calibrated values.

Note
Before calling this function, please ensure the functional conversion is one-shot conversion mode normal conversion type and the operating clock are equal to bus frequency. ADC self-test should be run with MCR[ADCLKSE] bit set to 1. Self-test with ADCLKSE bit set to 0 can give erroneous results.


Parameters:

base – ADC peripheral base address. 
config – Pointer to the self-test configuration structure, please refer to adc_self_test_config_t for details. 







void ADC_SetSelfTestWdgConfig(ADC_Type *base, const adc_self_test_wdg_config_t *config)

This function is used to configure the ADC self-test watchdog. 

Parameters:

base – ADC peripheral base address. 
config – Pointer to the self-test watchdog configuration structure, please refer to adc_self_test_wdg_config_t for details. 







void ADC_GetCalibrationLastFailedTestResult(ADC_Type *base, int16_t *result)

This function is used to get the test result for the last failed test. 

Parameters:

base – ADC peripheral base address. 
result – Points to a 16-bit signed variable, and it is used to store the test result for the last failing test. 







static inline uint16_t ADC_GetCalibrationStepsStatus(ADC_Type *base)

This function is used to get the status of the calibration steps. 

Note
The status of calibration steps (step 0 to step 12) is stored in the CALSTAT register, and only the lower 12 bits are available in the returned result.


Parameters:

base – ADC peripheral base address.


Returns:
ADC self-test interrupt status mask. 






static inline void ADC_EnableSelfTest(ADC_Type *base)

This function is used to enable the ADC self-test. 
Decides whether to enable the ADC self-test. The self-test test is enabled by setting STCR2[EN], this field must be set before starting normal conversion and should not be changed while the conversion is in process. This field should only be reset after the end-of-conversion of the last self-test channel has been received.

Note
ADC self-test should be run with MCR[ADCLKSE] bit set to 1. Self-test with ADCLKSE bit set to 0 can give erroneous results. In the case of Inject Conversion mode, test channel conversion is not performed. It is performed only during normal conversions.


Parameters:

base – ADC peripheral base address. 







static inline void ADC_DisableSelfTest(ADC_Type *base)

This function is used to disable the ADC self-test. 

Parameters:

base – ADC peripheral base address. 







static inline void ADC_EnableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_wdg_threshold_t wdgID)

This function is used to enable the ADC self-test watchdog threshold for algorithm S step 0/1/2 and algorithm C. 
The user can pass kADC_SelfTestWdgThresholdForAlgSStep0 as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm S step 0; pass kADC_SelfTestWdgThresholdForAlgSStep1Integer as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm S step 1; pass kADC_SelfTestWdgThresholdForAlgSStep2 as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm S step 2; pass kADC_SelfTestWdgThresholdForAlgCStep0 as parameter ‘wdgID’ to enable the self-test watchdog threshold function for algorithm C; Other enumerations in adc_self_test_wdg_threshold_t have no use.

Parameters:

base – ADC peripheral base address. 
wdgID – Watchdog threshold index to enable, please refer to adc_self_test_wdg_threshold_t for details. 







static inline void ADC_DisableSelfTestWdgThreshold(ADC_Type *base, adc_self_test_wdg_threshold_t wdgID)

This function is used to disable the ADC self-test watchdog threshold for algorithm S step 0/1/2 and algorithm C. 
The user can pass kADC_SelfTestWdgThresholdForAlgSStep0 as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm S step 0; pass kADC_SelfTestWdgThresholdForAlgSStep1Integer as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm S step 1; pass kADC_SelfTestWdgThresholdForAlgSStep2 as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm S step 2; pass kADC_SelfTestWdgThresholdForAlgCStep0 as parameter ‘wdgID’ to disable the self-test watchdog threshold function for algorithm C; Other enumerations in adc_self_test_wdg_threshold_t have no use.

Parameters:

base – ADC peripheral base address. 
wdgID – Watchdog threshold index to disable, please refer to adc_self_test_wdg_threshold_t for details. 







static inline void ADC_EnableSelfTestWdgTimer(ADC_Type *base, adc_alg_type_t wdgTimerType)

This function is used to enable the ADC self-test watchdog timer for algorithm S or/and algorithm C. 
The user can pass kADC_SelfTestForAlgS as parameter ‘wdgTimerType’ to enable the watchdog timer for algorithm S; pass kADC_SelfTestForAlgC as parameter ‘wdgTimerType’ to enable the watchdog timer for algorithm C; pass kADC_SelfTestForAlgSAndC as parameter ‘wdgTimerType’ to enable the watchdog timer for algorithm S and C.

Parameters:

base – ADC peripheral base address. 
wdgTimerType – Watchdog timer type to enable, please refer to adc_alg_type_t for details. 







static inline void ADC_DisableSelfTestWdgTimer(ADC_Type *base, adc_alg_type_t wdgTimerType)

This function is used to disable the ADC self-test watchdog timer. 
The user can pass kADC_SelfTestForAlgS as parameter ‘wdgTimerType’ to disable the watchdog timer for algorithm S; pass kADC_SelfTestForAlgC as parameter ‘wdgTimerType’ to disable the watchdog timer for algorithm C; pass kADC_SelfTestForAlgSAndC as parameter ‘wdgTimerType’ to disable the watchdog timer for algorithm S and C.

Parameters:

base – ADC peripheral base address. 
wdgTimerType – Watchdog timer type to disable, please refer to adc_alg_type_t for details. 







static inline void ADC_SetSelfTestWdgTimerVal(ADC_Type *base, adc_wdg_timer_val_t wdgTimerVal)

This function is used to set the ADC self-test watchdog timer value. 

Parameters:

base – ADC peripheral base address. 
wdgTimerVal – Watchdog timer value, please refer to adc_wdg_timer_val_t for details. 







static inline uint16_t ADC_GetSelfTestChannelConvFailedData(ADC_Type *base, adc_self_test_wdg_threshold_t type)

This function is used to get the ADC self-test channel converted data when ERR_S0/ERR_S1_INTEGER/ ERR_S1_FRACTION/ERR_S2/ERR_C occurred. 

Note
The user can pass kADC_SelfTestWdgThresholdForAlgSStep0 as parameter ‘type’ to get the converted data when ERR_S0 occurred; pass kADC_SelfTestWdgThresholdForAlgSStep1Integer as parameter ‘type’ to get the converted data when ERR_S1_INTEGER occurred; pass kADC_SelfTestWdgThresholdForAlgSStep1Fraction as parameter ‘type’ to get the converted data when ERR_S1_FRACTION occurred; pass kADC_SelfTestWdgThresholdForAlgSStep2 as parameter ‘type’ to get the converted data when ERR_S2 occurred; pass kADC_SelfTestWdgThresholdForAlgCStep0 as parameter ‘type’ to get the converted data when ERR_C occurred; Other enumerations in adc_self_test_wdg_threshold_t have no use.


Parameters:

base – ADC peripheral base address. 
type – Watchdog threshold index to get the ADC self-test channel converted data, please refer to adc_self_test_wdg_threshold_t for details. 







static inline void ADC_EnableSelfTestInt(ADC_Type *base, uint32_t mask)

This function is used to enable the ADC self-test-related interrupts. 

Note
Watchdog timer feature is applicable only for scan operation mode and not for one-shot operation mode.


Parameters:

base – ADC peripheral base address. 
mask – Mask value to enable the ADC self-test related interrupts, please refer to _adc_self_test_int_enable for details. 







static inline void ADC_DisableSelfTestInt(ADC_Type *base, uint32_t mask)

This function is used to disable the ADC self-test interrupt. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value to disable the ADC self-test related interrupts, please refer to _adc_self_test_int_enable for details. 







static inline uint32_t ADC_GetSelfTestIntStatus(ADC_Type *base)

This function is used to get the ADC self-test interrupts status. 

Parameters:

base – ADC peripheral base address.


Returns:
ADC self-test related interrupts status mask. 






static inline void ADC_ClearSelfTestIntStatus(ADC_Type *base, uint32_t mask)

This function is used to clear the ADC self-test interrupts status. 

Parameters:

base – ADC peripheral base address. 
mask – Mask value for flags to be cleared, please refer to _adc_self_test_int_flag for details. 







bool ADC_GetChannelConvResult(ADC_Type *base, adc_conv_result_t *result, uint8_t channelIndex)

This function is used to get the specific ADC channel’s conversion result. 
CDR[VALID] indicates whether a new conversion is available, this field is automatically reset to 0 when the data is read. CDR[OVERW] Indicates whether the previous conversion data was overwritten without having been read, in which case the overwritten data is lost.

Parameters:

base – SAR ADC peripheral base address. 
result – Pointer to SAR ADC channels conversion result structure, please refer to adc_conv_result_t for details. 
channelIndex – Channel index to get the conversion result.


Returns:
Indicates whether the acquisition of the specific channel conversion result is successful or not.

true Obtaining the specific channel conversion result successfully, and the conversion result is stored in the input parameter result.
false Obtaining the specific channel conversion result failed. 








bool ADC_GetSelfTestChannelConvData(ADC_Type *base, adc_self_test_conv_result_t *result)

This function is used to get the test channel converted data when algorithm S step 0, algorithm S step 2, or algorithm C step executes. 

Parameters:

base – ADC peripheral base address. 
result – Pointer to the SAR ADC self-test channel conversion result structure, please refer to adc_self_test_conv_result_t for details.


Returns:
Indicates whether the acquisition of the self-test channel conversion result is successful or not.

true Obtaining the self-test channel conversion result successfully, and the conversion result is stored in the input parameter ‘result’.
false Obtaining the self-test channel conversion result failed. 








bool ADC_GetSelfTestChannelConvDataForAlgSStep1(ADC_Type *base, adc_self_test_conv_result_t *result)

This function is used to get the test channel converted data when algorithm S step 1 executes. 

Parameters:

base – ADC peripheral base address. 
result – Pointer to the SAR ADC self-test channel conversion result structure, please refer to adc_self_test_conv_result_t for details.


Returns:
Indicates whether the acquisition of the self-test channel conversion result is successful or not.

true Obtaining the self-test channel conversion result successfully, and the conversion result is stored in the input parameter ‘result’.
false Obtaining the self-test channel conversion result failed. 








FSL_SAR_ADC_DRIVER_VERSION

SAR ADC driver version 2.3.0. 




enum _adc_conv_int_enable

This enumeration provides the mask for the ADC end-of-conversion and end-of-chain interrupts enabling. 
Values:


enumerator kADC_NormalConvChainEndIntEnable

Enable end of normal chain conversion interrupt. 




enumerator kADC_NormalConvEndIntEnable

Enable end of normal conversion interrupt. 




enumerator kADC_InjectConvChainEndIntEnable

Enable end of inject chain conversion interrupt. 




enumerator kADC_InjectConvEndIntEnable

Enable end of inject conversion interrupt. 






enum _adc_wdg_threshold_int_enable

This enumeration provides the mask for the ADC analog watchdog threshold interrupts enabling. 
Values:


enumerator kADC_wdg0LowThresholdIntEnable

Enable watchdog 0 low threshold interrupt. 




enumerator kADC_wdg0HighThresholdIntEnable

Enable watchdog 0 high threshold interrupt. 




enumerator kADC_wdg1LowThresholdIntEnable

Enable watchdog 1 low threshold interrupt. 




enumerator kADC_wdg1HighThresholdIntEnable

Enable watchdog 1 high threshold interrupt. 




enumerator kADC_wdg2LowThresholdIntEnable

Enable watchdog 2 low threshold interrupt. 




enumerator kADC_wdg2HighThresholdIntEnable

Enable watchdog 2 high threshold interrupt. 




enumerator kADC_wdg3LowThresholdIntEnable

Enable watchdog 3 low threshold interrupt. 




enumerator kADC_wdg3HighThresholdIntEnable

Enable watchdog 3 high threshold interrupt. 




enumerator kADC_wdg4LowThresholdIntEnable

Enable watchdog 4 low threshold interrupt. 




enumerator kADC_wdg4HighThresholdIntEnable

Enable watchdog 4 high threshold interrupt. 




enumerator kADC_wdg5LowThresholdIntEnable

Enable watchdog 5 low threshold interrupt. 




enumerator kADC_wdg5HighThresholdIntEnable

Enable watchdog 5 high threshold interrupt. 




enumerator kADC_wdg6LowThresholdIntEnable

Enable watchdog 6 low threshold interrupt. 




enumerator kADC_wdg6HighThresholdIntEnable

Enable watchdog 6 high threshold interrupt. 




enumerator kADC_wdg7LowThresholdIntEnable

Enable watchdog 7 low threshold interrupt. 




enumerator kADC_wdg7HighThresholdIntEnable

Enable watchdog 7 high threshold interrupt. 






enum _adc_self_test_int_enable

This enumeration provides the mask for the ADC self-test related interrupts enabling. 
Values:


enumerator kADC_AlgSStep0ErrIntEnable

Enable self-test algorithm S step0 error interrupt. 




enumerator kADC_AlgSStep1ErrIntEnable

Enable self-test algorithm S step1 error interrupt. 




enumerator kADC_AlgSStep2ErrIntEnable

Enable self-test algorithm S step2 error interrupt. 




enumerator kADC_AlgCErrIntEnable

Enable self-test algorithm C error interrupt. 




enumerator kADC_AlgSEndIntEnable

Enable self-test algorithm S end interrupt. 




enumerator kADC_AlgCEndIntEnable

Enable self-test algorithm C end interrupt. 




enumerator kADC_ConvEndIntEnable

Enable self-test conversion end interrupt. 




enumerator kADC_WdgTimeErrIntEnable

Enable watchdog time error interrupt. 




enumerator kADC_WdgSequenceErrIntEnable

Enable watchdog sequence error interrupt. 






enum _adc_conv_int_flag

This enumeration provides the mask for the ADC end-of-conversion and end-of-chain interrupts flag. 
Values:


enumerator kADC_NormalConvChainEndIntFlag

Indicates whether the end of normal chain conversion interrupt has occurred. 




enumerator kADC_NormalConvEndIntFlag

Indicates whether the end of conversion interrupt has occurred. 




enumerator kADC_InjectConvChainEndIntFlag

Indicates whether the end of inject chain conversion interrupt has occurred. 




enumerator kADC_InjectConvEndIntFlag

Indicates whether the end of inject conversion interrupt has occurred. 






enum _adc_wdg_threshold_int_flag

This enumeration provides the mask for the ADC analog watchdog threshold interrupts flag. 
Values:


enumerator kADC_wdg0LowThresholdIntFlag

Indicates whether the watchdog 0 low threshold interrupt has occurred. 




enumerator kADC_wdg0HighThresholdIntFlag

Indicates whether the watchdog 0 high threshold interrupt has occurred. 




enumerator kADC_wdg1LowThresholdIntFlag

Indicates whether the watchdog 1 low threshold interrupt has occurred. 




enumerator kADC_wdg1HighThresholdIntFlag

Indicates whether the watchdog 1 high threshold interrupt has occurred. 




enumerator kADC_wdg2LowThresholdIntFlag

Indicates whether the watchdog 2 low threshold interrupt has occurred. 




enumerator kADC_wdg2HighThresholdIntFlag

Indicates whether the watchdog 2 high threshold interrupt has occurred. 




enumerator kADC_wdg3LowThresholdIntFlag

Indicates whether the watchdog 3 low threshold interrupt has occurred. 




enumerator kADC_wdg3HighThresholdIntFlag

Indicates whether the watchdog 3 high threshold interrupt has occurred. 




enumerator kADC_wdg4LowThresholdIntFlag

Indicates whether the watchdog 4 low threshold interrupt has occurred. 




enumerator kADC_wdg4HighThresholdIntFlag

Indicates whether the watchdog 4 high threshold interrupt has occurred. 




enumerator kADC_wdg5LowThresholdIntFlag

Indicates whether the watchdog 5 low threshold interrupt has occurred. 




enumerator kADC_wdg5HighThresholdIntFlag

Indicates whether the watchdog 5 high threshold interrupt has occurred. 




enumerator kADC_wdg6LowThresholdIntFlag

Indicates whether the watchdog 6 low threshold interrupt has occurred. 




enumerator kADC_wdg6HighThresholdIntFlag

Indicates whether the watchdog 6 high threshold interrupt has occurred. 




enumerator kADC_wdg7LowThresholdIntFlag

Indicates whether the watchdog 7 low threshold interrupt has occurred. 




enumerator kADC_wdg7HighThresholdIntFlag

Indicates whether the watchdog 7 high threshold interrupt has occurred. 






enum _adc_self_test_int_flag

This enumeration provides the mask for the ADC self-test-related interrupts flag. 
Values:


enumerator kADC_AlgSStep0ErrIntFlag

Indicates whether the self-test algorithm S step0 error interrupt has occurred. 




enumerator kADC_AlgSStep1ErrIntFlag

Indicates whether the self-test algorithm S step1 error interrupt has occurred. 




enumerator kADC_AlgSStep2ErrIntFlag

Indicates whether the self-test algorithm S step2 error interrupt has occurred. 




enumerator kADC_AlgCErrIntFlag

Indicates whether the self-test algorithm C error interrupt has occurred. 




enumerator kADC_AlgSEndIntFlag

Indicates whether the algorithm S end interrupt has completed. 




enumerator kADC_AlgCEndIntFlag

Indicates whether the algorithm C end interrupt has completed. 




enumerator kADC_SelfTestConvEndIntFlag

Indicates whether the self-test end-of-conversion interrupt has completed. 




enumerator kADC_OverWriteErrIntFlag

Indicates whether the overwrite error interrupt has occurred. 




enumerator kADC_WdgTimeErrIntFlag

Indicates whether the watchdog time error interrupt has occurred. 




enumerator kADC_WdgSequenceErrIntFlag

Indicates whether the watchdog sequence error interrupt has occurred. 






enum _adc_ext_trig

This enumeration provides the selection of the ADC external trigger type. 
Values:


enumerator kADC_ExtTrigDisable

Normal trigger input does not start a conversion. 




enumerator kADC_ExtTrigFallingEdge

Normal trigger (falling edge) input starts a conversion. 




enumerator kADC_ExtTrigRisingEdge

Normal trigger (rising edge) input starts a conversion. 






enum _adc_state

This enumeration provides the selection of the ADC state. 
Values:


enumerator kADC_AdcIdle

Indicates the ADC is in the IDLE state. 




enumerator kADC_AdcPowerdown

Indicates the ADC is in the power-down state. 




enumerator kADC_AdcWait

Indicates the ADC is in the wait state. 




enumerator kADC_AdcBusyInCalibration

Indicates the ADC is in the calibration busy state. 




enumerator kADC_AdcSample

Indicates the ADC is in the sample state. 




enumerator kADC_AdcConv

Indicates the ADC is in the conversion state. 






enum _adc_conv_mode

This enumeration provides the selection of the ADC conversion mode, including normal conversion one-shot mode, normal conversion scan mode, and inject conversion one-shot mode. 
Values:


enumerator kADC_NormalConvOneShotMode

Normal conversion one-shot mode. 




enumerator kADC_NormalConvScanMode

Normal conversion scan mode. 




enumerator kADC_InjectConvOneShotMode

Inject conversion one-shot mode. 






enum _adc_clock_frequency

This enumeration provides the selection of the ADC operating clock frequency, including half-bus frequency and full bus frequency. 
Values:


enumerator kADC_HalfBusFrequency

Half of bus clock frequency. 




enumerator kADC_FullBusFrequency

Equal to bus clock frequency. 






enum _adc_conv_data_align

This enumeration provides the selection of the ADC conversion data alignment, including the right alignment and left alignment. 
Values:


enumerator kADC_ConvDataRightAlign

Conversion data is right aligned. 




enumerator kADC_ConvDataLeftAlign

Conversion data is left aligned. 






enum _adc_presample_voltage_src

This enumeration provides the selection of the ADC internal analog input voltage sources for pre-sample, including DVDD0P8/2, AVDD1P8/4, VREFL_1p8 and VREFH_1p8. 
Values:


enumerator kADC_PresampleVoltageSrcVREL

Use VREL as pre-sample voltage source. 




enumerator kADC_PresampleVoltageSrcVREH

Use VREH as pre-sample voltage source. 






enum _adc_dma_request_clear_src

This enumeration provides the selection of the DMA request clear sources, including clear by acknowledgment from the DMA controller and clear on a read of the data register. 
Values:


enumerator kADC_DMARequestClearByAck

DMA request cleared by acknowledgment from DMA controller. 




enumerator kADC_DMARequestClearOnRead

DMA request cleared on a read of the data register. 






enum _adc_average_sample_numbers

This enumeration provides the selection of the ADC calibration averaging sample numbers, including 16, 32, 128, and 512 averaging samples. 
Values:


enumerator kADC_AverageSampleNumbers16

Use 16 averaging samples during calibration. 




enumerator kADC_AverageSampleNumbers32

Use 32 averaging samples during calibration. 




enumerator kADC_AverageSampleNumbers128

Use 128 averaging samples during calibration. 




enumerator kADC_AverageSampleNumbers512

Use 512 averaging samples during calibration. 






enum _adc_sample_time

This enumeration provides the selection of the ADC sample time of calibration conversions, including 22, 8, 16 and 32 cycles of ADC_CLK. 
Values:


enumerator kADC_SampleTime22

Use 22 cycles of ADC_CLK as sample time of calibration conversions. 




enumerator kADC_SampleTime8

Use 8 cycles of ADC_CLK as sample time of calibration conversions. 




enumerator kADC_SampleTime16

Use 16 cycles of ADC_CLK as sample time of calibration conversions. 




enumerator kADC_SampleTime32

Use 32 cycles of ADC_CLK as sample time of calibration conversions. 






enum _adc_wdg_threshold_int

This enumeration provides the selection of the ADC analog watchdog threshold low and high interrupt enable. 
Values:


enumerator kADC_LowHighThresholdIntDisable

Enable the ADC analog watchdog low and high threshold interrupts. 




enumerator kADC_LowThresholdIntEnable

Enable the ADC analog watchdog low threshold interrupt. 




enumerator kADC_HighThresholdIntEnable

Enable the ADC analog watchdog high threshold interrupt. 




enumerator kADC_LowHighThresholdIntEnable

Enable the ADC analog watchdog low and high threshold interrupts. 






enum _adc_alg_type

This enumeration provides the selection of the ADC self-test algorithm type, including algorithm S, algorithm C and algorithm S and C. 

Note
The meaning of enumeration member ‘kADC_SelfTestForAlgSAndC’ in different conversion modes is different, in the one-shot conversion mode, it means executing algorithm S; in the scan conversion mode, it means executing algorithm S and C. 

Values:


enumerator kADC_SelfTestForAlgS

Use algorithm S for self-test. 




enumerator kADC_SelfTestForAlgC

Use algorithm C for self-test. 




enumerator kADC_SelfTestForAlgSAndC

Use algorithm S for one-shot conversion mode self-test, use algorithm S and algorithm C for scan conversion mode self-test. 






enum _adc_self_test_wdg_threshold

This enumeration provides the selection of the ADC self-test watchdog thresholds for algorithm S step 0 - 2, and watchdog thresholds for algorithm C step 0 and step x (x = 1 - 11). 
Values:


enumerator kADC_SelfTestWdgThresholdForAlgSStep0

Self-test watchdog threshold for the algorithm S step 0. 




enumerator kADC_SelfTestWdgThresholdForAlgSStep1

Self-test watchdog threshold for the algorithm S step 1 fraction part. 




enumerator kADC_SelfTestWdgThresholdForAlgSStep2

Self-test watchdog threshold for the algorithm S step 2. 




enumerator kADC_SelfTestWdgThresholdForAlgCStep0

Self-test watchdog threshold for the algorithm C step 0. 




enumerator kADC_SelfTestWdgThresholdForAlgCStepx

Self-test watchdog threshold for the algorithm C step x. 






enum _adc_wdg_timer_val

This enumeration provides the selection of the ADC self-test watchdog timer value, including 0.1ms, 0.5ms, 1ms, 2ms, 5ms, 10ms, 20ms and 50ms. 
Values:


enumerator kADC_SelfTestWdgTimerVal0

0.1ms ((0008h × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal1

0.5ms ((0027h × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal2

1ms ((004Eh × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal3

2ms ((009Ch × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal4

5ms ((0187h × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal5

10ms ((030Dh × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal6

20ms ((061Ah × Prescaler) cycles at 80 MHz). 




enumerator kADC_SelfTestWdgTimerVal7

50ms ((0F42h × Prescaler) cycles at 80 MHz). 






typedef enum _adc_ext_trig adc_ext_trig_t

This enumeration provides the selection of the ADC external trigger type. 




typedef enum _adc_state adc_state_t

This enumeration provides the selection of the ADC state. 




typedef enum _adc_conv_mode adc_conv_mode_t

This enumeration provides the selection of the ADC conversion mode, including normal conversion one-shot mode, normal conversion scan mode, and inject conversion one-shot mode. 




typedef enum _adc_clock_frequency adc_clock_frequency_t

This enumeration provides the selection of the ADC operating clock frequency, including half-bus frequency and full bus frequency. 




typedef enum _adc_conv_data_align adc_conv_data_align_t

This enumeration provides the selection of the ADC conversion data alignment, including the right alignment and left alignment. 




typedef enum _adc_presample_voltage_src adc_presample_voltage_src_t

This enumeration provides the selection of the ADC internal analog input voltage sources for pre-sample, including DVDD0P8/2, AVDD1P8/4, VREFL_1p8 and VREFH_1p8. 




typedef enum _adc_dma_request_clear_src adc_dma_request_clear_src_t

This enumeration provides the selection of the DMA request clear sources, including clear by acknowledgment from the DMA controller and clear on a read of the data register. 




typedef enum _adc_average_sample_numbers adc_average_sample_numbers_t

This enumeration provides the selection of the ADC calibration averaging sample numbers, including 16, 32, 128, and 512 averaging samples. 




typedef enum _adc_sample_time adc_sample_time_t

This enumeration provides the selection of the ADC sample time of calibration conversions, including 22, 8, 16 and 32 cycles of ADC_CLK. 




typedef enum _adc_wdg_threshold_int adc_wdg_threshold_int_t

This enumeration provides the selection of the ADC analog watchdog threshold low and high interrupt enable. 




typedef enum _adc_alg_type adc_alg_type_t

This enumeration provides the selection of the ADC self-test algorithm type, including algorithm S, algorithm C and algorithm S and C. 

Note
The meaning of enumeration member ‘kADC_SelfTestForAlgSAndC’ in different conversion modes is different, in the one-shot conversion mode, it means executing algorithm S; in the scan conversion mode, it means executing algorithm S and C. 





typedef enum _adc_self_test_wdg_threshold adc_self_test_wdg_threshold_t

This enumeration provides the selection of the ADC self-test watchdog thresholds for algorithm S step 0 - 2, and watchdog thresholds for algorithm C step 0 and step x (x = 1 - 11). 




typedef enum _adc_wdg_timer_val adc_wdg_timer_val_t

This enumeration provides the selection of the ADC self-test watchdog timer value, including 0.1ms, 0.5ms, 1ms, 2ms, 5ms, 10ms, 20ms and 50ms. 




typedef struct _adc_config adc_config_t

This structure is used to configure the ADC module. 




typedef struct _adc_channel_config adc_channel_config_t

This structure is used to configure the ADC conversion channel. 




typedef struct _adc_chain_config adc_chain_config_t

This structure is used to configure the ADC conversion chain. 




typedef struct _adc_wdg_config adc_wdg_config_t

This structure is used to configure the ADC analog watchdog. 




typedef struct _adc_calibration_config adc_calibration_config_t

This structure is used to configure the ADC calibration. 




typedef struct _adc_user_offset_gain_config adc_user_offset_gain_config_t

This structure is used to configure the ADC user offset and gain. 




typedef struct _adc_self_test_config adc_self_test_config_t

This structure is used to configure the ADC self-test. 




typedef struct _adc_self_test_wdg_config adc_self_test_wdg_config_t

This structure is used to configure the ADC self-test watchdog for algorithm steps. 

Note
The algorithm S step 2 only has the ‘LowThrsholdVal’. 





typedef struct _adc_conv_result adc_conv_result_t

This structure is used to save the result information when obtaining the conversion result. 




typedef struct _adc_self_test_conv_result adc_self_test_conv_result_t

This structure is used to save the result information when obtaining the self-test channel conversion result. 

Note
The member ‘convData’ is used to store self-test channel conversion results. Only when executing step 1 of algorithm S, member ‘convDataFraction’ will be used to store the fractional part data. When executing other algorithms, this member will not be used. 





ADC_GROUP_COUNTS





ADC_THRESHOLD_COUNTS





ADC_SELF_TEST_THRESHOLD_COUNTS





GET_REGINDEX(channelIndex)





GET_BITINDEX(channelIndex)





REGISTER_READWRITE(baseRegister, shiftIndex)





REGISTER_READONLY(baseRegister, shiftIndex)





NCMR_IO(base, registerIndex)





JCMR_IO(base, registerIndex)





PSR_IO(base, registerIndex)





DMAR_IO(base, registerIndex)





CWSELR_IO(base, registerIndex)





CWENR_IO(base, registerIndex)





CIMR_IO(base, registerIndex)





CEOCFR_IO(base, registerIndex)





AWORR_IO(base, registerIndex)





STAWR_IO(base, registerIndex)





CEOCFR_I(base, registerIndex)





AWORR_I(base, registerIndex)





CDR_I(base, registerIndex)





WDG_SELECT_MASK(shiftIndex)





WDG_SELECT_SHIFT(shiftIndex)





WDG_SELECT(val, shiftIndex)





ADC_CDR_VALID_MASK





ADC_CDR_VALID_SHIFT





ADC_CDR_OVERW_MASK





ADC_CDR_OVERW_SHIFT





ADC_CDR_RESULT_MASK





ADC_CDR_RESULT_SHIFT





ADC_CDR_CDATA_MASK





ADC_CDR_CDATA_SHIFT





ADC_STAWR_AWDE_MASK





ADC_STAWR_THRL_MASK





ADC_STAWR_THRL_SHIFT





ADC_STAWR_THRL(val)





ADC_STAWR_THRH_MASK





ADC_STAWR_THRH_SHIFT





ADC_STAWR_THRH(val)





ADC_CALSTAT_MAX





ADC_CALSTAT_SIGN





struct _adc_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC module. 

Public Members


bool enableAutoClockOff

Decides whether to enable the ADC auto clock-off function, when set to true, the internal ADC clock is automatically switched off during IDLE mode to reduce power consumption (without going into power-down mode). 




bool enableOverWrite

Decides whether to enable the latest conversion to overwrite the current value in the data registers. 




bool enableConvertPresampleVal

Decides whether to convert the pre-sampled value, if enabled, pre-sampling is followed by the conversion, sampling will be bypassed and conversion of the pre-sampled data will be done. 




adc_ext_trig_t extTrig

Specifies whether the normal trigger (with trigger type) input starts a conversion. 




adc_conv_data_align_t convDataAlign

Selects the conversion data alignment. 




adc_clock_frequency_t clockFrequency

Selects the ADC clock frequency. 




adc_dma_request_clear_src_t dmaRequestClearSrc

Selects DMA request clear source. 




adc_presample_voltage_src_t presampleVoltageSrc[1]

Selects analog input voltages for group 0 (corresponding to channel 0 to channel 31) and group 32 (corresponding to channel 32 to channel 63) pre-sampling. 




uint8_t samplePhaseDuration[1]

Sets the sample phase duration in terms of the ADC controller clock for group 0 (corresponding to channel 0 to channel 31) and group 32 (corresponding to channel 32 to channel 63), the minimum acceptable value is 8, configuring to a value lower than 8 sets the sample period to 8 cycles. 







struct _adc_channel_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC conversion channel. 

Public Members


uint8_t channelIndex

Sets the conversion channel index. 




bool enableInt

Decides Whether to enable the interrupt function of the current conversion channel. 




bool enablePresample

Decides whether to enable the pre-sample function of the current conversion channel. 




bool enableDmaTransfer

Decides whether to enable the DMA transfer function of the current conversion channel. 




bool enableWdg

Decides whether to enable the analog watchdog function of the current conversion channel. 




uint8_t wdgIndex

Indicates which analog watchdog to provide the low and high threshold value. 







struct _adc_chain_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC conversion chain. 

Public Members


adc_conv_mode_t convMode

Selects conversion mode. 




bool enableGlobalChannelConvEndInt

Global control function to determine whether to enable the interrupt function of conversion channels. 




bool enableChainConvEndInt

Decides whether to enable the current chain end-of-conversion interrupt. 




uint8_t channelCount

Indicates the channel counts. 




adc_channel_config_t *channelConfig

Chain channels configuration. 







struct _adc_wdg_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC analog watchdog. 

Public Members


uint8_t wdgIndex

Indicates the analog watchdog index 




adc_wdg_threshold_int_t wdgThresholdInt

Selects watchdog threshold low or/and high interrupt to enable/disable. 




uint16_t lowThresholdVal

Sets the ADC analog watchdog low threshold value. 




uint16_t highThresholdVal

Sets the ADC analog watchdog high threshold value. 







struct _adc_calibration_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC calibration. 

Public Members


bool enableAverage

Decides whether to enable averaging of calibration time. 




adc_sample_time_t sampleTime

Selects sample time of calibration conversions. 




adc_average_sample_numbers_t averageSampleNumbers

Selects calibration averaging sample numbers. 







struct _adc_user_offset_gain_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC user offset and gain. 

Public Members


int8_t userOffset

Sets user defined gain value. 




int16_t userGain

Sets user defined offset value. 







struct _adc_self_test_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC self-test. 

Public Members


adc_alg_type_t algType

Selects the self-test algorithm. 




uint8_t algSteps

Sets the self-test algorithm steps, it should be programmed to zero in scan mode. 




uint8_t algSSamplePhaseDuration

Sets the self-test algorithm S conversion sampling phase duration. 




uint8_t algCSamplePhaseDuration

Sets the self-test algorithm C conversion sampling phase duration. 




uint8_t baudRate

Sets the baud rate for the selected algorithm in scan mode, must write to this field before enabling a self-test channel. 







struct _adc_self_test_wdg_config


#include <fsl_sar_adc.h>
This structure is used to configure the ADC self-test watchdog for algorithm steps. 

Note
The algorithm S step 2 only has the ‘LowThrsholdVal’. 


Public Members


adc_self_test_wdg_threshold_t wdgThresholdId

Indicates the self-test watchdog index 




uint16_t lowThrsholdVal

Sets the self-test watchdog low threshold value. 




uint16_t highThrsholdVal

Sets the self-test watchdog high threshold value. 







struct _adc_conv_result


#include <fsl_sar_adc.h>
This structure is used to save the result information when obtaining the conversion result. 

Public Members


bool overWrittenFlag

Indicates when conversion data was overwritten by a newer result, the new data is written or discarded according to MCR[OWREN]. 




uint8_t convMode

Indicates the mode of conversion for the corresponding channel. 




uint16_t convData

Stores the conversion data corresponding to the internal channel. 







struct _adc_self_test_conv_result


#include <fsl_sar_adc.h>
This structure is used to save the result information when obtaining the self-test channel conversion result. 

Note
The member ‘convData’ is used to store self-test channel conversion results. Only when executing step 1 of algorithm S, member ‘convDataFraction’ will be used to store the fractional part data. When executing other algorithms, this member will not be used. 


Public Members


bool overWrittenFlag

Indicates when conversion data is overwritten by a newer result. 




uint16_t convData

Stores the conversion data corresponding to the internal self-test channel. 




uint16_t convDataFraction

This field is only used to store the fractional part conversion result. 







SEMA42: Hardware Semaphores Driver#


FSL_SEMA42_DRIVER_VERSION

SEMA42 driver version. 





SEMA42 status return codes. 
Values:


enumerator kStatus_SEMA42_Busy

SEMA42 gate has been locked by other processor. 




enumerator kStatus_SEMA42_Reseting

SEMA42 gate reseting is ongoing. 






enum _sema42_gate_status

SEMA42 gate lock status. 
Values:


enumerator kSEMA42_Unlocked

The gate is unlocked. 




enumerator kSEMA42_LockedByProc0

The gate is locked by processor 0. 




enumerator kSEMA42_LockedByProc1

The gate is locked by processor 1. 




enumerator kSEMA42_LockedByProc2

The gate is locked by processor 2. 




enumerator kSEMA42_LockedByProc3

The gate is locked by processor 3. 




enumerator kSEMA42_LockedByProc4

The gate is locked by processor 4. 




enumerator kSEMA42_LockedByProc5

The gate is locked by processor 5. 




enumerator kSEMA42_LockedByProc6

The gate is locked by processor 6. 




enumerator kSEMA42_LockedByProc7

The gate is locked by processor 7. 




enumerator kSEMA42_LockedByProc8

The gate is locked by processor 8. 




enumerator kSEMA42_LockedByProc9

The gate is locked by processor 9. 




enumerator kSEMA42_LockedByProc10

The gate is locked by processor 10. 




enumerator kSEMA42_LockedByProc11

The gate is locked by processor 11. 




enumerator kSEMA42_LockedByProc12

The gate is locked by processor 12. 




enumerator kSEMA42_LockedByProc13

The gate is locked by processor 13. 




enumerator kSEMA42_LockedByProc14

The gate is locked by processor 14. 






typedef enum _sema42_gate_status sema42_gate_status_t

SEMA42 gate lock status. 




void SEMA42_Init(SEMA42_Type *base)

Initializes the SEMA42 module. 
This function initializes the SEMA42 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either SEMA42_ResetGate or SEMA42_ResetAllGates function.

Parameters:

base – SEMA42 peripheral base address. 







void SEMA42_Deinit(SEMA42_Type *base)

De-initializes the SEMA42 module. 
This function de-initializes the SEMA42 module. It only disables the clock.

Parameters:

base – SEMA42 peripheral base address. 







status_t SEMA42_TryLock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum)

Tries to lock the SEMA42 gate. 
This function tries to lock the specific SEMA42 gate. If the gate has been locked by another processor, this function returns an error code.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number to lock. 
procNum – Current processor number.


Return values:

kStatus_Success – Lock the sema42 gate successfully. 
kStatus_SEMA42_Busy – Sema42 gate has been locked by another processor. 







status_t SEMA42_Lock(SEMA42_Type *base, uint8_t gateNum, uint8_t procNum)

Locks the SEMA42 gate. 
This function locks the specific SEMA42 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.
If SEMA42_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number to lock. 
procNum – Current processor number.


Return values:

kStatus_Success – The gate was successfully locked. 
kStatus_Timeout – Timeout occurred while waiting for the gate to be unlocked. 


Returns:
status_t 






static inline void SEMA42_Unlock(SEMA42_Type *base, uint8_t gateNum)

Unlocks the SEMA42 gate. 
This function unlocks the specific SEMA42 gate. It only writes unlock value to the SEMA42 gate register. However, it does not check whether the SEMA42 gate is locked by the current processor or not. As a result, if the SEMA42 gate is not locked by the current processor, this function has no effect.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number to unlock. 







static inline sema42_gate_status_t SEMA42_GetGateStatus(SEMA42_Type *base, uint8_t gateNum)

Gets the status of the SEMA42 gate. 
This function checks the lock status of a specific SEMA42 gate.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number.


Returns:
status Current status. 






status_t SEMA42_ResetGate(SEMA42_Type *base, uint8_t gateNum)

Resets the SEMA42 gate to an unlocked status. 
This function resets a SEMA42 gate to an unlocked status.

Parameters:

base – SEMA42 peripheral base address. 
gateNum – Gate number.


Return values:

kStatus_Success – SEMA42 gate is reset successfully. 
kStatus_SEMA42_Reseting – Some other reset process is ongoing. 







static inline status_t SEMA42_ResetAllGates(SEMA42_Type *base)

Resets all SEMA42 gates to an unlocked status. 
This function resets all SEMA42 gate to an unlocked status.

Parameters:

base – SEMA42 peripheral base address.


Return values:

kStatus_Success – SEMA42 is reset successfully. 
kStatus_SEMA42_Reseting – Some other reset process is ongoing. 







SEMA42_GATE_NUM_RESET_ALL

The number to reset all SEMA42 gates. 




SEMA42_GATEn(base, n)

SEMA42 gate n register address. 
The SEMA42 gates are sorted in the order 3, 2, 1, 0, 7, 6, 5, 4, … not in the order 0, 1, 2, 3, 4, 5, 6, 7, … The macro SEMA42_GATEn gets the SEMA42 gate based on the gate index.
The input gate index is XOR’ed with 3U: 0 ^ 3 = 3 1 ^ 3 = 2 2 ^ 3 = 1 3 ^ 3 = 0 4 ^ 3 = 7 5 ^ 3 = 6 6 ^ 3 = 5 7 ^ 3 = 4 … 




SEMA42_BUSY_POLL_COUNT

Maximum polling iterations for SEMA42 waiting loops. 
This parameter defines the maximum number of iterations for any polling loop in the SEMA42 driver code before timing out and returning an error.
It applies to all waiting loops in SEMA42 driver, such as waiting for a gate to be unlocked, waiting for a reset to complete, or waiting for a resource to become available.
This is a count of loop iterations, not a time-based value.
If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if hardware doesn’t respond or if a resource is never released. 




TMU: Thermal Management Unit Driver#


enum _tmu_monitor_site

TMU monitor site. 
Values:


enumerator kTMU_MonitorSite0

TMU monitoring site 0. 






enum _tmu_interrupt_enable

TMU interrupt enable. 
Values:


enumerator kTMU_ImmediateTemperatureInterruptEnable

Immediate temperature threshold exceeded interrupt enable. 




enumerator kTMU_AverageTemperatureInterruptEnable

Average temperature threshold exceeded interrupt enable. 




enumerator kTMU_AverageTemperatureCriticalInterruptEnable

Average temperature critical threshold exceeded interrupt enable. 




enumerator kTMU_RisingTemperatureCriticalInterruptEnable

Rising temperature critical threshold exceeded interrupt enable. 




enumerator kTMU_FallingTemperatureCriticalInterruptEnable

Falling temperature critical threshold exceeded interrupt enable. 






enum _tmu_interrupt_status_flags

TMU interrupt status flags. 
Values:


enumerator kTMU_ImmediateTemperatureStatusFlags

Immediate temperature threshold exceeded(IHTT). 




enumerator kTMU_AverageTemperatureStatusFlags

Average temperature threshold exceeded(AHTT). 




enumerator kTMU_AverageTemperatureCriticalStatusFlags

Average temperature critical threshold exceeded.(AHTCT) 




enumerator kTMU_RisingTemperatureCriticalStatusFlags

Rising temperature critical threshold exceeded.(RTRCT) 




enumerator kTMU_FallingTemperatureCriticalStatusFlags

Falling temperature critical threshold exceeded.(FTRCT) 






enum _tmu_status_flags

TMU status flags. 
Values:


enumerator kTMU_IntervalExceededStatusFlags

Monitoring interval exceeded. The time required to perform measurement of all monitored sites has exceeded the monitoring interval as defined by TMTMIR. 




enumerator kTMU_OutOfLowRangeStatusFlags

Out-of-range low temperature measurement detected. A temperature sensor detected a temperature reading below the lowest measurable temperature of 0 °C. 




enumerator kTMU_OutOfHighRangeStatusFlags

Out-of-range high temperature measurement detected. A temperature sensor detected a temperature reading above the highest measurable temperature of 160 °C. 






enum _tmu_average_low_pass_filter

Average low pass filter setting. 
Values:


enumerator kTMU_AverageLowPassFilter1_0

Average low pass filter = 1. 




enumerator kTMU_AverageLowPassFilter0_5

Average low pass filter = 0.5. 




enumerator kTMU_AverageLowPassFilter0_25

Average low pass filter = 0.25. 




enumerator kTMU_AverageLowPassFilter0_125

Average low pass filter = 0.125. 






typedef struct _tmu_thresold_config tmu_thresold_config_t

configuration for TMU thresold. 




typedef struct _tmu_interrupt_status tmu_interrupt_status_t

TMU interrupt status. 




typedef enum _tmu_average_low_pass_filter tmu_average_low_pass_filter_t

Average low pass filter setting. 




typedef struct _tmu_config tmu_config_t

Configuration for TMU module. 




void TMU_Init(TMU_Type *base, const tmu_config_t *config)

Enable the access to TMU registers and Initialize TMU module. 

Parameters:

base – TMU peripheral base address. 
config – Pointer to configuration structure. Refer to “tmu_config_t” structure. 







void TMU_Deinit(TMU_Type *base)

De-initialize TMU module and Disable the access to DCDC registers. 

Parameters:

base – TMU peripheral base address. 







void TMU_GetDefaultConfig(tmu_config_t *config)

Gets the default configuration for TMU. 
This function initializes the user configuration structure to default value. The default value are:
Example: 
config->monitorInterval = 0U;
config->monitorSiteSelection = 0U;
config->averageLPF = kTMU_AverageLowPassFilter1_0;




Parameters:

config – Pointer to TMU configuration structure. 







static inline void TMU_Enable(TMU_Type *base, bool enable)

Enable/Disable the TMU module. 

Parameters:

base – TMU peripheral base address. 
enable – Switcher to enable/disable TMU. 







static inline void TMU_EnableInterrupts(TMU_Type *base, uint32_t mask)

Enable the TMU interrupts. 

Parameters:

base – TMU peripheral base address. 
mask – The interrupt mask. Refer to “_tmu_interrupt_enable” enumeration. 







static inline void TMU_DisableInterrupts(TMU_Type *base, uint32_t mask)

Disable the TMU interrupts. 

Parameters:

base – TMU peripheral base address. 
mask – The interrupt mask. Refer to “_tmu_interrupt_enable” enumeration. 







void TMU_GetInterruptStatusFlags(TMU_Type *base, tmu_interrupt_status_t *status)

Get interrupt status flags. 

Parameters:

base – TMU peripheral base address. 
status – The pointer to interrupt status structure. Record the current interrupt status. Please refer to “tmu_interrupt_status_t” structure. 







void TMU_ClearInterruptStatusFlags(TMU_Type *base, uint32_t mask)

Clear interrupt status flags and corresponding interrupt critical site capture register. 

Parameters:

base – TMU peripheral base address. 
mask – The mask of interrupt status flags. Refer to “_tmu_interrupt_status_flags” enumeration. 







static inline uint32_t TMU_GetStatusFlags(TMU_Type *base)

Get TMU status flags. 

Parameters:

base – TMU peripheral base address.


Returns:
The mask of status flags. Refer to “_tmu_status_flags” enumeration. 






status_t TMU_GetHighestTemperature(TMU_Type *base, uint32_t *temperature)

Get the highest temperature reached for any enabled monitored site within the temperature sensor range. 

Parameters:

base – TMU peripheral base address. 
temperature – Highest temperature recorded in degrees Celsius by any enabled monitored site.


Return values:

kStatus_Success – Temperature reading is valid. 
kStatus_Fail – Temperature reading is not valid due to no measured temperature within the sensor range of 0-160 °C for an enabled monitored site. 


Returns:
Execution status. 






status_t TMU_GetLowestTemperature(TMU_Type *base, uint32_t *temperature)

Get the lowest temperature reached for any enabled monitored site within the temperature sensor range. 

Parameters:

base – TMU peripheral base address. 
temperature – Lowest temperature recorded in degrees Celsius by any enabled monitored site.


Return values:

kStatus_Success – Temperature reading is valid. 
kStatus_Fail – Temperature reading is not valid due to no measured temperature within the sensor range of 0-160 °C for an enabled monitored site. 


Returns:
Execution status. 






status_t TMU_GetImmediateTemperature(TMU_Type *base, float *temperature)

Get the last immediate temperature at site n. The site must be part of the list of enabled monitored sites as defined by monitorSiteSelection in “tmu_config_t” structure. 

Parameters:

base – TMU peripheral base address. 
temperature – Last immediate temperature reading at site 0.


Return values:

kStatus_Success – Temperature reading is valid. 
kStatus_Fail – Temperature reading is not valid because temperature out of sensor range or first measurement still pending. 


Returns:
Execution status. 






status_t TMU_GetAverageTemperature(TMU_Type *base, uint32_t *temperature)

Get the last average temperature at site n. The site must be part of the list of enabled monitored sites as defined by monitorSiteSelection in “tmu_config_t” structure. 

Parameters:

base – TMU peripheral base address. 
temperature – Last average temperature reading at site 0.


Return values:

kStatus_Success – Temperature reading is valid. 
kStatus_Fail – Temperature reading is not valid because temperature out of sensor range or first measurement still pending. 


Returns:
Execution status. 






void TMU_SetHighTemperatureThresold(TMU_Type *base, const tmu_thresold_config_t *config)

Configure the high temperature thresold value and enable/disable relevant thresold. 

Parameters:

base – TMU peripheral base address. 
config – Pointer to configuration structure. Refer to “tmu_thresold_config_t” structure. 







FSL_TMU_DRIVER_VERSION

TMU driver version. 
Version 2.1.0. 




struct _tmu_thresold_config


#include <fsl_tmu.h>
configuration for TMU thresold. 

Public Members


bool immediateThresoldEnable

Enable high temperature immediate threshold. 




bool averageThresoldEnable

Enable high temperature average threshold. 




bool averageCriticalThresoldEnable

Enable high temperature average critical threshold. 




bool risingCriticalThresoldEnable

Enable rising temperature rate critical threshold. 




bool fallingCriticalThresoldEnable

Enable rising temperature rate critical threshold. 




uint8_t immediateThresoldValue

Range:0U-160U. Valid when corresponding thresold is enabled. High temperature immediate threshold value. Determines the current upper temperature threshold, for anyenabled monitored site. 




uint8_t averageThresoldValue

Range:0U-160U. Valid when corresponding thresold is enabled. High temperature average threshold value. Determines the average upper temperature threshold, for any enabled monitored site. 




uint8_t averageCriticalThresoldValue

Range:0U-160U. Valid when corresponding thresold is enabled. High temperature average critical threshold value. Determines the average upper critical temperature threshold, for any enabled monitored site. 




uint8_t risingfallingCriticalThresoldValue

Range:0U-160U. Valid when corresponding thresold is enabled. Rising temperature rate critical threshold value. Determines the rising upper critical temperature threshold, for any enabled monitored site. 







struct _tmu_interrupt_status


#include <fsl_tmu.h>
TMU interrupt status. 

Public Members


uint32_t interruptDetectMask

The mask of interrupt status flags. Refer to “_tmu_interrupt_status_flags” enumeration. 




uint16_t immediateInterruptsSiteMask

The mask of the temperature sensor site associated with a detected IHTT event. Please refer to “_tmu_monitor_site” enumeration. 




uint16_t averageInterruptsSiteMask

The mask of the temperature sensor site associated with a detected AHTT event. Please refer to “_tmu_monitor_site” enumeration. 




uint16_t averageCriticalInterruptsSiteMask

The mask of the temperature sensor site associated with a detected AHTCT event. Please refer to “_tmu_monitor_site” enumeration. 




uint16_t risingCriticalInterruptsSiteMask

The mask of the temperature sensor site associated with a detected RTRCT event. Please refer to “_tmu_monitor_site” enumeration. 




uint16_t fallingCriticalInterruptsSiteMask

The mask of the temperature sensor site associated with a detected FTRCT event. Please refer to “_tmu_monitor_site” enumeration. 







struct _tmu_config


#include <fsl_tmu.h>
Configuration for TMU module. 

Public Members


uint8_t monitorInterval

Temperature monitoring interval in seconds. Please refer to specific table in RM. 




uint16_t monitorSiteSelection

By setting the select bit for a temperature sensor site, it is enabled and included in all monitoring functions. If no site is selected, site 0 is monitored by default. Refer to “_tmu_monitor_site” enumeration. Please look up relevant table in reference manual. 




tmu_average_low_pass_filter_t averageLPF

The average temperature is calculated as: ALPF x Current_Temp + (1 - ALPF) x Average_Temp. For proper operation, this field should only change when monitoring is disabled. 







TPM: Timer PWM Module#


uint32_t TPM_GetInstance(TPM_Type *base)

Gets the instance from the base address. 

Parameters:

base – TPM peripheral base address 


Returns:
The TPM instance 






void TPM_Init(TPM_Type *base, const tpm_config_t *config)

Ungates the TPM clock and configures the peripheral for basic operation. 

Note
This API should be called at the beginning of the application using the TPM driver.


Parameters:

base – TPM peripheral base address 
config – Pointer to user’s TPM config structure. 







void TPM_Deinit(TPM_Type *base)

Stops the counter and gates the TPM clock. 

Parameters:

base – TPM peripheral base address 







void TPM_GetDefaultConfig(tpm_config_t *config)

Fill in the TPM config struct with the default settings. 
The default values are: 
     config->prescale = kTPM_Prescale_Divide_1;
     config->useGlobalTimeBase = false;
     config->syncGlobalTimeBase = false;
     config->dozeEnable = false;
     config->dbgMode = false;
     config->enableReloadOnTrigger = false;
     config->enableStopOnOverflow = false;
     config->enableStartOnTrigger = false;
#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
     config->enablePauseOnTrigger = false;
#endif
     config->triggerSelect = kTPM_Trigger_Select_0;
#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
     config->triggerSource = kTPM_TriggerSource_External;
     config->extTriggerPolarity = kTPM_ExtTrigger_Active_High;
#endif
#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL
     config->chnlPolarity = 0U;
#endif


 

Parameters:

config – Pointer to user’s TPM config structure. 







tpm_clock_prescale_t TPM_CalculateCounterClkDiv(TPM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz)

Calculates the counter clock prescaler. 
This function calculates the values for SC[PS].

return Calculated clock prescaler value. 

Parameters:

base – TPM peripheral base address 
counterPeriod_Hz – The desired frequency in Hz which corresponding to the time when the counter reaches the mod value 
srcClock_Hz – TPM counter clock in Hz







static inline void TPM_Reset(TPM_Type *base)

Performs a software reset on the TPM module. 
Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.

Note
TPM software reset is available on certain SoC’s only


Parameters:

base – TPM peripheral base address 







status_t TPM_SetupPwm(TPM_Type *base, const tpm_chnl_pwm_signal_param_t *chnlParams, uint8_t numOfChnls, tpm_pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)

Configures the PWM signal parameters. 
User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this function to configure all the TPM channels that will be used to output a PWM signal

Parameters:

base – TPM peripheral base address 
chnlParams – Array of PWM channel parameters to configure the channel(s) 
numOfChnls – Number of channels to configure, this should be the size of the array passed in 
mode – PWM operation mode, options available in enumeration tpm_pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz 
srcClock_Hz – TPM counter clock in Hz


Returns:
kStatus_Success PWM setup successful kStatus_Error PWM setup failed kStatus_Timeout PWM setup timeout when write register CnV or MOD 






status_t TPM_UpdatePwmDutycycle(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_pwm_mode_t currentPwmMode, uint8_t dutyCyclePercent)

Update the duty cycle of an active PWM signal. 

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number. In combined mode, this represents the channel pair number 
currentPwmMode – The current PWM mode set during PWM setup 
dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle) 


Returns:
kStatus_Success if the PWM setup was successful, kStatus_Error on failure 






void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level)

Update the edge level selection for a channel. 

Note
When the TPM has PWM pause level select feature (FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT = 1), the PWM output cannot be turned off by selecting the output level. In this case, must use TPM_DisableChannel API to close the PWM output.


Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
level – The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. See the appropriate SoC reference manual for details about this field. 







static inline uint8_t TPM_GetChannelContorlBits(TPM_Type *base, tpm_chnl_t chnlNumber)

Get the channel control bits value (mode, edge and level bit fileds). 
This function disable the channel by clear all mode and level control bits.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
The contorl bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t. 






static inline status_t TPM_DisableChannel(TPM_Type *base, tpm_chnl_t chnlNumber)

Dsiable the channel. 
This function disable the channel by clear all mode and level control bits.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






static inline status_t TPM_EnableChannel(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t control)

Enable the channel according to mode and level configs. 
This function enable the channel output according to input mode/level config parameters.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
control – The contorl bits value. This is the logical OR of members of the enumeration tpm_chnl_control_bit_mask_t. 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode)

Enables capturing an input signal on the channel using the function parameters. 
When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into the CnV register. The user has to read the CnV register separately to get this value.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
captureMode – Specifies which edge to capture 







status_t TPM_SetupOutputCompare(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_output_compare_mode_t compareMode, uint32_t compareValue)

Configures the TPM to generate timed pulses. 
When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel output is changed based on what is specified in the compareMode argument.

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
compareMode – Action to take on the channel output when the compare condition is met 
compareValue – Value to be programmed in the CnV register. 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnV 






void TPM_SetupDualEdgeCapture(TPM_Type *base, tpm_chnl_t chnlPairNumber, const tpm_dual_edge_capture_param_t *edgeParam, uint32_t filterValue)

Configures the dual edge capture mode of the TPM. 
This function allows to measure a pulse width of the signal on the input of channel of a channel pair. The filter function is disabled if the filterVal argument passed is zero.

Parameters:

base – TPM peripheral base address 
chnlPairNumber – The TPM channel pair number; options are 0, 1, 2, 3 
edgeParam – Sets up the dual edge capture function 
filterValue – Filter value, specify 0 to disable filter. 







void TPM_SetupQuadDecode(TPM_Type *base, const tpm_phase_params_t *phaseAParams, const tpm_phase_params_t *phaseBParams, tpm_quad_decode_mode_t quadMode)

Configures the parameters and activates the quadrature decode mode. 

Parameters:

base – TPM peripheral base address 
phaseAParams – Phase A configuration parameters 
phaseBParams – Phase B configuration parameters 
quadMode – Selects encoding mode used in quadrature decoder mode 







static inline void TPM_SetChannelPolarity(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)

Set the input and output polarity of each of the channels. 

Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
enable – true: Set the channel polarity to active high; false: Set the channel polarity to active low; 







static inline void TPM_EnableChannelExtTrigger(TPM_Type *base, tpm_chnl_t chnlNumber, bool enable)

Enable external trigger input to be used by channel. 
In input capture mode, configures the trigger input that is used by the channel to capture the counter value. In output compare or PWM mode, configures the trigger input used to modulate the channel output. When modulating the output, the output is forced to the channel initial value whenever the trigger is not asserted.

Note
No matter how many external trigger sources there are, only input trigger 0 and 1 are used. The even numbered channels share the input trigger 0 and the odd numbered channels share the second input trigger 1.


Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 
enable – true: Configures trigger input 0 or 1 to be used by channel; false: Trigger input has no effect on the channel 







void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask)

Enables the selected TPM interrupts. 

Parameters:

base – TPM peripheral base address 
mask – The interrupts to enable. This is a logical OR of members of the enumeration tpm_interrupt_enable_t







void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask)

Disables the selected TPM interrupts. 

Parameters:

base – TPM peripheral base address 
mask – The interrupts to disable. This is a logical OR of members of the enumeration tpm_interrupt_enable_t







uint32_t TPM_GetEnabledInterrupts(TPM_Type *base)

Gets the enabled TPM interrupts. 

Parameters:

base – TPM peripheral base address


Returns:
The enabled interrupts. This is the logical OR of members of the enumeration tpm_interrupt_enable_t






void TPM_RegisterCallBack(TPM_Type *base, tpm_callback_t callback)

Register callback. 
If channel or overflow interrupt is enabled by the user, then a callback can be registered which will be invoked when the interrupt is triggered.

Parameters:

base – TPM peripheral base address 
callback – Callback function 







void TPM_DriverIRQHandler(uint32_t instance)

TPM driver IRQ handler common entry. 
This function provides the common IRQ request entry for TPM.

Parameters:

instance – TPM instance. 







static inline uint32_t TPM_GetChannelValue(TPM_Type *base, tpm_chnl_t chnlNumber)

Gets the TPM channel value. 

Note
The TPM channel value contain the captured TPM counter value for the input modes or the match value for the output modes.


Parameters:

base – TPM peripheral base address 
chnlNumber – The channel number 


Returns:
The channle CnV regisyer value. 






static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)

Gets the TPM status flags. 

Parameters:

base – TPM peripheral base address


Returns:
The status flags. This is the logical OR of members of the enumeration tpm_status_flags_t






static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)

Clears the TPM status flags. 

Parameters:

base – TPM peripheral base address 
mask – The status flags to clear. This is a logical OR of members of the enumeration tpm_status_flags_t







static inline status_t TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks)

Sets the timer period in units of ticks. 
Timers counts from 0 until it equals the count value set here. The count value is written to the MOD register.

Note

This API allows the user to use the TPM module as a timer. Do not mix usage of this API with TPM’s PWM setup API’s.
Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.




Parameters:

base – TPM peripheral base address 
ticks – A timer period in units of ticks, which should be equal or greater than 1. 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base)

Reads the current timer counting value. 
This function returns the real-time timer counting value in a range from 0 to a timer period.

Note
Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.


Parameters:

base – TPM peripheral base address


Returns:
The current counter value in ticks 






static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)

Starts the TPM counter. 

Parameters:

base – TPM peripheral base address 
clockSource – TPM clock source; once clock source is set the counter will start running 







static inline status_t TPM_StopTimer(TPM_Type *base)

Stops the TPM counter. 

Parameters:

base – TPM peripheral base address 


Returns:
kStatus_Success PWM setup successful kStatus_Timeout PWM setup timeout when write register CnSC 






FSL_TPM_DRIVER_VERSION

TPM driver version 2.4.2. 




enum _tpm_chnl

List of TPM channels. 

Note
Actual number of available channels is SoC dependent 

Values:


enumerator kTPM_Chnl_0

TPM channel number 0 




enumerator kTPM_Chnl_1

TPM channel number 1 




enumerator kTPM_Chnl_2

TPM channel number 2 




enumerator kTPM_Chnl_3

TPM channel number 3 




enumerator kTPM_Chnl_4

TPM channel number 4 




enumerator kTPM_Chnl_5

TPM channel number 5 




enumerator kTPM_Chnl_6

TPM channel number 6 




enumerator kTPM_Chnl_7

TPM channel number 7 






enum _tpm_pwm_mode

TPM PWM operation modes. 
Values:


enumerator kTPM_EdgeAlignedPwm

Edge aligned PWM 




enumerator kTPM_CenterAlignedPwm

Center aligned PWM 




enumerator kTPM_CombinedPwm

Combined PWM (Edge-aligned, center-aligned, or asymmetrical PWMs can be obtained in combined mode using different software configurations) 






enum _tpm_pwm_level_select

TPM PWM output pulse mode: high-true, low-true or no output. 

Note
When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output level. In this case, the channel must be closed to close the PWM output. 

Values:


enumerator kTPM_HighTrue

High true pulses 




enumerator kTPM_LowTrue

Low true pulses 






enum _tpm_pwm_pause_level_select

TPM PWM output when first enabled or paused: set or clear. 
Values:


enumerator kTPM_ClearOnPause

Clear Output when counter first enabled or paused. 




enumerator kTPM_SetOnPause

Set Output when counter first enabled or paused. 






enum _tpm_chnl_control_bit_mask

List of TPM channel modes and level control bit mask. 
Values:


enumerator kTPM_ChnlELSnAMask

Channel ELSA bit mask. 




enumerator kTPM_ChnlELSnBMask

Channel ELSB bit mask. 




enumerator kTPM_ChnlMSAMask

Channel MSA bit mask. 




enumerator kTPM_ChnlMSBMask

Channel MSB bit mask. 






enum _tpm_trigger_select

Trigger sources available. 
This is used for both internal & external trigger sources (external trigger sources available in certain SoC’s)

Note
The actual trigger sources available is SoC-specific. 

Values:


enumerator kTPM_Trigger_Select_0





enumerator kTPM_Trigger_Select_1





enumerator kTPM_Trigger_Select_2





enumerator kTPM_Trigger_Select_3





enumerator kTPM_Trigger_Select_4





enumerator kTPM_Trigger_Select_5





enumerator kTPM_Trigger_Select_6





enumerator kTPM_Trigger_Select_7





enumerator kTPM_Trigger_Select_8





enumerator kTPM_Trigger_Select_9





enumerator kTPM_Trigger_Select_10





enumerator kTPM_Trigger_Select_11





enumerator kTPM_Trigger_Select_12





enumerator kTPM_Trigger_Select_13





enumerator kTPM_Trigger_Select_14





enumerator kTPM_Trigger_Select_15







enum _tpm_trigger_source

Trigger source options available. 

Note
This selection is available only on some SoC’s. For SoC’s without this selection, the only trigger source available is internal triger. 

Values:


enumerator kTPM_TriggerSource_External

Use external trigger input 




enumerator kTPM_TriggerSource_Internal

Use internal trigger (channel pin input capture) 






enum _tpm_ext_trigger_polarity

External trigger source polarity. 

Note
Selects the polarity of the external trigger source. 

Values:


enumerator kTPM_ExtTrigger_Active_High

External trigger input is active high 




enumerator kTPM_ExtTrigger_Active_Low

External trigger input is active low 






enum _tpm_output_compare_mode

TPM output compare modes. 
Values:


enumerator kTPM_NoOutputSignal

No channel output when counter reaches CnV 




enumerator kTPM_ToggleOnMatch

Toggle output 




enumerator kTPM_ClearOnMatch

Clear output 




enumerator kTPM_SetOnMatch

Set output 




enumerator kTPM_HighPulseOutput

Pulse output high 




enumerator kTPM_LowPulseOutput

Pulse output low 






enum _tpm_input_capture_edge

TPM input capture edge. 
Values:


enumerator kTPM_RisingEdge

Capture on rising edge only 




enumerator kTPM_FallingEdge

Capture on falling edge only 




enumerator kTPM_RiseAndFallEdge

Capture on rising or falling edge 






enum _tpm_quad_decode_mode

TPM quadrature decode modes. 

Note
This mode is available only on some SoC’s. 

Values:


enumerator kTPM_QuadPhaseEncode

Phase A and Phase B encoding mode 




enumerator kTPM_QuadCountAndDir

Count and direction encoding mode 






enum _tpm_phase_polarity

TPM quadrature phase polarities. 
Values:


enumerator kTPM_QuadPhaseNormal

Phase input signal is not inverted 




enumerator kTPM_QuadPhaseInvert

Phase input signal is inverted 






enum _tpm_clock_source

TPM clock source selection. 
Values:


enumerator kTPM_SystemClock

System clock 




enumerator kTPM_ExternalClock

External TPM_EXTCLK pin clock 




enumerator kTPM_ExternalInputTriggerClock

Selected external input trigger clock 






enum _tpm_clock_prescale

TPM prescale value selection for the clock source. 
Values:


enumerator kTPM_Prescale_Divide_1

Divide by 1 




enumerator kTPM_Prescale_Divide_2

Divide by 2 




enumerator kTPM_Prescale_Divide_4

Divide by 4 




enumerator kTPM_Prescale_Divide_8

Divide by 8 




enumerator kTPM_Prescale_Divide_16

Divide by 16 




enumerator kTPM_Prescale_Divide_32

Divide by 32 




enumerator kTPM_Prescale_Divide_64

Divide by 64 




enumerator kTPM_Prescale_Divide_128

Divide by 128 






enum _tpm_interrupt_enable

List of TPM interrupts. 
Values:


enumerator kTPM_Chnl0InterruptEnable

Channel 0 interrupt. 




enumerator kTPM_Chnl1InterruptEnable

Channel 1 interrupt. 




enumerator kTPM_Chnl2InterruptEnable

Channel 2 interrupt. 




enumerator kTPM_Chnl3InterruptEnable

Channel 3 interrupt. 




enumerator kTPM_Chnl4InterruptEnable

Channel 4 interrupt. 




enumerator kTPM_Chnl5InterruptEnable

Channel 5 interrupt. 




enumerator kTPM_Chnl6InterruptEnable

Channel 6 interrupt. 




enumerator kTPM_Chnl7InterruptEnable

Channel 7 interrupt. 




enumerator kTPM_TimeOverflowInterruptEnable

Time overflow interrupt. 






enum _tpm_status_flags

List of TPM flags. 
Values:


enumerator kTPM_Chnl0Flag

Channel 0 flag 




enumerator kTPM_Chnl1Flag

Channel 1 flag 




enumerator kTPM_Chnl2Flag

Channel 2 flag 




enumerator kTPM_Chnl3Flag

Channel 3 flag 




enumerator kTPM_Chnl4Flag

Channel 4 flag 




enumerator kTPM_Chnl5Flag

Channel 5 flag 




enumerator kTPM_Chnl6Flag

Channel 6 flag 




enumerator kTPM_Chnl7Flag

Channel 7 flag 




enumerator kTPM_TimeOverflowFlag

Time overflow flag 






typedef enum _tpm_chnl tpm_chnl_t

List of TPM channels. 

Note
Actual number of available channels is SoC dependent 





typedef enum _tpm_pwm_mode tpm_pwm_mode_t

TPM PWM operation modes. 




typedef enum _tpm_pwm_level_select tpm_pwm_level_select_t

TPM PWM output pulse mode: high-true, low-true or no output. 

Note
When the TPM has PWM pause level select feature, the PWM output cannot be turned off by selecting the output level. In this case, the channel must be closed to close the PWM output. 





typedef enum _tpm_pwm_pause_level_select tpm_pwm_pause_level_select_t

TPM PWM output when first enabled or paused: set or clear. 




typedef enum _tpm_chnl_control_bit_mask tpm_chnl_control_bit_mask_t

List of TPM channel modes and level control bit mask. 




typedef struct _tpm_chnl_pwm_signal_param tpm_chnl_pwm_signal_param_t

Options to configure a TPM channel’s PWM signal. 




typedef enum _tpm_trigger_select tpm_trigger_select_t

Trigger sources available. 
This is used for both internal & external trigger sources (external trigger sources available in certain SoC’s)

Note
The actual trigger sources available is SoC-specific. 





typedef enum _tpm_trigger_source tpm_trigger_source_t

Trigger source options available. 

Note
This selection is available only on some SoC’s. For SoC’s without this selection, the only trigger source available is internal triger. 





typedef enum _tpm_ext_trigger_polarity tpm_ext_trigger_polarity_t

External trigger source polarity. 

Note
Selects the polarity of the external trigger source. 





typedef enum _tpm_output_compare_mode tpm_output_compare_mode_t

TPM output compare modes. 




typedef enum _tpm_input_capture_edge tpm_input_capture_edge_t

TPM input capture edge. 




typedef struct _tpm_dual_edge_capture_param tpm_dual_edge_capture_param_t

TPM dual edge capture parameters. 

Note
This mode is available only on some SoC’s. 





typedef enum _tpm_quad_decode_mode tpm_quad_decode_mode_t

TPM quadrature decode modes. 

Note
This mode is available only on some SoC’s. 





typedef enum _tpm_phase_polarity tpm_phase_polarity_t

TPM quadrature phase polarities. 




typedef struct _tpm_phase_param tpm_phase_params_t

TPM quadrature decode phase parameters. 




typedef enum _tpm_clock_source tpm_clock_source_t

TPM clock source selection. 




typedef enum _tpm_clock_prescale tpm_clock_prescale_t

TPM prescale value selection for the clock source. 




typedef struct _tpm_config tpm_config_t

TPM config structure. 
This structure holds the configuration settings for the TPM peripheral. To initialize this structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 




typedef enum _tpm_interrupt_enable tpm_interrupt_enable_t

List of TPM interrupts. 




typedef enum _tpm_status_flags tpm_status_flags_t

List of TPM flags. 




typedef void (*tpm_callback_t)(TPM_Type *base)

TPM callback function pointer. 

Param base:
TPM peripheral base address. 






TPM_TIMEOUT

Max loops to wait for writing register. 
When writing MOD CnV CnSC and SC register, driver will wait until register is updated. This parameter defines how many loops to check completion before return timeout. If defined as 0, driver will wait forever until completion. 




TPM_MAX_COUNTER_VALUE(x)

Help macro to get the max counter value. 




struct _tpm_chnl_pwm_signal_param


#include <fsl_tpm.h>
Options to configure a TPM channel’s PWM signal. 

Public Members


tpm_chnl_t chnlNumber

TPM channel to configure. In combined mode (available in some SoC’s), this represents the channel pair number 




tpm_pwm_pause_level_select_t pauseLevel

PWM output level when counter first enabled or paused 




tpm_pwm_level_select_t level

PWM output active level select 




uint8_t dutyCyclePercent

PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle) 




uint8_t firstEdgeDelayPercent

Used only in combined PWM mode to generate asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure, leave as 0. Should be specified as percentage of the PWM period, (dutyCyclePercent + firstEdgeDelayPercent) value should be not greate than 100. 




bool enableComplementary

Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals; 




tpm_pwm_pause_level_select_t secPauseLevel

Used only in combined PWM mode. Define the second channel output level when counter first enabled or paused 




uint8_t deadTimeValue[2]

The dead time value for channel n and n+1 in combined complementary PWM mode. Deadtime insertion is disabled when this value is zero, otherwise deadtime insertion for channel n/n+1 is configured as (deadTimeValue * 4) clock cycles. deadTimeValue’s available range is 0 ~ 15. 







struct _tpm_dual_edge_capture_param


#include <fsl_tpm.h>
TPM dual edge capture parameters. 

Note
This mode is available only on some SoC’s. 


Public Members


bool enableSwap

true: Use channel n+1 input, channel n input is ignored; false: Use channel n input, channel n+1 input is ignored 




tpm_input_capture_edge_t currChanEdgeMode

Input capture edge select for channel n 




tpm_input_capture_edge_t nextChanEdgeMode

Input capture edge select for channel n+1 







struct _tpm_phase_param


#include <fsl_tpm.h>
TPM quadrature decode phase parameters. 

Public Members


uint32_t phaseFilterVal

Filter value, filter is disabled when the value is zero 




tpm_phase_polarity_t phasePolarity

Phase polarity 







struct _tpm_config


#include <fsl_tpm.h>
TPM config structure. 
This structure holds the configuration settings for the TPM peripheral. To initialize this structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a pointer to your config structure instance.
The config struct can be made const so it resides in flash 

Public Members


tpm_clock_prescale_t prescale

Select TPM clock prescale value 




bool useGlobalTimeBase

true: The TPM channels use an external global time base (the local counter still use for generate overflow interrupt and DMA request); false: All TPM channels use the local counter as their timebase 




bool syncGlobalTimeBase

true: The TPM counter is synchronized to the global time base; false: disabled 




tpm_trigger_select_t triggerSelect

Input trigger to use for controlling the counter operation 




tpm_trigger_source_t triggerSource

Decides if we use external or internal trigger. 




tpm_ext_trigger_polarity_t extTriggerPolarity

when using external trigger source, need selects the polarity of it. 




bool enableDoze

true: TPM counter is paused in doze mode; false: TPM counter continues in doze mode 




bool enableDebugMode

true: TPM counter continues in debug mode; false: TPM counter is paused in debug mode 




bool enableReloadOnTrigger

true: TPM counter is reloaded on trigger; false: TPM counter not reloaded 




bool enableStopOnOverflow

true: TPM counter stops after overflow; false: TPM counter continues running after overflow 




bool enableStartOnTrigger

true: TPM counter only starts when a trigger is detected; false: TPM counter starts immediately 




bool enablePauseOnTrigger

true: TPM counter will pause while trigger remains asserted; false: TPM counter continues running 




uint8_t chnlPolarity

Defines the input/output polarity of the channels in POL register 







TRDC: Trusted Resource Domain Controller#


void TRDC_Init(TRDC_Type *base)

Initializes the TRDC module. 
This function enables the TRDC clock.

Parameters:

base – TRDC peripheral base address. 







void TRDC_Deinit(TRDC_Type *base)

De-initializes the TRDC module. 
This function disables the TRDC clock.

Parameters:

base – TRDC peripheral base address. 







static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)

Gets the domain ID of the current bus master. 

Parameters:

base – TRDC peripheral base address. 


Returns:
Domain ID of current bus master. 






void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config)

Gets the TRDC hardware configuration. 
This function gets the TRDC hardware configurations, including number of bus masters, number of domains, number of MRCs and number of PACs.

Parameters:

base – TRDC peripheral base address. 
config – Pointer to the structure to get the configuration. 







static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)

Sets the TRDC DAC(Domain Assignment Controllers) global valid. 
Once enabled, it will remain enabled until next reset.

Parameters:

base – TRDC peripheral base address. 







static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum)

Locks the bus master domain assignment register. 
This function locks the master domain assignment. After it is locked, the register can’t be changed until next reset.

Parameters:

base – TRDC peripheral base address. 
master – Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance. 
regNum – Which register to configure, processor master can have more than one register for the MDAC configuration. 
assignIndex – Which assignment register to lock. 







static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid)

Sets the master domain assignment as valid or invalid. 
This function sets the master domain assignment as valid or invalid.

Parameters:

base – TRDC peripheral base address. 
master – Which master to configure. 
regNum – Which register to configure, processor master can have more than one register for the MDAC configuration. 
assignIndex – Index for the domain assignment register. 
valid – True to set valid, false to set invalid. 







void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment)

Gets the default master domain assignment for the processor bus master. 
This function gets the default master domain assignment for the processor bus master. It should only be used for the processor bus masters, such as CORE0. This function sets the assignment as follows:
assignment->domainId           = 0U;
assignment->domainIdSelect     = kTRDC_DidMda;
assignment->lock               = 0U;



Parameters:

domainAssignment – Pointer to the assignment structure. 







void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment)

Gets the default master domain assignment for non-processor bus master. 
This function gets the default master domain assignment for non-processor bus master. It should only be used for the non-processor bus masters, such as DMA. This function sets the assignment as follows:
assignment->domainId            = 0U;
assignment->privilegeAttr       = kTRDC_ForceUser;
assignment->secureAttr       = kTRDC_ForceSecure;
assignment->bypassDomainId      = 0U;
assignment->lock                = 0U;



Parameters:

domainAssignment – Pointer to the assignment structure. 







void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum, const trdc_processor_domain_assignment_t *domainAssignment)

Sets the processor bus master domain assignment. 
This function sets the processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to set.
Example: Set domain assignment for core 0.
trdc_processor_domain_assignment_t processorAssignment;

TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);

processorAssignment.domainId = 0;
processorAssignment.xxx      = xxx;
TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);



Parameters:

base – TRDC peripheral base address. 
master – Which master to configure, refer to trdc_master_t in processor header file. 
regNum – Which register to configure, processor master can have more than one register for the MDAC configuration. 
domainAssignment – Pointer to the assignment structure. 







void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, uint8_t master, const trdc_non_processor_domain_assignment_t *domainAssignment)

Sets the non-processor bus master domain assignment. 
This function sets the non-processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to set.
Example: Set domain assignment for DMA0. 
trdc_non_processor_domain_assignment_t nonProcessorAssignment;

TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
nonProcessorAssignment.domainId = 1;
nonProcessorAssignment.xxx      = xxx;

TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);




Parameters:

base – TRDC peripheral base address. 
master – Which master to configure, refer to trdc_master_t in processor header file. 
domainAssignment – Pointer to the assignment structure. 







static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base)

Gets the bit map of the bus master(s) that is(are) sourcing a PID register. 
This function sets the non-processor master domain assignment as valid.

Parameters:

base – TRDC peripheral base address. 


Returns:
the bit map of the master(s). Bit 1 sets indicates bus master 1. 






void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig)

Sets the current Process identifier(PID) for processor core. 
Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. Secure privileged software saves and restores the PID as part of any context switch. This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality.

Parameters:

base – TRDC peripheral base address. 
master – Which processor master to configure, refer to trdc_master_t in processor header file. 
pidConfig – Pointer to the configuration structure. 







void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration)

Gets the default IDAU(Implementation-Defined Attribution Unit) configuration. 
config->lockSecureVTOR    = false;
config->lockNonsecureVTOR = false;
config->lockSecureMPU     = false;
config->lockNonsecureMPU  = false;
config->lockSAU           = false;



Parameters:

domainAssignment – Pointer to the configuration structure. 







void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration)

Sets the IDAU(Implementation-Defined Attribution Unit) control configuration. 
Example: Lock the secure and non-secure MPU registers.
trdc_idau_config_t idauConfiguration;

TRDC_GetDefaultIDAUConfig(&idauConfiguration);

idauConfiguration.lockSecureMPU = true;
idauConfiguration.lockNonsecureMPU      = true;
TRDC_SetIDAU(TRDC, &idauConfiguration);



Parameters:

base – TRDC peripheral base address. 
domainAssignment – Pointer to the configuration structure. 







static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)

Enables/disables the FLW(flash logical window) function. 

Parameters:

base – TRDC peripheral base address. 
enable – True to enable, false to disable. 







static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)

Locks FLW registers. Once locked the registers can noy be updated until next reset. 

Parameters:

base – TRDC peripheral base address. 







static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)

Gets the FLW physical base address. 

Parameters:

base – TRDC peripheral base address. 


Returns:
Physical address of the FLW function. 






static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)

Sets the FLW size. 

Parameters:

base – TRDC peripheral base address. 
size – Size of the FLW in unit of 32k bytes. 







void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration)

Gets the default FLW(Flsh Logical Window) configuration. 
config->blockCount    = false;
config->arrayBaseAddr = false;
config->lock     = false;
config->enable  = false;



Parameters:

flwConfiguration – Pointer to the configuration structure. 







void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration)

Sets the FLW function’s configuration. 
trdc_flw_config_t flwConfiguration;

TRDC_GetDefaultIDAUConfig(&flwConfiguration);

flwConfiguration.blockCount = 32U;
flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
TRDC_SetIDAU(TRDC, &flwConfiguration);



Parameters:

base – TRDC peripheral base address. 
flwConfiguration – Pointer to the configuration structure. 







status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error)

Gets and clears the first domain error of the current domain. 
This function gets the first access violation information for the current domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.

Parameters:

base – TRDC peripheral base address. 
error – Pointer to the error information. 


Returns:
If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData. 






status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId)

Gets and clears the first domain error of the specific domain. 
This function gets the first access violation information for the specific domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.

Parameters:

base – TRDC peripheral base address. 
error – Pointer to the error information. 
domainId – The error of which domain to get and clear. 


Returns:
If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData. 






static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)

Sets the TRDC MRC(Memory Region Checkers) global valid. 
Once enabled, it will remain enabled until next reset.

Parameters:

base – TRDC peripheral base address. 







static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)

Gets the TRDC MRC(Memory Region Checkers) region number valid. 

Parameters:

base – TRDC peripheral base address. 


Returns:
the region number of the given MRC instance 






void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mrcIdx, uint8_t regIdx)

Sets the memory access configuration for one of the access control register of one MRC. 
Example: Enable the secure operations and lock the configuration for MRC0 region 1.
trdc_memory_access_control_config_t config;

config.securePrivX = true;
config.securePrivW = true;
config.securePrivR = true;
config.lock = true;
TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);



Parameters:

base – TRDC peripheral base address. 
config – Pointer to the configuration structure. 
mrcIdx – MRC index. 
regIdx – Register number. 







void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable)

Enables the update of the selected domians. 
After the domians’ update are enabled, their regions’ NSE bits can be set or clear.

Parameters:

base – TRDC peripheral base address. 
mrcIdx – MRC index. 
domianMask – Bit mask of the domains to be enabled. 
enable – True to enable, false to disable. 







void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)

Sets the NSE bits of the selected regions for domains. 
This function sets the NSE bits for the selected regions for the domains whose update are enabled.

Parameters:

base – TRDC peripheral base address. 
mrcIdx – MRC index. 
regionMask – Bit mask of the regions whose NSE bits to set. 







void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)

Clears the NSE bits of the selected regions for domains. 
This function clears the NSE bits for the selected regions for the domains whose update are enabled.

Parameters:

base – TRDC peripheral base address. 
mrcIdx – MRC index. 
regionMask – Bit mask of the regions whose NSE bits to clear. 







void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask)

Clears the NSE bits for all the regions of the selected domains. 
This function clears the NSE bits for all regions of selected domains whose update are enabled.

Parameters:

base – TRDC peripheral base address. 
mrcIdx – MRC index. 
domainMask – Bit mask of the domians whose NSE bits to clear. 







void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config)

Sets the configuration for one of the region descriptor per domain per MRC instnce. 
This function sets the configuration for one of the region descriptor, including the start and end address of the region, memory access control policy and valid.

Parameters:

base – TRDC peripheral base address. 
config – Pointer to region descriptor configuration structure. 







static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)

Sets the TRDC MBC(Memory Block Checkers) global valid. 
Once enabled, it will remain enabled until next reset.

Parameters:

base – TRDC peripheral base address. 







void TRDC_GetMbcHardwareConfig(TRDC_Type *base, trdc_slave_memory_hardware_config_t *config, uint8_t mbcIdx, uint8_t slvIdx)

Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker). 

Parameters:

base – TRDC peripheral base address. 
config – Pointer to the structure to get the configuration. 
mbcIdx – MBC number. 
slvIdx – Slave number. 







void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx)

Sets the NSR update configuration for one of the MBC instance. 
After set the NSE configuration, the configured memory area can be updateby NSE set/clear.

Parameters:

base – TRDC peripheral base address. 
config – Pointer to NSE update configuration structure. 
mbcIdx – MBC index. 







void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)

Sets the NSE bits of the selected configuration words according to NSE update configuration. 
This function sets the NSE bits of the word for the configured regio, memory.

Parameters:

base – TRDC peripheral base address. 
mbcIdx – MBC index. 
bitMask – Mask of the bits whose NSE bits to set. 







void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)

Clears the NSE bits of the selected configuration words according to NSE update configuration. 
This function sets the NSE bits of the word for the configured regio, memory.

Parameters:

base – TRDC peripheral base address. 
mbcIdx – MBC index. 
bitMask – Mask of the bits whose NSE bits to clear. 







void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave)

Clears all configuration words’ NSE bits of the selected domain and memory. 

Parameters:

base – TRDC peripheral base address. 
mbcIdx – MBC index. 
domainMask – Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2. 
slaveMask – Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1’s NSE bits. 







void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mbcIdx, uint8_t rgdIdx)

Sets the memory access configuration for one of the region descriptor of one MBC. 
Example: Enable the secure operations and lock the configuration for MRC0 region 1.
trdc_memory_access_control_config_t config;

config.securePrivX = true;
config.securePrivW = true;
config.securePrivR = true;
config.lock = true;
TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);



Parameters:

base – TRDC peripheral base address. 
config – Pointer to the configuration structure. 
mbcIdx – MBC index. 
rgdIdx – Region descriptor number. 







void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config)

Sets the configuration for one of the memory block per domain per MBC instnce. 
This function sets the configuration for one of the memory block, including the memory access control policy and nse enable.

Parameters:

base – TRDC peripheral base address. 
config – Pointer to memory block configuration structure. 







enum _trdc_did_sel

TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation. 
Values:


enumerator kTRDC_DidMda

Use MDAn[2:0] as DID. 




enumerator kTRDC_DidInput

Use the input DID (DID_in) as DID. 




enumerator kTRDC_DidMdaAndInput

Use MDAn[2] concatenated with DID_in[1:0] as DID. 




enumerator kTRDC_DidReserved

Reserved. 






enum _trdc_secure_attr

TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment. 
Values:


enumerator kTRDC_ForceSecure

Force the bus attribute for this master to secure. 




enumerator kTRDC_ForceNonSecure

Force the bus attribute for this master to non-secure. 




enumerator kTRDC_MasterSecure

Use the bus master’s secure/nonsecure attribute directly. 




enumerator kTRDC_MasterSecure1

Use the bus master’s secure/nonsecure attribute directly. 






enum _trdc_pid_domain_hit_config

The configuration of domain hit evaluation of PID. 
Values:


enumerator kTRDC_pidDomainHitNone0

No PID is included in the domain hit evaluation. 




enumerator kTRDC_pidDomainHitNone1

No PID is included in the domain hit evaluation. 




enumerator kTRDC_pidDomainHitInclusive

The PID is included in the domain hit evaluation when (PID & ~PIDM). 




enumerator kTRDC_pidDomainHitExclusive

The PID is included in the domain hit evaluation when ~(PID & ~PIDM). 






enum _trdc_privilege_attr

TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment. 
Values:


enumerator kTRDC_ForceUser

Force the bus attribute for this master to user. 




enumerator kTRDC_ForcePrivilege

Force the bus attribute for this master to privileged. 




enumerator kTRDC_MasterPrivilege

Use the bus master’s attribute directly. 




enumerator kTRDC_MasterPrivilege1

Use the bus master’s attribute directly. 






enum _trdc_pid_lock

PID lock configuration. 
Values:


enumerator kTRDC_PidUnlocked0

The PID value can be updated by any secure priviledged write. 




enumerator kTRDC_PidUnlocked1

The PID value can be updated by any secure priviledged write. 




enumerator kTRDC_PidUnlocked2

The PID value can be updated by any secure priviledged write from the bus master that first configured this register. 




enumerator kTRDC_PidLocked

The PID value is locked until next reset. 






enum _trdc_controller

TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count. 
Values:


enumerator kTRDC_MemBlockController0

Memory block checker 0. 




enumerator kTRDC_MemBlockController1

Memory block checker 1. 




enumerator kTRDC_MemBlockController2

Memory block checker 2. 




enumerator kTRDC_MemBlockController3

Memory block checker 3. 




enumerator kTRDC_MemRegionChecker0

Memory region checker 0. 




enumerator kTRDC_MemRegionChecker1

Memory region checker 1. 




enumerator kTRDC_MemRegionChecker2

Memory region checker 2. 




enumerator kTRDC_MemRegionChecker3

Memory region checker 3. 




enumerator kTRDC_MemRegionChecker4

Memory region checker 4. 




enumerator kTRDC_MemRegionChecker5

Memory region checker 5. 




enumerator kTRDC_MemRegionChecker6

Memory region checker 6. 






enum _trdc_error_state

TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST]. 
Values:


enumerator kTRDC_ErrorStateNone

No access violation detected. 




enumerator kTRDC_ErrorStateNone1

No access violation detected. 




enumerator kTRDC_ErrorStateSingle

Single access violation detected. 




enumerator kTRDC_ErrorStateMulti

Multiple access violation detected. 






enum _trdc_error_attr

TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR]. 
Values:


enumerator kTRDC_ErrorSecureUserInst

Secure user mode, instruction fetch access. 




enumerator kTRDC_ErrorSecureUserData

Secure user mode, data access. 




enumerator kTRDC_ErrorSecurePrivilegeInst

Secure privileged mode, instruction fetch access. 




enumerator kTRDC_ErrorSecurePrivilegeData

Secure privileged mode, data access. 




enumerator kTRDC_ErrorNonSecureUserInst

NonSecure user mode, instruction fetch access. 




enumerator kTRDC_ErrorNonSecureUserData

NonSecure user mode, data access. 




enumerator kTRDC_ErrorNonSecurePrivilegeInst

NonSecure privileged mode, instruction fetch access. 




enumerator kTRDC_ErrorNonSecurePrivilegeData

NonSecure privileged mode, data access. 






enum _trdc_error_type

TRDC domain error access type definition TRDC_DERR_W1_n[ERW]. 
Values:


enumerator kTRDC_ErrorTypeRead

Error occurs on read reference. 




enumerator kTRDC_ErrorTypeWrite

Error occurs on write reference. 






enum _trdc_region_descriptor

The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions. 
Values:


enumerator kTRDC_RegionDescriptor0

Region descriptor 0. 




enumerator kTRDC_RegionDescriptor1

Region descriptor 1. 




enumerator kTRDC_RegionDescriptor2

Region descriptor 2. 




enumerator kTRDC_RegionDescriptor3

Region descriptor 3. 




enumerator kTRDC_RegionDescriptor4

Region descriptor 4. 




enumerator kTRDC_RegionDescriptor5

Region descriptor 5. 




enumerator kTRDC_RegionDescriptor6

Region descriptor 6. 




enumerator kTRDC_RegionDescriptor7

Region descriptor 7. 




enumerator kTRDC_RegionDescriptor8

Region descriptor 8. 




enumerator kTRDC_RegionDescriptor9

Region descriptor 9. 




enumerator kTRDC_RegionDescriptor10

Region descriptor 10. 




enumerator kTRDC_RegionDescriptor11

Region descriptor 11. 




enumerator kTRDC_RegionDescriptor12

Region descriptor 12. 




enumerator kTRDC_RegionDescriptor13

Region descriptor 13. 




enumerator kTRDC_RegionDescriptor14

Region descriptor 14. 




enumerator kTRDC_RegionDescriptor15

Region descriptor 15. 






enum _trdc_MRC_domain

The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or several domains. 
Values:


enumerator kTRDC_MrcDomain0

Domain 0. 




enumerator kTRDC_MrcDomain1

Domain 1. 




enumerator kTRDC_MrcDomain2

Domain 2. 




enumerator kTRDC_MrcDomain3

Domain 3. 




enumerator kTRDC_MrcDomain4

Domain 4. 




enumerator kTRDC_MrcDomain5

Domain 5. 




enumerator kTRDC_MrcDomain6

Domain 6. 




enumerator kTRDC_MrcDomain7

Domain 7. 




enumerator kTRDC_MrcDomain8

Domain 8. 




enumerator kTRDC_MrcDomain9

Domain 9. 




enumerator kTRDC_MrcDomain10

Domain 10. 




enumerator kTRDC_MrcDomain11

Domain 11. 




enumerator kTRDC_MrcDomain12

Domain 12. 




enumerator kTRDC_MrcDomain13

Domain 13. 




enumerator kTRDC_MrcDomain14

Domain 14. 




enumerator kTRDC_MrcDomain15

Domain 15. 






enum _trdc_MBC_domain

The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several domains. 
Values:


enumerator kTRDC_MbcDomain0

Domain 0. 




enumerator kTRDC_MbcDomain1

Domain 1. 




enumerator kTRDC_MbcDomain2

Domain 2. 




enumerator kTRDC_MbcDomain3

Domain 3. 




enumerator kTRDC_MbcDomain4

Domain 4. 




enumerator kTRDC_MbcDomain5

Domain 5. 




enumerator kTRDC_MbcDomain6

Domain 6. 




enumerator kTRDC_MbcDomain7

Domain 7. 






enum _trdc_MBC_memory

The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several memory block. 
Values:


enumerator kTRDC_MbcSlaveMemory0

Memory 0. 




enumerator kTRDC_MbcSlaveMemory1

Memory 1. 




enumerator kTRDC_MbcSlaveMemory2

Memory 2. 




enumerator kTRDC_MbcSlaveMemory3

Memory 3. 






enum _trdc_MBC_bit

The MBC bit enumeration, used to form a mask to set/clear configured words’ NSE. 
Values:


enumerator kTRDC_MbcBit0

Bit 0. 




enumerator kTRDC_MbcBit1

Bit 1. 




enumerator kTRDC_MbcBit2

Bit 2. 




enumerator kTRDC_MbcBit3

Bit 3. 




enumerator kTRDC_MbcBit4

Bit 4. 




enumerator kTRDC_MbcBit5

Bit 5. 




enumerator kTRDC_MbcBit6

Bit 6. 




enumerator kTRDC_MbcBit7

Bit 7. 




enumerator kTRDC_MbcBit8

Bit 8. 




enumerator kTRDC_MbcBit9

Bit 9. 




enumerator kTRDC_MbcBit10

Bit 10. 




enumerator kTRDC_MbcBit11

Bit 11. 




enumerator kTRDC_MbcBit12

Bit 12. 




enumerator kTRDC_MbcBit13

Bit 13. 




enumerator kTRDC_MbcBit14

Bit 14. 




enumerator kTRDC_MbcBit15

Bit 15. 




enumerator kTRDC_MbcBit16

Bit 16. 




enumerator kTRDC_MbcBit17

Bit 17. 




enumerator kTRDC_MbcBit18

Bit 18. 




enumerator kTRDC_MbcBit19

Bit 19. 




enumerator kTRDC_MbcBit20

Bit 20. 




enumerator kTRDC_MbcBit21

Bit 21. 




enumerator kTRDC_MbcBit22

Bit 22. 




enumerator kTRDC_MbcBit23

Bit 23. 




enumerator kTRDC_MbcBit24

Bit 24. 




enumerator kTRDC_MbcBit25

Bit 25. 




enumerator kTRDC_MbcBit26

Bit 26. 




enumerator kTRDC_MbcBit27

Bit 27. 




enumerator kTRDC_MbcBit28

Bit 28. 




enumerator kTRDC_MbcBit29

Bit 29. 




enumerator kTRDC_MbcBit30

Bit 30. 




enumerator kTRDC_MbcBit31

Bit 31. 






typedef struct _trdc_hardware_config trdc_hardware_config_t

TRDC hardware configuration. 




typedef struct _trdc_slave_memory_hardware_config trdc_slave_memory_hardware_config_t

Hardware configuration of the two slave memories within each MBC(memory block checker). 




typedef enum _trdc_did_sel trdc_did_sel_t

TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation. 




typedef enum _trdc_secure_attr trdc_secure_attr_t

TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment. 




typedef enum _trdc_pid_domain_hit_config trdc_pid_domain_hit_config_t

The configuration of domain hit evaluation of PID. 




typedef struct _trdc_processor_domain_assignment trdc_processor_domain_assignment_t

Domain assignment for the processor bus master. 




typedef enum _trdc_privilege_attr trdc_privilege_attr_t

TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment. 




typedef struct _trdc_non_processor_domain_assignment trdc_non_processor_domain_assignment_t

Domain assignment for the non-processor bus master. 




typedef enum _trdc_pid_lock trdc_pid_lock_t

PID lock configuration. 




typedef struct _trdc_pid_config trdc_pid_config_t

Process identifier(PID) configuration for processor cores. 




typedef struct _trdc_idau_config trdc_idau_config_t

IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control. 




typedef struct _trdc_flw_config trdc_flw_config_t

FLW(Flash Logical Window) configuration. 




typedef enum _trdc_controller trdc_controller_t

TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count. 




typedef enum _trdc_error_state trdc_error_state_t

TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST]. 




typedef enum _trdc_error_attr trdc_error_attr_t

TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR]. 




typedef enum _trdc_error_type trdc_error_type_t

TRDC domain error access type definition TRDC_DERR_W1_n[ERW]. 




typedef struct _trdc_domain_error trdc_domain_error_t

TRDC domain error definition. 




typedef struct _trdc_memory_access_control_config trdc_memory_access_control_config_t

Memory access control configuration for MBC/MRC. 




typedef struct _trdc_mrc_region_descriptor_config trdc_mrc_region_descriptor_config_t

The configuration of each region descriptor per domain per MRC instance. 




typedef struct _trdc_mbc_nse_update_config trdc_mbc_nse_update_config_t

The configuration of MBC NSE update. 




typedef struct _trdc_mbc_memory_block_config trdc_mbc_memory_block_config_t

The configuration of each memory block per domain per MBC instance. 




FSL_TRDC_DRIVER_VERSION





struct _trdc_hardware_config


#include <fsl_trdc.h>
TRDC hardware configuration. 

Public Members


uint8_t masterNumber

Number of bus masters. 




uint8_t domainNumber

Number of domains. 




uint8_t mbcNumber

Number of MBCs. 




uint8_t mrcNumber

Number of MRCs. 







struct _trdc_slave_memory_hardware_config


#include <fsl_trdc.h>
Hardware configuration of the two slave memories within each MBC(memory block checker). 

Public Members


uint32_t blockNum

Number of blocks. 




uint32_t blockSize

Block size. 







struct _trdc_processor_domain_assignment


#include <fsl_trdc.h>
Domain assignment for the processor bus master. 

Public Members


uint32_t domainId

Domain ID. 




uint32_t domainIdSelect

Domain ID select method, see trdc_did_sel_t. 




uint32_t pidDomainHitConfig

The configuration of the domain hit evaluation for PID, see trdc_pid_domain_hit_config_t. 




uint32_t pidMask

The mask combined with PID, so multiple PID can be included as part of the domain hit determination. Set to 0 to disable. 




uint32_t secureAttr

Secure attribute, see trdc_secure_attr_t. 




uint32_t pid

The process identifier, combined with pidMask to form the domain hit determination. 




uint32_t __pad0__

Reserved. 




uint32_t lock

Lock the register. 




uint32_t __pad1__

Reserved. 







struct _trdc_non_processor_domain_assignment


#include <fsl_trdc.h>
Domain assignment for the non-processor bus master. 

Public Members


uint32_t domainId

Domain ID. 




uint32_t privilegeAttr

Privileged attribute, see trdc_privilege_attr_t. 




uint32_t secureAttr

Secure attribute, see trdc_secure_attr_t. 




uint32_t bypassDomainId

Bypass domain ID. 




uint32_t __pad0__

Reserved. 




uint32_t lock

Lock the register. 




uint32_t __pad1__

Reserved. 







struct _trdc_pid_config


#include <fsl_trdc.h>
Process identifier(PID) configuration for processor cores. 

Public Members


uint32_t pid

The process identifier of the executing task. The highest bit can be used to define secure/nonsecure attribute of the task. 




uint32_t __pad0__

Reserved. 




uint32_t lock

How to lock the register, see trdc_pid_lock_t. 




uint32_t __pad1__

Reserved. 







struct _trdc_idau_config


#include <fsl_trdc.h>
IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control. 

Public Members


uint32_t __pad0__

Reserved. 




uint32_t lockSecureVTOR

Disable writes to secure VTOR(Vector Table Offset Register). 




uint32_t lockNonsecureVTOR

Disable writes to non-secure VTOR, Application interrupt and Reset Control Registers. 




uint32_t lockSecureMPU

Disable writes to secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor in Secure state. 




uint32_t lockNonsecureMPU

Disable writes to non-secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor. 




uint32_t lockSAU

Disable writes to SAU(Security Attribution Unit) registers. 




uint32_t __pad1__

Reserved. 







struct _trdc_flw_config


#include <fsl_trdc.h>
FLW(Flash Logical Window) configuration. 

Public Members


uint16_t blockCount

Block count of the Flash Logic Window in 32KByte blocks. 




uint32_t arrayBaseAddr

Flash array base address of the Flash Logical Window. 




bool lock

Disable writes to FLW registers. 




bool enable

Enable FLW function. 







struct _trdc_domain_error


#include <fsl_trdc.h>
TRDC domain error definition. 

Public Members


trdc_controller_t controller

Which controller captured access violation. 




uint32_t address

Access address that generated access violation. 




trdc_error_state_t errorState

Error state. 




trdc_error_attr_t errorAttr

Error attribute. 




trdc_error_type_t errorType

Error type. 




uint8_t errorPort

Error port. 




uint8_t domainId

Domain ID. 




uint8_t slaveMemoryIdx

The slave memory index. Only apply when violation in MBC. 







struct _trdc_memory_access_control_config


#include <fsl_trdc.h>
Memory access control configuration for MBC/MRC. 

Public Members


uint32_t nonsecureUsrX

Allow nonsecure user execute access. 




uint32_t nonsecureUsrW

Allow nonsecure user write access. 




uint32_t nonsecureUsrR

Allow nonsecure user read access. 




uint32_t __pad0__

Reserved. 




uint32_t nonsecurePrivX

Allow nonsecure privilege execute access. 




uint32_t nonsecurePrivW

Allow nonsecure privilege write access. 




uint32_t nonsecurePrivR

Allow nonsecure privilege read access. 




uint32_t __pad1__

Reserved. 




uint32_t secureUsrX

Allow secure user execute access. 




uint32_t secureUsrW

Allow secure user write access. 




uint32_t secureUsrR

Allow secure user read access. 




uint32_t __pad2__

Reserved. 




uint32_t securePrivX

Allownsecure privilege execute access. 




uint32_t securePrivW

Allownsecure privilege write access. 




uint32_t securePrivR

Allownsecure privilege read access. 




uint32_t __pad3__

Reserved. 




uint32_t lock

Lock the configuration until next reset, only apply to access control register 0. 







struct _trdc_mrc_region_descriptor_config


#include <fsl_trdc.h>
The configuration of each region descriptor per domain per MRC instance. 

Public Members


uint8_t memoryAccessControlSelect

Select one of the 8 access control policies for this region, for access cotrol policies see trdc_memory_access_control_config_t. 




uint32_t startAddr

Physical start address. 




bool valid

Lock the register. 




bool nseEnable

Enable non-secure accesses and disable secure accesses. 




uint32_t endAddr

Physical start address. 




uint8_t mrcIdx

The index of the MRC for this configuration to take effect. 




uint8_t domainIdx

The index of the domain for this configuration to take effect. 




uint8_t regionIdx

The index of the region for this configuration to take effect. 







struct _trdc_mbc_nse_update_config


#include <fsl_trdc.h>
The configuration of MBC NSE update. 

Public Members


uint32_t __pad0__

Reserved. 




uint32_t wordIdx

MBC configuration word index to be updated. 




uint32_t __pad1__

Reserved. 




uint32_t memorySelect

Bit mask of the selected memory to be updated. _trdc_MBC_memory. 




uint32_t __pad2__

Reserved. 




uint32_t domianSelect

Bit mask of the selected domain to be updated. _trdc_MBC_domain. 




uint32_t __pad3__

Reserved. 




uint32_t autoIncrement

Whether to increment the word index after current word is updated using this configuration. 







struct _trdc_mbc_memory_block_config


#include <fsl_trdc.h>
The configuration of each memory block per domain per MBC instance. 

Public Members


uint32_t memoryAccessControlSelect

Select one of the 8 access control policies for this memory block, for access cotrol policies see trdc_memory_access_control_config_t. 




uint32_t nseEnable

Enable non-secure accesses and disable secure accesses. 




uint32_t mbcIdx

The index of the MBC for this configuration to take effect. 




uint32_t domainIdx

The index of the domain for this configuration to take effect. 




uint32_t slaveMemoryIdx

The index of the slave memory for this configuration to take effect. 




uint32_t memoryBlockIdx

The index of the memory block for this configuration to take effect. 







Trdc_core#


typedef struct _TRDC_General_Type TRDC_General_Type

TRDC general configuration register definition. 




typedef struct _TRDC_FLW_Type TRDC_FLW_Type

TRDC flash logical control register definition. 




typedef struct _TRDC_DomainError_Type TRDC_DomainError_Type

TRDC domain error register definition. 




typedef struct _TRDC_DomainAssignment_Type TRDC_DomainAssignment_Type

TRDC master domain assignment register definition. 




typedef struct _TRDC_MBC_Type TRDC_MBC_Type

TRDC MBC control register definition. 




typedef struct _TRDC_MRC_Type TRDC_MRC_Type

TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word]. 




TRDC_GENERAL_BASE(base)

TRDC base address convert macro. 




TRDC_FLW_BASE(base)





TRDC_DOMAIN_ERROR_BASE(base)





TRDC_DOMAIN_ASSIGNMENT_BASE(base)





TRDC_MBC_BASE(base, instance)





TRDC_MRC_BASE(base, instance)





struct _TRDC_General_Type


#include <fsl_trdc_core.h>
TRDC general configuration register definition. 

Public Members


__IO uint32_t TRDC_CR
TRDC Register, offset: 0x0 




__I uint32_t TRDC_HWCFG0
TRDC Hardware Configuration Register 0, offset: 0xF0 




__I uint32_t TRDC_HWCFG1
TRDC Hardware Configuration Register 1, offset: 0xF4 




__I uint32_t TRDC_HWCFG2
TRDC Hardware Configuration Register 2, offset: 0xF8 




__I uint32_t TRDC_HWCFG3
TRDC Hardware Configuration Register 3, offset: 0xFC 




__I uint8_t DACFG [8]
Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 




__IO uint32_t TRDC_IDAU_CR
TRDC IDAU Control Register, offset: 0x1C0 







struct _TRDC_FLW_Type


#include <fsl_trdc_core.h>
TRDC flash logical control register definition. 

Public Members


__IO uint32_t TRDC_FLW_CTL
TRDC FLW Control, offset: 0x1E0 




__I uint32_t TRDC_FLW_PBASE
TRDC FLW Physical Base, offset: 0x1E4 




__IO uint32_t TRDC_FLW_ABASE
TRDC FLW Array Base, offset: 0x1E8 




__IO uint32_t TRDC_FLW_BCNT
TRDC FLW Block Count, offset: 0x1EC 







struct _TRDC_DomainError_Type


#include <fsl_trdc_core.h>
TRDC domain error register definition. 

Public Members


__IO uint32_t TRDC_FDID
TRDC Fault Domain ID, offset: 0x1FC 




__I uint32_t TRDC_DERRLOC [16]
TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 







struct _TRDC_DomainAssignment_Type


#include <fsl_trdc_core.h>
TRDC master domain assignment register definition. 

Public Members


__IO uint32_t PID [8]
Process Identifier, array offset: 0x700, array step: 0x4 







struct _TRDC_MBC_Type


#include <fsl_trdc_core.h>
TRDC MBC control register definition. 

Public Members


__I uint32_t MBC_MEM_GLBCFG [4]
MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_NSE_BLK_INDEX
MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 




__O uint32_t MBC_NSE_BLK_SET
MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 




__O uint32_t MBC_NSE_BLK_CLR
MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 




__O uint32_t MBC_NSE_BLK_CLR_ALL
MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 




__IO uint32_t MBC_MEMN_GLBAC [8]
MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W [64]
MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W [16]
MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W [8]
MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4 




__IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W [2]
MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4 







struct _TRDC_MRC_Type


#include <fsl_trdc_core.h>
TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word]. 

Public Members


__I uint32_t MRC_GLBCFG
MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000 




__IO uint32_t MRC_NSE_RGN_INDIRECT
MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000 




__O uint32_t MRC_NSE_RGN_SET
MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000 




__O uint32_t MRC_NSE_RGN_CLR
MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000 




__O uint32_t MRC_NSE_RGN_CLR_ALL
MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000 




__IO uint32_t MRC_GLBAC [8]
MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4 




__IO uint32_t MRC_DOM0_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM0_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000 




__IO uint32_t MRC_DOM1_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14140, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM1_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000 




__IO uint32_t MRC_DOM2_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14240, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM2_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000 




__IO uint32_t MRC_DOM3_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14340, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM3_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000 




__IO uint32_t MRC_DOM4_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14440, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM4_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000 




__IO uint32_t MRC_DOM5_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14540, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM5_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000 




__IO uint32_t MRC_DOM6_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14640, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM6_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000 




__IO uint32_t MRC_DOM7_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14740, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM7_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000 




__IO uint32_t MRC_DOM8_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14840, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM8_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000 




__IO uint32_t MRC_DOM9_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14940, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM9_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000 




__IO uint32_t MRC_DOM10_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM10_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000 




__IO uint32_t MRC_DOM11_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM11_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000 




__IO uint32_t MRC_DOM12_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM12_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000 




__IO uint32_t MRC_DOM13_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM13_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000 




__IO uint32_t MRC_DOM14_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM14_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000 




__IO uint32_t MRC_DOM15_RGD_W [16][2]
MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4 




__IO uint32_t MRC_DOM15_RGD_NSE
MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000 







struct MBC_DERR


Public Members


__I uint32_t W0
MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 




__I uint32_t W1
MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 




__O uint32_t W3
MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 







struct MRC_DERR


Public Members


__I uint32_t W0
MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 




__I uint32_t W1
MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 




__O uint32_t W3
MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 







union __unnamed95__


Public Members


struct _TRDC_DomainAssignment_Type MDA_DFMT0[8]





struct _TRDC_DomainAssignment_Type MDA_DFMT1[8]








struct MDA_DFMT0


Public Members


__IO uint32_t MDA_W_DFMT0 [8]
DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4 







struct MDA_DFMT1


Public Members


__IO uint32_t MDA_W_DFMT1 [1]
DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4 







TSTMR: Timestamp Timer Driver#


void TSTMR_Init(TSTMR_Type *base)

Init TSTMR. 
This function initializes the TSTMR module.

Parameters:

base – TSTMR peripheral base address. 







void TSTMR_Deinit(TSTMR_Type *base)

Deinit TSTMR. 
This function deinitializes the TSTMR module.

Parameters:

base – TSTMR peripheral base address. 







FSL_TSTMR_DRIVER_VERSION

Version 2.1.0 




static inline uint64_t TSTMR_ReadTimeStamp(TSTMR_Type *base)

Reads the time stamp. 
This function reads the low and high registers and returns the 56-bit free running counter value. This can be read by software at any time to determine the software ticks. TSTMR registers can be read with 32-bit accesses only. The TSTMR LOW read should occur first, followed by the TSTMR HIGH read.

Parameters:

base – TSTMR peripheral base address.


Returns:
The 56-bit time stamp value. 






void TSTMR_DelayUs(TSTMR_Type *base, uint64_t delayInUs)

Delays for a specified number of microseconds. 
This function repeatedly reads the timestamp register and waits for the user-specified delay value.

Parameters:

base – TSTMR peripheral base address. 
delayInUs – Delay value in microseconds. 







WDOG32: 32-bit Watchdog Timer#


void WDOG32_GetDefaultConfig(wdog32_config_t *config)

Initializes the WDOG32 configuration structure. 
This function initializes the WDOG32 configuration structure to default values. The default values are: 
wdog32Config->enableWdog32 = true;
wdog32Config->clockSource = kWDOG32_ClockSource1;
wdog32Config->prescaler = kWDOG32_ClockPrescalerDivide1;
wdog32Config->workMode.enableWait = true;
wdog32Config->workMode.enableStop = false;
wdog32Config->workMode.enableDebug = false;
wdog32Config->testMode = kWDOG32_TestModeDisabled;
wdog32Config->enableUpdate = true;
wdog32Config->enableInterrupt = false;
wdog32Config->enableWindowMode = false;
wdog32Config->windowValue = 0U;
wdog32Config->timeoutValue = 0xFFFFU;




See also
wdog32_config_t



Parameters:

config – Pointer to the WDOG32 configuration structure. 







status_t WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config)

Initializes the WDOG32 module. 
This function initializes the WDOG32. To reconfigure the WDOG32 without forcing a reset first, enableUpdate must be set to true in the configuration.
Example: 
wdog32_config_t config;
WDOG32_GetDefaultConfig(&config);
config.timeoutValue = 0x7ffU;
config.enableUpdate = true;
WDOG32_Init(wdog_base,&config);




Note
If there is errata ERR010536 (FSL_FEATURE_WDOG_HAS_ERRATA_010536 defined as 1), then after calling this function, user need delay at least 4 LPO clock cycles before accessing other WDOG32 registers.


Parameters:

base – WDOG32 peripheral base address. 
config – The configuration of the WDOG32.


Return values:

kStatus_Success – The initialization was successful 
kStatus_Timeout – The initialization timed out 







status_t WDOG32_Deinit(WDOG_Type *base)

De-initializes the WDOG32 module. 
This function shuts down the WDOG32. Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled.

Parameters:

base – WDOG32 peripheral base address.


Return values:

kStatus_Success – The de-initialization was successful 
kStatus_Timeout – The de-initialization timed out 







status_t WDOG32_Unlock(WDOG_Type *base)

Unlocks the WDOG32 register written. 
This function unlocks the WDOG32 register written.
Before starting the unlock sequence and following the configuration, disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. After the configuration finishes, re-enable the global interrupts.

Parameters:

base – WDOG32 peripheral base address


Return values:

kStatus_Success – The unlock sequence was successful 
kStatus_Timeout – The unlock sequence timed out 







void WDOG32_Enable(WDOG_Type *base)

Enables the WDOG32 module. 
This function writes a value into the WDOG_CS register to enable the WDOG32. The WDOG_CS register is a write-once register. Please check the enableUpdate is set to true for calling WDOG32_Init to do wdog initialize. Before call the re-configuration APIs, ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

base – WDOG32 peripheral base address. 







void WDOG32_Disable(WDOG_Type *base)

Disables the WDOG32 module. 
This function writes a value into the WDOG_CS register to disable the WDOG32. The WDOG_CS register is a write-once register. Please check the enableUpdate is set to true for calling WDOG32_Init to do wdog initialize. Before call the re-configuration APIs, ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

base – WDOG32 peripheral base address 







void WDOG32_EnableInterrupts(WDOG_Type *base, uint32_t mask)

Enables the WDOG32 interrupt. 
This function writes a value into the WDOG_CS register to enable the WDOG32 interrupt. The WDOG_CS register is a write-once register. Please check the enableUpdate is set to true for calling WDOG32_Init to do wdog initialize. Before call the re-configuration APIs, ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

base – WDOG32 peripheral base address. 
mask – The interrupts to enable. The parameter can be a combination of the following source if defined: 

kWDOG32_InterruptEnable 









void WDOG32_DisableInterrupts(WDOG_Type *base, uint32_t mask)

Disables the WDOG32 interrupt. 
This function writes a value into the WDOG_CS register to disable the WDOG32 interrupt. The WDOG_CS register is a write-once register. Please check the enableUpdate is set to true for calling WDOG32_Init to do wdog initialize. Before call the re-configuration APIs, ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

base – WDOG32 peripheral base address. 
mask – The interrupts to disabled. The parameter can be a combination of the following source if defined: 

kWDOG32_InterruptEnable 









static inline uint32_t WDOG32_GetStatusFlags(WDOG_Type *base)

Gets the WDOG32 all status flags. 
This function gets all status flags.
Example to get the running flag: 
uint32_t status;
status = WDOG32_GetStatusFlags(wdog_base) & kWDOG32_RunningFlag;


 
See also
_wdog32_status_flags_t

true: related status flag has been set.
false: related status flag is not set. 





Parameters:

base – WDOG32 peripheral base address 


Returns:
State of the status flag: asserted (true) or not-asserted (false). 






void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask)

Clears the WDOG32 flag. 
This function clears the WDOG32 status flag.
Example to clear an interrupt flag: 
WDOG32_ClearStatusFlags(wdog_base,kWDOG32_InterruptFlag);


 

Parameters:

base – WDOG32 peripheral base address. 
mask – The status flags to clear. The parameter can be any combination of the following values: 

kWDOG32_InterruptFlag 









void WDOG32_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)

Sets the WDOG32 timeout value. 
This function writes a timeout value into the WDOG_TOVAL register. The WDOG_TOVAL register is a write-once register. To ensure the reconfiguration fits the timing of WCT, unlock function will be called inline.

Parameters:

base – WDOG32 peripheral base address 
timeoutCount – WDOG32 timeout value, count of WDOG32 clock ticks. 







void WDOG32_SetWindowValue(WDOG_Type *base, uint16_t windowValue)

Sets the WDOG32 window value. 
This function writes a window value into the WDOG_WIN register. The WDOG_WIN register is a write-once register. Please check the enableUpdate is set to true for calling WDOG32_Init to do wdog initialize. Before call the re-configuration APIs, ensure that the WCT window is still open and this register has not been written in this WCT while the function is called.

Parameters:

base – WDOG32 peripheral base address. 
windowValue – WDOG32 window value. 







static inline void WDOG32_Refresh(WDOG_Type *base)

Refreshes the WDOG32 timer. 
This function feeds the WDOG32. This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted.

Parameters:

base – WDOG32 peripheral base address 







static inline uint16_t WDOG32_GetCounterValue(WDOG_Type *base)

Gets the WDOG32 counter value. 
This function gets the WDOG32 counter value.

Parameters:

base – WDOG32 peripheral base address. 


Returns:
Current WDOG32 counter value. 






WDOG_FIRST_WORD_OF_UNLOCK

First word of unlock sequence 




WDOG_SECOND_WORD_OF_UNLOCK

Second word of unlock sequence 




WDOG_FIRST_WORD_OF_REFRESH

First word of refresh sequence 




WDOG_SECOND_WORD_OF_REFRESH

Second word of refresh sequence 




FSL_WDOG32_DRIVER_VERSION

WDOG32 driver version. 




enum _wdog32_clock_source

Max loops to wait for WDOG32 unlock sequence complete. 
This is the maximum number of loops to wait for the wdog32 unlock sequence to complete. If set to 0, it will wait indefinitely until the unlock sequence is complete.
Max loops to wait for WDOG32 reconfiguration complete.
This is the maximum number of loops to wait for the wdog32 reconfiguration to complete. If set to 0, it will wait indefinitely until the reconfiguration is complete.
Describes WDOG32 clock source. 
Values:


enumerator kWDOG32_ClockSource0

Clock source 0 




enumerator kWDOG32_ClockSource1

Clock source 1 




enumerator kWDOG32_ClockSource2

Clock source 2 




enumerator kWDOG32_ClockSource3

Clock source 3 






enum _wdog32_clock_prescaler

Describes the selection of the clock prescaler. 
Values:


enumerator kWDOG32_ClockPrescalerDivide1

Divided by 1 




enumerator kWDOG32_ClockPrescalerDivide256

Divided by 256 






enum _wdog32_test_mode

Describes WDOG32 test mode. 
Values:


enumerator kWDOG32_TestModeDisabled

Test Mode disabled 




enumerator kWDOG32_UserModeEnabled

User Mode enabled 




enumerator kWDOG32_LowByteTest

Test Mode enabled, only low byte is used 




enumerator kWDOG32_HighByteTest

Test Mode enabled, only high byte is used 






enum _wdog32_interrupt_enable_t

WDOG32 interrupt configuration structure. 
This structure contains the settings for all of the WDOG32 interrupt configurations. 
Values:


enumerator kWDOG32_InterruptEnable

Interrupt is generated before forcing a reset 






enum _wdog32_status_flags_t

WDOG32 status flags. 
This structure contains the WDOG32 status flags for use in the WDOG32 functions. 
Values:


enumerator kWDOG32_RunningFlag

Running flag, set when WDOG32 is enabled 




enumerator kWDOG32_InterruptFlag

Interrupt flag, set when interrupt occurs 






typedef enum _wdog32_clock_source wdog32_clock_source_t

Max loops to wait for WDOG32 unlock sequence complete. 
This is the maximum number of loops to wait for the wdog32 unlock sequence to complete. If set to 0, it will wait indefinitely until the unlock sequence is complete.
Max loops to wait for WDOG32 reconfiguration complete.
This is the maximum number of loops to wait for the wdog32 reconfiguration to complete. If set to 0, it will wait indefinitely until the reconfiguration is complete.
Describes WDOG32 clock source. 




typedef enum _wdog32_clock_prescaler wdog32_clock_prescaler_t

Describes the selection of the clock prescaler. 




typedef struct _wdog32_work_mode wdog32_work_mode_t

Defines WDOG32 work mode. 




typedef enum _wdog32_test_mode wdog32_test_mode_t

Describes WDOG32 test mode. 




typedef struct _wdog32_config wdog32_config_t

Describes WDOG32 configuration structure. 




struct _wdog32_work_mode


#include <fsl_wdog32.h>
Defines WDOG32 work mode. 

Public Members


bool enableWait

Enables or disables WDOG32 in wait mode 




bool enableStop

Enables or disables WDOG32 in stop mode 




bool enableDebug

Enables or disables WDOG32 in debug mode 







struct _wdog32_config


#include <fsl_wdog32.h>
Describes WDOG32 configuration structure. 

Public Members


bool enableWdog32

Enables or disables WDOG32 




wdog32_clock_source_t clockSource

Clock source select 




wdog32_clock_prescaler_t prescaler

Clock prescaler value 




wdog32_work_mode_t workMode

Configures WDOG32 work mode in debug stop and wait mode 




wdog32_test_mode_t testMode

Configures WDOG32 test mode 




bool enableUpdate

Update write-once register enable 




bool enableInterrupt

Enables or disables WDOG32 interrupt 




bool enableWindowMode

Enables or disables WDOG32 window mode 




uint16_t windowValue

Window value 




uint16_t timeoutValue

Timeout value 







CACHE: CACHE Memory Controller#


uint32_t XCACHE_GetInstanceByAddr(uint32_t address)

brief Returns an instance number given physical memory address.
param address The physical memory address. 

Returns:
XCACHE instance number starting from 0. 






void XCACHE_EnableCache(XCACHE_Type *base)

Enables the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_DisableCache(XCACHE_Type *base)

Disables the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_InvalidateCache(XCACHE_Type *base)

Invalidates the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cache by range. 

Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address of cache. 
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size. 







void XCACHE_CleanCache(XCACHE_Type *base)

Cleans the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_CleanCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cache by range. 

Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address of cache. 
size_byte – size of the memory to be cleaned, should be larger than 0, better to align with cache line size. 







void XCACHE_CleanInvalidateCache(XCACHE_Type *base)

Cleans and invalidates the cache. 

Parameters:

base – XCACHE peripheral base address. 







void XCACHE_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and invalidate cache by range. 

Note
Address and size should be aligned to “XCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to XCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address of cache. 
size_byte – size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size. 







static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates instruction cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size. 







static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates data cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be invalidated, should be larger than 0, better to align with cache line size. 







static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Clean data cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be cleaned, should be larger than 0, better to align with cache line size. 







static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates data cache by range. 

Note
Address and size should be aligned to XCACHE_LINESIZE_BYTE due to the cache operation unit FSL_FEATURE_XCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. 


Parameters:

address – The physical address. 
size_byte – size of the memory to be Cleaned and Invalidated, should be larger than 0, better to align with cache line size. 







FSL_CACHE_DRIVER_VERSION

cache driver version. 




XCACHE_LINESIZE_BYTE

cache line size.

MIMX9322

Contents

MIMX9322#

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

eDMA core Driver#

eDMA soc Driver#

ENET: Ethernet MAC Driver#

EQOS-TSN: Ethernet QoS with TSN Driver#

Enet_qos_qos#

FGPIO Driver#

FlexCAN: Flex Controller Area Network Driver#

FlexCAN Driver#

FlexCAN eDMA Driver#

FlexIO: FlexIO Driver#

FlexIO Driver#

FlexIO eDMA I2S Driver#

FlexIO eDMA SPI Driver#

FlexIO eDMA UART Driver#

FlexIO I2C Master Driver#

FlexIO I2S Driver#

FlexIO SPI Driver#

FlexIO UART Driver#

FLEXSPI: Flexible Serial Peripheral Interface Driver#

FLEXSPI eDMA Driver#

I3C: I3C Driver#

I3C Common Driver#

I3C Master Driver#

I3C Master DMA Driver#

I3C Slave Driver#

I3C Slave DMA Driver#

Common Driver#

LPI2C: Low Power Inter-Integrated Circuit Driver#

LPI2C Master Driver#

LPI2C Master DMA Driver#

LPI2C Slave Driver#

LPIT: Low-Power Interrupt Timer#

LPSPI: Low Power Serial Peripheral Interface#

LPSPI Peripheral driver#

LPSPI eDMA Driver#

LPTMR: Low-Power Timer#

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver#

LPUART Driver#

LPUART eDMA Driver#

MCM: Miscellaneous Control Module#

Mipi_dsi#

MIPI_DSI: MIPI DSI Host Controller#

MU: Messaging Unit#

OTFAD: On The Fly AES-128 Decryption Driver#

PDM: Microphone Interface#

PDM Driver#

PDM EDMA Driver#

RGPIO: Rapid General-Purpose Input/Output Driver#

RGPIO Driver#

SAI: Serial Audio Interface#

SAI Driver#

SAI EDMA Driver#

SAR_ADC: SAR_ADC Module#

SEMA42: Hardware Semaphores Driver#

TMU: Thermal Management Unit Driver#

TPM: Timer PWM Module#

TRDC: Trusted Resource Domain Controller#

Trdc_core#

TSTMR: Timestamp Timer Driver#

WDOG32: 32-bit Watchdog Timer#

CACHE: CACHE Memory Controller#