MIMX8MQ6#

CACHE: LMEM CACHE Memory Controller#

void L1CACHE_EnableCodeCache(void): Enables the processor code bus cache.

void L1CACHE_DisableCodeCache(void): Disables the processor code bus cache.

void L1CACHE_InvalidateCodeCache(void): Invalidates the processor code bus cache.

void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates processor code bus cache by range.

Note

Address and size should be aligned to “L1CODCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The physical address of cache.
size_byte – size of the memory to be invalidated.

void L1CACHE_CleanCodeCache(void): Cleans the processor code bus cache.

void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte)

Cleans processor code bus cache by range.

Note

Address and size should be aligned to “L1CODEBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The physical address of cache.
size_byte – size of the memory to be cleaned.

void L1CACHE_CleanInvalidateCodeCache(void): Cleans and invalidates the processor code bus cache.

void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and invalidate processor code bus cache by range.

Note

Parameters:

address – The physical address of cache.
size_byte – size of the memory to be Cleaned and Invalidated.

static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable)

Enables/disables the processor code bus write buffer.

Parameters:

enable – The enable or disable flag. true - enable the code bus write buffer. false - disable the code bus write buffer.

void L1CACHE_EnableSystemCache(void): Enables the processor system bus cache.

void L1CACHE_DisableSystemCache(void): Disables the processor system bus cache.

void L1CACHE_InvalidateSystemCache(void): Invalidates the processor system bus cache.

void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates processor system bus cache by range.

Note

Address and size should be aligned to “L1SYSTEMBUSCACHE_LINESIZE_BYTE”. The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The physical address of cache.
size_byte – size of the memory to be invalidated.

void L1CACHE_CleanSystemCache(void): Cleans the processor system bus cache.

void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte)

Cleans processor system bus cache by range.

Note

Parameters:

address – The physical address of cache.
size_byte – size of the memory to be cleaned.

void L1CACHE_CleanInvalidateSystemCache(void): Cleans and invalidates the processor system bus cache.

void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates processor system bus cache by range.

Note

Parameters:

address – The physical address of cache.
size_byte – size of the memory to be Clean and Invalidated.

static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable)

Enables/disables the processor system bus write buffer.

Parameters:

enable – The enable or disable flag. true - enable the code bus write buffer. false - disable the code bus write buffer.

void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m4 L1 instrument cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.

Parameters:

address – The start address of the memory to be invalidated.
size_byte – The memory size.

static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Invalidates cortex-m4 L1 data cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

Parameters:

address – The start address of the memory to be invalidated.
size_byte – The memory size.

void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans cortex-m4 L1 data cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

Parameters:

address – The start address of the memory to be cleaned.
size_byte – The memory size.

void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates cortex-m4 L1 data cache by range.

Note

The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.

Parameters:

address – The start address of the memory to be clean and invalidated.
size_byte – The memory size.

static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates instruction cache by range.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The physical address.
size_byte – size of the memory to be invalidated.

static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)

Invalidates data cache by range.

Note

Address and size should be aligned to 16-Byte due to the cache operation unit FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Parameters:

address – The physical address.
size_byte – size of the memory to be invalidated.

static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)

Clean data cache by range.

Note

Parameters:

address – The physical address.
size_byte – size of the memory to be cleaned.

static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)

Cleans and Invalidates data cache by range.

Note

Parameters:

address – The physical address.
size_byte – size of the memory to be Cleaned and Invalidated.

FSL_CACHE_DRIVER_VERSION: cache driver version.

L1CODEBUSCACHE_LINESIZE_BYTE

code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too.

The code bus CACHE line size is 16B = 128b.

L1SYSTEMBUSCACHE_LINESIZE_BYTE: The system bus CACHE line size is 16B = 128b.

Clock#

enum _clock_name

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_CoreM4Clk: ARM M4 Core clock

enumerator kCLOCK_AxiClk: Main AXI bus clock.

enumerator kCLOCK_AhbClk: AHB bus clock.

enumerator kCLOCK_IpgClk: IPG bus clock.

enumerator kCLOCK_Osc25MClk: OSC 25M clock.

enumerator kCLOCK_Osc27MClk: OSC 27M clock.

enumerator kCLOCK_ArmPllClk: Arm PLL clock.

enumerator kCLOCK_VpuPllClk: Vpu PLL clock.

enumerator kCLOCK_DramPllClk: Dram PLL clock.

enumerator kCLOCK_SysPll1Clk: Sys PLL1 clock.

enumerator kCLOCK_SysPll1Div2Clk: Sys PLL1 clock divided by 2.

enumerator kCLOCK_SysPll1Div3Clk: Sys PLL1 clock divided by 3.

enumerator kCLOCK_SysPll1Div4Clk: Sys PLL1 clock divided by 4.

enumerator kCLOCK_SysPll1Div5Clk: Sys PLL1 clock divided by 5.

enumerator kCLOCK_SysPll1Div6Clk: Sys PLL1 clock divided by 6.

enumerator kCLOCK_SysPll1Div8Clk: Sys PLL1 clock divided by 8.

enumerator kCLOCK_SysPll1Div10Clk: Sys PLL1 clock divided by 10.

enumerator kCLOCK_SysPll1Div20Clk: Sys PLL1 clock divided by 20.

enumerator kCLOCK_SysPll2Clk: Sys PLL2 clock.

enumerator kCLOCK_SysPll2Div2Clk: Sys PLL2 clock divided by 2.

enumerator kCLOCK_SysPll2Div3Clk: Sys PLL2 clock divided by 3.

enumerator kCLOCK_SysPll2Div4Clk: Sys PLL2 clock divided by 4.

enumerator kCLOCK_SysPll2Div5Clk: Sys PLL2 clock divided by 5.

enumerator kCLOCK_SysPll2Div6Clk: Sys PLL2 clock divided by 6.

enumerator kCLOCK_SysPll2Div8Clk: Sys PLL2 clock divided by 8.

enumerator kCLOCK_SysPll2Div10Clk: Sys PLL2 clock divided by 10.

enumerator kCLOCK_SysPll2Div20Clk: Sys PLL2 clock divided by 20.

enumerator kCLOCK_SysPll3Clk: Sys PLL3 clock.

enumerator kCLOCK_AudioPll1Clk: Audio PLL1 clock.

enumerator kCLOCK_AudioPll2Clk: Audio PLL2 clock.

enumerator kCLOCK_VideoPll1Clk: Video PLL1 clock.

enumerator kCLOCK_ExtClk1: External clock1.

enumerator kCLOCK_ExtClk2: External clock2.

enumerator kCLOCK_ExtClk3: External clock3.

enumerator kCLOCK_ExtClk4: External clock4.

enumerator kCLOCK_NoneName: None Clock Name.

enum _clock_ip_name

CCM CCGR gate control.

Values:

enumerator kCLOCK_IpInvalid

enumerator kCLOCK_Debug: DEBUG Clock Gate.

enumerator kCLOCK_Dram: DRAM Clock Gate.

enumerator kCLOCK_Ecspi1: ECSPI1 Clock Gate.

enumerator kCLOCK_Ecspi2: ECSPI2 Clock Gate.

enumerator kCLOCK_Ecspi3: ECSPI3 Clock Gate.

enumerator kCLOCK_Gpio1: GPIO1 Clock Gate.

enumerator kCLOCK_Gpio2: GPIO2 Clock Gate.

enumerator kCLOCK_Gpio3: GPIO3 Clock Gate.

enumerator kCLOCK_Gpio4: GPIO4 Clock Gate.

enumerator kCLOCK_Gpio5: GPIO5 Clock Gate.

enumerator kCLOCK_Gpt1: GPT1 Clock Gate.

enumerator kCLOCK_Gpt2: GPT2 Clock Gate.

enumerator kCLOCK_Gpt3: GPT3 Clock Gate.

enumerator kCLOCK_Gpt4: GPT4 Clock Gate.

enumerator kCLOCK_Gpt5: GPT5 Clock Gate.

enumerator kCLOCK_Gpt6: GPT6 Clock Gate.

enumerator kCLOCK_I2c1: I2C1 Clock Gate.

enumerator kCLOCK_I2c2: I2C2 Clock Gate.

enumerator kCLOCK_I2c3: I2C3 Clock Gate.

enumerator kCLOCK_I2c4: I2C4 Clock Gate.

enumerator kCLOCK_Iomux: IOMUX Clock Gate.

enumerator kCLOCK_Ipmux1: IPMUX1 Clock Gate.

enumerator kCLOCK_Ipmux2: IPMUX2 Clock Gate.

enumerator kCLOCK_Ipmux3: IPMUX3 Clock Gate.

enumerator kCLOCK_Ipmux4: IPMUX4 Clock Gate.

enumerator kCLOCK_M4: M4 Clock Gate.

enumerator kCLOCK_Mu: MU Clock Gate.

enumerator kCLOCK_Ocram: OCRAM Clock Gate.

enumerator kCLOCK_OcramS: OCRAM S Clock Gate.

enumerator kCLOCK_Pwm1: PWM1 Clock Gate.

enumerator kCLOCK_Pwm2: PWM2 Clock Gate.

enumerator kCLOCK_Pwm3: PWM3 Clock Gate.

enumerator kCLOCK_Pwm4: PWM4 Clock Gate.

enumerator kCLOCK_Qspi: QSPI Clock Gate.

enumerator kCLOCK_Rdc: RDC Clock Gate.

enumerator kCLOCK_Sai1: SAI1 Clock Gate.

enumerator kCLOCK_Sai2: SAI2 Clock Gate.

enumerator kCLOCK_Sai3: SAI3 Clock Gate.

enumerator kCLOCK_Sai4: SAI4 Clock Gate.

enumerator kCLOCK_Sai5: SAI5 Clock Gate.

enumerator kCLOCK_Sai6: SAI6 Clock Gate.

enumerator kCLOCK_Sdma1: SDMA1 Clock Gate.

enumerator kCLOCK_Sdma2: SDMA2 Clock Gate.

enumerator kCLOCK_Sec_Debug: SEC_DEBUG Clock Gate.

enumerator kCLOCK_Sema42_1: RDC SEMA42 Clock Gate.

enumerator kCLOCK_Sema42_2: RDC SEMA42 Clock Gate.

enumerator kCLOCK_Sim_display: SIM_Display Clock Gate.

enumerator kCLOCK_Sim_m: SIM_M Clock Gate.

enumerator kCLOCK_Sim_main: SIM_MAIN Clock Gate.

enumerator kCLOCK_Sim_s: SIM_S Clock Gate.

enumerator kCLOCK_Sim_wakeup: SIM_WAKEUP Clock Gate.

enumerator kCLOCK_Uart1: UART1 Clock Gate.

enumerator kCLOCK_Uart2: UART2 Clock Gate.

enumerator kCLOCK_Uart3: UART3 Clock Gate.

enumerator kCLOCK_Uart4: UART4 Clock Gate.

enumerator kCLOCK_Wdog1: WDOG1 Clock Gate.

enumerator kCLOCK_Wdog2: WDOG2 Clock Gate.

enumerator kCLOCK_Wdog3: WDOG3 Clock Gate.

enumerator kCLOCK_TempSensor: TempSensor Clock Gate.

enum _clock_root_control

ccm root name used to get clock frequency.

Values:

enumerator kCLOCK_RootM4: ARM Cortex-M4 Clock control name.

enumerator kCLOCK_RootAxi: AXI Clock control name.

enumerator kCLOCK_RootNoc: NOC Clock control name.

enumerator kCLOCK_RootAhb: AHB Clock control name.

enumerator kCLOCK_RootIpg: IPG Clock control name.

enumerator kCLOCK_RootDramAlt: DRAM ALT Clock control name.

enumerator kCLOCK_RootSai1: SAI1 Clock control name.

enumerator kCLOCK_RootSai2: SAI2 Clock control name.

enumerator kCLOCK_RootSai3: SAI3 Clock control name.

enumerator kCLOCK_RootSai4: SAI4 Clock control name.

enumerator kCLOCK_RootSai5: SAI5 Clock control name.

enumerator kCLOCK_RootSai6: SAI6 Clock control name.

enumerator kCLOCK_RootQspi: QSPI Clock control name.

enumerator kCLOCK_RootI2c1: I2C1 Clock control name.

enumerator kCLOCK_RootI2c2: I2C2 Clock control name.

enumerator kCLOCK_RootI2c3: I2C3 Clock control name.

enumerator kCLOCK_RootI2c4: I2C4 Clock control name.

enumerator kCLOCK_RootUart1: UART1 Clock control name.

enumerator kCLOCK_RootUart2: UART2 Clock control name.

enumerator kCLOCK_RootUart3: UART3 Clock control name.

enumerator kCLOCK_RootUart4: UART4 Clock control name.

enumerator kCLOCK_RootEcspi1: ECSPI1 Clock control name.

enumerator kCLOCK_RootEcspi2: ECSPI2 Clock control name.

enumerator kCLOCK_RootEcspi3: ECSPI3 Clock control name.

enumerator kCLOCK_RootPwm1: PWM1 Clock control name.

enumerator kCLOCK_RootPwm2: PWM2 Clock control name.

enumerator kCLOCK_RootPwm3: PWM3 Clock control name.

enumerator kCLOCK_RootPwm4: PWM4 Clock control name.

enumerator kCLOCK_RootGpt1: GPT1 Clock control name.

enumerator kCLOCK_RootGpt2: GPT2 Clock control name.

enumerator kCLOCK_RootGpt3: GPT3 Clock control name.

enumerator kCLOCK_RootGpt4: GPT4 Clock control name.

enumerator kCLOCK_RootGpt5: GPT5 Clock control name.

enumerator kCLOCK_RootGpt6: GPT6 Clock control name.

enumerator kCLOCK_RootWdog: WDOG Clock control name.

enum _clock_root

ccm clock root used to get clock frequency.

Values:

enumerator kCLOCK_M4ClkRoot: ARM Cortex-M4 Clock control name.

enumerator kCLOCK_AxiClkRoot: AXI Clock control name.

enumerator kCLOCK_NocClkRoot: NOC Clock control name.

enumerator kCLOCK_AhbClkRoot: AHB Clock control name.

enumerator kCLOCK_IpgClkRoot: IPG Clock control name.

enumerator kCLOCK_DramAltClkRoot: DRAM ALT Clock control name.

enumerator kCLOCK_Sai1ClkRoot: SAI1 Clock control name.

enumerator kCLOCK_Sai2ClkRoot: SAI2 Clock control name.

enumerator kCLOCK_Sai3ClkRoot: SAI3 Clock control name.

enumerator kCLOCK_Sai4ClkRoot: SAI4 Clock control name.

enumerator kCLOCK_Sai5ClkRoot: SAI5 Clock control name.

enumerator kCLOCK_Sai6ClkRoot: SAI6 Clock control name.

enumerator kCLOCK_QspiClkRoot: QSPI Clock control name.

enumerator kCLOCK_I2c1ClkRoot: I2C1 Clock control name.

enumerator kCLOCK_I2c2ClkRoot: I2C2 Clock control name.

enumerator kCLOCK_I2c3ClkRoot: I2C3 Clock control name.

enumerator kCLOCK_I2c4ClkRoot: I2C4 Clock control name.

enumerator kCLOCK_Uart1ClkRoot: UART1 Clock control name.

enumerator kCLOCK_Uart2ClkRoot: UART2 Clock control name.

enumerator kCLOCK_Uart3ClkRoot: UART3 Clock control name.

enumerator kCLOCK_Uart4ClkRoot: UART4 Clock control name.

enumerator kCLOCK_Ecspi1ClkRoot: ECSPI1 Clock control name.

enumerator kCLOCK_Ecspi2ClkRoot: ECSPI2 Clock control name.

enumerator kCLOCK_Ecspi3ClkRoot: ECSPI3 Clock control name.

enumerator kCLOCK_Pwm1ClkRoot: PWM1 Clock control name.

enumerator kCLOCK_Pwm2ClkRoot: PWM2 Clock control name.

enumerator kCLOCK_Pwm3ClkRoot: PWM3 Clock control name.

enumerator kCLOCK_Pwm4ClkRoot: PWM4 Clock control name.

enumerator kCLOCK_Gpt1ClkRoot: GPT1 Clock control name.

enumerator kCLOCK_Gpt2ClkRoot: GPT2 Clock control name.

enumerator kCLOCK_Gpt3ClkRoot: GPT3 Clock control name.

enumerator kCLOCK_Gpt4ClkRoot: GPT4 Clock control name.

enumerator kCLOCK_Gpt5ClkRoot: GPT5 Clock control name.

enumerator kCLOCK_Gpt6ClkRoot: GPT6 Clock control name.

enumerator kCLOCK_WdogClkRoot: WDOG Clock control name.

enum _clock_rootmux_m4_clk_sel

Root clock select enumeration for ARM Cortex-M4 core.

Values:

enumerator kCLOCK_M4RootmuxOsc25m: ARM Cortex-M4 Clock from OSC 25M.

enumerator kCLOCK_M4RootmuxSysPll2Div5: ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.

enumerator kCLOCK_M4RootmuxSysPll2Div4: ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.

enumerator kCLOCK_M4RootmuxSysPll1Div3: ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.

enumerator kCLOCK_M4RootmuxSysPll1: ARM Cortex-M4 Clock from SYSTEM PLL1.

enumerator kCLOCK_M4RootmuxAudioPll1: ARM Cortex-M4 Clock from AUDIO PLL1.

enumerator kCLOCK_M4RootmuxVideoPll1: ARM Cortex-M4 Clock from VIDEO PLL1.

enumerator kCLOCK_M4RootmuxSysPll3: ARM Cortex-M4 Clock from SYSTEM PLL3.

enum _clock_rootmux_axi_clk_sel

Root clock select enumeration for AXI bus.

Values:

enumerator kCLOCK_AxiRootmuxOsc25m: ARM AXI Clock from OSC 25M.

enumerator kCLOCK_AxiRootmuxSysPll2Div3: ARM AXI Clock from SYSTEM PLL2 divided by 3.

enumerator kCLOCK_AxiRootmuxSysPll1: ARM AXI Clock from SYSTEM PLL1.

enumerator kCLOCK_AxiRootmuxSysPll2Div4: ARM AXI Clock from SYSTEM PLL2 divided by 4.

enumerator kCLOCK_AxiRootmuxSysPll2: ARM AXI Clock from SYSTEM PLL2.

enumerator kCLOCK_AxiRootmuxAudioPll1: ARM AXI Clock from AUDIO PLL1.

enumerator kCLOCK_AxiRootmuxVideoPll1: ARM AXI Clock from VIDEO PLL1.

enumerator kCLOCK_AxiRootmuxSysPll1Div8: ARM AXI Clock from SYSTEM PLL1 divided by 8.

enum _clock_rootmux_ahb_clk_sel

Root clock select enumeration for AHB bus.

Values:

enumerator kCLOCK_AhbRootmuxOsc25m: ARM AHB Clock from OSC 25M.

enumerator kCLOCK_AhbRootmuxSysPll1Div6: ARM AHB Clock from SYSTEM PLL1 divided by 6.

enumerator kCLOCK_AhbRootmuxSysPll1: ARM AHB Clock from SYSTEM PLL1.

enumerator kCLOCK_AhbRootmuxSysPll1Div2: ARM AHB Clock from SYSTEM PLL1 divided by 2.

enumerator kCLOCK_AhbRootmuxSysPll2Div8: ARM AHB Clock from SYSTEM PLL2 divided by 8.

enumerator kCLOCK_AhbRootmuxSysPll3: ARM AHB Clock from SYSTEM PLL3.

enumerator kCLOCK_AhbRootmuxAudioPll1: ARM AHB Clock from AUDIO PLL1.

enumerator kCLOCK_AhbRootmuxVideoPll1: ARM AHB Clock from VIDEO PLL1.

enum _clock_rootmux_qspi_clk_sel

Root clock select enumeration for QSPI peripheral.

Values:

enumerator kCLOCK_QspiRootmuxOsc25m: ARM QSPI Clock from OSC 25M.

enumerator kCLOCK_QspiRootmuxSysPll1Div2: ARM QSPI Clock from SYSTEM PLL1 divided by 2.

enumerator kCLOCK_QspiRootmuxSysPll1: ARM QSPI Clock from SYSTEM PLL1.

enumerator kCLOCK_QspiRootmuxSysPll2Div2: ARM QSPI Clock from SYSTEM PLL2 divided by 2.

enumerator kCLOCK_QspiRootmuxAudioPll2: ARM QSPI Clock from AUDIO PLL2.

enumerator kCLOCK_QspiRootmuxSysPll1Div3: ARM QSPI Clock from SYSTEM PLL1 divided by 3

enumerator kCLOCK_QspiRootmuxSysPll3: ARM QSPI Clock from SYSTEM PLL3.

enumerator kCLOCK_QspiRootmuxSysPll1Div8: ARM QSPI Clock from SYSTEM PLL1 divided by 8.

enum _clock_rootmux_ecspi_clk_sel

Root clock select enumeration for ECSPI peripheral.

Values:

enumerator kCLOCK_EcspiRootmuxOsc25m: ECSPI Clock from OSC 25M.

enumerator kCLOCK_EcspiRootmuxSysPll2Div5: ECSPI Clock from SYSTEM PLL2 divided by 5.

enumerator kCLOCK_EcspiRootmuxSysPll1Div20: ECSPI Clock from SYSTEM PLL1 divided by 20.

enumerator kCLOCK_EcspiRootmuxSysPll1Div5: ECSPI Clock from SYSTEM PLL1 divided by 5.

enumerator kCLOCK_EcspiRootmuxSysPll1: ECSPI Clock from SYSTEM PLL1.

enumerator kCLOCK_EcspiRootmuxSysPll3: ECSPI Clock from SYSTEM PLL3.

enumerator kCLOCK_EcspiRootmuxSysPll2Div4: ECSPI Clock from SYSTEM PLL2 divided by 4.

enumerator kCLOCK_EcspiRootmuxAudioPll2: ECSPI Clock from AUDIO PLL2.

enum _clock_rootmux_i2c_clk_sel

Root clock select enumeration for I2C peripheral.

Values:

enumerator kCLOCK_I2cRootmuxOsc25m: I2C Clock from OSC 25M.

enumerator kCLOCK_I2cRootmuxSysPll1Div5: I2C Clock from SYSTEM PLL1 divided by 5.

enumerator kCLOCK_I2cRootmuxSysPll2Div20: I2C Clock from SYSTEM PLL2 divided by 20.

enumerator kCLOCK_I2cRootmuxSysPll3: I2C Clock from SYSTEM PLL3 .

enumerator kCLOCK_I2cRootmuxAudioPll1: I2C Clock from AUDIO PLL1.

enumerator kCLOCK_I2cRootmuxVideoPll1: I2C Clock from VIDEO PLL1.

enumerator kCLOCK_I2cRootmuxAudioPll2: I2C Clock from AUDIO PLL2.

enumerator kCLOCK_I2cRootmuxSysPll1Div6: I2C Clock from SYSTEM PLL1 divided by 6.

enum _clock_rootmux_uart_clk_sel

Root clock select enumeration for UART peripheral.

Values:

enumerator kCLOCK_UartRootmuxOsc25m: UART Clock from OSC 25M.

enumerator kCLOCK_UartRootmuxSysPll1Div10: UART Clock from SYSTEM PLL1 divided by 10.

enumerator kCLOCK_UartRootmuxSysPll2Div5: UART Clock from SYSTEM PLL2 divided by 5.

enumerator kCLOCK_UartRootmuxSysPll2Div10: UART Clock from SYSTEM PLL2 divided by 10.

enumerator kCLOCK_UartRootmuxSysPll3: UART Clock from SYSTEM PLL3.

enumerator kCLOCK_UartRootmuxExtClk2: UART Clock from External Clock 2.

enumerator kCLOCK_UartRootmuxExtClk34: UART Clock from External Clock 3, External Clock 4.

enumerator kCLOCK_UartRootmuxAudioPll2: UART Clock from Audio PLL2.

enum _clock_rootmux_gpt

Root clock select enumeration for GPT peripheral.

Values:

enumerator kCLOCK_GptRootmuxOsc25m: GPT Clock from OSC 25M.

enumerator kCLOCK_GptRootmuxSystemPll2Div10: GPT Clock from SYSTEM PLL2 divided by 10.

enumerator kCLOCK_GptRootmuxSysPll1Div2: GPT Clock from SYSTEM PLL1 divided by 2.

enumerator kCLOCK_GptRootmuxSysPll1Div20: GPT Clock from SYSTEM PLL1 divided by 20.

enumerator kCLOCK_GptRootmuxVideoPll1: GPT Clock from VIDEO PLL1.

enumerator kCLOCK_GptRootmuxSystemPll1Div10: GPT Clock from SYSTEM PLL1 divided by 10.

enumerator kCLOCK_GptRootmuxAudioPll1: GPT Clock from AUDIO PLL1.

enumerator kCLOCK_GptRootmuxExtClk123: GPT Clock from External Clock1, External Clock2, External Clock3.

enum _clock_rootmux_wdog_clk_sel

Root clock select enumeration for WDOG peripheral.

Values:

enumerator kCLOCK_WdogRootmuxOsc25m: WDOG Clock from OSC 25M.

enumerator kCLOCK_WdogRootmuxSysPll1Div6: WDOG Clock from SYSTEM PLL1 divided by 6.

enumerator kCLOCK_WdogRootmuxSysPll1Div5: WDOG Clock from SYSTEM PLL1 divided by 5.

enumerator kCLOCK_WdogRootmuxVpuPll: WDOG Clock from VPU DLL.

enumerator kCLOCK_WdogRootmuxSystemPll2Div8: WDOG Clock from SYSTEM PLL2 divided by 8.

enumerator kCLOCK_WdogRootmuxSystemPll3: WDOG Clock from SYSTEM PLL3.

enumerator kCLOCK_WdogRootmuxSystemPll1Div10: WDOG Clock from SYSTEM PLL1 divided by 10.

enumerator kCLOCK_WdogRootmuxSystemPll2Div6: WDOG Clock from SYSTEM PLL2 divided by 6.

enum _clock_rootmux_pwm_clk_sel

Root clock select enumeration for PWM peripheral.

Values:

enumerator kCLOCK_PwmRootmuxOsc25m: PWM Clock from OSC 25M.

enumerator kCLOCK_PwmRootmuxSysPll2Div10: PWM Clock from SYSTEM PLL2 divided by 10.

enumerator kCLOCK_PwmRootmuxSysPll1Div5: PWM Clock from SYSTEM PLL1 divided by 5.

enumerator kCLOCK_PwmRootmuxSysPll1Div20: PWM Clock from SYSTEM PLL1 divided by 20.

enumerator kCLOCK_PwmRootmuxSystemPll3: PWM Clock from SYSTEM PLL3.

enumerator kCLOCK_PwmRootmuxExtClk12: PWM Clock from External Clock1, External Clock2.

enumerator kCLOCK_PwmRootmuxSystemPll1Div10: PWM Clock from SYSTEM PLL1 divided by 10.

enumerator kCLOCK_PwmRootmuxVideoPll1: PWM Clock from VIDEO PLL1.

enum _clock_rootmux_sai_clk_sel

Root clock select enumeration for SAI peripheral.

Values:

enumerator kCLOCK_SaiRootmuxOsc25m: SAI Clock from OSC 25M.

enumerator kCLOCK_SaiRootmuxAudioPll1: SAI Clock from AUDIO PLL1.

enumerator kCLOCK_SaiRootmuxAudioPll2: SAI Clock from AUDIO PLL2.

enumerator kCLOCK_SaiRootmuxVideoPll1: SAI Clock from VIDEO PLL1.

enumerator kCLOCK_SaiRootmuxSysPll1Div6: SAI Clock from SYSTEM PLL1 divided by 6.

enumerator kCLOCK_SaiRootmuxOsc27m: SAI Clock from OSC 27M.

enumerator kCLOCK_SaiRootmuxExtClk123: SAI Clock from External Clock1, External Clock2, External Clock3.

enumerator kCLOCK_SaiRootmuxExtClk234: SAI Clock from External Clock2, External Clock3, External Clock4.

enum _clock_rootmux_noc_clk_sel

Root clock select enumeration for NOC CLK.

Values:

enumerator kCLOCK_NocRootmuxOsc25m: NOC Clock from OSC 25M.

enumerator kCLOCK_NocRootmuxSysPll1: NOC Clock from SYSTEM PLL1.

enumerator kCLOCK_NocRootmuxSysPll3: NOC Clock from SYSTEM PLL3.

enumerator kCLOCK_NocRootmuxSysPll2: NOC Clock from SYSTEM PLL2.

enumerator kCLOCK_NocRootmuxSysPll2Div2: NOC Clock from SYSTEM PLL2 divided by 2.

enumerator kCLOCK_NocRootmuxAudioPll1: NOC Clock from AUDIO PLL1.

enumerator kCLOCK_NocRootmuxVideoPll1: NOC Clock from VIDEO PLL1.

enumerator kCLOCK_NocRootmuxAudioPll2: NOC Clock from AUDIO PLL2.

enum _clock_pll_gate

CCM PLL gate control.

Values:

enumerator kCLOCK_ArmPllGate: ARM PLL Gate.

enumerator kCLOCK_GpuPllGate: GPU PLL Gate.

enumerator kCLOCK_VpuPllGate: VPU PLL Gate.

enumerator kCLOCK_DramPllGate: DRAM PLL1 Gate.

enumerator kCLOCK_SysPll1Gate: SYSTEM PLL1 Gate.

enumerator kCLOCK_SysPll1Div2Gate: SYSTEM PLL1 Div2 Gate.

enumerator kCLOCK_SysPll1Div3Gate: SYSTEM PLL1 Div3 Gate.

enumerator kCLOCK_SysPll1Div4Gate: SYSTEM PLL1 Div4 Gate.

enumerator kCLOCK_SysPll1Div5Gate: SYSTEM PLL1 Div5 Gate.

enumerator kCLOCK_SysPll1Div6Gate: SYSTEM PLL1 Div6 Gate.

enumerator kCLOCK_SysPll1Div8Gate: SYSTEM PLL1 Div8 Gate.

enumerator kCLOCK_SysPll1Div10Gate: SYSTEM PLL1 Div10 Gate.

enumerator kCLOCK_SysPll1Div20Gate: SYSTEM PLL1 Div20 Gate.

enumerator kCLOCK_SysPll2Gate: SYSTEM PLL2 Gate.

enumerator kCLOCK_SysPll2Div2Gate: SYSTEM PLL2 Div2 Gate.

enumerator kCLOCK_SysPll2Div3Gate: SYSTEM PLL2 Div3 Gate.

enumerator kCLOCK_SysPll2Div4Gate: SYSTEM PLL2 Div4 Gate.

enumerator kCLOCK_SysPll2Div5Gate: SYSTEM PLL2 Div5 Gate.

enumerator kCLOCK_SysPll2Div6Gate: SYSTEM PLL2 Div6 Gate.

enumerator kCLOCK_SysPll2Div8Gate: SYSTEM PLL2 Div8 Gate.

enumerator kCLOCK_SysPll2Div10Gate: SYSTEM PLL2 Div10 Gate.

enumerator kCLOCK_SysPll2Div20Gate: SYSTEM PLL2 Div20 Gate.

enumerator kCLOCK_SysPll3Gate: SYSTEM PLL3 Gate.

enumerator kCLOCK_AudioPll1Gate: AUDIO PLL1 Gate.

enumerator kCLOCK_AudioPll2Gate: AUDIO PLL2 Gate.

enumerator kCLOCK_VideoPll1Gate: VIDEO PLL1 Gate.

enumerator kCLOCK_VideoPll2Gate: VIDEO PLL2 Gate.

enum _clock_gate_value

CCM gate control value.

Values:

enumerator kCLOCK_ClockNotNeeded: Clock always disabled.

enumerator kCLOCK_ClockNeededRun: Clock enabled when CPU is running.

enumerator kCLOCK_ClockNeededRunWait: Clock enabled when CPU is running or in WAIT mode.

enumerator kCLOCK_ClockNeededAll: Clock always enabled.

enum _clock_pll_bypass_ctrl

PLL control names for PLL bypass.

These constants define the PLL control names for PLL bypass.

0:15: REG offset to CCM_ANALOG_BASE in bytes.
16:20: bypass bit shift.

Values:

enumerator kCLOCK_AudioPll1BypassCtrl: CCM Audio PLL1 bypass Control.

enumerator kCLOCK_AudioPll2BypassCtrl: CCM Audio PLL2 bypass Control.

enumerator kCLOCK_VideoPll1BypassCtrl: CCM Video Pll1 bypass Control.

enumerator kCLOCK_GpuPLLPwrBypassCtrl: CCM Gpu PLL bypass Control.

enumerator kCLOCK_VpuPllPwrBypassCtrl: CCM Vpu PLL bypass Control.

enumerator kCLOCK_ArmPllPwrBypassCtrl: CCM Arm PLL bypass Control.

enumerator kCLOCK_SysPll1InternalPll1BypassCtrl: CCM System PLL1 internal pll1 bypass Control.

enumerator kCLOCK_SysPll1InternalPll2BypassCtrl: CCM System PLL1 internal pll2 bypass Control.

enumerator kCLOCK_SysPll2InternalPll1BypassCtrl: CCM Analog System PLL1 internal pll1 bypass Control.

enumerator kCLOCK_SysPll2InternalPll2BypassCtrl: CCM Analog VIDEO System PLL1 internal pll1 bypass Control.

enumerator kCLOCK_SysPll3InternalPll1BypassCtrl: CCM Analog VIDEO PLL bypass Control.

enumerator kCLOCK_SysPll3InternalPll2BypassCtrl: CCM Analog VIDEO PLL bypass Control.

enumerator kCLOCK_VideoPll2InternalPll1BypassCtrl: CCM Analog 480M PLL bypass Control.

enumerator kCLOCK_VideoPll2InternalPll2BypassCtrl: CCM Analog 480M PLL bypass Control.

enumerator kCLOCK_DramPllInternalPll1BypassCtrl: CCM Analog 480M PLL bypass Control.

enumerator kCLOCK_DramPllInternalPll2BypassCtrl: CCM Analog 480M PLL bypass Control.

enum _ccm_analog_pll_clke

PLL clock names for clock enable/disable settings.

These constants define the PLL clock names for PLL clock enable/disable operations.

0:15: REG offset to CCM_ANALOG_BASE in bytes.
16:20: Clock enable bit shift.

Values:

enumerator kCLOCK_AudioPll1Clke: Audio pll1 clke

enumerator kCLOCK_AudioPll2Clke: Audio pll2 clke

enumerator kCLOCK_VideoPll1Clke: Video pll1 clke

enumerator kCLOCK_GpuPllClke: Gpu pll clke

enumerator kCLOCK_VpuPllClke: Vpu pll clke

enumerator kCLOCK_ArmPllClke: Arm pll clke

enumerator kCLOCK_SystemPll1Clke: System pll1 clke

enumerator kCLOCK_SystemPll1Div2Clke: System pll1 Div2 clke

enumerator kCLOCK_SystemPll1Div3Clke: System pll1 Div3 clke

enumerator kCLOCK_SystemPll1Div4Clke: System pll1 Div4 clke

enumerator kCLOCK_SystemPll1Div5Clke: System pll1 Div5 clke

enumerator kCLOCK_SystemPll1Div6Clke: System pll1 Div6 clke

enumerator kCLOCK_SystemPll1Div8Clke: System pll1 Div8 clke

enumerator kCLOCK_SystemPll1Div10Clke: System pll1 Div10 clke

enumerator kCLOCK_SystemPll1Div20Clke: System pll1 Div20 clke

enumerator kCLOCK_SystemPll2Clke: System pll2 clke

enumerator kCLOCK_SystemPll2Div2Clke: System pll2 Div2 clke

enumerator kCLOCK_SystemPll2Div3Clke: System pll2 Div3 clke

enumerator kCLOCK_SystemPll2Div4Clke: System pll2 Div4 clke

enumerator kCLOCK_SystemPll2Div5Clke: System pll2 Div5 clke

enumerator kCLOCK_SystemPll2Div6Clke: System pll2 Div6 clke

enumerator kCLOCK_SystemPll2Div8Clke: System pll2 Div8 clke

enumerator kCLOCK_SystemPll2Div10Clke: System pll2 Div10 clke

enumerator kCLOCK_SystemPll2Div20Clke: System pll2 Div20 clke

enumerator kCLOCK_SystemPll3Clke: System pll3 clke

enumerator kCLOCK_VideoPll2Clke: Video pll2 clke

enumerator kCLOCK_DramPllClke: Dram pll clke

enumerator kCLOCK_OSC25MClke: OSC25M clke

enumerator kCLOCK_OSC27MClke: OSC27M clke

enum _clock_pll_ctrl

ANALOG Power down override control.

Values:

enumerator kCLOCK_AudioPll1Ctrl

enumerator kCLOCK_AudioPll2Ctrl

enumerator kCLOCK_VideoPll1Ctrl

enumerator kCLOCK_GpuPllCtrl

enumerator kCLOCK_VpuPllCtrl

enumerator kCLOCK_ArmPllCtrl

enumerator kCLOCK_SystemPll1Ctrl

enumerator kCLOCK_SystemPll2Ctrl

enumerator kCLOCK_SystemPll3Ctrl

enumerator kCLOCK_VideoPll2Ctrl

enumerator kCLOCK_DramPllCtrl

enum _osc_mode

OSC work mode.

Values:

enumerator kOSC_OscMode: OSC oscillator mode

enumerator kOSC_ExtMode: OSC external mode

enum _osc32_src

OSC 32K input select.

Values:

enumerator kOSC32_Src25MDiv800: source from 25M divide 800

enumerator kOSC32_SrcRTC: source from RTC

enum _ccm_analog_pll_ref_clk

PLL reference clock select.

Values:

enumerator kANALOG_PllRefOsc25M: reference OSC 25M

enumerator kANALOG_PllRefOsc27M: reference OSC 27M

enumerator kANALOG_PllRefOscHdmiPhy27M: reference HDMI PHY 27M

enumerator kANALOG_PllRefClkPN: reference CLK_P_N

typedef enum _clock_name clock_name_t: Clock name used to get clock frequency.

typedef enum _clock_ip_name clock_ip_name_t: CCM CCGR gate control.

typedef enum _clock_root_control clock_root_control_t: ccm root name used to get clock frequency.

typedef enum _clock_root clock_root_t: ccm clock root used to get clock frequency.

typedef enum _clock_rootmux_m4_clk_sel clock_rootmux_m4_clk_sel_t: Root clock select enumeration for ARM Cortex-M4 core.

typedef enum _clock_rootmux_axi_clk_sel clock_rootmux_axi_clk_sel_t: Root clock select enumeration for AXI bus.

typedef enum _clock_rootmux_ahb_clk_sel clock_rootmux_ahb_clk_sel_t: Root clock select enumeration for AHB bus.

typedef enum _clock_rootmux_qspi_clk_sel clock_rootmux_qspi_clk_sel_t: Root clock select enumeration for QSPI peripheral.

typedef enum _clock_rootmux_ecspi_clk_sel clock_rootmux_ecspi_clk_sel_t: Root clock select enumeration for ECSPI peripheral.

typedef enum _clock_rootmux_i2c_clk_sel clock_rootmux_i2c_clk_sel_t: Root clock select enumeration for I2C peripheral.

typedef enum _clock_rootmux_uart_clk_sel clock_rootmux_uart_clk_sel_t: Root clock select enumeration for UART peripheral.

typedef enum _clock_rootmux_gpt clock_rootmux_gpt_t: Root clock select enumeration for GPT peripheral.

typedef enum _clock_rootmux_wdog_clk_sel clock_rootmux_wdog_clk_sel_t: Root clock select enumeration for WDOG peripheral.

typedef enum _clock_rootmux_pwm_clk_sel clock_rootmux_Pwm_clk_sel_t: Root clock select enumeration for PWM peripheral.

typedef enum _clock_rootmux_sai_clk_sel clock_rootmux_sai_clk_sel_t: Root clock select enumeration for SAI peripheral.

typedef enum _clock_rootmux_noc_clk_sel clock_rootmux_noc_clk_sel_t: Root clock select enumeration for NOC CLK.

typedef enum _clock_pll_gate clock_pll_gate_t: CCM PLL gate control.

typedef enum _clock_gate_value clock_gate_value_t: CCM gate control value.

typedef enum _clock_pll_bypass_ctrl clock_pll_bypass_ctrl_t

PLL control names for PLL bypass.

These constants define the PLL control names for PLL bypass.

0:15: REG offset to CCM_ANALOG_BASE in bytes.
16:20: bypass bit shift.

typedef enum _ccm_analog_pll_clke clock_pll_clke_t

PLL clock names for clock enable/disable settings.

These constants define the PLL clock names for PLL clock enable/disable operations.

0:15: REG offset to CCM_ANALOG_BASE in bytes.
16:20: Clock enable bit shift.

typedef enum _clock_pll_ctrl clock_pll_ctrl_t: ANALOG Power down override control.

typedef enum _osc32_src osc32_src_t: OSC 32K input select.

typedef struct _osc_config osc_config_t: OSC configuration structure.

typedef struct _ccm_analog_frac_pll_config ccm_analog_frac_pll_config_t: Fractional-N PLL configuration. Note: all the dividers in this configuration structure are the actually divider, software will map it to register value.

typedef struct _ccm_analog_sscg_pll_config ccm_analog_sscg_pll_config_t: SSCG PLL configuration. Note: all the dividers in this configuration structure are the actually divider, software will map it to register value.

FSL_CLOCK_DRIVER_VERSION: CLOCK driver version 2.4.1.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY

OSC25M_CLK_FREQ: XTAL 25M clock frequency.

OSC27M_CLK_FREQ: XTAL 27M clock frequency.

HDMI_PHY_27M_FREQ: HDMI PHY 27M clock frequency.

CLKPN_FREQ: clock1PN frequency.

ECSPI_CLOCKS: Clock ip name array for ECSPI.

GPIO_CLOCKS: Clock ip name array for GPIO.

GPT_CLOCKS: Clock ip name array for GPT.

I2C_CLOCKS: Clock ip name array for I2C.

IOMUX_CLOCKS: Clock ip name array for IOMUX.

IPMUX_CLOCKS: Clock ip name array for IPMUX.

PWM_CLOCKS: Clock ip name array for PWM.

RDC_CLOCKS: Clock ip name array for RDC.

SAI_CLOCKS: Clock ip name array for SAI.

RDC_SEMA42_CLOCKS: Clock ip name array for RDC SEMA42.

UART_CLOCKS: Clock ip name array for UART.

USDHC_CLOCKS: Clock ip name array for USDHC.

WDOG_CLOCKS: Clock ip name array for WDOG.

TMU_CLOCKS: Clock ip name array for TEMPSENSOR.

SDMA_CLOCKS: Clock ip name array for SDMA.

MU_CLOCKS: Clock ip name array for MU.

QSPI_CLOCKS: Clock ip name array for QSPI.

CCM_BIT_FIELD_EXTRACTION(val, mask, shift): CCM reg macros to extract corresponding registers bit field.

CCM_REG_OFF(root, off): CCM reg macros to map corresponding registers.

CCM_REG(root)

CCM_REG_SET(root)

CCM_REG_CLR(root)

AUDIO_PLL1_CFG0_OFFSET: CCM Analog registers offset.

AUDIO_PLL2_CFG0_OFFSET

VIDEO_PLL1_CFG0_OFFSET

GPU_PLL_CFG0_OFFSET

VPU_PLL_CFG0_OFFSET

ARM_PLL_CFG0_OFFSET

SYS_PLL1_CFG0_OFFSET

SYS_PLL2_CFG0_OFFSET

SYS_PLL3_CFG0_OFFSET

VIDEO_PLL2_CFG0_OFFSET

DRAM_PLL_CFG0_OFFSET

OSC_MISC_CFG_OFFSET

CCM_ANALOG_TUPLE(reg, shift): CCM ANALOG tuple macros to map corresponding registers and bit fields.

CCM_ANALOG_TUPLE_SHIFT(tuple)

CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)

CCM_ANALOG_TUPLE_REG(base, tuple)

CCM_TUPLE(ccgr, root): CCM CCGR and root tuple.

CCM_TUPLE_CCGR(tuple)

CCM_TUPLE_ROOT(tuple)

CLOCK_ROOT_SOURCE: clock root source

CLOCK_ROOT_CONTROL_TUPLE

kCLOCK_CoreSysClk: For compatible with other platforms without CCM.

CLOCK_GetCoreSysClkFreq: For compatible with other platforms without CCM.

static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)

Set clock root mux. User maybe need to set more than one mux ROOT according to the clock tree description in the reference manual.

Parameters:

rootClk – Root clock control (see clock_root_control_t enumeration).
mux – Root mux value (see _ccm_rootmux_xxx enumeration).

static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)

Get clock root mux. In order to get the clock source of root, user maybe need to get more than one ROOT’s mux value to obtain the final clock source of root.

Parameters:

rootClk – Root clock control (see clock_root_control_t enumeration).

Returns:

Root mux value (see _ccm_rootmux_xxx enumeration).

static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)

Enable clock root.

Parameters:

rootClk – Root clock control (see clock_root_control_t enumeration)

static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)

Disable clock root.

Parameters:

rootClk – Root control (see clock_root_control_t enumeration)

static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)

Check whether clock root is enabled.

Parameters:

rootClk – Root control (see clock_root_control_t enumeration)

Returns:

CCM root enabled or not.

true: Clock root is enabled.
false: Clock root is disabled.

void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post)

Update clock root in one step, for dynamical clock switching Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value.

Parameters:

ccmRootClk – Root control (see clock_root_control_t enumeration)
mux – root mux value (see _ccm_rootmux_xxx enumeration)
pre – Pre divider value (0-7, divider=n+1)
post – Post divider value (0-63, divider=n+1)

void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post)

Set root clock divider Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value.

Parameters:

ccmRootClk – Root control (see clock_root_control_t enumeration)
pre – Pre divider value (1-8)
post – Post divider value (1-64)

static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)

Get clock root PRE_PODF. In order to get the clock source of root, user maybe need to get more than one ROOT’s mux value to obtain the final clock source of root.

Parameters:

rootClk – Root clock name (see clock_root_control_t enumeration).

Returns:

Root Pre divider value.

static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)

Get clock root POST_PODF. In order to get the clock source of root, user maybe need to get more than one ROOT’s mux value to obtain the final clock source of root.

Parameters:

rootClk – Root clock name (see clock_root_control_t enumeration).

Returns:

Root Post divider value.

void CLOCK_InitOSC25M(const osc_config_t *config)

OSC25M init.

Parameters:

config – osc configuration.

void CLOCK_DeinitOSC25M(void): OSC25M deinit.

void CLOCK_InitOSC27M(const osc_config_t *config)

OSC27M init.

Parameters:

config – osc configuration.

void CLOCK_DeinitOSC27M(void): OSC27M deinit.

static inline void CLOCK_SwitchOSC32Src(osc32_src_t sel)

switch 32KHZ OSC input

Parameters:

sel – OSC32 input clock select

static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control)

Set PLL or CCGR gate control.

Parameters:

ccmGate – Gate control (see clock_pll_gate_t and clock_ip_name_t enumeration)
control – Gate control value (see clock_gate_value_t)

void CLOCK_EnableClock(clock_ip_name_t ccmGate)

Enable CCGR clock gate and root clock gate for each module User should set specific gate for each module according to the description of the table of system clocks, gating and override in CCM chapter of reference manual. Take care of that one module may need to set more than one clock gate.

Parameters:

ccmGate – Gate control for each module (see clock_ip_name_t enumeration).

void CLOCK_DisableClock(clock_ip_name_t ccmGate)

Disable CCGR clock gate for the each module User should set specific gate for each module according to the description of the table of system clocks, gating and override in CCM chapter of reference manual. Take care of that one module may need to set more than one clock gate.

Parameters:

ccmGate – Gate control for each module (see clock_ip_name_t enumeration).

static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)

Power up PLL.

Parameters:

base – CCM_ANALOG base pointer.
pllControl – PLL control name (see clock_pll_ctrl_t enumeration)

static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)

Power down PLL.

Parameters:

base – CCM_ANALOG base pointer.
pllControl – PLL control name (see clock_pll_ctrl_t enumeration)

static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)

PLL bypass setting.

Parameters:

base – CCM_ANALOG base pointer.
pllControl – PLL control name (see ccm_analog_pll_control_t enumeration)
bypass – Bypass the PLL.
- true: Bypass the PLL.
- false: Do not bypass the PLL.

static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)

Check if PLL is bypassed.

Parameters:

base – CCM_ANALOG base pointer.
pllControl – PLL control name (see ccm_analog_pll_control_t enumeration)

Returns:

PLL bypass status.

true: The PLL is bypassed.
false: The PLL is not bypassed.

static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)

Check if PLL clock is locked.

Parameters:

base – CCM_ANALOG base pointer.
pllControl – PLL control name (see clock_pll_ctrl_t enumeration)

Returns:

PLL lock status.

true: The PLL clock is locked.
false: The PLL clock is not locked.

static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)

Enable PLL clock.

Parameters:

base – CCM_ANALOG base pointer.
pllClock – PLL clock name (see ccm_analog_pll_clock_t enumeration)

static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)

Disable PLL clock.

Parameters:

base – CCM_ANALOG base pointer.
pllClock – PLL clock name (see ccm_analog_pll_clock_t enumeration)

static inline void CLOCK_OverrideAnalogClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)

Override PLL clock output enable.

Parameters:

base – CCM_ANALOG base pointer.
ovClock – PLL clock name (see clock_pll_clke_t enumeration)
override – Override the PLL.
- true: Override the PLL clke, CCM will handle it.
- false: Do not override the PLL clke.

static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)

Override PLL power down.

Parameters:

base – CCM_ANALOG base pointer.
pdClock – PLL clock name (see clock_pll_ctrl_t enumeration)
override – Override the PLL.
- true: Override the PLL clke, CCM will handle it.
- false: Do not override the PLL clke.

void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config)

Initializes the ANALOG ARM PLL.

Note

This function can’t detect whether the Arm PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

void CLOCK_DeinitArmPll(void): De-initialize the ARM PLL.

void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config)

Initializes the ANALOG SYS PLL1.

Note

This function can’t detect whether the SYS PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).

void CLOCK_DeinitSysPll1(void): De-initialize the System PLL1.

void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config)

Initializes the ANALOG SYS PLL2.

Note

This function can’t detect whether the SYS PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).

void CLOCK_DeinitSysPll2(void): De-initialize the System PLL2.

void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config)

Initializes the ANALOG SYS PLL3.

Note

This function can’t detect whether the SYS PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).

void CLOCK_DeinitSysPll3(void): De-initialize the System PLL3.

void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config)

Initializes the ANALOG DDR PLL.

Note

This function can’t detect whether the DDR PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).

void CLOCK_DeinitDramPll(void): De-initialize the Dram PLL.

void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config)

Initializes the ANALOG AUDIO PLL1.

Note

This function can’t detect whether the AUDIO PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

void CLOCK_DeinitAudioPll1(void): De-initialize the Audio PLL1.

void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config)

Initializes the ANALOG AUDIO PLL2.

Note

This function can’t detect whether the AUDIO PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

void CLOCK_DeinitAudioPll2(void): De-initialize the Audio PLL2.

void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config)

Initializes the ANALOG VIDEO PLL1.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).

void CLOCK_DeinitVideoPll1(void): De-initialize the Video PLL1.

void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config)

Initializes the ANALOG VIDEO PLL2.

Note

This function can’t detect whether the VIDEO PLL has been enabled and used by some IPs.

Parameters:

config – Pointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).

void CLOCK_DeinitVideoPll2(void): De-initialize the Video PLL2.

void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type)

Initializes the ANALOG SSCG PLL.

Parameters:

base – CCM ANALOG base address
config – Pointer to the configuration structure(see ccm_analog_sscg_pll_config_t enumeration).
type – sscg pll type

uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass)

Get the ANALOG SSCG PLL clock frequency.

Parameters:

base – CCM ANALOG base address.
type – sscg pll type
refClkFreq – reference clock frequency
pll1Bypass – pll1 bypass flag

Returns:

Clock frequency

void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type)

Initializes the ANALOG Fractional PLL.

Parameters:

base – CCM ANALOG base address.
config – Pointer to the configuration structure(see ccm_analog_frac_pll_config_t enumeration).
type – fractional pll type.

uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq)

Gets the ANALOG Fractional PLL clock frequency.

Parameters:

base – CCM_ANALOG base pointer.
type – fractional pll type.
refClkFreq – reference clock frequency

Returns:

Clock frequency

uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll)

Gets PLL clock frequency.

Parameters:

pll – fractional pll type.

Returns:

Clock frequency

uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl)

Gets PLL reference clock frequency.

Parameters:

ctrl – fractional pll type.

Returns:

Clock frequency

uint32_t CLOCK_GetFreq(clock_name_t clockName)

Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters:

clockName – Clock names defined in clock_name_t

Returns:

Clock frequency value in hertz

uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot)

Gets the frequency of selected clock root.

Parameters:

clockRoot – The clock root used to get the frequency, please refer to clock_root_t.

Returns:

The frequency of selected clock root.

uint32_t CLOCK_GetCoreM4Freq(void)

Get the CCM Cortex M4 core frequency.

Returns:: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAxiFreq(void)

Get the CCM Axi bus frequency.

Returns:: Clock frequency; If the clock is invalid, returns 0.

uint32_t CLOCK_GetAhbFreq(void)

Get the CCM Ahb bus frequency.

Returns:: Clock frequency; If the clock is invalid, returns 0.

uint8_t oscMode: ext or osc mode

uint8_t oscDiv: osc divider

uint8_t refSel: pll reference clock sel

uint8_t refDiv: A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ

uint32_t fractionDiv: Inlcude fraction divider(divider:1:2^24) output clock range is 2000MHZ-4000MHZ

uint8_t intDiv

uint8_t outDiv: output clock divide, output clock range is 30MHZ to 2000MHZ, must be a even value

uint8_t refSel: pll reference clock sel

uint8_t refDiv1: A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,post_divide REF must be within the range 25MHZ~54MHZ

uint8_t refDiv2: A 6bit divider to make sure the post_divide REF must be within the range 54MHZ~75MHZ

uint32_t loopDivider1: A 6bit internal PLL1 feedback clock divider, output clock range must be within the range 1600MHZ-2400MHZ

uint32_t loopDivider2: A 6bit internal PLL2 feedback clock divider, output clock range must be within the range 1200MHZ-2400MHZ

uint8_t outDiv: A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ

struct _osc_config: #include <fsl_clock.h>

OSC configuration structure.

struct _ccm_analog_frac_pll_config: #include <fsl_clock.h>

Fractional-N PLL configuration. Note: all the dividers in this configuration structure are the actually divider, software will map it to register value.

struct _ccm_analog_sscg_pll_config: #include <fsl_clock.h>

SSCG PLL configuration. Note: all the dividers in this configuration structure are the actually divider, software will map it to register value.

ECSPI: Enhanced Configurable Serial Peripheral Interface Driver#

ECSPI Driver#

void ECSPI_MasterGetDefaultConfig(ecspi_master_config_t *config)

Sets the ECSPI configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in ECSPI_MasterInit(). User may use the initialized structure unchanged in ECSPI_MasterInit, or modify some fields of the structure before calling ECSPI_MasterInit. After calling this API, the master is ready to transfer. Example:

ecspi_master_config_t config;
ECSPI_MasterGetDefaultConfig(&config);

Parameters:

config – pointer to config structure

void ECSPI_MasterInit(ECSPI_Type *base, const ecspi_master_config_t *config, uint32_t srcClock_Hz)

Initializes the ECSPI with configuration.

The configuration structure can be filled by user from scratch, or be set with default values by ECSPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. Example

ecspi_master_config_t config = {
.baudRate_Bps = 400000,
...
};
ECSPI_MasterInit(ECSPI0, &config);

Parameters:

base – ECSPI base pointer
config – pointer to master configuration structure
srcClock_Hz – Source clock frequency.

void ECSPI_SlaveGetDefaultConfig(ecspi_slave_config_t *config)

Sets the ECSPI configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in ECSPI_SlaveInit(). User may use the initialized structure unchanged in ECSPI_SlaveInit(), or modify some fields of the structure before calling ECSPI_SlaveInit(). After calling this API, the master is ready to transfer. Example:

ecspi_Slaveconfig_t config;
ECSPI_SlaveGetDefaultConfig(&config);

Parameters:

config – pointer to config structure

void ECSPI_SlaveInit(ECSPI_Type *base, const ecspi_slave_config_t *config)

Initializes the ECSPI with configuration.

The configuration structure can be filled by user from scratch, or be set with default values by ECSPI_SlaveGetDefaultConfig(). After calling this API, the slave is ready to transfer. Example

ecspi_Salveconfig_t config = {
.baudRate_Bps = 400000,
...
};
ECSPI_SlaveInit(ECSPI1, &config);

Parameters:

base – ECSPI base pointer
config – pointer to master configuration structure

void ECSPI_Deinit(ECSPI_Type *base)

De-initializes the ECSPI.

Calling this API resets the ECSPI module, gates the ECSPI clock. The ECSPI module can’t work unless calling the ECSPI_MasterInit/ECSPI_SlaveInit to initialize module.

Parameters:

base – ECSPI base pointer

static inline void ECSPI_Enable(ECSPI_Type *base, bool enable)

Enables or disables the ECSPI.

Parameters:

base – ECSPI base pointer
enable – pass true to enable module, false to disable module

static inline uint32_t ECSPI_GetStatusFlags(ECSPI_Type *base)

Gets the status flag.

Parameters:

base – ECSPI base pointer

Returns:

ECSPI Status, use status flag to AND _ecspi_flags could get the related status.

static inline void ECSPI_ClearStatusFlags(ECSPI_Type *base, uint32_t mask)

Clear the status flag.

Parameters:

base – ECSPI base pointer
mask – ECSPI Status, use status flag to AND _ecspi_flags could get the related status.

static inline void ECSPI_EnableInterrupts(ECSPI_Type *base, uint32_t mask)

Enables the interrupt for the ECSPI.

Parameters:

base – ECSPI base pointer
mask – ECSPI interrupt source. The parameter can be any combination of the following values:
- kECSPI_TxfifoEmptyInterruptEnable
- kECSPI_TxFifoDataRequstInterruptEnable
- kECSPI_TxFifoFullInterruptEnable
- kECSPI_RxFifoReadyInterruptEnable
- kECSPI_RxFifoDataRequstInterruptEnable
- kECSPI_RxFifoFullInterruptEnable
- kECSPI_RxFifoOverFlowInterruptEnable
- kECSPI_TransferCompleteInterruptEnable
- kECSPI_AllInterruptEnable

static inline void ECSPI_DisableInterrupts(ECSPI_Type *base, uint32_t mask)

Disables the interrupt for the ECSPI.

Parameters:

base – ECSPI base pointer
mask – ECSPI interrupt source. The parameter can be any combination of the following values:
- kECSPI_TxfifoEmptyInterruptEnable
- kECSPI_TxFifoDataRequstInterruptEnable
- kECSPI_TxFifoFullInterruptEnable
- kECSPI_RxFifoReadyInterruptEnable
- kECSPI_RxFifoDataRequstInterruptEnable
- kECSPI_RxFifoFullInterruptEnable
- kECSPI_RxFifoOverFlowInterruptEnable
- kECSPI_TransferCompleteInterruptEnable
- kECSPI_AllInterruptEnable

static inline void ECSPI_SoftwareReset(ECSPI_Type *base)

Software reset.

Parameters:

base – ECSPI base pointer

static inline bool ECSPI_IsMaster(ECSPI_Type *base, ecspi_channel_source_t channel)

Mode check.

Parameters:

base – ECSPI base pointer
channel – ECSPI channel source

Returns:

mode of channel

static inline void ECSPI_EnableDMA(ECSPI_Type *base, uint32_t mask, bool enable)

Enables the DMA source for ECSPI.

Parameters:

base – ECSPI base pointer
mask – ECSPI DMA source. The parameter can be any of the following values:
- kECSPI_TxDmaEnable
- kECSPI_RxDmaEnable
- kECSPI_DmaAllEnable
enable – True means enable DMA, false means disable DMA

static inline uint8_t ECSPI_GetTxFifoCount(ECSPI_Type *base)

Get the Tx FIFO data count.

Parameters:

base – ECSPI base pointer.

Returns:

the number of words in Tx FIFO buffer.

static inline uint8_t ECSPI_GetRxFifoCount(ECSPI_Type *base)

Get the Rx FIFO data count.

Parameters:

base – ECSPI base pointer.

Returns:

the number of words in Rx FIFO buffer.

static inline void ECSPI_SetChannelSelect(ECSPI_Type *base, ecspi_channel_source_t channel)

Set channel select for transfer.

Parameters:

base – ECSPI base pointer
channel – Channel source.

void ECSPI_SetChannelConfig(ECSPI_Type *base, ecspi_channel_source_t channel, const ecspi_channel_config_t *config)

Set channel select configuration for transfer.

The purpose of this API is to set the channel will be use to transfer. User may use this API after instance has been initialized or before transfer start. The configuration structure ecspi_channel_config can be filled by user from scratch. After calling this API, user can select this channel as transfer channel.

Parameters:

base – ECSPI base pointer
channel – Channel source.
config – Configuration struct of channel

void ECSPI_SetBaudRate(ECSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the baud rate for ECSPI transfer. This is only used in master.

Parameters:

base – ECSPI base pointer
baudRate_Bps – baud rate needed in Hz.
srcClock_Hz – ECSPI source clock frequency in Hz.

status_t ECSPI_WriteBlocking(ECSPI_Type *base, const uint32_t *buffer, size_t size)

Sends a buffer of data bytes using a blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – ECSPI base pointer
buffer – The data bytes to send
size – The number of data bytes to send

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_ECSPI_Timeout – The transfer timed out and was aborted.

static inline void ECSPI_WriteData(ECSPI_Type *base, uint32_t data)

Writes a data into the ECSPI data register.

Parameters:

base – ECSPI base pointer
data – Data needs to be write.

static inline uint32_t ECSPI_ReadData(ECSPI_Type *base)

Gets a data from the ECSPI data register.

Parameters:

base – ECSPI base pointer

Returns:

Data in the register.

void ECSPI_MasterTransferCreateHandle(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_master_callback_t callback, void *userData)

Initializes the ECSPI master handle.

This function initializes the ECSPI master handle which can be used for other ECSPI master transactional APIs. Usually, for a specified ECSPI instance, call this API once to get the initialized handle.

Parameters:

base – ECSPI peripheral base address.
handle – ECSPI handle pointer.
callback – Callback function.
userData – User data.

status_t ECSPI_MasterTransferBlocking(ECSPI_Type *base, ecspi_transfer_t *xfer)

Transfers a block of data using a polling method.

Parameters:

base – SPI base pointer
xfer – pointer to spi_xfer_config_t structure

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_ECSPI_Timeout – The transfer timed out and was aborted.

status_t ECSPI_MasterTransferNonBlocking(ECSPI_Type *base, ecspi_master_handle_t *handle, ecspi_transfer_t *xfer)

Performs a non-blocking ECSPI interrupt transfer.

Note

The API immediately returns after transfer initialization is finished.

Note

If ECSPI transfer data frame size is 16 bits, the transfer size cannot be an odd number.

Parameters:

base – ECSPI peripheral base address.
handle – pointer to ecspi_master_handle_t structure which stores the transfer state
xfer – pointer to ecspi_transfer_t structure

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_ECSPI_Busy – ECSPI is not idle, is running another transfer.

status_t ECSPI_MasterTransferGetCount(ECSPI_Type *base, ecspi_master_handle_t *handle, size_t *count)

Gets the bytes of the ECSPI interrupt transferred.

Parameters:

base – ECSPI peripheral base address.
handle – Pointer to ECSPI transfer handle, this should be a static variable.
count – Transferred bytes of ECSPI master.

Return values:

kStatus_ECSPI_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void ECSPI_MasterTransferAbort(ECSPI_Type *base, ecspi_master_handle_t *handle)

Aborts an ECSPI transfer using interrupt.

Parameters:

base – ECSPI peripheral base address.
handle – Pointer to ECSPI transfer handle, this should be a static variable.

void ECSPI_MasterTransferHandleIRQ(ECSPI_Type *base, ecspi_master_handle_t *handle)

Interrupts the handler for the ECSPI.

Parameters:

base – ECSPI peripheral base address.
handle – pointer to ecspi_master_handle_t structure which stores the transfer state.

void ECSPI_SlaveTransferCreateHandle(ECSPI_Type *base, ecspi_slave_handle_t *handle, ecspi_slave_callback_t callback, void *userData)

Initializes the ECSPI slave handle.

This function initializes the ECSPI slave handle which can be used for other ECSPI slave transactional APIs. Usually, for a specified ECSPI instance, call this API once to get the initialized handle.

Parameters:

base – ECSPI peripheral base address.
handle – ECSPI handle pointer.
callback – Callback function.
userData – User data.

static inline status_t ECSPI_SlaveTransferNonBlocking(ECSPI_Type *base, ecspi_slave_handle_t *handle, ecspi_transfer_t *xfer)

Performs a non-blocking ECSPI slave interrupt transfer.

Note

The API returns immediately after the transfer initialization is finished.

Parameters:

base – ECSPI peripheral base address.
handle – pointer to ecspi_master_handle_t structure which stores the transfer state
xfer – pointer to ecspi_transfer_t structure

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_ECSPI_Busy – ECSPI is not idle, is running another transfer.

static inline status_t ECSPI_SlaveTransferGetCount(ECSPI_Type *base, ecspi_slave_handle_t *handle, size_t *count)

Gets the bytes of the ECSPI interrupt transferred.

Parameters:

base – ECSPI peripheral base address.
handle – Pointer to ECSPI transfer handle, this should be a static variable.
count – Transferred bytes of ECSPI slave.

Return values:

kStatus_ECSPI_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

static inline void ECSPI_SlaveTransferAbort(ECSPI_Type *base, ecspi_slave_handle_t *handle)

Aborts an ECSPI slave transfer using interrupt.

Parameters:

base – ECSPI peripheral base address.
handle – Pointer to ECSPI transfer handle, this should be a static variable.

void ECSPI_SlaveTransferHandleIRQ(ECSPI_Type *base, ecspi_slave_handle_t *handle)

Interrupts a handler for the ECSPI slave.

Parameters:

base – ECSPI peripheral base address.
handle – pointer to ecspi_slave_handle_t structure which stores the transfer state

FSL_ECSPI_DRIVER_VERSION: ECSPI driver version.

Return status for the ECSPI driver.

Values:

enumerator kStatus_ECSPI_Busy: ECSPI bus is busy

enumerator kStatus_ECSPI_Idle: ECSPI is idle

enumerator kStatus_ECSPI_Error: ECSPI error

enumerator kStatus_ECSPI_HardwareOverFlow: ECSPI hardware overflow

enumerator kStatus_ECSPI_Timeout: ECSPI timeout polling status flags.

enum _ecspi_clock_polarity

ECSPI clock polarity configuration.

Values:

enumerator kECSPI_PolarityActiveHigh: Active-high ECSPI polarity high (idles low).

enumerator kECSPI_PolarityActiveLow: Active-low ECSPI polarity low (idles high).

enum _ecspi_clock_phase

ECSPI clock phase configuration.

Values:

enumerator kECSPI_ClockPhaseFirstEdge: First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

enumerator kECSPI_ClockPhaseSecondEdge: First edge on SPSCK occurs at the start of the first cycle of a data transfer.

ECSPI interrupt sources.

Values:

enumerator kECSPI_TxfifoEmptyInterruptEnable: Transmit FIFO buffer empty interrupt

enumerator kECSPI_TxFifoDataRequstInterruptEnable: Transmit FIFO data requst interrupt

enumerator kECSPI_TxFifoFullInterruptEnable: Transmit FIFO full interrupt

enumerator kECSPI_RxFifoReadyInterruptEnable: Receiver FIFO ready interrupt

enumerator kECSPI_RxFifoDataRequstInterruptEnable: Receiver FIFO data requst interrupt

enumerator kECSPI_RxFifoFullInterruptEnable: Receiver FIFO full interrupt

enumerator kECSPI_RxFifoOverFlowInterruptEnable: Receiver FIFO buffer overflow interrupt

enumerator kECSPI_TransferCompleteInterruptEnable: Transfer complete interrupt

enumerator kECSPI_AllInterruptEnable: All interrupt

ECSPI status flags.

Values:

enumerator kECSPI_TxfifoEmptyFlag: Transmit FIFO buffer empty flag

enumerator kECSPI_TxFifoDataRequstFlag: Transmit FIFO data requst flag

enumerator kECSPI_TxFifoFullFlag: Transmit FIFO full flag

enumerator kECSPI_RxFifoReadyFlag: Receiver FIFO ready flag

enumerator kECSPI_RxFifoDataRequstFlag: Receiver FIFO data requst flag

enumerator kECSPI_RxFifoFullFlag: Receiver FIFO full flag

enumerator kECSPI_RxFifoOverFlowFlag: Receiver FIFO buffer overflow flag

enumerator kECSPI_TransferCompleteFlag: Transfer complete flag

ECSPI DMA enable.

Values:

enumerator kECSPI_TxDmaEnable: Tx DMA request source

enumerator kECSPI_RxDmaEnable: Rx DMA request source

enumerator kECSPI_DmaAllEnable: All DMA request source

enum _ecspi_data_ready

ECSPI SPI_RDY signal configuration.

Values:

enumerator kECSPI_DataReadyIgnore: SPI_RDY signal is ignored

enumerator kECSPI_DataReadyFallingEdge: SPI_RDY signal will be triggerd by the falling edge

enumerator kECSPI_DataReadyLowLevel: SPI_RDY signal will be triggerd by a low level

enum _ecspi_channel_source

ECSPI channel select source.

Values:

enumerator kECSPI_Channel0: Channel 0 is selectd

enumerator kECSPI_Channel1: Channel 1 is selectd

enumerator kECSPI_Channel2: Channel 2 is selectd

enumerator kECSPI_Channel3: Channel 3 is selectd

enum _ecspi_master_slave_mode

ECSPI master or slave mode configuration.

Values:

enumerator kECSPI_Slave: ECSPI peripheral operates in slave mode.

enumerator kECSPI_Master: ECSPI peripheral operates in master mode.

enum _ecspi_data_line_inactive_state_t

ECSPI data line inactive state configuration.

Values:

enumerator kECSPI_DataLineInactiveStateHigh: The data line inactive state stays high.

enumerator kECSPI_DataLineInactiveStateLow: The data line inactive state stays low.

enum _ecspi_clock_inactive_state_t

ECSPI clock inactive state configuration.

Values:

enumerator kECSPI_ClockInactiveStateLow: The SCLK inactive state stays low.

enumerator kECSPI_ClockInactiveStateHigh: The SCLK inactive state stays high.

enum _ecspi_chip_select_active_state_t

ECSPI active state configuration.

Values:

enumerator kECSPI_ChipSelectActiveStateLow: The SS signal line active stays low.

enumerator kECSPI_ChipSelectActiveStateHigh: The SS signal line active stays high.

enum _ecspi_sample_period_clock_source

ECSPI sample period clock configuration.

Values:

enumerator kECSPI_spiClock: The sample period clock source is SCLK.

enumerator kECSPI_lowFreqClock: The sample seriod clock source is low_frequency reference clock(32.768 kHz).

typedef enum _ecspi_clock_polarity ecspi_clock_polarity_t: ECSPI clock polarity configuration.

typedef enum _ecspi_clock_phase ecspi_clock_phase_t: ECSPI clock phase configuration.

typedef enum _ecspi_data_ready ecspi_Data_ready_t: ECSPI SPI_RDY signal configuration.

typedef enum _ecspi_channel_source ecspi_channel_source_t: ECSPI channel select source.

typedef enum _ecspi_master_slave_mode ecspi_master_slave_mode_t: ECSPI master or slave mode configuration.

typedef enum _ecspi_data_line_inactive_state_t ecspi_data_line_inactive_state_t: ECSPI data line inactive state configuration.

typedef enum _ecspi_clock_inactive_state_t ecspi_clock_inactive_state_t: ECSPI clock inactive state configuration.

typedef enum _ecspi_chip_select_active_state_t ecspi_chip_select_active_state_t: ECSPI active state configuration.

typedef enum _ecspi_sample_period_clock_source ecspi_sample_period_clock_source_t: ECSPI sample period clock configuration.

typedef struct _ecspi_channel_config ecspi_channel_config_t: ECSPI user channel configure structure.

typedef struct _ecspi_master_config ecspi_master_config_t: ECSPI master configure structure.

typedef struct _ecspi_slave_config ecspi_slave_config_t: ECSPI slave configure structure.

typedef struct _ecspi_transfer ecspi_transfer_t: ECSPI transfer structure.

typedef struct _ecspi_master_handle ecspi_master_handle_t

typedef ecspi_master_handle_t ecspi_slave_handle_t: Slave handle is the same with master handle

typedef void (*ecspi_master_callback_t)(ECSPI_Type *base, ecspi_master_handle_t *handle, status_t status, void *userData): ECSPI master callback for finished transmit.

typedef void (*ecspi_slave_callback_t)(ECSPI_Type *base, ecspi_slave_handle_t *handle, status_t status, void *userData): ECSPI slave callback for finished transmit.

uint32_t ECSPI_GetInstance(ECSPI_Type *base)

Get the instance for ECSPI module.

Parameters:

base – ECSPI base address

ECSPI_DUMMYDATA: ECSPI dummy transfer data, the data is sent while txBuff is NULL.

SPI_RETRY_TIMES: Retry times for waiting flag.

struct _ecspi_channel_config

#include <fsl_ecspi.h>

ECSPI user channel configure structure.

Public Members

ecspi_master_slave_mode_t channelMode: Channel mode

ecspi_clock_inactive_state_t clockInactiveState: Clock line (SCLK) inactive state

ecspi_data_line_inactive_state_t dataLineInactiveState: Data line (MOSI&MISO) inactive state

ecspi_chip_select_active_state_t chipSlectActiveState: Chip select(SS) line active state

ecspi_clock_polarity_t polarity: Clock polarity

ecspi_clock_phase_t phase: Clock phase

struct _ecspi_master_config

#include <fsl_ecspi.h>

ECSPI master configure structure.

Public Members

ecspi_channel_source_t channel: Channel number

ecspi_channel_config_t channelConfig: Channel configuration

ecspi_sample_period_clock_source_t samplePeriodClock: Sample period clock source

uint16_t burstLength: Burst length. The length shall be less than 4096 bits

uint8_t chipSelectDelay: SS delay time

uint16_t samplePeriod: Sample period

uint8_t txFifoThreshold: TX Threshold

uint8_t rxFifoThreshold: RX Threshold

uint32_t baudRate_Bps: ECSPI baud rate for master mode

bool enableLoopback: Enable the ECSPI loopback test.

struct _ecspi_slave_config

#include <fsl_ecspi.h>

ECSPI slave configure structure.

Public Members

uint16_t burstLength: Burst length. The length shall be less than 4096 bits

uint8_t txFifoThreshold: TX Threshold

uint8_t rxFifoThreshold: RX Threshold

ecspi_channel_config_t channelConfig: Channel configuration

struct _ecspi_transfer

#include <fsl_ecspi.h>

ECSPI transfer structure.

Public Members

const uint32_t *txData: Send buffer

uint32_t *rxData: Receive buffer

size_t dataSize: Transfer bytes

ecspi_channel_source_t channel: ECSPI channel select

struct _ecspi_master_handle

#include <fsl_ecspi.h>

ECSPI master handle structure.

Public Members

ecspi_channel_source_t channel: Channel number

const uint32_t *volatile txData: Transfer buffer

uint32_t *volatile rxData: Receive buffer

volatile size_t txRemainingBytes: Send data remaining in bytes

volatile size_t rxRemainingBytes: Receive data remaining in bytes

volatile uint32_t state: ECSPI internal state

size_t transferSize: Bytes to be transferred

ecspi_master_callback_t callback: ECSPI callback

void *userData: Callback parameter

GPIO: General-Purpose Input/Output Driver#

void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)

Initializes the GPIO peripheral according to the specified parameters in the initConfig.

Parameters:

base – GPIO base pointer.
pin – Specifies the pin number
Config – pointer to a gpio_pin_config_t structure that contains the configuration information.

void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the individual GPIO pin to logic 1 or 0.

Parameters:

base – GPIO base pointer.
pin – GPIO port pin number.
output – GPIOpin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the individual GPIO pin to logic 1 or 0.

Deprecated:: Do not use this function. It has been superceded by GPIO_PinWrite.

static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 1.

Parameters:

base – GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
mask – GPIO pin number macro

static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 1.

Deprecated:: Do not use this function. It has been superceded by GPIO_PortSet.

static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 0.

Parameters:

base – GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
mask – GPIO pin number macro

static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 0.

Deprecated:: Do not use this function. It has been superceded by GPIO_PortClear.

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple GPIO pins.

Parameters:

base – GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
mask – GPIO pin number macro

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)

Reads the current input value of the GPIO port.

Parameters:

base – GPIO base pointer.
pin – GPIO port pin number.

Return values:

GPIO – port input value.

static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)

Reads the current input value of the GPIO port.

Deprecated:: Do not use this function. It has been superceded by GPIO_PinRead.

static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)

Reads the current GPIO pin pad status.

Parameters:

base – GPIO base pointer.
pin – GPIO port pin number.

Return values:

GPIO – pin pad status value.

static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)

Reads the current GPIO pin pad status.

Deprecated:: Do not use this function. It has been superceded by GPIO_PinReadPadStatus.

void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)

Sets the current pin interrupt mode.

Parameters:

base – GPIO base pointer.
pin – GPIO port pin number.
pinInterruptMode – pointer to a gpio_interrupt_mode_t structure that contains the interrupt mode information.

static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)

Sets the current pin interrupt mode.

Deprecated:: Do not use this function. It has been superceded by GPIO_PinSetInterruptConfig.

static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask)

Enables the specific pin interrupt.

Parameters:

base – GPIO base pointer.
mask – GPIO pin number macro.

static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask)

Enables the specific pin interrupt.

Parameters:

base – GPIO base pointer.
mask – GPIO pin number macro.

static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask)

Disables the specific pin interrupt.

Parameters:

base – GPIO base pointer.
mask – GPIO pin number macro.

static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask)

Disables the specific pin interrupt.

Deprecated:: Do not use this function. It has been superceded by GPIO_PortDisableInterrupts.

static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)

Reads individual pin interrupt status.

Parameters:

base – GPIO base pointer.

Return values:

current – pin interrupt status flag.

static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)

Reads individual pin interrupt status.

Parameters:

base – GPIO base pointer.

Return values:

current – pin interrupt status flag.

static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)

Clears pin interrupt flag. Status flags are cleared by writing a 1 to the corresponding bit position.

Parameters:

base – GPIO base pointer.
mask – GPIO pin number macro.

static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)

Clears pin interrupt flag. Status flags are cleared by writing a 1 to the corresponding bit position.

Parameters:

base – GPIO base pointer.
mask – GPIO pin number macro.

FSL_GPIO_DRIVER_VERSION: GPIO driver version.

enum _gpio_pin_direction

GPIO direction definition.

Values:

enumerator kGPIO_DigitalInput: Set current pin as digital input.

enumerator kGPIO_DigitalOutput: Set current pin as digital output.

enum _gpio_interrupt_mode

GPIO interrupt mode definition.

Values:

enumerator kGPIO_NoIntmode: Set current pin general IO functionality.

enumerator kGPIO_IntLowLevel: Set current pin interrupt is low-level sensitive.

enumerator kGPIO_IntHighLevel: Set current pin interrupt is high-level sensitive.

enumerator kGPIO_IntRisingEdge: Set current pin interrupt is rising-edge sensitive.

enumerator kGPIO_IntFallingEdge: Set current pin interrupt is falling-edge sensitive.

enumerator kGPIO_IntRisingOrFallingEdge: Enable the edge select bit to override the ICR register’s configuration.

typedef enum _gpio_pin_direction gpio_pin_direction_t: GPIO direction definition.

typedef enum _gpio_interrupt_mode gpio_interrupt_mode_t: GPIO interrupt mode definition.

typedef struct _gpio_pin_config gpio_pin_config_t: GPIO Init structure definition.

struct _gpio_pin_config

#include <fsl_gpio.h>

GPIO Init structure definition.

Public Members

gpio_pin_direction_t direction: Specifies the pin direction.

uint8_t outputLogic: Set a default output logic, which has no use in input

gpio_interrupt_mode_t interruptMode: Specifies the pin interrupt mode, a value of gpio_interrupt_mode_t.

GPT: General Purpose Timer#

void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)

Initialize GPT to reset state and initialize running mode.

Parameters:

base – GPT peripheral base address.
initConfig – GPT mode setting configuration.

void GPT_Deinit(GPT_Type *base)

Disables the module and gates the GPT clock.

Parameters:

base – GPT peripheral base address.

void GPT_GetDefaultConfig(gpt_config_t *config)

Fills in the GPT configuration structure with default settings.

The default values are:

config->clockSource = kGPT_ClockSource_Periph;
config->divider = 1U;
config->enableRunInStop = true;
config->enableRunInWait = true;
config->enableRunInDoze = false;
config->enableRunInDbg = false;
config->enableFreeRun = false;
config->enableMode  = true;

Parameters:

config – Pointer to the user configuration structure.

static inline void GPT_SoftwareReset(GPT_Type *base)

Software reset of GPT module.

Parameters:

base – GPT peripheral base address.

static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource)

Set clock source of GPT.

Parameters:

base – GPT peripheral base address.
gptClkSource – Clock source (see gpt_clock_source_t typedef enumeration).

static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base)

Get clock source of GPT.

Parameters:

base – GPT peripheral base address.

Returns:

clock source (see gpt_clock_source_t typedef enumeration).

static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider)

Set pre scaler of GPT.

Parameters:

base – GPT peripheral base address.
divider – Divider of GPT (1-4096).

static inline uint32_t GPT_GetClockDivider(GPT_Type *base)

Get clock divider in GPT module.

Parameters:

base – GPT peripheral base address.

Returns:

clock divider in GPT module (1-4096).

static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider)

OSC 24M pre-scaler before selected by clock source.

Parameters:

base – GPT peripheral base address.
divider – OSC Divider(1-16).

static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base)

Get OSC 24M clock divider in GPT module.

Parameters:

base – GPT peripheral base address.

Returns:

OSC clock divider in GPT module (1-16).

static inline void GPT_StartTimer(GPT_Type *base)

Start GPT timer.

Parameters:

base – GPT peripheral base address.

static inline void GPT_StopTimer(GPT_Type *base)

Stop GPT timer.

Parameters:

base – GPT peripheral base address.

static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)

Reads the current GPT counting value.

Parameters:

base – GPT peripheral base address.

Returns:

Current GPT counter value.

static inline void GPT_SetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel, gpt_input_operation_mode_t mode)

Set GPT operation mode of input capture channel.

Parameters:

base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).
mode – GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT operation mode of input capture channel.

Parameters:

base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture operation mode (see gpt_input_operation_mode_t typedef enumeration).

static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel)

Get GPT input capture value of certain channel.

Parameters:

base – GPT peripheral base address.
channel – GPT capture channel (see gpt_input_capture_channel_t typedef enumeration).

Returns:

GPT input capture value.

static inline void GPT_SetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel, gpt_output_operation_mode_t mode)

Set GPT operation mode of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
mode – GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT operation mode of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output operation mode (see gpt_output_operation_mode_t typedef enumeration).

static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)

Set GPT output compare value of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).
value – GPT output compare value.

static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel)

Get GPT output compare value of output compare channel.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

Returns:

GPT output compare value.

static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel)

Force GPT output action on output compare channel, ignoring comparator.

Parameters:

base – GPT peripheral base address.
channel – GPT output compare channel (see gpt_output_compare_channel_t typedef enumeration).

static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)

Enables the selected GPT interrupts.

Parameters:

base – GPT peripheral base address.
mask – The interrupts to enable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)

Disables the selected GPT interrupts.

Parameters:

base – GPT peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)

Gets the enabled GPT interrupts.

Parameters:

base – GPT peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration gpt_interrupt_enable_t

static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Get GPT status flags.

Parameters:

base – GPT peripheral base address.
flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

Returns:

GPT status, each bit represents one status flag.

static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags)

Clears the GPT status flags.

Parameters:

base – GPT peripheral base address.
flags – GPT status flag mask (see gpt_status_flag_t for bit definition).

FSL_GPT_DRIVER_VERSION

enum _gpt_clock_source

List of clock sources.

Note

Actual number of clock sources is SoC dependent

Values:

enumerator kGPT_ClockSource_Off: GPT Clock Source Off.

enumerator kGPT_ClockSource_Periph: GPT Clock Source from Peripheral Clock.

enumerator kGPT_ClockSource_HighFreq: GPT Clock Source from High Frequency Reference Clock.

enumerator kGPT_ClockSource_Ext: GPT Clock Source from external pin.

enumerator kGPT_ClockSource_LowFreq: GPT Clock Source from Low Frequency Reference Clock.

enumerator kGPT_ClockSource_Osc: GPT Clock Source from Crystal oscillator.

enum _gpt_input_capture_channel

List of input capture channel number.

Values:

enumerator kGPT_InputCapture_Channel1: GPT Input Capture Channel1.

enumerator kGPT_InputCapture_Channel2: GPT Input Capture Channel2.

enum _gpt_input_operation_mode

List of input capture operation mode.

Values:

enumerator kGPT_InputOperation_Disabled: Don’t capture.

enumerator kGPT_InputOperation_RiseEdge: Capture on rising edge of input pin.

enumerator kGPT_InputOperation_FallEdge: Capture on falling edge of input pin.

enumerator kGPT_InputOperation_BothEdge: Capture on both edges of input pin.

enum _gpt_output_compare_channel

List of output compare channel number.

Values:

enumerator kGPT_OutputCompare_Channel1: Output Compare Channel1.

enumerator kGPT_OutputCompare_Channel2: Output Compare Channel2.

enumerator kGPT_OutputCompare_Channel3: Output Compare Channel3.

enum _gpt_output_operation_mode

List of output compare operation mode.

Values:

enumerator kGPT_OutputOperation_Disconnected: Don’t change output pin.

enumerator kGPT_OutputOperation_Toggle: Toggle output pin.

enumerator kGPT_OutputOperation_Clear: Set output pin low.

enumerator kGPT_OutputOperation_Set: Set output pin high.

enumerator kGPT_OutputOperation_Activelow: Generate a active low pulse on output pin.

enum _gpt_interrupt_enable

List of GPT interrupts.

Values:

enumerator kGPT_OutputCompare1InterruptEnable: Output Compare Channel1 interrupt enable

enumerator kGPT_OutputCompare2InterruptEnable: Output Compare Channel2 interrupt enable

enumerator kGPT_OutputCompare3InterruptEnable: Output Compare Channel3 interrupt enable

enumerator kGPT_InputCapture1InterruptEnable: Input Capture Channel1 interrupt enable

enumerator kGPT_InputCapture2InterruptEnable: Input Capture Channel1 interrupt enable

enumerator kGPT_RollOverFlagInterruptEnable: Counter rolled over interrupt enable

enum _gpt_status_flag

Status flag.

Values:

enumerator kGPT_OutputCompare1Flag: Output compare channel 1 event.

enumerator kGPT_OutputCompare2Flag: Output compare channel 2 event.

enumerator kGPT_OutputCompare3Flag: Output compare channel 3 event.

enumerator kGPT_InputCapture1Flag: Input Capture channel 1 event.

enumerator kGPT_InputCapture2Flag: Input Capture channel 2 event.

enumerator kGPT_RollOverFlag: Counter reaches maximum value and rolled over to 0 event.

typedef enum _gpt_clock_source gpt_clock_source_t: List of clock sources.

Note

Actual number of clock sources is SoC dependent

typedef enum _gpt_input_capture_channel gpt_input_capture_channel_t: List of input capture channel number.

typedef enum _gpt_input_operation_mode gpt_input_operation_mode_t: List of input capture operation mode.

typedef enum _gpt_output_compare_channel gpt_output_compare_channel_t: List of output compare channel number.

typedef enum _gpt_output_operation_mode gpt_output_operation_mode_t: List of output compare operation mode.

typedef enum _gpt_interrupt_enable gpt_interrupt_enable_t: List of GPT interrupts.

typedef enum _gpt_status_flag gpt_status_flag_t: Status flag.

typedef struct _gpt_init_config gpt_config_t: Structure to configure the running mode.

struct _gpt_init_config

#include <fsl_gpt.h>

Structure to configure the running mode.

Public Members

gpt_clock_source_t clockSource: clock source for GPT module.

uint32_t divider: clock divider (prescaler+1) from clock source to counter.

bool enableFreeRun: true: FreeRun mode, false: Restart mode.

bool enableRunInWait: GPT enabled in wait mode.

bool enableRunInStop: GPT enabled in stop mode.

bool enableRunInDoze: GPT enabled in doze mode.

bool enableRunInDbg: GPT enabled in debug mode.

bool enableMode: true: counter reset to 0 when enabled; false: counter retain its value when enabled.

I2C: Inter-Integrated Circuit Driver#

I2C Driver#

void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the I2C peripheral. Call this API to ungate the I2C clock and configure the I2C with master configuration.

Note

This API should be called at the beginning of the application. Otherwise, any operation to the I2C module can cause a hard fault because the clock is not enabled. The configuration structure can be custom filled or it can be set with default values by using the I2C_MasterGetDefaultConfig(). After calling this API, the master is ready to transfer. This is an example.

i2c_master_config_t config = {
.enableMaster = true,
.baudRate_Bps = 100000
};
I2C_MasterInit(I2C0, &config, 12000000U);

Parameters:

base – I2C base pointer
masterConfig – A pointer to the master configuration structure
srcClock_Hz – I2C peripheral clock frequency in Hz

void I2C_MasterDeinit(I2C_Type *base)

De-initializes the I2C master peripheral. Call this API to gate the I2C clock. The I2C master module can’t work unless the I2C_MasterInit is called.

Parameters:

base – I2C base pointer

void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)

Sets the I2C master configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterInit(). Use the initialized structure unchanged in the I2C_MasterInit() or modify the structure before calling the I2C_MasterInit(). This is an example.

i2c_master_config_t config;
I2C_MasterGetDefaultConfig(&config);

Parameters:

masterConfig – A pointer to the master configuration structure.

void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig)

Initializes the I2C peripheral. Call this API to ungate the I2C clock and initialize the I2C with the slave configuration.

Note

This API should be called at the beginning of the application. Otherwise, any operation to the I2C module can cause a hard fault because the clock is not enabled. The configuration structure can partly be set with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. This is an example.

i2c_slave_config_t config = {
.enableSlave = true,
.slaveAddress = 0x1DU,
};
I2C_SlaveInit(I2C0, &config);

Parameters:

base – I2C base pointer
slaveConfig – A pointer to the slave configuration structure

void I2C_SlaveDeinit(I2C_Type *base)

De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. The I2C slave module can’t work unless the I2C_SlaveInit is called to enable the clock.

Parameters:

base – I2C base pointer

void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)

Sets the I2C slave configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveInit(). Modify fields of the structure before calling the I2C_SlaveInit(). This is an example.

i2c_slave_config_t config;
I2C_SlaveGetDefaultConfig(&config);

Parameters:

slaveConfig – A pointer to the slave configuration structure.

static inline void I2C_Enable(I2C_Type *base, bool enable)

Enables or disables the I2C peripheral operation.

Parameters:

base – I2C base pointer
enable – Pass true to enable and false to disable the module.

static inline uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)

Gets the I2C status flags.

Parameters:

base – I2C base pointer

Returns:

status flag, use status flag to AND _i2c_flags to get the related status.

static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)

Clears the I2C status flag state.

The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag.

Parameters:

base – I2C base pointer
statusMask – The status flag mask, defined in type i2c_status_flag_t. The parameter can be any combination of the following values:
- kI2C_ArbitrationLostFlag
- kI2C_IntPendingFlag

static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)

Gets the I2C status flags.

Parameters:

base – I2C base pointer

Returns:

status flag, use status flag to AND _i2c_flags to get the related status.

static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)

Clears the I2C status flag state.

The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag

Parameters:

base – I2C base pointer
statusMask – The status flag mask, defined in type i2c_status_flag_t. The parameter can be any combination of the following values:
- kI2C_IntPendingFlagFlag

void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)

Enables I2C interrupt requests.

Parameters:

base – I2C base pointer
mask – interrupt source The parameter can be combination of the following source if defined:
- kI2C_GlobalInterruptEnable
- kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
- kI2C_SdaTimeoutInterruptEnable

void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask)

Disables I2C interrupt requests.

Parameters:

base – I2C base pointer
mask – interrupt source The parameter can be combination of the following source if defined:
- kI2C_GlobalInterruptEnable
- kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
- kI2C_SdaTimeoutInterruptEnable

void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the I2C master transfer baud rate.

Parameters:

base – I2C base pointer
baudRate_Bps – the baud rate value in bps
srcClock_Hz – Source clock

status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)

Sends a START on the I2C bus.

This function is used to initiate a new master mode transfer by sending the START signal. The slave address is sent following the I2C START signal.

Parameters:

base – I2C peripheral base pointer
address – 7-bit slave device address.
direction – Master transfer directions(transmit/receive).

Return values:

kStatus_Success – Successfully send the start signal.
kStatus_I2C_Busy – Current bus is busy.

status_t I2C_MasterStop(I2C_Type *base)

Sends a STOP signal on the I2C bus.

Return values:

kStatus_Success – Successfully send the stop signal.
kStatus_I2C_Timeout – Send stop signal failed, timeout.

status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)

Sends a REPEATED START on the I2C bus.

Parameters:

base – I2C peripheral base pointer
address – 7-bit slave device address.
direction – Master transfer directions(transmit/receive).

Return values:

kStatus_Success – Successfully send the start signal.
kStatus_I2C_Busy – Current bus is busy but not occupied by current I2C master.

status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)

Performs a polling send transaction on the I2C bus.

Parameters:

base – The I2C peripheral base pointer.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
flags – Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag to issue a stop and kI2C_TransferNoStop to not send a stop.

Return values:

kStatus_Success – Successfully complete the data transmission.
kStatus_I2C_ArbitrationLost – Transfer error, arbitration lost.
kStataus_I2C_Nak – Transfer error, receive NAK during transfer.

status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)

Performs a polling receive transaction on the I2C bus.

Note

The I2C_MasterReadBlocking function stops the bus before reading the final byte. Without stopping the bus prior for the final read, the bus issues another read, resulting in garbage data being read into the data register.

Parameters:

base – I2C peripheral base pointer.
rxBuff – The pointer to the data to store the received data.
rxSize – The length in bytes of the data to be received.
flags – Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag to issue a stop and kI2C_TransferNoStop to not send a stop.

Return values:

kStatus_Success – Successfully complete the data transmission.
kStatus_I2C_Timeout – Send stop signal failed, timeout.

status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)

Performs a polling send transaction on the I2C bus.

Parameters:

base – The I2C peripheral base pointer.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.

Return values:

kStatus_Success – Successfully complete the data transmission.
kStatus_I2C_ArbitrationLost – Transfer error, arbitration lost.
kStataus_I2C_Nak – Transfer error, receive NAK during transfer.

status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)

Performs a polling receive transaction on the I2C bus.

Parameters:

base – I2C peripheral base pointer.
rxBuff – The pointer to the data to store the received data.
rxSize – The length in bytes of the data to be received.

status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to arbitration lost or receiving a NAK.

Parameters:

base – I2C peripheral base address.
xfer – Pointer to the transfer structure.

Return values:

kStatus_Success – Successfully complete the data transmission.
kStatus_I2C_Busy – Previous transmission still not finished.
kStatus_I2C_Timeout – Transfer error, wait signal timeout.
kStatus_I2C_ArbitrationLost – Transfer error, arbitration lost.
kStataus_I2C_Nak – Transfer error, receive NAK during transfer.

void I2C_MasterTransferCreateHandle(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_callback_t callback, void *userData)

Initializes the I2C handle which is used in transactional functions.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_master_handle_t structure to store the transfer state.
callback – pointer to user callback function.
userData – user parameter passed to the callback function.

status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)

Performs a master interrupt non-blocking transfer on the I2C bus.

Note

Calling the API returns immediately after transfer initiates. The user needs to call I2C_MasterGetTransferCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer is finished.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_master_handle_t structure which stores the transfer state.
xfer – pointer to i2c_master_transfer_t structure.

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_I2C_Busy – Previous transmission still not finished.
kStatus_I2C_Timeout – Transfer error, wait signal timeout.

status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_master_handle_t structure which stores the transfer state

Return values:

kStatus_I2C_Timeout – Timeout during polling flag.
kStatus_Success – Successfully abort the transfer.

void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)

Master interrupt handler.

Parameters:

base – I2C base pointer.
i2cHandle – pointer to i2c_master_handle_t structure.

void I2C_SlaveTransferCreateHandle(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_callback_t callback, void *userData)

Initializes the I2C handle which is used in transactional functions.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_slave_handle_t structure to store the transfer state.
callback – pointer to user callback function.
userData – user parameter passed to the callback function.

status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers.

Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of i2c_slave_transfer_event_t enumerators for the events you wish to receive. The kI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The I2C peripheral base address.
handle – Pointer to i2c_slave_handle_t structure which stores the transfer state.
eventMask – Bit mask formed by OR’ing together i2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI2C_SlaveAllEvents to enable all events.

Return values:

kStatus_Success – Slave transfers were successfully started.
kStatus_I2C_Busy – Slave transfers have already been started on this handle.

void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)

Aborts the slave transfer.

Note

This API can be called at any time to stop slave for handling the bus events.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_slave_handle_t structure which stores the transfer state.

status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)

Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.

Parameters:

base – I2C base pointer.
handle – pointer to i2c_slave_handle_t structure.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)

Slave interrupt handler.

Parameters:

base – I2C base pointer.
i2cHandle – pointer to i2c_slave_handle_t structure which stores the transfer state

FSL_I2C_DRIVER_VERSION: I2C driver version.

I2C status return codes.

Values:

enumerator kStatus_I2C_Busy: I2C is busy with current transfer.

enumerator kStatus_I2C_Idle: Bus is Idle.

enumerator kStatus_I2C_Nak: NAK received during transfer.

enumerator kStatus_I2C_ArbitrationLost: Arbitration lost during transfer.

enumerator kStatus_I2C_Timeout: Timeout polling status flags.

enumerator kStatus_I2C_Addr_Nak: NAK received during the address probe.

enum _i2c_flags

I2C peripheral flags.

The following status register flags can be cleared:

kI2C_ArbitrationLostFlag
kI2C_IntPendingFlag

Note

These enumerations are meant to be OR’d together to form a bit mask.

Values:

enumerator kI2C_ReceiveNakFlag: I2C receive NAK flag.

enumerator kI2C_IntPendingFlag: I2C interrupt pending flag.

enumerator kI2C_TransferDirectionFlag: I2C transfer direction flag.

enumerator kI2C_ArbitrationLostFlag: I2C arbitration lost flag.

enumerator kI2C_BusBusyFlag: I2C bus busy flag.

enumerator kI2C_AddressMatchFlag: I2C address match flag.

enumerator kI2C_TransferCompleteFlag: I2C transfer complete flag.

enum _i2c_interrupt_enable

I2C feature interrupt source.

Values:

enumerator kI2C_GlobalInterruptEnable: I2C global interrupt.

enum _i2c_direction

The direction of master and slave transfers.

Values:

enumerator kI2C_Write: Master transmits to the slave.

enumerator kI2C_Read: Master receives from the slave.

enum _i2c_master_transfer_flags

I2C transfer control flag.

Values:

enumerator kI2C_TransferDefaultFlag: A transfer starts with a start signal, stops with a stop signal.

enumerator kI2C_TransferNoStartFlag: A transfer starts without a start signal, only support write only or write+read with no start flag, do not support read only with no start flag.

enumerator kI2C_TransferRepeatedStartFlag: A transfer starts with a repeated start signal.

enumerator kI2C_TransferNoStopFlag: A transfer ends without a stop signal.

enum _i2c_slave_transfer_event

Set of events sent to the callback for nonblocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

Values:

enumerator kI2C_SlaveAddressMatchEvent: Received the slave address after a start or repeated start.

enumerator kI2C_SlaveTransmitEvent: A callback is requested to provide data to transmit (slave-transmitter role).

enumerator kI2C_SlaveReceiveEvent: A callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kI2C_SlaveTransmitAckEvent: A callback needs to either transmit an ACK or NACK.

enumerator kI2C_SlaveCompletionEvent: A stop was detected or finished transfer, completing the transfer.

enumerator kI2C_SlaveAllEvents: A bit mask of all available events.

typedef enum _i2c_direction i2c_direction_t: The direction of master and slave transfers.

typedef struct _i2c_master_config i2c_master_config_t: I2C master user configuration.

typedef struct _i2c_master_handle i2c_master_handle_t: I2C master handle typedef.

typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, i2c_master_handle_t *handle, status_t status, void *userData): I2C master transfer callback typedef.

typedef struct _i2c_master_transfer i2c_master_transfer_t: I2C master transfer structure.

typedef enum _i2c_slave_transfer_event i2c_slave_transfer_event_t

Set of events sent to the callback for nonblocking slave transfers.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

typedef struct _i2c_slave_handle i2c_slave_handle_t: I2C slave handle typedef.

typedef struct _i2c_slave_config i2c_slave_config_t: I2C slave user configuration.

typedef struct _i2c_slave_transfer i2c_slave_transfer_t: I2C slave transfer structure.

typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData): I2C slave transfer callback typedef.

I2C_RETRY_TIMES: Retry times for waiting flag.

struct _i2c_master_config

#include <fsl_i2c.h>

I2C master user configuration.

Public Members

bool enableMaster: Enables the I2C peripheral at initialization time.

uint32_t baudRate_Bps: Baud rate configuration of I2C peripheral.

struct _i2c_master_transfer

#include <fsl_i2c.h>

I2C master transfer structure.

Public Members

uint32_t flags: A transfer flag which controls the transfer.

uint8_t slaveAddress: 7-bit slave address.

i2c_direction_t direction: A transfer direction, read or write.

uint32_t subaddress: A sub address. Transferred MSB first.

uint8_t subaddressSize: A size of the command buffer.

uint8_t *volatile data: A transfer buffer.

volatile size_t dataSize: A transfer size.

struct _i2c_master_handle

#include <fsl_i2c.h>

I2C master handle structure.

Public Members

i2c_master_transfer_t transfer: I2C master transfer copy.

size_t transferSize: Total bytes to be transferred.

uint8_t state: A transfer state maintained during transfer.

i2c_master_transfer_callback_t completionCallback: A callback function called when the transfer is finished.

void *userData: A callback parameter passed to the callback function.

struct _i2c_slave_config

#include <fsl_i2c.h>

I2C slave user configuration.

Public Members

bool enableSlave: Enables the I2C peripheral at initialization time.

uint16_t slaveAddress: A slave address configuration.

struct _i2c_slave_transfer

#include <fsl_i2c.h>

I2C slave transfer structure.

Public Members

i2c_slave_transfer_event_t event: A reason that the callback is invoked.

uint8_t *volatile data: A transfer buffer.

volatile size_t dataSize: A transfer size.

status_t completionStatus: Success or error code describing how the transfer completed. Only applies for kI2C_SlaveCompletionEvent.

size_t transferredCount: A number of bytes actually transferred since the start or since the last repeated start.

struct _i2c_slave_handle

#include <fsl_i2c.h>

I2C slave handle structure.

Public Members

volatile uint8_t state: A transfer state maintained during transfer.

i2c_slave_transfer_t transfer: I2C slave transfer copy.

uint32_t eventMask: A mask of enabled events.

i2c_slave_transfer_callback_t callback: A callback function called at the transfer event.

void *userData: A callback parameter passed to the callback.

Iomuxc_driver#

static inline void IOMUXC_SetPinMux(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t inputOnfield)

Sets the IOMUXC pin mux mode.

This is an example to set the I2C4_SDA as the pwm1_OUT:

IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);

Note

The first five parameters can be filled with the pin function ID macros.

Parameters:

muxRegister – The pin mux register_
muxMode – The pin mux mode_
inputRegister – The select input register_
inputDaisy – The input daisy_
configRegister – The config register_
inputOnfield – The pad->module input inversion_

static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t muxMode, uint32_t inputRegister, uint32_t inputDaisy, uint32_t configRegister, uint32_t configValue)

Sets the IOMUXC pin configuration.

This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:

IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))

Note

The previous five parameters can be filled with the pin function ID macros.

Parameters:

muxRegister – The pin mux register_
muxMode – The pin mux mode_
inputRegister – The select input register_
inputDaisy – The input daisy_
configRegister – The config register_
configValue – The pin config value_

FSL_IOMUXC_DRIVER_VERSION: IOMUXC driver version 2.0.1.

IOMUXC_PMIC_STBY_REQ

IOMUXC_PMIC_ON_REQ

IOMUXC_ONOFF

IOMUXC_POR_B

IOMUXC_RTC_RESET_B

IOMUXC_GPIO1_IO00_GPIO1_IO00

IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT

IOMUXC_GPIO1_IO00_XTALOSC_REF_CLK_32K

IOMUXC_GPIO1_IO00_CCM_EXT_CLK1

IOMUXC_GPIO1_IO01_GPIO1_IO01

IOMUXC_GPIO1_IO01_PWM1_OUT

IOMUXC_GPIO1_IO01_XTALOSC_REF_CLK_24M

IOMUXC_GPIO1_IO01_CCM_EXT_CLK2

IOMUXC_GPIO1_IO02_GPIO1_IO02

IOMUXC_GPIO1_IO02_WDOG1_WDOG_B

IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY

IOMUXC_GPIO1_IO03_GPIO1_IO03

IOMUXC_GPIO1_IO03_USDHC1_VSELECT

IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0

IOMUXC_GPIO1_IO04_GPIO1_IO04

IOMUXC_GPIO1_IO04_USDHC2_VSELECT

IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1

IOMUXC_GPIO1_IO05_GPIO1_IO05

IOMUXC_GPIO1_IO05_M4_NMI

IOMUXC_GPIO1_IO05_CCM_PMIC_READY

IOMUXC_GPIO1_IO06_GPIO1_IO06

IOMUXC_GPIO1_IO06_ENET1_MDC

IOMUXC_GPIO1_IO06_USDHC1_CD_B

IOMUXC_GPIO1_IO06_CCM_EXT_CLK3

IOMUXC_GPIO1_IO07_GPIO1_IO07

IOMUXC_GPIO1_IO07_ENET1_MDIO

IOMUXC_GPIO1_IO07_USDHC1_WP

IOMUXC_GPIO1_IO07_CCM_EXT_CLK4

IOMUXC_GPIO1_IO08_GPIO1_IO08

IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN

IOMUXC_GPIO1_IO08_USDHC2_RESET_B

IOMUXC_GPIO1_IO09_GPIO1_IO09

IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT

IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0

IOMUXC_GPIO1_IO10_GPIO1_IO10

IOMUXC_GPIO1_IO10_USB1_OTG_ID

IOMUXC_GPIO1_IO11_GPIO1_IO11

IOMUXC_GPIO1_IO11_USB2_OTG_ID

IOMUXC_GPIO1_IO11_CCM_PMIC_READY

IOMUXC_GPIO1_IO12_GPIO1_IO12

IOMUXC_GPIO1_IO12_USB1_OTG_PWR

IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1

IOMUXC_GPIO1_IO13_GPIO1_IO13

IOMUXC_GPIO1_IO13_USB1_OTG_OC

IOMUXC_GPIO1_IO13_PWM2_OUT

IOMUXC_GPIO1_IO14_GPIO1_IO14

IOMUXC_GPIO1_IO14_USB2_OTG_PWR

IOMUXC_GPIO1_IO14_PWM3_OUT

IOMUXC_GPIO1_IO14_CCM_CLKO1

IOMUXC_GPIO1_IO15_GPIO1_IO15

IOMUXC_GPIO1_IO15_USB2_OTG_OC

IOMUXC_GPIO1_IO15_PWM4_OUT

IOMUXC_GPIO1_IO15_CCM_CLKO2

IOMUXC_ENET_MDC_ENET1_MDC

IOMUXC_ENET_MDC_GPIO1_IO16

IOMUXC_ENET_MDIO_ENET1_MDIO

IOMUXC_ENET_MDIO_GPIO1_IO17

IOMUXC_ENET_TD3_ENET1_RGMII_TD3

IOMUXC_ENET_TD3_GPIO1_IO18

IOMUXC_ENET_TD2_ENET1_RGMII_TD2

IOMUXC_ENET_TD2_ENET1_TX_CLK

IOMUXC_ENET_TD2_GPIO1_IO19

IOMUXC_ENET_TD1_ENET1_RGMII_TD1

IOMUXC_ENET_TD1_GPIO1_IO20

IOMUXC_ENET_TD0_ENET1_RGMII_TD0

IOMUXC_ENET_TD0_GPIO1_IO21

IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL

IOMUXC_ENET_TX_CTL_GPIO1_IO22

IOMUXC_ENET_TXC_ENET1_RGMII_TXC

IOMUXC_ENET_TXC_ENET1_TX_ER

IOMUXC_ENET_TXC_GPIO1_IO23

IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL

IOMUXC_ENET_RX_CTL_GPIO1_IO24

IOMUXC_ENET_RXC_ENET1_RGMII_RXC

IOMUXC_ENET_RXC_ENET1_RX_ER

IOMUXC_ENET_RXC_GPIO1_IO25

IOMUXC_ENET_RD0_ENET1_RGMII_RD0

IOMUXC_ENET_RD0_GPIO1_IO26

IOMUXC_ENET_RD1_ENET1_RGMII_RD1

IOMUXC_ENET_RD1_GPIO1_IO27

IOMUXC_ENET_RD2_ENET1_RGMII_RD2

IOMUXC_ENET_RD2_GPIO1_IO28

IOMUXC_ENET_RD3_ENET1_RGMII_RD3

IOMUXC_ENET_RD3_GPIO1_IO29

IOMUXC_SD1_CLK_USDHC1_CLK

IOMUXC_SD1_CLK_GPIO2_IO00

IOMUXC_SD1_CMD_USDHC1_CMD

IOMUXC_SD1_CMD_GPIO2_IO01

IOMUXC_SD1_DATA0_USDHC1_DATA0

IOMUXC_SD1_DATA0_GPIO2_IO02

IOMUXC_SD1_DATA1_USDHC1_DATA1

IOMUXC_SD1_DATA1_GPIO2_IO03

IOMUXC_SD1_DATA2_USDHC1_DATA2

IOMUXC_SD1_DATA2_GPIO2_IO04

IOMUXC_SD1_DATA3_USDHC1_DATA3

IOMUXC_SD1_DATA3_GPIO2_IO05

IOMUXC_SD1_DATA4_USDHC1_DATA4

IOMUXC_SD1_DATA4_GPIO2_IO06

IOMUXC_SD1_DATA5_USDHC1_DATA5

IOMUXC_SD1_DATA5_GPIO2_IO07

IOMUXC_SD1_DATA6_USDHC1_DATA6

IOMUXC_SD1_DATA6_GPIO2_IO08

IOMUXC_SD1_DATA7_USDHC1_DATA7

IOMUXC_SD1_DATA7_GPIO2_IO09

IOMUXC_SD1_RESET_B_USDHC1_RESET_B

IOMUXC_SD1_RESET_B_GPIO2_IO10

IOMUXC_SD1_STROBE_USDHC1_STROBE

IOMUXC_SD1_STROBE_GPIO2_IO11

IOMUXC_SD2_CD_B_USDHC2_CD_B

IOMUXC_SD2_CD_B_GPIO2_IO12

IOMUXC_SD2_CLK_USDHC2_CLK

IOMUXC_SD2_CLK_GPIO2_IO13

IOMUXC_SD2_CMD_USDHC2_CMD

IOMUXC_SD2_CMD_GPIO2_IO14

IOMUXC_SD2_DATA0_USDHC2_DATA0

IOMUXC_SD2_DATA0_GPIO2_IO15

IOMUXC_SD2_DATA1_USDHC2_DATA1

IOMUXC_SD2_DATA1_GPIO2_IO16

IOMUXC_SD2_DATA2_USDHC2_DATA2

IOMUXC_SD2_DATA2_GPIO2_IO17

IOMUXC_SD2_DATA3_USDHC2_DATA3

IOMUXC_SD2_DATA3_GPIO2_IO18

IOMUXC_SD2_RESET_B_USDHC2_RESET_B

IOMUXC_SD2_RESET_B_GPIO2_IO19

IOMUXC_SD2_WP_USDHC2_WP

IOMUXC_SD2_WP_GPIO2_IO20

IOMUXC_NAND_ALE_RAWNAND_ALE

IOMUXC_NAND_ALE_QSPI_A_SCLK

IOMUXC_NAND_ALE_GPIO3_IO00

IOMUXC_NAND_CE0_B_RAWNAND_CE0_B

IOMUXC_NAND_CE0_B_QSPI_A_SS0_B

IOMUXC_NAND_CE0_B_GPIO3_IO01

IOMUXC_NAND_CE1_B_RAWNAND_CE1_B

IOMUXC_NAND_CE1_B_QSPI_A_SS1_B

IOMUXC_NAND_CE1_B_GPIO3_IO02

IOMUXC_NAND_CE2_B_RAWNAND_CE2_B

IOMUXC_NAND_CE2_B_QSPI_B_SS0_B

IOMUXC_NAND_CE2_B_GPIO3_IO03

IOMUXC_NAND_CE3_B_RAWNAND_CE3_B

IOMUXC_NAND_CE3_B_QSPI_B_SS1_B

IOMUXC_NAND_CE3_B_GPIO3_IO04

IOMUXC_NAND_CLE_RAWNAND_CLE

IOMUXC_NAND_CLE_QSPI_B_SCLK

IOMUXC_NAND_CLE_GPIO3_IO05

IOMUXC_NAND_DATA00_RAWNAND_DATA00

IOMUXC_NAND_DATA00_QSPI_A_DATA0

IOMUXC_NAND_DATA00_GPIO3_IO06

IOMUXC_NAND_DATA01_RAWNAND_DATA01

IOMUXC_NAND_DATA01_QSPI_A_DATA1

IOMUXC_NAND_DATA01_GPIO3_IO07

IOMUXC_NAND_DATA02_RAWNAND_DATA02

IOMUXC_NAND_DATA02_QSPI_A_DATA2

IOMUXC_NAND_DATA02_GPIO3_IO08

IOMUXC_NAND_DATA03_RAWNAND_DATA03

IOMUXC_NAND_DATA03_QSPI_A_DATA3

IOMUXC_NAND_DATA03_GPIO3_IO09

IOMUXC_NAND_DATA04_RAWNAND_DATA04

IOMUXC_NAND_DATA04_QSPI_B_DATA0

IOMUXC_NAND_DATA04_GPIO3_IO10

IOMUXC_NAND_DATA05_RAWNAND_DATA05

IOMUXC_NAND_DATA05_QSPI_B_DATA1

IOMUXC_NAND_DATA05_GPIO3_IO11

IOMUXC_NAND_DATA06_RAWNAND_DATA06

IOMUXC_NAND_DATA06_QSPI_B_DATA2

IOMUXC_NAND_DATA06_GPIO3_IO12

IOMUXC_NAND_DATA07_RAWNAND_DATA07

IOMUXC_NAND_DATA07_QSPI_B_DATA3

IOMUXC_NAND_DATA07_GPIO3_IO13

IOMUXC_NAND_DQS_RAWNAND_DQS

IOMUXC_NAND_DQS_QSPI_A_DQS

IOMUXC_NAND_DQS_GPIO3_IO14

IOMUXC_NAND_RE_B_RAWNAND_RE_B

IOMUXC_NAND_RE_B_QSPI_B_DQS

IOMUXC_NAND_RE_B_GPIO3_IO15

IOMUXC_NAND_READY_B_RAWNAND_READY_B

IOMUXC_NAND_READY_B_GPIO3_IO16

IOMUXC_NAND_WE_B_RAWNAND_WE_B

IOMUXC_NAND_WE_B_GPIO3_IO17

IOMUXC_NAND_WP_B_RAWNAND_WP_B

IOMUXC_NAND_WP_B_GPIO3_IO18

IOMUXC_SAI5_RXFS_SAI5_RX_SYNC

IOMUXC_SAI5_RXFS_SAI1_TX_DATA0

IOMUXC_SAI5_RXFS_GPIO3_IO19

IOMUXC_SAI5_RXC_SAI5_RX_BCLK

IOMUXC_SAI5_RXC_SAI1_TX_DATA1

IOMUXC_SAI5_RXC_GPIO3_IO20

IOMUXC_SAI5_RXD0_SAI5_RX_DATA0

IOMUXC_SAI5_RXD0_SAI1_TX_DATA2

IOMUXC_SAI5_RXD0_GPIO3_IO21

IOMUXC_SAI5_RXD1_SAI5_RX_DATA1

IOMUXC_SAI5_RXD1_SAI1_TX_DATA3

IOMUXC_SAI5_RXD1_SAI1_TX_SYNC

IOMUXC_SAI5_RXD1_SAI5_TX_SYNC

IOMUXC_SAI5_RXD1_GPIO3_IO22

IOMUXC_SAI5_RXD2_SAI5_RX_DATA2

IOMUXC_SAI5_RXD2_SAI1_TX_DATA4

IOMUXC_SAI5_RXD2_SAI1_TX_SYNC

IOMUXC_SAI5_RXD2_SAI5_TX_BCLK

IOMUXC_SAI5_RXD2_GPIO3_IO23

IOMUXC_SAI5_RXD3_SAI5_RX_DATA3

IOMUXC_SAI5_RXD3_SAI1_TX_DATA5

IOMUXC_SAI5_RXD3_SAI1_TX_SYNC

IOMUXC_SAI5_RXD3_SAI5_TX_DATA0

IOMUXC_SAI5_RXD3_GPIO3_IO24

IOMUXC_SAI5_MCLK_SAI5_MCLK

IOMUXC_SAI5_MCLK_SAI1_TX_BCLK

IOMUXC_SAI5_MCLK_SAI4_MCLK

IOMUXC_SAI5_MCLK_GPIO3_IO25

IOMUXC_SAI1_RXFS_SAI1_RX_SYNC

IOMUXC_SAI1_RXFS_SAI5_RX_SYNC

IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK

IOMUXC_SAI1_RXFS_GPIO4_IO00

IOMUXC_SAI1_RXC_SAI1_RX_BCLK

IOMUXC_SAI1_RXC_SAI5_RX_BCLK

IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL

IOMUXC_SAI1_RXC_GPIO4_IO01

IOMUXC_SAI1_RXD0_SAI1_RX_DATA0

IOMUXC_SAI1_RXD0_SAI5_RX_DATA0

IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0

IOMUXC_SAI1_RXD0_GPIO4_IO02

IOMUXC_SAI1_RXD0_SRC_BOOT_CFG0

IOMUXC_SAI1_RXD1_SAI1_RX_DATA1

IOMUXC_SAI1_RXD1_SAI5_RX_DATA1

IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1

IOMUXC_SAI1_RXD1_GPIO4_IO03

IOMUXC_SAI1_RXD1_SRC_BOOT_CFG1

IOMUXC_SAI1_RXD2_SAI1_RX_DATA2

IOMUXC_SAI1_RXD2_SAI5_RX_DATA2

IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2

IOMUXC_SAI1_RXD2_GPIO4_IO04

IOMUXC_SAI1_RXD2_SRC_BOOT_CFG2

IOMUXC_SAI1_RXD3_SAI1_RX_DATA3

IOMUXC_SAI1_RXD3_SAI5_RX_DATA3

IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3

IOMUXC_SAI1_RXD3_GPIO4_IO05

IOMUXC_SAI1_RXD3_SRC_BOOT_CFG3

IOMUXC_SAI1_RXD4_SAI1_RX_DATA4

IOMUXC_SAI1_RXD4_SAI6_TX_BCLK

IOMUXC_SAI1_RXD4_SAI6_RX_BCLK

IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4

IOMUXC_SAI1_RXD4_GPIO4_IO06

IOMUXC_SAI1_RXD4_SRC_BOOT_CFG4

IOMUXC_SAI1_RXD5_SAI1_RX_DATA5

IOMUXC_SAI1_RXD5_SAI6_TX_DATA0

IOMUXC_SAI1_RXD5_SAI6_RX_DATA0

IOMUXC_SAI1_RXD5_SAI1_RX_SYNC

IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5

IOMUXC_SAI1_RXD5_GPIO4_IO07

IOMUXC_SAI1_RXD5_SRC_BOOT_CFG5

IOMUXC_SAI1_RXD6_SAI1_RX_DATA6

IOMUXC_SAI1_RXD6_SAI6_TX_SYNC

IOMUXC_SAI1_RXD6_SAI6_RX_SYNC

IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6

IOMUXC_SAI1_RXD6_GPIO4_IO08

IOMUXC_SAI1_RXD6_SRC_BOOT_CFG6

IOMUXC_SAI1_RXD7_SAI1_RX_DATA7

IOMUXC_SAI1_RXD7_SAI6_MCLK

IOMUXC_SAI1_RXD7_SAI1_TX_SYNC

IOMUXC_SAI1_RXD7_SAI1_TX_DATA4

IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7

IOMUXC_SAI1_RXD7_GPIO4_IO09

IOMUXC_SAI1_RXD7_SRC_BOOT_CFG7

IOMUXC_SAI1_TXFS_SAI1_TX_SYNC

IOMUXC_SAI1_TXFS_SAI5_TX_SYNC

IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO

IOMUXC_SAI1_TXFS_GPIO4_IO10

IOMUXC_SAI1_TXC_SAI1_TX_BCLK

IOMUXC_SAI1_TXC_SAI5_TX_BCLK

IOMUXC_SAI1_TXC_CORESIGHT_EVENTI

IOMUXC_SAI1_TXC_GPIO4_IO11

IOMUXC_SAI1_TXD0_SAI1_TX_DATA0

IOMUXC_SAI1_TXD0_SAI5_TX_DATA0

IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8

IOMUXC_SAI1_TXD0_GPIO4_IO12

IOMUXC_SAI1_TXD0_SRC_BOOT_CFG8

IOMUXC_SAI1_TXD1_SAI1_TX_DATA1

IOMUXC_SAI1_TXD1_SAI5_TX_DATA1

IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9

IOMUXC_SAI1_TXD1_GPIO4_IO13

IOMUXC_SAI1_TXD1_SRC_BOOT_CFG9

IOMUXC_SAI1_TXD2_SAI1_TX_DATA2

IOMUXC_SAI1_TXD2_SAI5_TX_DATA2

IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10

IOMUXC_SAI1_TXD2_GPIO4_IO14

IOMUXC_SAI1_TXD2_SRC_BOOT_CFG10

IOMUXC_SAI1_TXD3_SAI1_TX_DATA3

IOMUXC_SAI1_TXD3_SAI5_TX_DATA3

IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11

IOMUXC_SAI1_TXD3_GPIO4_IO15

IOMUXC_SAI1_TXD3_SRC_BOOT_CFG11

IOMUXC_SAI1_TXD4_SAI1_TX_DATA4

IOMUXC_SAI1_TXD4_SAI6_RX_BCLK

IOMUXC_SAI1_TXD4_SAI6_TX_BCLK

IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12

IOMUXC_SAI1_TXD4_GPIO4_IO16

IOMUXC_SAI1_TXD4_SRC_BOOT_CFG12

IOMUXC_SAI1_TXD5_SAI1_TX_DATA5

IOMUXC_SAI1_TXD5_SAI6_RX_DATA0

IOMUXC_SAI1_TXD5_SAI6_TX_DATA0

IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13

IOMUXC_SAI1_TXD5_GPIO4_IO17

IOMUXC_SAI1_TXD5_SRC_BOOT_CFG13

IOMUXC_SAI1_TXD6_SAI1_TX_DATA6

IOMUXC_SAI1_TXD6_SAI6_RX_SYNC

IOMUXC_SAI1_TXD6_SAI6_TX_SYNC

IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14

IOMUXC_SAI1_TXD6_GPIO4_IO18

IOMUXC_SAI1_TXD6_SRC_BOOT_CFG14

IOMUXC_SAI1_TXD7_SAI1_TX_DATA7

IOMUXC_SAI1_TXD7_SAI6_MCLK

IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15

IOMUXC_SAI1_TXD7_GPIO4_IO19

IOMUXC_SAI1_TXD7_SRC_BOOT_CFG15

IOMUXC_SAI1_MCLK_SAI1_MCLK

IOMUXC_SAI1_MCLK_SAI5_MCLK

IOMUXC_SAI1_MCLK_SAI1_TX_BCLK

IOMUXC_SAI1_MCLK_GPIO4_IO20

IOMUXC_SAI2_RXFS_SAI2_RX_SYNC

IOMUXC_SAI2_RXFS_SAI5_TX_SYNC

IOMUXC_SAI2_RXFS_GPIO4_IO21

IOMUXC_SAI2_RXC_SAI2_RX_BCLK

IOMUXC_SAI2_RXC_SAI5_TX_BCLK

IOMUXC_SAI2_RXC_GPIO4_IO22

IOMUXC_SAI2_RXD0_SAI2_RX_DATA0

IOMUXC_SAI2_RXD0_SAI5_TX_DATA0

IOMUXC_SAI2_RXD0_GPIO4_IO23

IOMUXC_SAI2_TXFS_SAI2_TX_SYNC

IOMUXC_SAI2_TXFS_SAI5_TX_DATA1

IOMUXC_SAI2_TXFS_GPIO4_IO24

IOMUXC_SAI2_TXC_SAI2_TX_BCLK

IOMUXC_SAI2_TXC_SAI5_TX_DATA2

IOMUXC_SAI2_TXC_GPIO4_IO25

IOMUXC_SAI2_TXD0_SAI2_TX_DATA0

IOMUXC_SAI2_TXD0_SAI5_TX_DATA3

IOMUXC_SAI2_TXD0_GPIO4_IO26

IOMUXC_SAI2_MCLK_SAI2_MCLK

IOMUXC_SAI2_MCLK_SAI5_MCLK

IOMUXC_SAI2_MCLK_GPIO4_IO27

IOMUXC_SAI3_RXFS_SAI3_RX_SYNC

IOMUXC_SAI3_RXFS_GPT1_CAPTURE1

IOMUXC_SAI3_RXFS_SAI5_RX_SYNC

IOMUXC_SAI3_RXFS_GPIO4_IO28

IOMUXC_SAI3_RXC_SAI3_RX_BCLK

IOMUXC_SAI3_RXC_GPT1_CAPTURE2

IOMUXC_SAI3_RXC_SAI5_RX_BCLK

IOMUXC_SAI3_RXC_GPIO4_IO29

IOMUXC_SAI3_RXD_SAI3_RX_DATA0

IOMUXC_SAI3_RXD_GPT1_COMPARE1

IOMUXC_SAI3_RXD_SAI5_RX_DATA0

IOMUXC_SAI3_RXD_GPIO4_IO30

IOMUXC_SAI3_TXFS_SAI3_TX_SYNC

IOMUXC_SAI3_TXFS_GPT1_CLK

IOMUXC_SAI3_TXFS_SAI5_RX_DATA1

IOMUXC_SAI3_TXFS_GPIO4_IO31

IOMUXC_SAI3_TXC_SAI3_TX_BCLK

IOMUXC_SAI3_TXC_GPT1_COMPARE2

IOMUXC_SAI3_TXC_SAI5_RX_DATA2

IOMUXC_SAI3_TXC_GPIO5_IO00

IOMUXC_SAI3_TXD_SAI3_TX_DATA0

IOMUXC_SAI3_TXD_GPT1_COMPARE3

IOMUXC_SAI3_TXD_SAI5_RX_DATA3

IOMUXC_SAI3_TXD_GPIO5_IO01

IOMUXC_SAI3_MCLK_SAI3_MCLK

IOMUXC_SAI3_MCLK_PWM4_OUT

IOMUXC_SAI3_MCLK_SAI5_MCLK

IOMUXC_SAI3_MCLK_GPIO5_IO02

IOMUXC_SPDIF_TX_SPDIF1_OUT

IOMUXC_SPDIF_TX_PWM3_OUT

IOMUXC_SPDIF_TX_GPIO5_IO03

IOMUXC_SPDIF_RX_SPDIF1_IN

IOMUXC_SPDIF_RX_PWM2_OUT

IOMUXC_SPDIF_RX_GPIO5_IO04

IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK

IOMUXC_SPDIF_EXT_CLK_PWM1_OUT

IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05

IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK

IOMUXC_ECSPI1_SCLK_UART3_RX

IOMUXC_ECSPI1_SCLK_UART3_TX

IOMUXC_ECSPI1_SCLK_GPIO5_IO06

IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI

IOMUXC_ECSPI1_MOSI_UART3_TX

IOMUXC_ECSPI1_MOSI_UART3_RX

IOMUXC_ECSPI1_MOSI_GPIO5_IO07

IOMUXC_ECSPI1_MISO_ECSPI1_MISO

IOMUXC_ECSPI1_MISO_UART3_CTS_B

IOMUXC_ECSPI1_MISO_UART3_RTS_B

IOMUXC_ECSPI1_MISO_GPIO5_IO08

IOMUXC_ECSPI1_SS0_ECSPI1_SS0

IOMUXC_ECSPI1_SS0_UART3_RTS_B

IOMUXC_ECSPI1_SS0_UART3_CTS_B

IOMUXC_ECSPI1_SS0_GPIO5_IO09

IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK

IOMUXC_ECSPI2_SCLK_UART4_RX

IOMUXC_ECSPI2_SCLK_UART4_TX

IOMUXC_ECSPI2_SCLK_GPIO5_IO10

IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI

IOMUXC_ECSPI2_MOSI_UART4_TX

IOMUXC_ECSPI2_MOSI_UART4_RX

IOMUXC_ECSPI2_MOSI_GPIO5_IO11

IOMUXC_ECSPI2_MISO_ECSPI2_MISO

IOMUXC_ECSPI2_MISO_UART4_CTS_B

IOMUXC_ECSPI2_MISO_UART4_RTS_B

IOMUXC_ECSPI2_MISO_GPIO5_IO12

IOMUXC_ECSPI2_SS0_ECSPI2_SS0

IOMUXC_ECSPI2_SS0_UART4_RTS_B

IOMUXC_ECSPI2_SS0_UART4_CTS_B

IOMUXC_ECSPI2_SS0_GPIO5_IO13

IOMUXC_I2C1_SCL_I2C1_SCL

IOMUXC_I2C1_SCL_ENET1_MDC

IOMUXC_I2C1_SCL_GPIO5_IO14

IOMUXC_I2C1_SDA_I2C1_SDA

IOMUXC_I2C1_SDA_ENET1_MDIO

IOMUXC_I2C1_SDA_GPIO5_IO15

IOMUXC_I2C2_SCL_I2C2_SCL

IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN

IOMUXC_I2C2_SCL_GPIO5_IO16

IOMUXC_I2C2_SDA_I2C2_SDA

IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT

IOMUXC_I2C2_SDA_GPIO5_IO17

IOMUXC_I2C3_SCL_I2C3_SCL

IOMUXC_I2C3_SCL_PWM4_OUT

IOMUXC_I2C3_SCL_GPT2_CLK

IOMUXC_I2C3_SCL_GPIO5_IO18

IOMUXC_I2C3_SDA_I2C3_SDA

IOMUXC_I2C3_SDA_PWM3_OUT

IOMUXC_I2C3_SDA_GPT3_CLK

IOMUXC_I2C3_SDA_GPIO5_IO19

IOMUXC_I2C4_SCL_I2C4_SCL

IOMUXC_I2C4_SCL_PWM2_OUT

IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B

IOMUXC_I2C4_SCL_GPIO5_IO20

IOMUXC_I2C4_SDA_I2C4_SDA

IOMUXC_I2C4_SDA_PWM1_OUT

IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B

IOMUXC_I2C4_SDA_GPIO5_IO21

IOMUXC_UART1_RXD_UART1_RX

IOMUXC_UART1_RXD_UART1_TX

IOMUXC_UART1_RXD_ECSPI3_SCLK

IOMUXC_UART1_RXD_GPIO5_IO22

IOMUXC_UART1_TXD_UART1_TX

IOMUXC_UART1_TXD_UART1_RX

IOMUXC_UART1_TXD_ECSPI3_MOSI

IOMUXC_UART1_TXD_GPIO5_IO23

IOMUXC_UART2_RXD_UART2_RX

IOMUXC_UART2_RXD_UART2_TX

IOMUXC_UART2_RXD_ECSPI3_MISO

IOMUXC_UART2_RXD_GPIO5_IO24

IOMUXC_UART2_TXD_UART2_TX

IOMUXC_UART2_TXD_UART2_RX

IOMUXC_UART2_TXD_ECSPI3_SS0

IOMUXC_UART2_TXD_GPIO5_IO25

IOMUXC_UART3_RXD_UART3_RX

IOMUXC_UART3_RXD_UART3_TX

IOMUXC_UART3_RXD_UART1_CTS_B

IOMUXC_UART3_RXD_UART1_RTS_B

IOMUXC_UART3_RXD_GPIO5_IO26

IOMUXC_UART3_TXD_UART3_TX

IOMUXC_UART3_TXD_UART3_RX

IOMUXC_UART3_TXD_UART1_RTS_B

IOMUXC_UART3_TXD_UART1_CTS_B

IOMUXC_UART3_TXD_GPIO5_IO27

IOMUXC_UART4_RXD_UART4_RX

IOMUXC_UART4_RXD_UART4_TX

IOMUXC_UART4_RXD_UART2_CTS_B

IOMUXC_UART4_RXD_UART2_RTS_B

IOMUXC_UART4_RXD_PCIE1_CLKREQ_B

IOMUXC_UART4_RXD_GPIO5_IO28

IOMUXC_UART4_TXD_UART4_TX

IOMUXC_UART4_TXD_UART4_RX

IOMUXC_UART4_TXD_UART2_RTS_B

IOMUXC_UART4_TXD_UART2_CTS_B

IOMUXC_UART4_TXD_PCIE2_CLKREQ_B

IOMUXC_UART4_TXD_GPIO5_IO29

IOMUXC_TEST_MODE

IOMUXC_BOOT_MODE0

IOMUXC_BOOT_MODE1

IOMUXC_JTAG_MOD

IOMUXC_JTAG_TRST_B

IOMUXC_JTAG_TDI

IOMUXC_JTAG_TMS

IOMUXC_JTAG_TCK

IOMUXC_JTAG_TDO

IOMUXC_RTC

FSL_COMPONENT_ID

Common Driver#

FSL_COMMON_DRIVER_VERSION: common driver version.

DEBUG_CONSOLE_DEVICE_TYPE_NONE: No debug console.

DEBUG_CONSOLE_DEVICE_TYPE_UART: Debug console based on UART.

DEBUG_CONSOLE_DEVICE_TYPE_LPUART: Debug console based on LPUART.

DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: Debug console based on LPSCI.

DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: Debug console based on USBCDC.

DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: Debug console based on FLEXCOMM.

DEBUG_CONSOLE_DEVICE_TYPE_IUART: Debug console based on i.MX UART.

DEBUG_CONSOLE_DEVICE_TYPE_VUSART: Debug console based on LPC_VUSART.

DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART: Debug console based on LPC_USART.

DEBUG_CONSOLE_DEVICE_TYPE_SWO: Debug console based on SWO.

DEBUG_CONSOLE_DEVICE_TYPE_QSCI: Debug console based on QSCI.

MIN(a, b): Computes the minimum of a and b.

MAX(a, b): Computes the maximum of a and b.

UINT16_MAX: Max value of uint16_t type.

UINT32_MAX: Max value of uint32_t type.

MCUX_MASK_INVERT_8(mask): 8-bit mask inversion.

MCUX_MASK_INVERT_16(mask): 16-bit mask inversion.

MCUX_MASK_INVERT_32(mask): 32-bit mask inversion for completeness.

MCUX_REG_WRITE8(reg, value): 8-bit register write macro

MCUX_REG_WRITE16(reg, value): 16-bit register write macro

MCUX_REG_WRITE32(reg, value): 32-bit register write macro

MCUX_REG_READ8(reg): 8-bit register read macro

MCUX_REG_READ16(reg): 16-bit register read macro

MCUX_REG_READ32(reg): 32-bit register read macro

MCUX_REG_BIT_SET8(reg, mask): 8-bit register bit set macro

MCUX_REG_BIT_SET16(reg, mask): 16-bit register bit set macro

MCUX_REG_BIT_SET32(reg, mask): 32-bit register bit set macro

MCUX_REG_BIT_CLEAR8(reg, mask): 8-bit register bit clear macro

MCUX_REG_BIT_CLEAR16(reg, mask): 16-bit register bit clear macro

MCUX_REG_BIT_CLEAR32(reg, mask): 32-bit register bit clear macro

MCUX_REG_BIT_GET8(reg, mask): 8-bit register bit get macro

MCUX_REG_BIT_GET16(reg, mask): 16-bit register bit get macro

MCUX_REG_BIT_GET32(reg, mask): 32-bit register bit get macro

MCUX_REG_MODIFY8(reg, mask, value): 32-bit register read-modify-write macro

MCUX_REG_MODIFY16(reg, mask, value): 16-bit register read-modify-write macro

MCUX_REG_MODIFY32(reg, mask, value): 32-bit register read-modify-write macro

SDK_ATOMIC_LOCAL_ADD(addr, val): Add value val from the variable at address address.

SDK_ATOMIC_LOCAL_SUB(addr, val): Subtract value val to the variable at address address.

SDK_ATOMIC_LOCAL_SET(addr, bits): Set the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR(addr, bits): Clear the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_TOGGLE(addr, bits): Toggle the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits): For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits.

SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue): For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false .

SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue): For the variable at address address, set as newValue value and return old value.

USEC_TO_COUNT(us, clockFreqInHz): Macro to convert a microsecond period to raw count value

COUNT_TO_USEC(count, clockFreqInHz): Macro to convert a raw count value to microsecond

MSEC_TO_COUNT(ms, clockFreqInHz): Macro to convert a millisecond period to raw count value

COUNT_TO_MSEC(count, clockFreqInHz): Macro to convert a raw count value to millisecond

SDK_ISR_EXIT_BARRIER

SDK_ALIGN(var, alignbytes): Macro to define a variable with alignbytes alignment

SDK_L1DCACHE_ALIGN(var): Macro to define a variable with L1 d-cache line size alignment

SDK_SIZEALIGN(var, alignbytes)

Macro to define a variable with L2 cache line size alignment

Macro to change a value to a given size aligned value (rounded up)

SDK_SIZEALIGN_UP(var, alignbytes): Macro to change a value to a given size aligned value (rounded up), the wrapper of SDK_SIZEALIGN

SDK_SIZEALIGN_DOWN(var, alignbytes): Macro to change a value to a given size aligned value (rounded down)

SDK_IS_ALIGNED(var, alignbytes): Macro to check if a value is aligned to a given size

AT_NONCACHEABLE_SECTION(var): Define a variable var, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes): Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_NONCACHEABLE_SECTION_INIT(var): Define a variable var with initial value, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes): Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_CACHE_LINE_SECTION(var): Define a variable var, which is cache line size aligned and be placed in CacheLineData section.

AT_CACHE_LINE_SECTION_INIT(var): Define a variable var with initial value, which is cache line size aligned and be placed in CacheLineData.init section.

CACHE_LINE_DATA

AT_QUICKACCESS_SECTION_CODE(func): Place function in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA(var): Place data in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes): Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes.

MCUX_RAMFUNC

Function attribute to place function in RAM. For example, to place function my_func in ram, use like:

MCUX_RAMFUNC my_func

RAMFUNCTION_SECTION_CODE(func): Place function in ram.

MCUX_DEPRECATED: Deprecated APIs.

MCUX_DEPRECATED_MACRO: Deprecated macros.

MCUX_EXPERIMENTAL: Experimental APIs.

MCUX_EXPERIMENTAL_MACRO: Experimental macros.

enum _status_groups

Status group numbers.

Values:

enumerator kStatusGroup_Generic: Group number for generic status codes.

enumerator kStatusGroup_FLASH: Group number for FLASH status codes.

enumerator kStatusGroup_LPSPI: Group number for LPSPI status codes.

enumerator kStatusGroup_FLEXIO_SPI: Group number for FLEXIO SPI status codes.

enumerator kStatusGroup_DSPI: Group number for DSPI status codes.

enumerator kStatusGroup_FLEXIO_UART: Group number for FLEXIO UART status codes.

enumerator kStatusGroup_FLEXIO_I2C: Group number for FLEXIO I2C status codes.

enumerator kStatusGroup_LPI2C: Group number for LPI2C status codes.

enumerator kStatusGroup_UART: Group number for UART status codes.

enumerator kStatusGroup_I2C: Group number for UART status codes.

enumerator kStatusGroup_LPSCI: Group number for LPSCI status codes.

enumerator kStatusGroup_LPUART: Group number for LPUART status codes.

enumerator kStatusGroup_SPI: Group number for SPI status code.

enumerator kStatusGroup_XRDC: Group number for XRDC status code.

enumerator kStatusGroup_SEMA42: Group number for SEMA42 status code.

enumerator kStatusGroup_SDHC: Group number for SDHC status code

enumerator kStatusGroup_SDMMC: Group number for SDMMC status code

enumerator kStatusGroup_SAI: Group number for SAI status code

enumerator kStatusGroup_MCG: Group number for MCG status codes.

enumerator kStatusGroup_SCG: Group number for SCG status codes.

enumerator kStatusGroup_SDSPI: Group number for SDSPI status codes.

enumerator kStatusGroup_FLEXIO_I2S: Group number for FLEXIO I2S status codes

enumerator kStatusGroup_FLEXIO_MCULCD: Group number for FLEXIO LCD status codes

enumerator kStatusGroup_FLASHIAP: Group number for FLASHIAP status codes

enumerator kStatusGroup_FLEXCOMM_I2C: Group number for FLEXCOMM I2C status codes

enumerator kStatusGroup_I2S: Group number for I2S status codes

enumerator kStatusGroup_IUART: Group number for IUART status codes

enumerator kStatusGroup_CSI: Group number for CSI status codes

enumerator kStatusGroup_MIPI_DSI: Group number for MIPI DSI status codes

enumerator kStatusGroup_SDRAMC: Group number for SDRAMC status codes.

enumerator kStatusGroup_POWER: Group number for POWER status codes.

enumerator kStatusGroup_ENET: Group number for ENET status codes.

enumerator kStatusGroup_PHY: Group number for PHY status codes.

enumerator kStatusGroup_TRGMUX: Group number for TRGMUX status codes.

enumerator kStatusGroup_SMARTCARD: Group number for SMARTCARD status codes.

enumerator kStatusGroup_LMEM: Group number for LMEM status codes.

enumerator kStatusGroup_QSPI: Group number for QSPI status codes.

enumerator kStatusGroup_DMA: Group number for DMA status codes.

enumerator kStatusGroup_EDMA: Group number for EDMA status codes.

enumerator kStatusGroup_DMAMGR: Group number for DMAMGR status codes.

enumerator kStatusGroup_FLEXCAN: Group number for FlexCAN status codes.

enumerator kStatusGroup_LTC: Group number for LTC status codes.

enumerator kStatusGroup_FLEXIO_CAMERA: Group number for FLEXIO CAMERA status codes.

enumerator kStatusGroup_LPC_SPI: Group number for LPC_SPI status codes.

enumerator kStatusGroup_LPC_USART: Group number for LPC_USART status codes.

enumerator kStatusGroup_DMIC: Group number for DMIC status codes.

enumerator kStatusGroup_SDIF: Group number for SDIF status codes.

enumerator kStatusGroup_SPIFI: Group number for SPIFI status codes.

enumerator kStatusGroup_OTP: Group number for OTP status codes.

enumerator kStatusGroup_MCAN: Group number for MCAN status codes.

enumerator kStatusGroup_CAAM: Group number for CAAM status codes.

enumerator kStatusGroup_ECSPI: Group number for ECSPI status codes.

enumerator kStatusGroup_USDHC: Group number for USDHC status codes.

enumerator kStatusGroup_LPC_I2C: Group number for LPC_I2C status codes.

enumerator kStatusGroup_DCP: Group number for DCP status codes.

enumerator kStatusGroup_MSCAN: Group number for MSCAN status codes.

enumerator kStatusGroup_ESAI: Group number for ESAI status codes.

enumerator kStatusGroup_FLEXSPI: Group number for FLEXSPI status codes.

enumerator kStatusGroup_MMDC: Group number for MMDC status codes.

enumerator kStatusGroup_PDM: Group number for MIC status codes.

enumerator kStatusGroup_SDMA: Group number for SDMA status codes.

enumerator kStatusGroup_ICS: Group number for ICS status codes.

enumerator kStatusGroup_SPDIF: Group number for SPDIF status codes.

enumerator kStatusGroup_LPC_MINISPI: Group number for LPC_MINISPI status codes.

enumerator kStatusGroup_HASHCRYPT: Group number for Hashcrypt status codes

enumerator kStatusGroup_LPC_SPI_SSP: Group number for LPC_SPI_SSP status codes.

enumerator kStatusGroup_I3C: Group number for I3C status codes

enumerator kStatusGroup_LPC_I2C_1: Group number for LPC_I2C_1 status codes.

enumerator kStatusGroup_NOTIFIER: Group number for NOTIFIER status codes.

enumerator kStatusGroup_DebugConsole: Group number for debug console status codes.

enumerator kStatusGroup_SEMC: Group number for SEMC status codes.

enumerator kStatusGroup_ApplicationRangeStart: Starting number for application groups.

enumerator kStatusGroup_IAP: Group number for IAP status codes

enumerator kStatusGroup_SFA: Group number for SFA status codes

enumerator kStatusGroup_SPC: Group number for SPC status codes.

enumerator kStatusGroup_PUF: Group number for PUF status codes.

enumerator kStatusGroup_TOUCH_PANEL: Group number for touch panel status codes

enumerator kStatusGroup_VBAT: Group number for VBAT status codes

enumerator kStatusGroup_XSPI: Group number for XSPI status codes

enumerator kStatusGroup_PNGDEC: Group number for PNGDEC status codes

enumerator kStatusGroup_JPEGDEC: Group number for JPEGDEC status codes

enumerator kStatusGroup_AUDMIX: Group number for AUDMIX status codes

enumerator kStatusGroup_HAL_GPIO: Group number for HAL GPIO status codes.

enumerator kStatusGroup_HAL_UART: Group number for HAL UART status codes.

enumerator kStatusGroup_HAL_TIMER: Group number for HAL TIMER status codes.

enumerator kStatusGroup_HAL_SPI: Group number for HAL SPI status codes.

enumerator kStatusGroup_HAL_I2C: Group number for HAL I2C status codes.

enumerator kStatusGroup_HAL_FLASH: Group number for HAL FLASH status codes.

enumerator kStatusGroup_HAL_PWM: Group number for HAL PWM status codes.

enumerator kStatusGroup_HAL_RNG: Group number for HAL RNG status codes.

enumerator kStatusGroup_HAL_I2S: Group number for HAL I2S status codes.

enumerator kStatusGroup_HAL_ADC_SENSOR: Group number for HAL ADC SENSOR status codes.

enumerator kStatusGroup_TIMERMANAGER: Group number for TiMER MANAGER status codes.

enumerator kStatusGroup_SERIALMANAGER: Group number for SERIAL MANAGER status codes.

enumerator kStatusGroup_LED: Group number for LED status codes.

enumerator kStatusGroup_BUTTON: Group number for BUTTON status codes.

enumerator kStatusGroup_EXTERN_EEPROM: Group number for EXTERN EEPROM status codes.

enumerator kStatusGroup_SHELL: Group number for SHELL status codes.

enumerator kStatusGroup_MEM_MANAGER: Group number for MEM MANAGER status codes.

enumerator kStatusGroup_LIST: Group number for List status codes.

enumerator kStatusGroup_OSA: Group number for OSA status codes.

enumerator kStatusGroup_COMMON_TASK: Group number for Common task status codes.

enumerator kStatusGroup_MSG: Group number for messaging status codes.

enumerator kStatusGroup_SDK_OCOTP: Group number for OCOTP status codes.

enumerator kStatusGroup_SDK_FLEXSPINOR: Group number for FLEXSPINOR status codes.

enumerator kStatusGroup_CODEC: Group number for codec status codes.

enumerator kStatusGroup_ASRC: Group number for codec status ASRC.

enumerator kStatusGroup_OTFAD: Group number for codec status codes.

enumerator kStatusGroup_SDIOSLV: Group number for SDIOSLV status codes.

enumerator kStatusGroup_MECC: Group number for MECC status codes.

enumerator kStatusGroup_ENET_QOS: Group number for ENET_QOS status codes.

enumerator kStatusGroup_LOG: Group number for LOG status codes.

enumerator kStatusGroup_I3CBUS: Group number for I3CBUS status codes.

enumerator kStatusGroup_QSCI: Group number for QSCI status codes.

enumerator kStatusGroup_ELEMU: Group number for ELEMU status codes.

enumerator kStatusGroup_QUEUEDSPI: Group number for QSPI status codes.

enumerator kStatusGroup_POWER_MANAGER: Group number for POWER_MANAGER status codes.

enumerator kStatusGroup_IPED: Group number for IPED status codes.

enumerator kStatusGroup_ELS_PKC: Group number for ELS PKC status codes.

enumerator kStatusGroup_CSS_PKC: Group number for CSS PKC status codes.

enumerator kStatusGroup_HOSTIF: Group number for HOSTIF status codes.

enumerator kStatusGroup_CLIF: Group number for CLIF status codes.

enumerator kStatusGroup_BMA: Group number for BMA status codes.

enumerator kStatusGroup_NETC: Group number for NETC status codes.

enumerator kStatusGroup_ELE: Group number for ELE status codes.

enumerator kStatusGroup_GLIKEY: Group number for GLIKEY status codes.

enumerator kStatusGroup_AON_POWER: Group number for AON_POWER status codes.

enumerator kStatusGroup_AON_COMMON: Group number for AON_COMMON status codes.

enumerator kStatusGroup_ENDAT3: Group number for ENDAT3 status codes.

enumerator kStatusGroup_HIPERFACE: Group number for HIPERFACE status codes.

enumerator kStatusGroup_NPX: Group number for NPX status codes.

enumerator kStatusGroup_ELA_CSEC: Group number for ELA_CSEC status codes.

enumerator kStatusGroup_FLEXIO_T_FORMAT: Group number for T-format status codes.

enumerator kStatusGroup_FLEXIO_A_FORMAT: Group number for A-format status codes.

enumerator kStatusGroup_LPC_QSPI: Group number for LPC QSPI status codes.

Generic status return codes.

Values:

enumerator kStatus_Success: Generic status for Success.

enumerator kStatus_Fail: Generic status for Fail.

enumerator kStatus_ReadOnly: Generic status for read only failure.

enumerator kStatus_OutOfRange: Generic status for out of range access.

enumerator kStatus_InvalidArgument: Generic status for invalid argument check.

enumerator kStatus_Timeout: Generic status for timeout.

enumerator kStatus_NoTransferInProgress: Generic status for no transfer in progress.

enumerator kStatus_Busy: Generic status for module is busy.

enumerator kStatus_NoData: Generic status for no data is found for the operation.

typedef int32_t status_t: Type used for all status and error return values.

void *SDK_Malloc(size_t size, size_t alignbytes)

Allocate memory with given alignment and aligned size.

This is provided to support the dynamically allocated memory used in cache-able region.

Parameters:

size – The length required to malloc.
alignbytes – The alignment size.

Return values:

The – allocated memory.

void SDK_Free(void *ptr)

Free memory.

Parameters:

ptr – The memory to be release.

void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

Parameters:

delayTime_us – Delay time in unit of microsecond.
coreClock_Hz – Core clock frequency with Hz.

static inline status_t EnableIRQ(IRQn_Type interrupt)

Enable specific interrupt.

Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number.

Return values:

kStatus_Success – Interrupt enabled successfully
kStatus_Fail – Failed to enable the interrupt

static inline status_t DisableIRQ(IRQn_Type interrupt)

Disable specific interrupt.

Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number.

Return values:

kStatus_Success – Interrupt disabled successfully
kStatus_Fail – Failed to disable the interrupt

static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)

Enable the IRQ, and also set the interrupt priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to Enable.
priNum – Priority number set to interrupt controller register.

Return values:

kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)

Set the IRQ priority.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to set.
priNum – Priority number set to interrupt controller register.

Return values:

kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)

Clear the pending IRQ flag.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The flag which IRQ to clear.

Return values:

kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.

static inline uint32_t DisableGlobalIRQ(void)

Disable the global IRQ.

Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:: Current primask value.

static inline void EnableGlobalIRQ(uint32_t primask)

Enable the global IRQ.

Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ().

static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)

static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)

FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ: Macro to use the default weak IRQ handler in drivers.

MAKE_STATUS(group, code): Construct a status code value from a group and code number.

MAKE_VERSION(major, minor, bugfix)

Construct the version number for drivers.

The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).

| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0

ARRAY_SIZE(x): Computes the number of elements in an array.

UINT64_H(X): Macro to get upper 32 bits of a 64-bit value

UINT64_L(X): Macro to get lower 32 bits of a 64-bit value

SUPPRESS_FALL_THROUGH_WARNING(): For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement.

MSDK_REG_SECURE_ADDR(x): Convert the register address to the one used in secure mode.

MSDK_REG_NONSECURE_ADDR(x): Convert the register address to the one used in non-secure mode.

MSDK_HAS_DWT_CYCCNT: The chip supports DWT CYCCNT or not.

MSDK_INVALID_IRQ_HANDLER: Invalid IRQ handler address.

MCM: Miscellaneous Control Module#

FSL_MCM_DRIVER_VERSION: MCM driver version.

Enum _mcm_interrupt_flag. Interrupt status flag mask. .

Values:

enumerator kMCM_CacheWriteBuffer: Cache Write Buffer Error Enable.

enumerator kMCM_ParityError: Cache Parity Error Enable.

enumerator kMCM_FPUInvalidOperation: FPU Invalid Operation Interrupt Enable.

enumerator kMCM_FPUDivideByZero: FPU Divide-by-zero Interrupt Enable.

enumerator kMCM_FPUOverflow: FPU Overflow Interrupt Enable.

enumerator kMCM_FPUUnderflow: FPU Underflow Interrupt Enable.

enumerator kMCM_FPUInexact: FPU Inexact Interrupt Enable.

enumerator kMCM_FPUInputDenormalInterrupt: FPU Input Denormal Interrupt Enable.

typedef union _mcm_buffer_fault_attribute mcm_buffer_fault_attribute_t: The union of buffer fault attribute.

typedef union _mcm_lmem_fault_attribute mcm_lmem_fault_attribute_t: The union of LMEM fault attribute.

static inline void MCM_EnableCrossbarRoundRobin(MCM_Type *base, bool enable)

Enables/Disables crossbar round robin.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable crossbar round robin.
- true Enable crossbar round robin.
- false disable crossbar round robin.

static inline void MCM_EnableInterruptStatus(MCM_Type *base, uint32_t mask)

Enables the interrupt.

Parameters:

base – MCM peripheral base address.
mask – Interrupt status flags mask(_mcm_interrupt_flag).

static inline void MCM_DisableInterruptStatus(MCM_Type *base, uint32_t mask)

Disables the interrupt.

Parameters:

base – MCM peripheral base address.
mask – Interrupt status flags mask(_mcm_interrupt_flag).

static inline uint16_t MCM_GetInterruptStatus(MCM_Type *base)

Gets the Interrupt status .

Parameters:

base – MCM peripheral base address.

static inline void MCM_ClearCacheWriteBufferErroStatus(MCM_Type *base)

Clears the Interrupt status .

Parameters:

base – MCM peripheral base address.

static inline uint32_t MCM_GetBufferFaultAddress(MCM_Type *base)

Gets buffer fault address.

Parameters:

base – MCM peripheral base address.

static inline void MCM_GetBufferFaultAttribute(MCM_Type *base, mcm_buffer_fault_attribute_t *bufferfault)

Gets buffer fault attributes.

Parameters:

base – MCM peripheral base address.
bufferfault – Structure to store the result.

static inline uint32_t MCM_GetBufferFaultData(MCM_Type *base)

Gets buffer fault data.

Parameters:

base – MCM peripheral base address.

static inline void MCM_LimitCodeCachePeripheralWriteBuffering(MCM_Type *base, bool enable)

Limit code cache peripheral write buffering.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable limit code cache peripheral write buffering.
- true Enable limit code cache peripheral write buffering.
- false disable limit code cache peripheral write buffering.

static inline void MCM_BypassFixedCodeCacheMap(MCM_Type *base, bool enable)

Bypass fixed code cache map.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable bypass fixed code cache map.
- true Enable bypass fixed code cache map.
- false disable bypass fixed code cache map.

static inline void MCM_EnableCodeBusCache(MCM_Type *base, bool enable)

Enables/Disables code bus cache.

Parameters:

base – MCM peripheral base address.
enable – Used to disable/enable code bus cache.
- true Enable code bus cache.
- false disable code bus cache.

static inline void MCM_ForceCodeCacheToNoAllocation(MCM_Type *base, bool enable)

Force code cache to no allocation.

Parameters:

base – MCM peripheral base address.
enable – Used to force code cache to allocation or no allocation.
- true Force code cache to no allocation.
- false Force code cache to allocation.

static inline void MCM_EnableCodeCacheWriteBuffer(MCM_Type *base, bool enable)

Enables/Disables code cache write buffer.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable code cache write buffer.
- true Enable code cache write buffer.
- false Disable code cache write buffer.

static inline void MCM_ClearCodeBusCache(MCM_Type *base)

Clear code bus cache.

Parameters:

base – MCM peripheral base address.

static inline void MCM_EnablePcParityFaultReport(MCM_Type *base, bool enable)

Enables/Disables PC Parity Fault Report.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable PC Parity Fault Report.
- true Enable PC Parity Fault Report.
- false disable PC Parity Fault Report.

static inline void MCM_EnablePcParity(MCM_Type *base, bool enable)

Enables/Disables PC Parity.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable PC Parity.
- true Enable PC Parity.
- false disable PC Parity.

static inline void MCM_LockConfigState(MCM_Type *base)

Lock the configuration state.

Parameters:

base – MCM peripheral base address.

static inline void MCM_EnableCacheParityReporting(MCM_Type *base, bool enable)

Enables/Disables cache parity reporting.

Parameters:

base – MCM peripheral base address.
enable – Used to enable/disable cache parity reporting.
- true Enable cache parity reporting.
- false disable cache parity reporting.

static inline uint32_t MCM_GetLmemFaultAddress(MCM_Type *base)

Gets LMEM fault address.

Parameters:

base – MCM peripheral base address.

static inline void MCM_GetLmemFaultAttribute(MCM_Type *base, mcm_lmem_fault_attribute_t *lmemFault)

Get LMEM fault attributes.

Parameters:

base – MCM peripheral base address.
lmemFault – Structure to store the result.

static inline uint64_t MCM_GetLmemFaultData(MCM_Type *base)

Gets LMEM fault data.

Parameters:

base – MCM peripheral base address.

MCM_LMFATR_TYPE_MASK

MCM_LMFATR_MODE_MASK

MCM_LMFATR_BUFF_MASK

MCM_LMFATR_CACH_MASK

MCM_ISCR_STAT_MASK

FSL_COMPONENT_ID

union _mcm_buffer_fault_attribute

#include <fsl_mcm.h>

The union of buffer fault attribute.

Public Members

uint32_t attribute: Indicates the faulting attributes, when a properly-enabled cache write buffer error interrupt event is detected.

struct _mcm_buffer_fault_attribute._mcm_buffer_fault_attribut attribute_memory

struct _mcm_buffer_fault_attribut

Public Members

uint32_t busErrorDataAccessType: Indicates the type of cache write buffer access.

uint32_t busErrorPrivilegeLevel: Indicates the privilege level of the cache write buffer access.

uint32_t busErrorSize: Indicates the size of the cache write buffer access.

uint32_t busErrorAccess: Indicates the type of system bus access.

uint32_t busErrorMasterID: Indicates the crossbar switch bus master number of the captured cache write buffer bus error.

uint32_t busErrorOverrun: Indicates if another cache write buffer bus error is detected.

union _mcm_lmem_fault_attribute

#include <fsl_mcm.h>

The union of LMEM fault attribute.

Public Members

uint32_t attribute: Indicates the attributes of the LMEM fault detected.

struct _mcm_lmem_fault_attribute._mcm_lmem_fault_attribut attribute_memory

struct _mcm_lmem_fault_attribut

Public Members

uint32_t parityFaultProtectionSignal: Indicates the features of parity fault protection signal.

uint32_t parityFaultMasterSize: Indicates the parity fault master size.

uint32_t parityFaultWrite: Indicates the parity fault is caused by read or write.

uint32_t backdoorAccess: Indicates the LMEM access fault is initiated by core access or backdoor access.

uint32_t parityFaultSyndrome: Indicates the parity fault syndrome.

uint32_t overrun: Indicates the number of faultss.

MU: Messaging Unit#

void MU_Init(MU_Type *base)

Initializes the MU module.

This function enables the MU clock only.

Parameters:

base – MU peripheral base address.

void MU_Deinit(MU_Type *base)

De-initializes the MU module.

This function disables the MU clock only.

Parameters:

base – MU peripheral base address.

static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)

Writes a message to the TX register.

This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.

while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.

Parameters:

base – MU peripheral base address.
regIndex – TX register index, see mu_msg_reg_index_t.
msg – Message to send.

status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)

Blocks to send a message.

This function waits until the TX register is empty and sends the message. If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and returns kStatus_Timeout.

Parameters:

base – MU peripheral base address.
regIndex – MU message register, see mu_msg_reg_index_t.
msg – Message to send.

Return values:

kStatus_Success – Message sent successfully.
kStatus_Timeout – Timeout occurred while waiting for TX register to be empty.

Returns:

status_t

static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)

Reads a message from the RX register.

This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.

uint32_t msg;
while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
{
}  Wait for the RX0 register full.

msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.

Parameters:

base – MU peripheral base address.
regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue)

Blocks to receive a message with timeout protection.

This function waits until the RX register is full and receives the message. If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

This function provides the same blocking behavior as MU_ReceiveMsg() but with additional timeout protection to prevent system hangs if the other core becomes unresponsive or if hardware issues occur.

Note

Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that this function includes timeout protection while MU_ReceiveMsg() waits indefinitely.

Parameters:

base – MU peripheral base address.
regIndex – RX register index, see mu_msg_reg_index_t.
readValue – Pointer to store the received message.

Return values:

kStatus_Success – Message received successfully.
kStatus_InvalidArgument – Invalid readValue pointer.
kStatus_Timeout – Timeout occurred while waiting for RX register to be full.

Returns:

status_t

uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)

Blocks to receive a message (infinite wait, no timeout protection).

This function waits until the RX register is full and receives the message. This function will wait indefinitely until a message is received.

Note

Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that MU_ReceiveMsgTimeout() includes timeout protection while this function waits indefinitely.

Warning

This function does not include timeout protection and may cause system hangs if the other core becomes unresponsive. For applications requiring timeout protection, use MU_ReceiveMsgTimeout() instead.

Parameters:

base – MU peripheral base address.
regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)

Sets the 3-bit MU flags reflect on the other MU side.

This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.

while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
{
}  Wait for previous MU flags updating.

MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.

Parameters:

base – MU peripheral base address.
flags – The 3-bit MU flags to set.

status_t MU_SetFlags(MU_Type *base, uint32_t flags)

Blocks setting the 3-bit MU flags reflect on the other MU side.

This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.

If MU_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

Parameters:

base – MU peripheral base address.
flags – The 3-bit MU flags to set.

Return values:

kStatus_Success – Flags were set successfully.
kStatus_Timeout – Timeout occurred while waiting for flags to update.

Returns:

status_t

static inline uint32_t MU_GetFlags(MU_Type *base)

Gets the current value of the 3-bit MU flags set by the other side.

This function gets the current 3-bit MU flags on the current side.

Parameters:

base – MU peripheral base address.

Returns:

flags Current value of the 3-bit flags.

static inline uint32_t MU_GetStatusFlags(MU_Type *base)

Gets the MU status flags.

This function returns the bit mask of the MU status flags. See _mu_status_flags.

uint32_t flags;
flags = MU_GetStatusFlags(base);  Get all status flags.
if (kMU_Tx0EmptyFlag & flags)
{
    The TX0 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
}
if (kMU_Tx1EmptyFlag & flags)
{
    The TX1 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
}

Parameters:

base – MU peripheral base address.

Returns:

Bit mask of the MU status flags, see _mu_status_flags.

static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)

Return the RX status flags.

This function return the RX status flags. Note: RFn bits of SR[27-24](mu status register) are mapped in reverse numerical order: RF0 -> SR[27] RF1 -> SR[26] RF2 -> SR[25] RF3 -> SR[24]

status_reg = MU_GetRxStatusFlags(base);

Parameters:

base – MU peripheral base address.

Returns:

MU RX status

static inline uint32_t MU_GetInterruptsPending(MU_Type *base)

Gets the MU IRQ pending status of enabled interrupts.

This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag

Parameters:

base – MU peripheral base address.

Returns:

Bit mask of the MU IRQs pending.

static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask)

Clears the specific MU status flags.

This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.

Clear general interrupt 0 and general interrupt 1 pending flags.
MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);

Parameters:

base – MU peripheral base address.
mask – Bit mask of the MU status flags. See _mu_status_flags. The following flags are cleared by hardware, this function could not clear them.
- kMU_Tx0EmptyFlag
- kMU_Tx1EmptyFlag
- kMU_Tx2EmptyFlag
- kMU_Tx3EmptyFlag
- kMU_Rx0FullFlag
- kMU_Rx1FullFlag
- kMU_Rx2FullFlag
- kMU_Rx3FullFlag
- kMU_EventPendingFlag
- kMU_FlagsUpdatingFlag
- kMU_OtherSideInResetFlag

static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask)

Enables the specific MU interrupts.

This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.

   Enable general interrupt 0 and TX0 empty interrupt.
MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

Parameters:

base – MU peripheral base address.
mask – Bit mask of the MU interrupts. See _mu_interrupt_enable.

static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask)

Disables the specific MU interrupts.

This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.

   Disable general interrupt 0 and TX0 empty interrupt.
MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

Parameters:

base – MU peripheral base address.
mask – Bit mask of the MU interrupts. See _mu_interrupt_enable.

status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask)

Triggers interrupts to the other core.

This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}

Parameters:

base – MU peripheral base address.
mask – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.

Return values:

kStatus_Success – Interrupts have been triggered successfully.
kStatus_Fail – Previous interrupts have not been accepted.

static inline void MU_MaskHardwareReset(MU_Type *base, bool mask)

Mask hardware reset by the other core.

The other core could call MU_HardwareResetOtherCore() to reset current core. To mask the reset, call this function and pass in true.

Parameters:

base – MU peripheral base address.
mask – Pass true to mask the hardware reset, pass false to unmask it.

FSL_MU_DRIVER_VERSION: MU driver version.

enum _mu_status_flags

MU status flags.

Values:

enumerator kMU_Tx0EmptyFlag: TX0 empty.

enumerator kMU_Tx1EmptyFlag: TX1 empty.

enumerator kMU_Tx2EmptyFlag: TX2 empty.

enumerator kMU_Tx3EmptyFlag: TX3 empty.

enumerator kMU_Rx0FullFlag: RX0 full.

enumerator kMU_Rx1FullFlag: RX1 full.

enumerator kMU_Rx2FullFlag: RX2 full.

enumerator kMU_Rx3FullFlag: RX3 full.

enumerator kMU_GenInt0Flag: General purpose interrupt 0 pending.

enumerator kMU_GenInt1Flag: General purpose interrupt 1 pending.

enumerator kMU_GenInt2Flag: General purpose interrupt 2 pending.

enumerator kMU_GenInt3Flag: General purpose interrupt 3 pending.

enumerator kMU_EventPendingFlag: MU event pending.

enumerator kMU_FlagsUpdatingFlag: MU flags update is on-going.

enumerator kMU_ResetAssertInterruptFlag: The other core reset assert interrupt pending.

enumerator kMU_ResetDeassertInterruptFlag: The other core reset de-assert interrupt pending.

enumerator kMU_OtherSideInResetFlag: The other side is in reset.

enumerator kMU_MuResetInterruptFlag: The other side initializes MU reset.

enumerator kMU_HardwareResetInterruptFlag: Current side has been hardware reset by the other side.

enum _mu_interrupt_enable

MU interrupt source to enable.

Values:

enumerator kMU_Tx0EmptyInterruptEnable: TX0 empty.

enumerator kMU_Tx1EmptyInterruptEnable: TX1 empty.

enumerator kMU_Tx2EmptyInterruptEnable: TX2 empty.

enumerator kMU_Tx3EmptyInterruptEnable: TX3 empty.

enumerator kMU_Rx0FullInterruptEnable: RX0 full.

enumerator kMU_Rx1FullInterruptEnable: RX1 full.

enumerator kMU_Rx2FullInterruptEnable: RX2 full.

enumerator kMU_Rx3FullInterruptEnable: RX3 full.

enumerator kMU_GenInt0InterruptEnable: General purpose interrupt 0.

enumerator kMU_GenInt1InterruptEnable: General purpose interrupt 1.

enumerator kMU_GenInt2InterruptEnable: General purpose interrupt 2.

enumerator kMU_GenInt3InterruptEnable: General purpose interrupt 3.

enumerator kMU_ResetAssertInterruptEnable: The other core reset assert interrupt.

enumerator kMU_ResetDeassertInterruptEnable: The other core reset de-assert interrupt.

enumerator kMU_MuResetInterruptEnable: The other side initializes MU reset. The interrupt is ORed with the general purpose interrupt 3. The general purpose interrupt 3 is issued when the other side set the MU reset and this interrupt is enabled.

enumerator kMU_HardwareResetInterruptEnable: Current side has been hardware reset by the other side.

enum _mu_interrupt_trigger

MU interrupt that could be triggered to the other core.

Values:

enumerator kMU_GenInt0InterruptTrigger: General purpose interrupt 0.

enumerator kMU_GenInt1InterruptTrigger: General purpose interrupt 1.

enumerator kMU_GenInt2InterruptTrigger: General purpose interrupt 2.

enumerator kMU_GenInt3InterruptTrigger: General purpose interrupt 3.

enum _mu_msg_reg_index

MU message register.

Values:

enumerator kMU_MsgReg0

enumerator kMU_MsgReg1

enumerator kMU_MsgReg2

enumerator kMU_MsgReg3

typedef enum _mu_msg_reg_index mu_msg_reg_index_t: MU message register.

MU_CR_NMI_MASK

MU_BUSY_POLL_COUNT

Maximum polling iterations for MU waiting loops.

This parameter defines the maximum number of iterations for any polling loop in the MU code before timing out and returning an error.

It applies to all waiting loops in MU driver, such as waiting for TX register to be empty or waiting for RX register to be full.

This is a count of loop iterations, not a time-based value.

If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if a core becomes unresponsive.

MU_GET_CORE_FLAG(flags)

MU_GET_STAT_FLAG(flags)

MU_GET_TX_FLAG(flags)

MU_GET_RX_FLAG(flags)

MU_GET_GI_FLAG(flags)

PWM: Pulse Width Modulation Driver#

status_t PWM_Init(PWM_Type *base, const pwm_config_t *config)

Ungates the PWM clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the PWM driver.

Parameters:

base – PWM peripheral base address
config – Pointer to user’s PWM config structure.

Returns:

kStatus_Success means success; else failed.

void PWM_Deinit(PWM_Type *base)

Gate the PWM submodule clock.

Parameters:

base – PWM peripheral base address

void PWM_GetDefaultConfig(pwm_config_t *config)

Fill in the PWM config struct with the default settings.

The default values are:

config->enableStopMode = false;
config->enableDozeMode = false;
config->enableWaitMode = false;
config->enableDozeMode = false;
config->clockSource = kPWM_LowFrequencyClock;
config->prescale = 0U;
config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison;
config->fifoWater = kPWM_FIFOWaterMark_2;
config->sampleRepeat = kPWM_EachSampleOnce;
config->byteSwap = kPWM_ByteNoSwap;
config->halfWordSwap = kPWM_HalfWordNoSwap;

Parameters:

config – Pointer to user’s PWM config structure.

static inline void PWM_StartTimer(PWM_Type *base)

Starts the PWM counter when the PWM is enabled.

When the PWM is enabled, it begins a new period, the output pin is set to start a new period while the prescaler and counter are released and counting begins.

Parameters:

base – PWM peripheral base address

static inline void PWM_StopTimer(PWM_Type *base)

Stops the PWM counter when the pwm is disabled.

Parameters:

base – PWM peripheral base address

static inline void PWM_EnableInterrupts(PWM_Type *base, uint32_t mask)

Enables the selected PWM interrupts.

Parameters:

base – PWM peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t

static inline void PWM_DisableInterrupts(PWM_Type *base, uint32_t mask)

Disables the selected PWM interrupts.

Parameters:

base – PWM peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t

static inline uint32_t PWM_GetEnabledInterrupts(PWM_Type *base)

Gets the enabled PWM interrupts.

Parameters:

base – PWM peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration pwm_interrupt_enable_t

static inline uint32_t PWM_GetStatusFlags(PWM_Type *base)

Gets the PWM status flags.

Parameters:

base – PWM peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration pwm_status_flags_t

static inline void PWM_clearStatusFlags(PWM_Type *base, uint32_t mask)

Clears the PWM status flags.

Parameters:

base – PWM peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration pwm_status_flags_t

static inline uint32_t PWM_GetFIFOAvailable(PWM_Type *base)

Gets the PWM FIFO available.

Parameters:

base – PWM peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration pwm_fifo_available_t

static inline void PWM_SetSampleValue(PWM_Type *base, uint32_t value)

Sets the PWM sample value.

Parameters:

base – PWM peripheral base address
value – The sample value. This is the input to the 4x16 FIFO. The value in this register denotes the value of the sample being currently used.

static inline uint32_t PWM_GetSampleValue(PWM_Type *base)

Gets the PWM sample value.

Parameters:

base – PWM peripheral base address

Returns:

The sample value. It can be read only when the PWM is enable.

FSL_PWM_DRIVER_VERSION

enum _pwm_clock_source

PWM clock source select.

Values:

enumerator kPWM_PeripheralClock: The Peripheral clock is used as the clock

enumerator kPWM_HighFrequencyClock: High-frequency reference clock is used as the clock

enumerator kPWM_LowFrequencyClock: Low-frequency reference clock(32KHz) is used as the clock

enum _pwm_fifo_water_mark

PWM FIFO water mark select. Sets the data level at which the FIFO empty flag will be set.

Values:

enumerator kPWM_FIFOWaterMark_1: FIFO empty flag is set when there are more than or equal to 1 empty slots

enumerator kPWM_FIFOWaterMark_2: FIFO empty flag is set when there are more than or equal to 2 empty slots

enumerator kPWM_FIFOWaterMark_3: FIFO empty flag is set when there are more than or equal to 3 empty slots

enumerator kPWM_FIFOWaterMark_4: FIFO empty flag is set when there are more than or equal to 4 empty slots

enum _pwm_byte_data_swap

PWM byte data swap select. It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register.

Values:

enumerator kPWM_ByteNoSwap: byte ordering remains the same

enumerator kPWM_ByteSwap: byte ordering is reversed

enum _pwm_half_word_data_swap

PWM half-word data swap select.

Values:

enumerator kPWM_HalfWordNoSwap: Half word swapping does not take place

enumerator kPWM_HalfWordSwap: Half word from write data bus are swapped

enum _pwm_output_configuration

PWM Output Configuration.

Values:

enumerator kPWM_SetAtRolloverAndClearAtcomparison: Output pin is set at rollover and cleared at comparison

enumerator kPWM_ClearAtRolloverAndSetAtcomparison: Output pin is cleared at rollover and set at comparison

enumerator kPWM_NoConfigure: PWM output is disconnected

enum _pwm_sample_repeat

PWM FIFO sample repeat It determines the number of times each sample from the FIFO is to be used.

Values:

enumerator kPWM_EachSampleOnce: Use each sample once

enumerator kPWM_EachSampletwice: Use each sample twice

enumerator kPWM_EachSampleFourTimes: Use each sample four times

enumerator kPWM_EachSampleEightTimes: Use each sample eight times

enum _pwm_interrupt_enable

List of PWM interrupt options.

Values:

enumerator kPWM_FIFOEmptyInterruptEnable: This bit controls the generation of the FIFO Empty interrupt.

enumerator kPWM_RolloverInterruptEnable: This bit controls the generation of the Rollover interrupt.

enumerator kPWM_CompareInterruptEnable: This bit controls the generation of the Compare interrupt

enum _pwm_status_flags

List of PWM status flags.

Values:

enumerator kPWM_FIFOEmptyFlag: This bit indicates the FIFO data level in comparison to the water level set by FWM field in the control register.

enumerator kPWM_RolloverFlag: This bit shows that a roll-over event has occurred.

enumerator kPWM_CompareFlag: This bit shows that a compare event has occurred.

enumerator kPWM_FIFOWriteErrorFlag: This bit shows that an attempt has been made to write FIFO when it is full.

enum _pwm_fifo_available

List of PWM FIFO available.

Values:

enumerator kPWM_NoDataInFIFOFlag: No data available

enumerator kPWM_OneWordInFIFOFlag: 1 word of data in FIFO

enumerator kPWM_TwoWordsInFIFOFlag: 2 word of data in FIFO

enumerator kPWM_ThreeWordsInFIFOFlag: 3 word of data in FIFO

enumerator kPWM_FourWordsInFIFOFlag: 4 word of data in FIFO

typedef enum _pwm_clock_source pwm_clock_source_t: PWM clock source select.

typedef enum _pwm_fifo_water_mark pwm_fifo_water_mark_t: PWM FIFO water mark select. Sets the data level at which the FIFO empty flag will be set.

typedef enum _pwm_byte_data_swap pwm_byte_data_swap_t: PWM byte data swap select. It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register.

typedef enum _pwm_half_word_data_swap pwm_half_word_data_swap_t: PWM half-word data swap select.

typedef enum _pwm_output_configuration pwm_output_configuration_t: PWM Output Configuration.

typedef enum _pwm_sample_repeat pwm_sample_repeat_t: PWM FIFO sample repeat It determines the number of times each sample from the FIFO is to be used.

typedef enum _pwm_interrupt_enable pwm_interrupt_enable_t: List of PWM interrupt options.

typedef enum _pwm_status_flags pwm_status_flags_t: List of PWM status flags.

typedef enum _pwm_fifo_available pwm_fifo_available_t: List of PWM FIFO available.

typedef struct _pwm_config pwm_config_t

static inline void PWM_SoftwareReset(PWM_Type *base)

Sofrware reset.

PWM is reset when this bit is set to 1. It is a self clearing bit. Setting this bit resets all the registers to their reset values except for the STOPEN, DOZEN, WAITEN, and DBGEN bits in this control register.

Parameters:

base – PWM peripheral base address

static inline void PWM_SetPeriodValue(PWM_Type *base, uint32_t value)

Sets the PWM period value.

Parameters:

base – PWM peripheral base address
value – The period value. The PWM period register (PWM_PWMPR) determines the period of the PWM output signal. Writing 0xFFFF to this register will achieve the same result as writing 0xFFFE. PWMO (Hz) = PCLK(Hz) / (period +2)

static inline uint32_t PWM_GetPeriodValue(PWM_Type *base)

Gets the PWM period value.

Parameters:

base – PWM peripheral base address

Returns:

The period value. The PWM period register (PWM_PWMPR) determines the period of the PWM output signal.

static inline uint32_t PWM_GetCounterValue(PWM_Type *base)

Gets the PWM counter value.

Parameters:

base – PWM peripheral base address

Returns:

The counter value. The current count value.

struct _pwm_config

Public Members

bool enableStopMode: True: PWM continues to run in stop mode; False: PWM is paused in stop mode.

bool enableDozeMode: True: PWM continues to run in doze mode; False: PWM is paused in doze mode.

bool enableWaitMode: True: PWM continues to run in wait mode; False: PWM is paused in wait mode.

bool enableDebugMode: True: PWM continues to run in debug mode; False: PWM is paused in debug mode.

uint16_t prescale: Pre-scaler to divide down the clock The prescaler value is not more than 0xFFF. Divide by (value + 1)

pwm_clock_source_t clockSource: Clock source for the counter

pwm_output_configuration_t outputConfig: Set the mode of the PWM output on the output pin.

pwm_fifo_water_mark_t fifoWater: Set the data level for FIFO.

pwm_sample_repeat_t sampleRepeat: The number of times each sample from the FIFO is to be used.

pwm_byte_data_swap_t byteSwap: It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register.

pwm_half_word_data_swap_t halfWordSwap: It determines which half word data from the 32-bit IP Bus interface is written into the lower 16 bits of the sample register.

QSPI: Quad Serial Peripheral Interface#

Quad Serial Peripheral Interface Driver#

uint32_t QSPI_GetInstance(QuadSPI_Type *base)

Get the instance number for QSPI.

Parameters:

base – QSPI base pointer.

void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz)

Initializes the QSPI module and internal state.

This function enables the clock for QSPI and also configures the QSPI with the input configure parameters. Users should call this function before any QSPI operations.

Parameters:

base – Pointer to QuadSPI Type.
config – QSPI configure structure.
srcClock_Hz – QSPI source clock frequency in Hz.

void QSPI_GetDefaultQspiConfig(qspi_config_t *config)

Gets default settings for QSPI.

Parameters:

config – QSPI configuration structure.

void QSPI_Deinit(QuadSPI_Type *base)

Deinitializes the QSPI module.

Clears the QSPI state and QSPI module registers.

Parameters:

base – Pointer to QuadSPI Type.

void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config)

Configures the serial flash parameter.

This function configures the serial flash relevant parameters, such as the size, command, and so on. The flash configuration value cannot have a default value. The user needs to configure it according to the QSPI features.

Parameters:

base – Pointer to QuadSPI Type.
config – Flash configuration parameters.

void QSPI_SetDelayChainConfig(QuadSPI_Type *base, qspi_delay_chain_config_t *config)

Configures the delay chain parameter.

This function configures the slave delay chain.

Parameters:

base – Pointer to QuadSPI Type.
config – Delay chain configuration parameters.

void QSPI_SoftwareReset(QuadSPI_Type *base)

Software reset for the QSPI logic.

This function sets the software reset flags for both AHB and buffer domain and resets both AHB buffer and also IP FIFOs.

Parameters:

base – Pointer to QuadSPI Type.

static inline void QSPI_Enable(QuadSPI_Type *base, bool enable)

Enables or disables the QSPI module.

Parameters:

base – Pointer to QuadSPI Type.
enable – True means enable QSPI, false means disable.

static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base)

Gets the state value of QSPI.

Parameters:

base – Pointer to QuadSPI Type.

Returns:

status flag, use status flag to AND _qspi_flags could get the related status.

static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base)

Gets QSPI error status flags.

Parameters:

base – Pointer to QuadSPI Type.

Returns:

status flag, use status flag to AND _qspi_error_flags could get the related status.

static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask)

Clears the QSPI error flags.

Parameters:

base – Pointer to QuadSPI Type.
mask – Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags.

static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask)

Enables the QSPI interrupts.

Parameters:

base – Pointer to QuadSPI Type.
mask – QSPI interrupt source.

static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask)

Disables the QSPI interrupts.

Parameters:

base – Pointer to QuadSPI Type.
mask – QSPI interrupt source.

static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable)

Enables the QSPI DMA source.

Parameters:

base – Pointer to QuadSPI Type.
mask – QSPI DMA source.
enable – True means enable DMA, false means disable.

static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base)

Gets the Tx data register address. It is used for DMA operation.

Parameters:

base – Pointer to QuadSPI Type.

Returns:

QSPI Tx data register address.

uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base)

Gets the Rx data register address used for DMA operation.

This function returns the Rx data register address or Rx buffer address according to the Rx read area settings.

Parameters:

base – Pointer to QuadSPI Type.

Returns:

QSPI Rx data register address.

static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)

Sets the IP command address.

Parameters:

base – Pointer to QuadSPI Type.
addr – IP command address.

static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)

Sets the IP command size.

Parameters:

base – Pointer to QuadSPI Type.
size – IP command size.

void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index)

Executes IP commands located in LUT table.

Parameters:

base – Pointer to QuadSPI Type.
index – IP command located in which LUT table index.

void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index)

Executes AHB commands located in LUT table.

Parameters:

base – Pointer to QuadSPI Type.
index – AHB command located in which LUT table index.

static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable)

Enables/disables the QSPI IP command parallel mode.

Parameters:

base – Pointer to QuadSPI Type.
enable – True means enable parallel mode, false means disable parallel mode.

static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)

Enables/disables the QSPI AHB command parallel mode.

Parameters:

base – Pointer to QuadSPI Type.
enable – True means enable parallel mode, false means disable parallel mode.

void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd)

Updates the LUT table.

Parameters:

base – Pointer to QuadSPI Type.
index – Which LUT index needs to be located. It should be an integer divided by 4.
cmd – Command sequence array.

static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask)

Clears the QSPI FIFO logic.

Parameters:

base – Pointer to QuadSPI Type.
mask – Which kind of QSPI FIFO to be cleared.

static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq)

@ brief Clears the command sequence for the IP/buffer command.

This function can reset the command sequence.

Parameters:

base – QSPI base address.
seq – Which command sequence need to reset, IP command, buffer command or both.

static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)

Enable or disable DDR mode.

Parameters:

base – QSPI base pointer
enable – True means enable DDR mode, false means disable DDR mode.

void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area)

@ brief Set the RX buffer readout area.

This function can set the RX buffer readout, from AHB bus or IP Bus.

Parameters:

base – QSPI base address.
area – QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.

void QSPI_WriteBlocking(QuadSPI_Type *base, const uint32_t *buffer, size_t size)

Sends a buffer of data bytes using a blocking method.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – QSPI base pointer
buffer – The data bytes to send
size – The number of data bytes to send

static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)

Writes data into FIFO.

Parameters:

base – QSPI base pointer
data – The data bytes to send

void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size)

Receives a buffer of data bytes using a blocking method.

Note

This function blocks via polling until all bytes have been sent. Users shall notice that this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. For flash contents read, please use AHB bus read, this is much more efficiency.

Parameters:

base – QSPI base pointer
buffer – The data bytes to send
size – The number of data bytes to receive

uint32_t QSPI_ReadData(QuadSPI_Type *base)

Receives data from data FIFO.

Parameters:

base – QSPI base pointer

Returns:

The data in the FIFO.

static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)

Writes data to the QSPI transmit buffer.

This function writes a continuous data to the QSPI transmit FIFO. This function is a block function and can return only when finished. This function uses polling methods.

Parameters:

base – Pointer to QuadSPI Type.
xfer – QSPI transfer structure.

static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)

Reads data from the QSPI receive buffer in polling way.

This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking function and can return only when finished. This function uses polling methods. Users shall notice that this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers. For flash contents read, please use AHB bus read, this is much more efficiency.

Parameters:

base – Pointer to QuadSPI Type.
xfer – QSPI transfer structure.

FSL_QSPI_DRIVER_VERSION: QSPI driver version.

Status structure of QSPI.

Values:

enumerator kStatus_QSPI_Idle: QSPI is in idle state

enumerator kStatus_QSPI_Busy: QSPI is busy

enumerator kStatus_QSPI_Error: Error occurred during QSPI transfer

enum _qspi_read_area

QSPI read data area, from IP FIFO or AHB buffer.

Values:

enumerator kQSPI_ReadAHB: QSPI read from AHB buffer.

enumerator kQSPI_ReadIP: QSPI read from IP FIFO.

enum _qspi_command_seq

QSPI command sequence type.

Values:

enumerator kQSPI_IPSeq: IP command sequence

enumerator kQSPI_BufferSeq: Buffer command sequence

enumerator kQSPI_AllSeq

enum _qspi_fifo

QSPI buffer type.

Values:

enumerator kQSPI_TxFifo: QSPI Tx FIFO

enumerator kQSPI_RxFifo: QSPI Rx FIFO

enumerator kQSPI_AllFifo: QSPI all FIFO, including Tx and Rx

enum _qspi_error_flags

QSPI error flags.

Values:

enumerator kQSPI_DataLearningFail: Data learning pattern failure flag

enumerator kQSPI_TxBufferFill: Tx buffer fill flag

enumerator kQSPI_TxBufferUnderrun: Tx buffer underrun flag

enumerator kQSPI_IllegalInstruction: Illegal instruction error flag

enumerator kQSPI_RxBufferOverflow: Rx buffer overflow flag

enumerator kQSPI_RxBufferDrain: Rx buffer drain flag

enumerator kQSPI_AHBSequenceError: AHB sequence error flag

enumerator kQSPI_AHBBufferOverflow: AHB buffer overflow flag

enumerator kQSPI_IPCommandUsageError: IP command usage error flag

enumerator kQSPI_IPCommandTriggerDuringAHBAccess: IP command trigger during AHB access error

enumerator kQSPI_IPCommandTriggerDuringIPAccess: IP command trigger cannot be executed

enumerator kQSPI_IPCommandTriggerDuringAHBGrant: IP command trigger during AHB grant error

enumerator kQSPI_IPCommandTransactionFinished: IP command transaction finished flag

enumerator kQSPI_FlagAll: All error flag

enum _qspi_flags

QSPI state bit.

Values:

enumerator kQSPI_DataLearningSamplePoint: Data learning sample point

enumerator kQSPI_TxBufferFull: Tx buffer full flag

enumerator kQSPI_TxBufferEnoughData: Tx buffer enough data available

enumerator kQSPI_RxDMA: Rx DMA is requesting or running

enumerator kQSPI_RxBufferFull: Rx buffer full

enumerator kQSPI_RxWatermark: Rx buffer watermark exceeded

enumerator kQSPI_AHB3BufferFull: AHB buffer 3 full

enumerator kQSPI_AHB2BufferFull: AHB buffer 2 full

enumerator kQSPI_AHB1BufferFull: AHB buffer 1 full

enumerator kQSPI_AHB0BufferFull: AHB buffer 0 full

enumerator kQSPI_AHB3BufferNotEmpty: AHB buffer 3 not empty

enumerator kQSPI_AHB2BufferNotEmpty: AHB buffer 2 not empty

enumerator kQSPI_AHB1BufferNotEmpty: AHB buffer 1 not empty

enumerator kQSPI_AHB0BufferNotEmpty: AHB buffer 0 not empty

enumerator kQSPI_AHBTransactionPending: AHB access transaction pending

enumerator kQSPI_AHBCommandPriorityGranted: AHB command priority granted

enumerator kQSPI_AHBAccess: AHB access

enumerator kQSPI_IPAccess: IP access

enumerator kQSPI_Busy: Module busy

enumerator kQSPI_StateAll: All flags

enum _qspi_interrupt_enable

QSPI interrupt enable.

Values:

enumerator kQSPI_DataLearningFailInterruptEnable: Data learning pattern failure interrupt enable

enumerator kQSPI_TxBufferFillInterruptEnable: Tx buffer fill interrupt enable

enumerator kQSPI_TxBufferUnderrunInterruptEnable: Tx buffer underrun interrupt enable

enumerator kQSPI_IllegalInstructionInterruptEnable: Illegal instruction error interrupt enable

enumerator kQSPI_RxBufferOverflowInterruptEnable: Rx buffer overflow interrupt enable

enumerator kQSPI_RxBufferDrainInterruptEnable: Rx buffer drain interrupt enable

enumerator kQSPI_AHBSequenceErrorInterruptEnable: AHB sequence error interrupt enable

enumerator kQSPI_AHBBufferOverflowInterruptEnable: AHB buffer overflow interrupt enable

enumerator kQSPI_IPCommandUsageErrorInterruptEnable: IP command usage error interrupt enable

enumerator kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable: IP command trigger during AHB access error

enumerator kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable: IP command trigger cannot be executed

enumerator kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable: IP command trigger during AHB grant error

enumerator kQSPI_IPCommandTransactionFinishedInterruptEnable: IP command transaction finished interrupt enable

enumerator kQSPI_AllInterruptEnable: All error interrupt enable

enum _qspi_dma_enable

QSPI DMA request flag.

Values:

enumerator kQSPI_RxBufferDrainDMAEnable: Rx buffer drain DMA

enumerator kQSPI_AllDDMAEnable

enum _qspi_dqs_phrase_shift

Phrase shift number for DQS mode.

Values:

enumerator kQSPI_DQSNoPhraseShift: No phase shift

enumerator kQSPI_DQSPhraseShift45Degree: Select 45 degree phase shift

enumerator kQSPI_DQSPhraseShift90Degree: Select 90 degree phase shift

enumerator kQSPI_DQSPhraseShift135Degree: Select 135 degree phase shift

enum _qspi_dqs_read_sample_clock

Qspi read sampling option.

Values:

enumerator kQSPI_ReadSampleClkInternalLoopback: Read sample clock adopts internal loopback mode.

enumerator kQSPI_ReadSampleClkLoopbackFromDqsPad: Dummy Read strobe generated by QSPI Controller and loopback from DQS pad.

enumerator kQSPI_ReadSampleClkExternalInputFromDqsPad: Flash provided Read strobe and input from DQS pad.

typedef enum _qspi_read_area qspi_read_area_t: QSPI read data area, from IP FIFO or AHB buffer.

typedef enum _qspi_command_seq qspi_command_seq_t: QSPI command sequence type.

typedef enum _qspi_fifo qspi_fifo_t: QSPI buffer type.

typedef enum _qspi_dqs_phrase_shift qspi_dqs_phrase_shift_t: Phrase shift number for DQS mode.

typedef enum _qspi_dqs_read_sample_clock qspi_dqs_read_sample_clock_t: Qspi read sampling option.

typedef struct QspiDQSConfig qspi_dqs_config_t: DQS configure features.

typedef struct QspiFlashTiming qspi_flash_timing_t: Flash timing configuration.

typedef struct QspiConfig qspi_config_t: QSPI configuration structure.

typedef struct _qspi_flash_config qspi_flash_config_t: External flash configuration items.

typedef struct _qspi_transfer qspi_transfer_t: Transfer structure for QSPI.

typedef struct _ip_command_config ip_command_config_t: 16-bit access reg for IPCR register

typedef struct _qspi_delay_chain_config qspi_delay_chain_config_t: Slave delay chain configuration items.

QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1): Macro functions for LUT table.

QSPI_CMD: Macro for QSPI LUT command.

QSPI_ADDR

QSPI_DUMMY

QSPI_MODE

QSPI_MODE2

QSPI_MODE4

QSPI_READ

QSPI_WRITE

QSPI_JMP_ON_CS

QSPI_ADDR_DDR

QSPI_MODE_DDR

QSPI_MODE2_DDR

QSPI_MODE4_DDR

QSPI_READ_DDR

QSPI_WRITE_DDR

QSPI_DATA_LEARN

QSPI_CMD_DDR

QSPI_CADDR

QSPI_CADDR_DDR

QSPI_STOP

QSPI_PAD_1: Macro for QSPI PAD.

QSPI_PAD_2

QSPI_PAD_4

QSPI_PAD_8

struct QspiDQSConfig

#include <fsl_qspi.h>

DQS configure features.

Public Members

uint32_t portADelayTapNum: Delay chain tap number selection for QSPI port A DQS

qspi_dqs_phrase_shift_t shift: Phase shift for internal DQS generation

qspi_dqs_read_sample_clock_t rxSampleClock: Read sample clock for Dqs.

bool enableDQSClkInverse: Enable inverse clock for internal DQS generation

struct QspiFlashTiming

#include <fsl_qspi.h>

Flash timing configuration.

Public Members

uint32_t dataHoldTime: Serial flash data in hold time

uint32_t CSHoldTime: Serial flash CS hold time in terms of serial flash clock cycles

uint32_t CSSetupTime: Serial flash CS setup time in terms of serial flash clock cycles

struct QspiConfig

#include <fsl_qspi.h>

QSPI configuration structure.

Public Members

uint8_t txWatermark: QSPI transmit watermark value

uint8_t rxWatermark: QSPI receive watermark value.

uint32_t AHBbufferSize[1]: AHB buffer size.

uint8_t AHBbufferMaster[1]: AHB buffer master.

bool enableAHBbuffer3AllMaster: Is AHB buffer3 for all master.

qspi_read_area_t area: Which area Rx data readout

bool enableQspi: Enable QSPI after initialization

struct _qspi_flash_config

#include <fsl_qspi.h>

External flash configuration items.

Public Members

uint32_t flashA1Size: Flash A1 size

uint32_t flashA2Size: Flash A2 size

uint32_t flashB1Size: Flash B1 size

uint32_t flashB2Size: Flash B2 size

uint32_t lookuptable[1]: Flash command in LUT

uint32_t CSHoldTime: CS line hold time

uint32_t CSSetupTime: CS line setup time

uint32_t cloumnspace: Column space size

uint32_t dataLearnValue: Data Learn value if enable data learn

bool enableWordAddress: If enable word address.

struct _qspi_transfer

#include <fsl_qspi.h>

Transfer structure for QSPI.

Public Members

uint32_t *data: Pointer to data to transmit

size_t dataSize: Bytes to be transmit

struct _ip_command_config: #include <fsl_qspi.h>

16-bit access reg for IPCR register

struct _qspi_delay_chain_config

#include <fsl_qspi.h>

Slave delay chain configuration items.

Public Members

bool highFreqDelay: Selects delay chain for low/high frequency of operation.

union IPCR_REG

Public Members

__IO uint32_t IPCR: IP Configuration Register

struct _ip_command_config BITFIELD

struct BITFIELD

Public Members

__IO uint16_t IDATZ: 16-bit access for IDATZ field in IPCR register

__IO uint8_t RESERVED_0: 8-bit access for RESERVED_0 field in IPCR register

__IO uint8_t SEQID: 8-bit access for SEQID field in IPCR register

RDC: Resource Domain Controller#

enum _rdc_interrupts

RDC interrupts.

Values:

enumerator kRDC_RestoreCompleteInterrupt: Interrupt generated when the RDC has completed restoring state to a recently re-powered memory regions.

enum _rdc_flags

RDC status.

Values:

enumerator kRDC_PowerDownDomainOn: Power down domain is ON.

enum _rdc_access_policy

Access permission policy.

Values:

enumerator kRDC_NoAccess: Could not read or write.

enumerator kRDC_WriteOnly: Write only.

enumerator kRDC_ReadOnly: Read only.

enumerator kRDC_ReadWrite: Read and write.

typedef struct _rdc_hardware_config rdc_hardware_config_t: RDC hardware configuration.

typedef struct _rdc_domain_assignment rdc_domain_assignment_t: Master domain assignment.

typedef struct _rdc_periph_access_config rdc_periph_access_config_t: Peripheral domain access permission configuration.

typedef struct _rdc_mem_access_config rdc_mem_access_config_t

Memory region domain access control configuration.

Note that when setting the rdc_mem_access_config_t::baseAddress and rdc_mem_access_config_t::endAddress, should be aligned to the region resolution, see rdc_mem_t definitions.

typedef struct _rdc_mem_status rdc_mem_status_t: Memory region access violation status.

void RDC_Init(RDC_Type *base)

Initializes the RDC module.

This function enables the RDC clock.

Parameters:

base – RDC peripheral base address.

void RDC_Deinit(RDC_Type *base)

De-initializes the RDC module.

This function disables the RDC clock.

Parameters:

base – RDC peripheral base address.

void RDC_GetHardwareConfig(RDC_Type *base, rdc_hardware_config_t *config)

Gets the RDC hardware configuration.

This function gets the RDC hardware configurations, including number of bus masters, number of domains, number of memory regions and number of peripherals.

Parameters:

base – RDC peripheral base address.
config – Pointer to the structure to get the configuration.

static inline void RDC_EnableInterrupts(RDC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

base – RDC peripheral base address.
mask – Interrupts to enable, it is OR’ed value of enum _rdc_interrupts.

static inline void RDC_DisableInterrupts(RDC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

base – RDC peripheral base address.
mask – Interrupts to disable, it is OR’ed value of enum _rdc_interrupts.

static inline uint32_t RDC_GetInterruptStatus(RDC_Type *base)

Get the interrupt pending status.

Parameters:

base – RDC peripheral base address.

Returns:

Interrupts pending status, it is OR’ed value of enum _rdc_interrupts.

static inline void RDC_ClearInterruptStatus(RDC_Type *base, uint32_t mask)

Clear interrupt pending status.

Parameters:

base – RDC peripheral base address.
mask – Status to clear, it is OR’ed value of enum _rdc_interrupts.

static inline uint32_t RDC_GetStatus(RDC_Type *base)

Get RDC status.

Parameters:

base – RDC peripheral base address.

Returns:

mask RDC status, it is OR’ed value of enum _rdc_flags.

static inline void RDC_ClearStatus(RDC_Type *base, uint32_t mask)

Clear RDC status.

Parameters:

base – RDC peripheral base address.
mask – RDC status to clear, it is OR’ed value of enum _rdc_flags.

void RDC_SetMasterDomainAssignment(RDC_Type *base, rdc_master_t master, const rdc_domain_assignment_t *domainAssignment)

Set master domain assignment.

Parameters:

base – RDC peripheral base address.
master – Which master to set.
domainAssignment – Pointer to the assignment.

void RDC_GetDefaultMasterDomainAssignment(rdc_domain_assignment_t *domainAssignment)

Get default master domain assignment.

The default configuration is:

assignment->domainId = 0U;
assignment->lock = 0U;

Parameters:

domainAssignment – Pointer to the assignment.

static inline void RDC_LockMasterDomainAssignment(RDC_Type *base, rdc_master_t master)

Lock master domain assignment.

Once locked, it could not be unlocked until next reset.

Parameters:

base – RDC peripheral base address.
master – Which master to lock.

void RDC_SetPeriphAccessConfig(RDC_Type *base, const rdc_periph_access_config_t *config)

Set peripheral access policy.

Parameters:

base – RDC peripheral base address.
config – Pointer to the policy configuration.

void RDC_GetDefaultPeriphAccessConfig(rdc_periph_access_config_t *config)

Get default peripheral access policy.

The default configuration is:

config->lock = false;
config->enableSema = false;
config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(1, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(2, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(3, kRDC_ReadWrite);

Parameters:

config – Pointer to the policy configuration.

static inline void RDC_LockPeriphAccessConfig(RDC_Type *base, rdc_periph_t periph)

Lock peripheral access policy configuration.

Once locked, it could not be unlocked until reset.

Parameters:

base – RDC peripheral base address.
periph – Which peripheral to lock.

static inline uint8_t RDC_GetPeriphAccessPolicy(RDC_Type *base, rdc_periph_t periph, uint8_t domainId)

Get the peripheral access policy for specific domain.

Parameters:

base – RDC peripheral base address.
periph – Which peripheral to get.
domainId – Get policy for which domain.

Returns:

Access policy, see _rdc_access_policy.

void RDC_SetMemAccessConfig(RDC_Type *base, const rdc_mem_access_config_t *config)

Set memory region access policy.

Note that when setting the baseAddress and endAddress in config, should be aligned to the region resolution, see rdc_mem_t definitions.

Parameters:

base – RDC peripheral base address.
config – Pointer to the policy configuration.

void RDC_GetDefaultMemAccessConfig(rdc_mem_access_config_t *config)

Get default memory region access policy.

The default configuration is:

config->lock = false;
config->baseAddress = 0;
config->endAddress = 0;
config->policy = RDC_ACCESS_POLICY(0, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(1, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(2, kRDC_ReadWrite) |
                 RDC_ACCESS_POLICY(3, kRDC_ReadWrite);

Parameters:

config – Pointer to the policy configuration.

static inline void RDC_LockMemAccessConfig(RDC_Type *base, rdc_mem_t mem)

Lock memory access policy configuration.

Once locked, it could not be unlocked until reset. After locked, you can only call RDC_SetMemAccessValid to enable the configuration, but can not disable it or change other settings.

Parameters:

base – RDC peripheral base address.
mem – Which memory region to lock.

static inline void RDC_SetMemAccessValid(RDC_Type *base, rdc_mem_t mem, bool valid)

Enable or disable memory access policy configuration.

Parameters:

base – RDC peripheral base address.
mem – Which memory region to operate.
valid – Pass in true to valid, false to invalid.

void RDC_GetMemViolationStatus(RDC_Type *base, rdc_mem_t mem, rdc_mem_status_t *status)

Get the memory region violation status.

The first access violation is captured. Subsequent violations are ignored until the status register is cleared. Contents are cleared upon reading the register. Clearing of contents occurs only when the status is read by the memory region’s associated domain ID(s).

Parameters:

base – RDC peripheral base address.
mem – Which memory region to get.
status – The returned status.

static inline void RDC_ClearMemViolationFlag(RDC_Type *base, rdc_mem_t mem)

Clear the memory region violation flag.

Parameters:

base – RDC peripheral base address.
mem – Which memory region to clear.

static inline uint8_t RDC_GetMemAccessPolicy(RDC_Type *base, rdc_mem_t mem, uint8_t domainId)

Get the memory region access policy for specific domain.

Parameters:

base – RDC peripheral base address.
mem – Which memory region to get.
domainId – Get policy for which domain.

Returns:

Access policy, see _rdc_access_policy.

static inline uint8_t RDC_GetCurrentMasterDomainId(RDC_Type *base)

Gets the domain ID of the current bus master.

This function returns the domain ID of the current bus master.

Parameters:

base – RDC peripheral base address.

Returns:

Domain ID of current bus master.

FSL_RDC_DRIVER_VERSION

RDC_ACCESS_POLICY(domainID, policy)

struct _rdc_hardware_config

#include <fsl_rdc.h>

RDC hardware configuration.

Public Members

uint32_t domainNumber: Number of domains.

uint32_t masterNumber: Number of bus masters.

uint32_t periphNumber: Number of peripherals.

uint32_t memNumber: Number of memory regions.

struct _rdc_domain_assignment

#include <fsl_rdc.h>

Master domain assignment.

Public Members

uint32_t domainId: Domain ID.

uint32_t __pad0__: Reserved.

uint32_t lock: Lock the domain assignment.

struct _rdc_periph_access_config

#include <fsl_rdc.h>

Peripheral domain access permission configuration.

Public Members

rdc_periph_t periph: Peripheral name.

bool lock: Lock the permission until reset.

bool enableSema: Enable semaphore or not, when enabled, master should call RDC_SEMA42_Lock to lock the semaphore gate accordingly before access the peripheral.

uint16_t policy: Access policy.

struct _rdc_mem_access_config

#include <fsl_rdc.h>

Memory region domain access control configuration.

Note that when setting the rdc_mem_access_config_t::baseAddress and rdc_mem_access_config_t::endAddress, should be aligned to the region resolution, see rdc_mem_t definitions.

Public Members

rdc_mem_t mem: Memory region descriptor name.

bool lock: Lock the configuration.

uint64_t baseAddress: Start address of the memory region.

uint64_t endAddress: End address of the memory region.

uint16_t policy: Access policy.

struct _rdc_mem_status

#include <fsl_rdc.h>

Memory region access violation status.

Public Members

bool hasViolation: Violating happens or not.

uint8_t domainID: Violating Domain ID.

uint64_t address: Violating Address.

RDC_SEMA42: Hardware Semaphores Driver#

FSL_RDC_SEMA42_DRIVER_VERSION: RDC_SEMA42 driver version.

void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base)

Initializes the RDC_SEMA42 module.

This function initializes the RDC_SEMA42 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or RDC_SEMA42_ResetAllGates function.

Parameters:

base – RDC_SEMA42 peripheral base address.

void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base)

De-initializes the RDC_SEMA42 module.

This function de-initializes the RDC_SEMA42 module. It only disables the clock.

Parameters:

base – RDC_SEMA42 peripheral base address.

status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)

Tries to lock the RDC_SEMA42 gate.

This function tries to lock the specific RDC_SEMA42 gate. If the gate has been locked by another processor, this function returns an error code.

Parameters:

base – RDC_SEMA42 peripheral base address.
gateNum – Gate number to lock.
masterIndex – Current processor master index.
domainId – Current processor domain ID.

Return values:

kStatus_Success – Lock the sema42 gate successfully.
kStatus_Failed – Sema42 gate has been locked by another processor.

void RDC_SEMA42_Lock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)

Locks the RDC_SEMA42 gate.

This function locks the specific RDC_SEMA42 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.

Parameters:

base – RDC_SEMA42 peripheral base address.
gateNum – Gate number to lock.
masterIndex – Current processor master index.
domainId – Current processor domain ID.

static inline void RDC_SEMA42_Unlock(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Unlocks the RDC_SEMA42 gate.

This function unlocks the specific RDC_SEMA42 gate. It only writes unlock value to the RDC_SEMA42 gate register. However, it does not check whether the RDC_SEMA42 gate is locked by the current processor or not. As a result, if the RDC_SEMA42 gate is not locked by the current processor, this function has no effect.

Parameters:

base – RDC_SEMA42 peripheral base address.
gateNum – Gate number to unlock.

static inline int32_t RDC_SEMA42_GetLockMasterIndex(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Gets which master has currently locked the gate.

Parameters:

base – RDC_SEMA42 peripheral base address.
gateNum – Gate number.

Returns:

Return -1 if the gate is not locked by any master, otherwise return the master index.

int32_t RDC_SEMA42_GetLockDomainID(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Gets which domain has currently locked the gate.

Parameters:

base – RDC_SEMA42 peripheral base address.
gateNum – Gate number.

Returns:

Return -1 if the gate is not locked by any domain, otherwise return the domain ID.

status_t RDC_SEMA42_ResetGate(RDC_SEMAPHORE_Type *base, uint8_t gateNum)

Resets the RDC_SEMA42 gate to an unlocked status.

This function resets a RDC_SEMA42 gate to an unlocked status.

Parameters:

base – RDC_SEMA42 peripheral base address.
gateNum – Gate number.

Return values:

kStatus_Success – RDC_SEMA42 gate is reset successfully.
kStatus_Failed – Some other reset process is ongoing.

static inline status_t RDC_SEMA42_ResetAllGates(RDC_SEMAPHORE_Type *base)

Resets all RDC_SEMA42 gates to an unlocked status.

This function resets all RDC_SEMA42 gate to an unlocked status.

Parameters:

base – RDC_SEMA42 peripheral base address.

Return values:

kStatus_Success – RDC_SEMA42 is reset successfully.
kStatus_RDC_SEMA42_Reseting – Some other reset process is ongoing.

RDC_SEMA42_GATE_NUM_RESET_ALL: The number to reset all RDC_SEMA42 gates.

RDC_SEMA42_GATEn(base, n): RDC_SEMA42 gate n register address.

RDC_SEMA42_GATE_COUNT: RDC_SEMA42 gate count.

RDC_SEMAPHORE_GATE_GTFSM_MASK

SAI: Serial Audio Interface#

SAI Driver#

void SAI_Init(I2S_Type *base)

Initializes the SAI peripheral.

This API gates the SAI clock. The SAI module can’t operate unless SAI_Init is called to enable the clock.

Parameters:

base – SAI base pointer.

void SAI_Deinit(I2S_Type *base)

De-initializes the SAI peripheral.

This API gates the SAI clock. The SAI module can’t operate unless SAI_TxInit or SAI_RxInit is called to enable the clock.

Parameters:

base – SAI base pointer.

void SAI_TxReset(I2S_Type *base)

Resets the SAI Tx.

This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.

Parameters:

base – SAI base pointer

void SAI_RxReset(I2S_Type *base)

Resets the SAI Rx.

This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.

Parameters:

base – SAI base pointer

void SAI_TxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Tx.

Parameters:

base – SAI base pointer.
enable – True means enable SAI Tx, false means disable.

void SAI_RxEnable(I2S_Type *base, bool enable)

Enables/disables the SAI Rx.

Parameters:

base – SAI base pointer.
enable – True means enable SAI Rx, false means disable.

static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction.

Select bit clock direction, master or slave.

Parameters:

base – SAI base pointer.
masterSlave – reference sai_master_slave_t.

static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx bit clock direction.

Select bit clock direction, master or slave.

Parameters:

base – SAI base pointer.
masterSlave – reference sai_master_slave_t.

static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Rx frame sync direction.

Select frame sync direction, master or slave.

Parameters:

base – SAI base pointer.
masterSlave – reference sai_master_slave_t.

static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)

Set Tx frame sync direction.

Select frame sync direction, master or slave.

Parameters:

base – SAI base pointer.
masterSlave – reference sai_master_slave_t.

void SAI_TxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Transmitter bit clock rate configurations.

Parameters:

base – SAI base pointer.
sourceClockHz – Bit clock source frequency.
sampleRate – Audio data sample rate.
bitWidth – Audio data bitWidth.
channelNumbers – Audio channel numbers.

void SAI_RxSetBitClockRate(I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers)

Receiver bit clock rate configurations.

Parameters:

base – SAI base pointer.
sourceClockHz – Bit clock source frequency.
sampleRate – Audio data sample rate.
bitWidth – Audio data bitWidth.
channelNumbers – Audio channel numbers.

void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Transmitter Bit clock configurations.

Parameters:

base – SAI base pointer.
masterSlave – master or slave.
config – bit clock other configurations, can be NULL in slave mode.

void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config)

Receiver Bit clock configurations.

Parameters:

base – SAI base pointer.
masterSlave – master or slave.
config – bit clock other configurations, can be NULL in slave mode.

void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config)

Master clock configurations.

Parameters:

base – SAI base pointer.
config – master clock configurations.

void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI transmitter fifo configurations.

Parameters:

base – SAI base pointer.
config – fifo configurations.

void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config)

SAI receiver fifo configurations.

Parameters:

base – SAI base pointer.
config – fifo configurations.

void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI transmitter Frame sync configurations.

Parameters:

base – SAI base pointer.
masterSlave – master or slave.
config – frame sync configurations, can be NULL in slave mode.

void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config)

SAI receiver Frame sync configurations.

Parameters:

base – SAI base pointer.
masterSlave – master or slave.
config – frame sync configurations, can be NULL in slave mode.

void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI transmitter Serial data configurations.

Parameters:

base – SAI base pointer.
config – serial data configurations.

void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config)

SAI receiver Serial data configurations.

Parameters:

base – SAI base pointer.
config – serial data configurations.

void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI transmitter configurations.

Parameters:

base – SAI base pointer.
config – transmitter configurations.

void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config)

SAI receiver configurations.

Parameters:

base – SAI base pointer.
config – receiver configurations.

void SAI_GetClassicI2SConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get classic I2S mode configurations.

Parameters:

config – transceiver configurations.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to be enable.

void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get left justified mode configurations.

Parameters:

config – transceiver configurations.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to be enable.

void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get right justified mode configurations.

Parameters:

config – transceiver configurations.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to be enable.

void SAI_GetTDMConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, uint32_t dataWordNum, uint32_t saiChannelMask)

Get TDM mode configurations.

Parameters:

config – transceiver configurations.
frameSyncWidth – length of frame sync.
bitWidth – audio data word width.
dataWordNum – word number in one frame.
saiChannelMask – mask value of the channel to be enable.

void SAI_GetDSPConfig(sai_transceiver_t *config, sai_frame_sync_len_t frameSyncWidth, sai_word_width_t bitWidth, sai_mono_stereo_t mode, uint32_t saiChannelMask)

Get DSP mode configurations.

DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:

SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
SAI_TxSetConfig(base, config)

Note

DSP mode is also called PCM mode which support MODE A and MODE B, DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:

SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
config->frameSync.frameSyncEarly    = true;
SAI_TxSetConfig(base, config)

Parameters:

config – transceiver configurations.
frameSyncWidth – length of frame sync.
bitWidth – audio data bitWidth.
mode – audio data channel.
saiChannelMask – mask value of the channel to enable.

static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state.

Parameters:

base – SAI base pointer

Returns:

SAI Tx status flag value. Use the Status Mask to get the status value needed.

static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Tx status flag state.

Parameters:

base – SAI base pointer
mask – State mask. It can be a combination of the following source if defined:
- kSAI_WordStartFlag
- kSAI_SyncErrorFlag
- kSAI_FIFOErrorFlag

static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)

Gets the SAI Tx status flag state.

Parameters:

base – SAI base pointer

Returns:

SAI Rx status flag value. Use the Status Mask to get the status value needed.

static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)

Clears the SAI Rx status flag state.

Parameters:

base – SAI base pointer
mask – State mask. It can be a combination of the following sources if defined.
- kSAI_WordStartFlag
- kSAI_SyncErrorFlag
- kSAI_FIFOErrorFlag

void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset .

FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like TCR1~TCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

base – SAI base pointer
resetType – Reset type, FIFO reset or software reset

void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)

Do software reset or FIFO reset .

FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software reset will not clear any configuration registers like RCR1~RCR5. This function will also clear all the error flags such as FIFO error, sync error etc.

Parameters:

base – SAI base pointer
resetType – Reset type, FIFO reset or software reset

void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Tx channel FIFO enable mask.

Parameters:

base – SAI base pointer
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.

void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)

Set the Rx channel FIFO enable mask.

Parameters:

base – SAI base pointer
mask – Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, 3 means both channel 0 and channel 1 enabled.

void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Tx data order.

Parameters:

base – SAI base pointer
order – Data order MSB or LSB

void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)

Set the Rx data order.

Parameters:

base – SAI base pointer
order – Data order MSB or LSB

void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order.

Parameters:

base – SAI base pointer
polarity –

void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order.

Parameters:

base – SAI base pointer
polarity –

void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Tx data order.

Parameters:

base – SAI base pointer
polarity –

void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)

Set the Rx data order.

Parameters:

base – SAI base pointer
polarity –

void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Tx FIFO packing feature.

Parameters:

base – SAI base pointer.
pack – FIFO pack type. It is element of sai_fifo_packing_t.

void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)

Set Rx FIFO packing feature.

Parameters:

base – SAI base pointer.
pack – FIFO pack type. It is element of sai_fifo_packing_t.

static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Tx FIFO error continue.

FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in TCSR register.

Parameters:

base – SAI base pointer.
isEnabled – Is FIFO error continue enabled, true means enable, false means disable.

static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)

Set Rx FIFO error continue.

FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature not enabled, SAI will hang and users need to clear FEF flag in RCSR register.

Parameters:

base – SAI base pointer.
isEnabled – Is FIFO error continue enabled, true means enable, false means disable.

static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Tx interrupt requests.

Parameters:

base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
- kSAI_WordStartInterruptEnable
- kSAI_SyncErrorInterruptEnable
- kSAI_FIFOWarningInterruptEnable
- kSAI_FIFORequestInterruptEnable
- kSAI_FIFOErrorInterruptEnable

static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)

Enables the SAI Rx interrupt requests.

Parameters:

base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
- kSAI_WordStartInterruptEnable
- kSAI_SyncErrorInterruptEnable
- kSAI_FIFOWarningInterruptEnable
- kSAI_FIFORequestInterruptEnable
- kSAI_FIFOErrorInterruptEnable

static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Tx interrupt requests.

Parameters:

base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
- kSAI_WordStartInterruptEnable
- kSAI_SyncErrorInterruptEnable
- kSAI_FIFOWarningInterruptEnable
- kSAI_FIFORequestInterruptEnable
- kSAI_FIFOErrorInterruptEnable

static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)

Disables the SAI Rx interrupt requests.

Parameters:

base – SAI base pointer
mask – interrupt source The parameter can be a combination of the following sources if defined.
- kSAI_WordStartInterruptEnable
- kSAI_SyncErrorInterruptEnable
- kSAI_FIFOWarningInterruptEnable
- kSAI_FIFORequestInterruptEnable
- kSAI_FIFOErrorInterruptEnable

static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Tx DMA requests.

Parameters:

base – SAI base pointer
mask – DMA source The parameter can be combination of the following sources if defined.
- kSAI_FIFOWarningDMAEnable
- kSAI_FIFORequestDMAEnable
enable – True means enable DMA, false means disable DMA.

static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)

Enables/disables the SAI Rx DMA requests.

Parameters:

base – SAI base pointer
mask – DMA source The parameter can be a combination of the following sources if defined.
- kSAI_FIFOWarningDMAEnable
- kSAI_FIFORequestDMAEnable
enable – True means enable DMA, false means disable DMA.

static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Tx data register address.

This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

base – SAI base pointer.
channel – Which data channel used.

Returns:

data register address.

static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)

Gets the SAI Rx data register address.

This API is used to provide a transfer address for the SAI DMA transfer configuration.

Parameters:

base – SAI base pointer.
channel – Which data channel used.

Returns:

data register address.

void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

base – SAI base pointer.
channel – Data channel used.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be written.
size – Bytes to be written.

void SAI_WriteMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Sends data to multi channel using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

base – SAI base pointer.
channel – Data channel used.
channelMask – channel mask.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be written.
size – Bytes to be written.

static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)

Writes data into SAI FIFO.

Parameters:

base – SAI base pointer.
channel – Data channel used.
data – Data needs to be written.

void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

base – SAI base pointer.
channel – Data channel used.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be read.
size – Bytes to be read.

void SAI_ReadMultiChannelBlocking(I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size)

Receives multi channel data using a blocking method.

Note

This function blocks by polling until data is ready to be sent.

Parameters:

base – SAI base pointer.
channel – Data channel used.
channelMask – channel mask.
bitWidth – How many bits in an audio word; usually 8/16/24/32 bits.
buffer – Pointer to the data to be read.
size – Bytes to be read.

static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)

Reads data from the SAI FIFO.

Parameters:

base – SAI base pointer.
channel – Data channel used.

Returns:

Data in SAI FIFO.

void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Tx handle.

This function initializes the Tx handle for the SAI Tx transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – SAI base pointer
handle – SAI handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function

void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)

Initializes the SAI Rx handle.

This function initializes the Rx handle for the SAI Rx transactional APIs. Call this function once to get the handle initialized.

Parameters:

base – SAI base pointer.
handle – SAI handle pointer.
callback – Pointer to the user callback function.
userData – User parameter passed to the callback function.

void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI transmitter transfer configurations.

This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

base – SAI base pointer.
handle – SAI handle pointer.
config – tranmitter configurations.

void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config)

SAI receiver transfer configurations.

This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo configurations.

Parameters:

base – SAI base pointer.
handle – SAI handle pointer.
config – receiver configurations.

status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking send transfer on SAI.

Note

This API returns immediately after the transfer initiates. Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.

Parameters:

base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
xfer – Pointer to the sai_transfer_t structure.

Return values:

kStatus_Success – Successfully started the data receive.
kStatus_SAI_TxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.

status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)

Performs an interrupt non-blocking receive transfer on SAI.

Note

This API returns immediately after the transfer initiates. Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer is finished.

Parameters:

base – SAI base pointer
handle – Pointer to the sai_handle_t structure which stores the transfer state.
xfer – Pointer to the sai_transfer_t structure.

Return values:

kStatus_Success – Successfully started the data receive.
kStatus_SAI_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.

status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a set byte count.

Parameters:

base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
count – Bytes count sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)

Gets a received byte count.

Parameters:

base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.
count – Bytes count received.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)

Aborts the current send.

Note

This API can be called any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – SAI base pointer.
handle – Pointer to the sai_handle_t structure which stores the transfer state.

void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)

Aborts the current IRQ receive.

Note

This API can be called when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – SAI base pointer
handle – Pointer to the sai_handle_t structure which stores the transfer state.

void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI send.

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortSend.

Parameters:

base – SAI base pointer.
handle – SAI eDMA handle pointer.

void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle)

Terminate all SAI receive.

This function will clear all transfer slots buffered in the sai queue. If users only want to abort the current transfer slot, please call SAI_TransferAbortReceive.

Parameters:

base – SAI base pointer.
handle – SAI eDMA handle pointer.

void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler.

Parameters:

base – SAI base pointer.
handle – Pointer to the sai_handle_t structure.

void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)

Tx interrupt handler.

Parameters:

base – SAI base pointer.
handle – Pointer to the sai_handle_t structure.

void SAI_DriverIRQHandler(uint32_t instance)

SAI driver IRQ handler common entry.

This function provides the common IRQ request entry for SAI.

Parameters:

instance – SAI instance.

FSL_SAI_DRIVER_VERSION: Version 2.4.11

_sai_status_t, SAI return status.

Values:

enumerator kStatus_SAI_TxBusy: SAI Tx is busy.

enumerator kStatus_SAI_RxBusy: SAI Rx is busy.

enumerator kStatus_SAI_TxError: SAI Tx FIFO error.

enumerator kStatus_SAI_RxError: SAI Rx FIFO error.

enumerator kStatus_SAI_QueueFull: SAI transfer queue is full.

enumerator kStatus_SAI_TxIdle: SAI Tx is idle

enumerator kStatus_SAI_RxIdle: SAI Rx is idle

_sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific

Values:

enumerator kSAI_Channel0Mask: channel 0 mask value

enumerator kSAI_Channel1Mask: channel 1 mask value

enumerator kSAI_Channel2Mask: channel 2 mask value

enumerator kSAI_Channel3Mask: channel 3 mask value

enumerator kSAI_Channel4Mask: channel 4 mask value

enumerator kSAI_Channel5Mask: channel 5 mask value

enumerator kSAI_Channel6Mask: channel 6 mask value

enumerator kSAI_Channel7Mask: channel 7 mask value

enum _sai_protocol

Define the SAI bus type.

Values:

enumerator kSAI_BusLeftJustified: Uses left justified format.

enumerator kSAI_BusRightJustified: Uses right justified format.

enumerator kSAI_BusI2S: Uses I2S format.

enumerator kSAI_BusPCMA: Uses I2S PCM A format.

enumerator kSAI_BusPCMB: Uses I2S PCM B format.

enum _sai_master_slave

Master or slave mode.

Values:

enumerator kSAI_Master: Master mode include bclk and frame sync

enumerator kSAI_Slave: Slave mode include bclk and frame sync

enumerator kSAI_Bclk_Master_FrameSync_Slave: bclk in master mode, frame sync in slave mode

enumerator kSAI_Bclk_Slave_FrameSync_Master: bclk in slave mode, frame sync in master mode

enum _sai_mono_stereo

Mono or stereo audio format.

Values:

enumerator kSAI_Stereo: Stereo sound.

enumerator kSAI_MonoRight: Only Right channel have sound.

enumerator kSAI_MonoLeft: Only left channel have sound.

enum _sai_data_order

SAI data order, MSB or LSB.

Values:

enumerator kSAI_DataLSB: LSB bit transferred first

enumerator kSAI_DataMSB: MSB bit transferred first

enum _sai_clock_polarity

SAI clock polarity, active high or low.

Values:

enumerator kSAI_PolarityActiveHigh: Drive outputs on rising edge

enumerator kSAI_PolarityActiveLow: Drive outputs on falling edge

enumerator kSAI_SampleOnFallingEdge: Sample inputs on falling edge

enumerator kSAI_SampleOnRisingEdge: Sample inputs on rising edge

enum _sai_sync_mode

Synchronous or asynchronous mode.

Values:

enumerator kSAI_ModeAsync: Asynchronous mode

enumerator kSAI_ModeSync: Synchronous mode (with receiver or transmit)

enumerator kSAI_ModeSyncWithOtherTx: Synchronous with another SAI transmit

enumerator kSAI_ModeSyncWithOtherRx: Synchronous with another SAI receiver

enum _sai_bclk_source

Bit clock source.

Values:

enumerator kSAI_BclkSourceBusclk: Bit clock using bus clock

enumerator kSAI_BclkSourceMclkOption1: Bit clock MCLK option 1

enumerator kSAI_BclkSourceMclkOption2: Bit clock MCLK option2

enumerator kSAI_BclkSourceMclkOption3: Bit clock MCLK option3

enumerator kSAI_BclkSourceMclkDiv: Bit clock using master clock divider

enumerator kSAI_BclkSourceOtherSai0: Bit clock from other SAI device

enumerator kSAI_BclkSourceOtherSai1: Bit clock from other SAI device

_sai_interrupt_enable_t, The SAI interrupt enable flag

Values:

enumerator kSAI_WordStartInterruptEnable: Word start flag, means the first word in a frame detected

enumerator kSAI_SyncErrorInterruptEnable: Sync error flag, means the sync error is detected

enumerator kSAI_FIFOWarningInterruptEnable: FIFO warning flag, means the FIFO is empty

enumerator kSAI_FIFOErrorInterruptEnable: FIFO error flag

enumerator kSAI_FIFORequestInterruptEnable: FIFO request, means reached watermark

_sai_dma_enable_t, The DMA request sources

Values:

enumerator kSAI_FIFOWarningDMAEnable: FIFO warning caused by the DMA request

enumerator kSAI_FIFORequestDMAEnable: FIFO request caused by the DMA request

_sai_flags, The SAI status flag

Values:

enumerator kSAI_WordStartFlag: Word start flag, means the first word in a frame detected

enumerator kSAI_SyncErrorFlag: Sync error flag, means the sync error is detected

enumerator kSAI_FIFOErrorFlag: FIFO error flag

enumerator kSAI_FIFORequestFlag: FIFO request flag.

enumerator kSAI_FIFOWarningFlag: FIFO warning flag

enum _sai_reset_type

The reset type.

Values:

enumerator kSAI_ResetTypeSoftware: Software reset, reset the logic state

enumerator kSAI_ResetTypeFIFO: FIFO reset, reset the FIFO read and write pointer

enumerator kSAI_ResetAll: All reset.

enum _sai_fifo_packing

The SAI packing mode The mode includes 8 bit and 16 bit packing.

Values:

enumerator kSAI_FifoPackingDisabled: Packing disabled

enumerator kSAI_FifoPacking8bit: 8 bit packing enabled

enumerator kSAI_FifoPacking16bit: 16bit packing enabled

enum _sai_sample_rate

Audio sample rate.

Values:

enumerator kSAI_SampleRate8KHz: Sample rate 8000 Hz

enumerator kSAI_SampleRate11025Hz: Sample rate 11025 Hz

enumerator kSAI_SampleRate12KHz: Sample rate 12000 Hz

enumerator kSAI_SampleRate16KHz: Sample rate 16000 Hz

enumerator kSAI_SampleRate22050Hz: Sample rate 22050 Hz

enumerator kSAI_SampleRate24KHz: Sample rate 24000 Hz

enumerator kSAI_SampleRate32KHz: Sample rate 32000 Hz

enumerator kSAI_SampleRate44100Hz: Sample rate 44100 Hz

enumerator kSAI_SampleRate48KHz: Sample rate 48000 Hz

enumerator kSAI_SampleRate96KHz: Sample rate 96000 Hz

enumerator kSAI_SampleRate192KHz: Sample rate 192000 Hz

enumerator kSAI_SampleRate384KHz: Sample rate 384000 Hz

enum _sai_word_width

Audio word width.

Values:

enumerator kSAI_WordWidth8bits: Audio data width 8 bits

enumerator kSAI_WordWidth16bits: Audio data width 16 bits

enumerator kSAI_WordWidth24bits: Audio data width 24 bits

enumerator kSAI_WordWidth32bits: Audio data width 32 bits

enum _sai_data_pin_state

sai data pin state definition

Values:

enumerator kSAI_DataPinStateTriState: transmit data pins are tri-stated when slots are masked or channels are disabled

enumerator kSAI_DataPinStateOutputZero: transmit data pins are never tri-stated and will output zero when slots are masked or channel disabled

enum _sai_fifo_combine

sai fifo combine mode definition

Values:

enumerator kSAI_FifoCombineDisabled: sai TX/RX fifo combine mode disabled

enumerator kSAI_FifoCombineModeEnabledOnRead: sai TX fifo combine mode enabled on FIFO reads

enumerator kSAI_FifoCombineModeEnabledOnWrite: sai TX fifo combine mode enabled on FIFO write

enumerator kSAI_RxFifoCombineModeEnabledOnWrite: sai RX fifo combine mode enabled on FIFO write

enumerator kSAI_RXFifoCombineModeEnabledOnRead: sai RX fifo combine mode enabled on FIFO reads

enumerator kSAI_FifoCombineModeEnabledOnReadWrite: sai TX/RX fifo combined mode enabled on FIFO read/writes

enum _sai_transceiver_type

sai transceiver type

Values:

enumerator kSAI_Transmitter: sai transmitter

enumerator kSAI_Receiver: sai receiver

enum _sai_frame_sync_len

sai frame sync len

Values:

enumerator kSAI_FrameSyncLenOneBitClk: 1 bit clock frame sync len for DSP mode

enumerator kSAI_FrameSyncLenPerWordWidth: Frame sync length decided by word width

typedef enum _sai_protocol sai_protocol_t: Define the SAI bus type.

typedef enum _sai_master_slave sai_master_slave_t: Master or slave mode.

typedef enum _sai_mono_stereo sai_mono_stereo_t: Mono or stereo audio format.

typedef enum _sai_data_order sai_data_order_t: SAI data order, MSB or LSB.

typedef enum _sai_clock_polarity sai_clock_polarity_t: SAI clock polarity, active high or low.

typedef enum _sai_sync_mode sai_sync_mode_t: Synchronous or asynchronous mode.

typedef enum _sai_bclk_source sai_bclk_source_t: Bit clock source.

typedef enum _sai_reset_type sai_reset_type_t: The reset type.

typedef enum _sai_fifo_packing sai_fifo_packing_t: The SAI packing mode The mode includes 8 bit and 16 bit packing.

typedef struct _sai_config sai_config_t: SAI user configuration structure.

typedef enum _sai_sample_rate sai_sample_rate_t: Audio sample rate.

typedef enum _sai_word_width sai_word_width_t: Audio word width.

typedef enum _sai_data_pin_state sai_data_pin_state_t: sai data pin state definition

typedef enum _sai_fifo_combine sai_fifo_combine_t: sai fifo combine mode definition

typedef enum _sai_transceiver_type sai_transceiver_type_t: sai transceiver type

typedef enum _sai_frame_sync_len sai_frame_sync_len_t: sai frame sync len

typedef struct _sai_transfer_format sai_transfer_format_t: sai transfer format

typedef struct _sai_master_clock sai_master_clock_t: master clock configurations

typedef struct _sai_fifo sai_fifo_t: sai fifo configurations

typedef struct _sai_bit_clock sai_bit_clock_t: sai bit clock configurations

typedef struct _sai_frame_sync sai_frame_sync_t: sai frame sync configurations

typedef struct _sai_serial_data sai_serial_data_t: sai serial data configurations

typedef struct _sai_transceiver sai_transceiver_t: sai transceiver configurations

typedef struct _sai_transfer sai_transfer_t: SAI transfer structure.

typedef struct _sai_handle sai_handle_t

typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData): SAI transfer callback prototype.

MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK

Used to control whether SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() allows a NULL FIFO watermark.

If this macro is set to 0 then SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig() will set the watermark to half of the FIFO’s depth if passed a NULL watermark.

MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG

Disable implicit channel data configuration within SAI_TxSetConfig()/SAI_RxSetConfig().

Use this macro to control whether SAI_RxSetConfig()/SAI_TxSetConfig() will attempt to implicitly configure the channel data. By channel data we mean the startChannel, channelMask, endChannel, and channelNums fields from the sai_transciever_t structure. By default, SAI_TxSetConfig()/SAI_RxSetConfig() will attempt to compute these fields, which may not be desired in cases where the user wants to set them before the call to said functions.

SAI_XFER_QUEUE_SIZE: SAI transfer queue size, user can refine it according to use case.

FSL_SAI_HAS_FIFO_EXTEND_FEATURE: sai fifo feature

struct _sai_config

#include <fsl_sai.h>

SAI user configuration structure.

Public Members

sai_protocol_t protocol: Audio bus protocol in SAI

sai_sync_mode_t syncMode: SAI sync mode, control Tx/Rx clock sync

bool mclkOutputEnable: Master clock output enable, true means master clock divider enabled

sai_bclk_source_t bclkSource: Bit Clock source

sai_master_slave_t masterSlave: Master or slave

struct _sai_transfer_format

#include <fsl_sai.h>

sai transfer format

Public Members

uint32_t sampleRate_Hz: Sample rate of audio data

uint32_t bitWidth: Data length of audio data, usually 8/16/24/32 bits

sai_mono_stereo_t stereo: Mono or stereo

uint32_t masterClockHz: Master clock frequency in Hz

uint8_t watermark: Watermark value

uint8_t channel: Transfer start channel

uint8_t channelMask: enabled channel mask value, reference _sai_channel_mask

uint8_t endChannel: end channel number

uint8_t channelNums: Total enabled channel numbers

sai_protocol_t protocol: Which audio protocol used

bool isFrameSyncCompact: True means Frame sync length is configurable according to bitWidth, false means frame sync length is 64 times of bit clock.

struct _sai_master_clock

#include <fsl_sai.h>

master clock configurations

Public Members

bool mclkOutputEnable: master clock output enable

uint32_t mclkHz: target mclk frequency

uint32_t mclkSourceClkHz: mclk source frequency

struct _sai_fifo

#include <fsl_sai.h>

sai fifo configurations

Public Members

bool fifoContinueOneError: fifo continues when error occur

sai_fifo_combine_t fifoCombine: fifo combine mode

sai_fifo_packing_t fifoPacking: fifo packing mode

uint8_t fifoWatermark: fifo watermark

struct _sai_bit_clock

#include <fsl_sai.h>

sai bit clock configurations

Public Members

bool bclkSrcSwap: bit clock source swap

bool bclkInputDelay: bit clock actually used by the transmitter is delayed by the pad output delay, this has effect of decreasing the data input setup time, but increasing the data output valid time .

sai_clock_polarity_t bclkPolarity: bit clock polarity

sai_bclk_source_t bclkSource: bit Clock source

struct _sai_frame_sync

#include <fsl_sai.h>

sai frame sync configurations

Public Members

uint8_t frameSyncWidth: frame sync width in number of bit clocks

bool frameSyncEarly: TRUE is frame sync assert one bit before the first bit of frame FALSE is frame sync assert with the first bit of the frame

bool frameSyncGenerateOnDemand: internal frame sync is generated when FIFO waring flag is clear

sai_clock_polarity_t frameSyncPolarity: frame sync polarity

struct _sai_serial_data

#include <fsl_sai.h>

sai serial data configurations

Public Members

sai_data_pin_state_t dataMode: sai data pin state when slots masked or channel disabled

sai_data_order_t dataOrder: configure whether the LSB or MSB is transmitted first

uint8_t dataWord0Length: configure the number of bits in the first word in each frame

uint8_t dataWordNLength: configure the number of bits in the each word in each frame, except the first word

uint8_t dataWordLength: used to record the data length for dma transfer

uint8_t dataFirstBitShifted: Configure the bit index for the first bit transmitted for each word in the frame

uint8_t dataWordNum: configure the number of words in each frame

uint32_t dataMaskedWord: configure whether the transmit word is masked

struct _sai_transceiver

#include <fsl_sai.h>

sai transceiver configurations

Public Members

sai_serial_data_t serialData: serial data configurations

sai_frame_sync_t frameSync: ws configurations

sai_bit_clock_t bitClock: bit clock configurations

sai_fifo_t fifo: fifo configurations

sai_master_slave_t masterSlave: transceiver is master or slave

sai_sync_mode_t syncMode: transceiver sync mode

uint8_t startChannel: Transfer start channel

uint8_t channelMask: enabled channel mask value, reference _sai_channel_mask

uint8_t endChannel: end channel number

uint8_t channelNums: Total enabled channel numbers

struct _sai_transfer

#include <fsl_sai.h>

SAI transfer structure.

Public Members

uint8_t *data: Data start address to transfer.

size_t dataSize: Transfer size.

struct _sai_handle

#include <fsl_sai.h>

SAI handle structure.

Public Members

I2S_Type *base: base address

uint32_t state: Transfer status

sai_transfer_callback_t callback: Callback function called at transfer event

void *userData: Callback parameter passed to callback function

uint8_t bitWidth: Bit width for transfer, 8/16/24/32 bits

uint8_t channel: Transfer start channel

uint8_t channelMask: enabled channel mask value, refernece _sai_channel_mask

uint8_t endChannel: end channel number

uint8_t channelNums: Total enabled channel numbers

sai_transfer_t saiQueue[(4U)]: Transfer queue storing queued transfer

size_t transferSize[(4U)]: Data bytes need to transfer

volatile uint8_t queueUser: Index for user to queue transfer

volatile uint8_t queueDriver: Index for driver to get the transfer data and size

uint8_t watermark: Watermark value

SEMA4: Hardware Semaphores Driver#

FSL_SEMA4_DRIVER_VERSION: SEMA4 driver version.

void SEMA4_Init(SEMA4_Type *base)

Initializes the SEMA4 module.

This function initializes the SEMA4 module. It only enables the clock but does not reset the gates because the module might be used by other processors at the same time. To reset the gates, call either SEMA4_ResetGate or SEMA4_ResetAllGates function.

Parameters:

base – SEMA4 peripheral base address.

void SEMA4_Deinit(SEMA4_Type *base)

De-initializes the SEMA4 module.

This function de-initializes the SEMA4 module. It only disables the clock.

Parameters:

base – SEMA4 peripheral base address.

status_t SEMA4_TryLock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum)

Tries to lock the SEMA4 gate.

This function tries to lock the specific SEMA4 gate. If the gate has been locked by another processor, this function returns an error code.

Parameters:

base – SEMA4 peripheral base address.
gateNum – Gate number to lock.
procNum – Current processor number.

Return values:

kStatus_Success – Lock the sema4 gate successfully.
kStatus_Fail – Sema4 gate has been locked by another processor.

status_t SEMA4_Lock(SEMA4_Type *base, uint8_t gateNum, uint8_t procNum)

Locks the SEMA4 gate.

This function locks the specific SEMA4 gate. If the gate has been locked by other processors, this function waits until it is unlocked and then lock it.

If SEMA4_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

Parameters:

base – SEMA4 peripheral base address.
gateNum – Gate number to lock.
procNum – Current processor number.

Return values:

kStatus_Success – The gate was successfully locked.
kStatus_Timeout – Timeout occurred while waiting for the gate to be unlocked.

Returns:

status_t

static inline void SEMA4_Unlock(SEMA4_Type *base, uint8_t gateNum)

Unlocks the SEMA4 gate.

This function unlocks the specific SEMA4 gate. It only writes unlock value to the SEMA4 gate register. However, it does not check whether the SEMA4 gate is locked by the current processor or not. As a result, if the SEMA4 gate is not locked by the current processor, this function has no effect.

Parameters:

base – SEMA4 peripheral base address.
gateNum – Gate number to unlock.

static inline int32_t SEMA4_GetLockProc(SEMA4_Type *base, uint8_t gateNum)

Gets the status of the SEMA4 gate.

This function checks the lock status of a specific SEMA4 gate.

Parameters:

base – SEMA4 peripheral base address.
gateNum – Gate number.

Returns:

Return -1 if the gate is unlocked, otherwise return the processor number which has locked the gate.

status_t SEMA4_ResetGate(SEMA4_Type *base, uint8_t gateNum)

Resets the SEMA4 gate to an unlocked status.

This function resets a SEMA4 gate to an unlocked status.

Parameters:

base – SEMA4 peripheral base address.
gateNum – Gate number.

Return values:

kStatus_Success – SEMA4 gate is reset successfully.
kStatus_Fail – Some other reset process is ongoing.

static inline status_t SEMA4_ResetAllGates(SEMA4_Type *base)

Resets all SEMA4 gates to an unlocked status.

This function resets all SEMA4 gate to an unlocked status.

Parameters:

base – SEMA4 peripheral base address.

Return values:

kStatus_Success – SEMA4 is reset successfully.
kStatus_Fail – Some other reset process is ongoing.

static inline void SEMA4_EnableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint16_t mask)

Enable the gate notification interrupt.

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle.

Parameters:

base – SEMA4 peripheral base address.
procNum – Current processor number.
mask – OR’ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1.

static inline void SEMA4_DisableGateNotifyInterrupt(SEMA4_Type *base, uint8_t procNum, uint16_t mask)

Disable the gate notification interrupt.

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle.

Parameters:

base – SEMA4 peripheral base address.
procNum – Current processor number.
mask – OR’ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1.

static inline uint32_t SEMA4_GetGateNotifyStatus(SEMA4_Type *base, uint8_t procNum)

Get the gate notification flags.

Gate notification provides such feature, when core tried to lock the gate and failed, it could get notification when the gate is idle. The status flags are cleared automatically when the gate is locked by current core or locked again before the other core.

Parameters:

base – SEMA4 peripheral base address.
procNum – Current processor number.

Returns:

OR’ed value of the gate index, for example: (1<<0) | (1<<1) means gate 0 and gate 1 flags are pending.

status_t SEMA4_ResetGateNotify(SEMA4_Type *base, uint8_t gateNum)

Resets the SEMA4 gate IRQ notification.

This function resets a SEMA4 gate IRQ notification.

Parameters:

base – SEMA4 peripheral base address.
gateNum – Gate number.

Return values:

kStatus_Success – Reset successfully.
kStatus_Fail – Some other reset process is ongoing.

static inline status_t SEMA4_ResetAllGateNotify(SEMA4_Type *base)

Resets all SEMA4 gates IRQ notification.

This function resets all SEMA4 gate IRQ notifications.

Parameters:

base – SEMA4 peripheral base address.

Return values:

kStatus_Success – Reset successfully.
kStatus_Fail – Some other reset process is ongoing.

SEMA4_GATE_NUM_RESET_ALL: The number to reset all SEMA4 gates.

SEMA4_GATEn(base, n): SEMA4 gate n register address.

SEMA4_BUSY_POLL_COUNT

Maximum polling iterations for SEMA4 waiting loops.

This parameter defines the maximum number of iterations for any polling loop in the SEMA4 driver code before timing out and returning an error.

It applies to all waiting loops in SEMA4 driver, such as waiting for a gate to be unlocked, waiting for a reset to complete, or waiting for a resource to become available.

This is a count of loop iterations, not a time-based value.

If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if hardware doesn’t respond or if a resource is never released.

SNVS: Secure Non-Volatile Storage#

Secure Non-Volatile Storage High-Power#

void SNVS_HP_Init(SNVS_Type *base)

Initialize the SNVS.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

base – SNVS peripheral base address

void SNVS_HP_Deinit(SNVS_Type *base)

Deinitialize the SNVS.

Parameters:

base – SNVS peripheral base address

void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config)

Ungates the SNVS clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

base – SNVS peripheral base address
config – Pointer to the user’s SNVS configuration structure.

void SNVS_HP_RTC_Deinit(SNVS_Type *base)

Stops the RTC and SRTC timers.

Parameters:

base – SNVS peripheral base address

void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config)

Fills in the SNVS config struct with the default settings.

The default values are as follows.

config->rtccalenable = false;
config->rtccalvalue = 0U;
config->PIFreq = 0U;

Parameters:

config – Pointer to the user’s SNVS configuration structure.

status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime)

Sets the SNVS RTC date and time according to the given time structure.

Parameters:

base – SNVS peripheral base address
datetime – Pointer to the structure where the date and time details are stored.

Returns:

kStatus_Success: Success in setting the time and starting the SNVS RTC kStatus_InvalidArgument: Error because the datetime format is incorrect

void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)

Gets the SNVS RTC time and stores it in the given time structure.

Parameters:

base – SNVS peripheral base address
datetime – Pointer to the structure where the date and time details are stored.

status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime)

Sets the SNVS RTC alarm time.

The function sets the RTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error.

Parameters:

base – SNVS peripheral base address
alarmTime – Pointer to the structure where the alarm time is stored.

Returns:

kStatus_Success: success in setting the SNVS RTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed

void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime)

Returns the SNVS RTC alarm time.

Parameters:

base – SNVS peripheral base address
datetime – Pointer to the structure where the alarm date and time details are stored.

void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base)

The function synchronizes RTC counter value with SRTC.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask)

Enables the selected SNVS interrupts.

Parameters:

base – SNVS peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration :: _snvs_hp_interrupts_t

static inline void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask)

Disables the selected SNVS interrupts.

Parameters:

base – SNVS peripheral base address
mask – The interrupts to disable. This is a logical OR of members of the enumeration :: _snvs_hp_interrupts_t

uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base)

Gets the enabled SNVS interrupts.

Parameters:

base – SNVS peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration :: _snvs_hp_interrupts_t

uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base)

Gets the SNVS status flags.

Parameters:

base – SNVS peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration :: _snvs_hp_status_flags_t

static inline void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask)

Clears the SNVS status flags.

Parameters:

base – SNVS peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration :: _snvs_hp_status_flags_t

static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base)

Starts the SNVS RTC time counter.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base)

Stops the SNVS RTC time counter.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_EnableHighAssuranceCounter(SNVS_Type *base, bool enable)

Enable or disable the High Assurance Counter (HAC)

Parameters:

base – SNVS peripheral base address
enable – Pass true to enable, false to disable.

static inline void SNVS_HP_StartHighAssuranceCounter(SNVS_Type *base, bool start)

Start or stop the High Assurance Counter (HAC)

Parameters:

base – SNVS peripheral base address
start – Pass true to start, false to stop.

static inline void SNVS_HP_SetHighAssuranceCounterInitialValue(SNVS_Type *base, uint32_t value)

Set the High Assurance Counter (HAC) initialize value.

Parameters:

base – SNVS peripheral base address
value – The initial value to set.

static inline void SNVS_HP_LoadHighAssuranceCounter(SNVS_Type *base)

Load the High Assurance Counter (HAC)

This function loads the HAC initialize value to counter register.

Parameters:

base – SNVS peripheral base address

static inline uint32_t SNVS_HP_GetHighAssuranceCounter(SNVS_Type *base)

Get the current High Assurance Counter (HAC) value.

Parameters:

base – SNVS peripheral base address

Returns:

HAC currnet value.

static inline void SNVS_HP_ClearHighAssuranceCounter(SNVS_Type *base)

Clear the High Assurance Counter (HAC)

This function can be called in a functional or soft fail state. When the HAC is enabled:

If the HAC is cleared in the soft fail state, the SSM transitions to the hard fail state immediately;
If the HAC is cleared in functional state, the SSM will transition to hard fail immediately after transitioning to soft fail.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_LockHighAssuranceCounter(SNVS_Type *base)

Lock the High Assurance Counter (HAC)

Once locked, the HAC initialize value could not be changed, the HAC enable status could not be changed. This could only be unlocked by system reset.

Parameters:

base – SNVS peripheral base address

FSL_SNVS_HP_DRIVER_VERSION: Version 2.3.2

enum _snvs_hp_interrupts

List of SNVS interrupts.

Values:

enumerator kSNVS_RTC_AlarmInterrupt: RTC time alarm

enumerator kSNVS_RTC_PeriodicInterrupt: RTC periodic interrupt

enum _snvs_hp_status_flags

List of SNVS flags.

Values:

enumerator kSNVS_RTC_AlarmInterruptFlag: RTC time alarm flag

enumerator kSNVS_RTC_PeriodicInterruptFlag: RTC periodic interrupt flag

enumerator kSNVS_ZMK_ZeroFlag: The ZMK is zero

enumerator kSNVS_OTPMK_ZeroFlag: The OTPMK is zero

enum _snvs_hp_sv_status_flags

List of SNVS security violation flags.

Values:

enumerator kSNVS_LP_ViolationFlag: Low Power section Security Violation

enumerator kSNVS_ZMK_EccFailFlag: Zeroizable Master Key Error Correcting Code Check Failure

enumerator kSNVS_LP_SoftwareViolationFlag: LP Software Security Violation

enumerator kSNVS_FatalSoftwareViolationFlag: Software Fatal Security Violation

enumerator kSNVS_SoftwareViolationFlag: Software Security Violation

enumerator kSNVS_Violation0Flag: Security Violation 0

enumerator kSNVS_Violation1Flag: Security Violation 1

enumerator kSNVS_Violation2Flag: Security Violation 2

enumerator kSNVS_Violation4Flag: Security Violation 4

enumerator kSNVS_Violation5Flag: Security Violation 5

enum _snvs_hp_ssm_state

List of SNVS Security State Machine State.

Values:

enumerator kSNVS_SSMInit: Init

enumerator kSNVS_SSMHardFail: Hard Fail

enumerator kSNVS_SSMSoftFail: Soft Fail

enumerator kSNVS_SSMInitInter: Init Intermediate (transition state between Init and Check)

enumerator kSNVS_SSMCheck: Check

enumerator kSNVS_SSMNonSecure: Non-Secure

enumerator kSNVS_SSMTrusted: Trusted

enumerator kSNVS_SSMSecure: Secure

typedef enum _snvs_hp_interrupts snvs_hp_interrupts_t: List of SNVS interrupts.

typedef enum _snvs_hp_status_flags snvs_hp_status_flags_t: List of SNVS flags.

typedef enum _snvs_hp_sv_status_flags snvs_hp_sv_status_flags_t: List of SNVS security violation flags.

typedef struct _snvs_hp_rtc_datetime snvs_hp_rtc_datetime_t: Structure is used to hold the date and time.

typedef struct _snvs_hp_rtc_config snvs_hp_rtc_config_t

SNVS config structure.

This structure holds the configuration settings for the SNVS peripheral. To initialize this structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

typedef enum _snvs_hp_ssm_state snvs_hp_ssm_state_t: List of SNVS Security State Machine State.

static inline void SNVS_HP_EnableMasterKeySelection(SNVS_Type *base, bool enable)

Enable or disable master key selection.

Parameters:

base – SNVS peripheral base address
enable – Pass true to enable, false to disable.

static inline void SNVS_HP_ProgramZeroizableMasterKey(SNVS_Type *base)

Trigger to program Zeroizable Master Key.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_ChangeSSMState(SNVS_Type *base)

Trigger SSM State Transition.

Trigger state transition of the system security monitor (SSM). It results only the following transitions of the SSM:

Check State -> Non-Secure (when Non-Secure Boot and not in Fab Configuration)
Check State –> Trusted (when Secure Boot or in Fab Configuration )
Trusted State –> Secure
Secure State –> Trusted
Soft Fail –> Non-Secure

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_SetSoftwareFatalSecurityViolation(SNVS_Type *base)

Trigger Software Fatal Security Violation.

The result SSM state transition is:

Check State -> Soft Fail
Non-Secure State -> Soft Fail
Trusted State -> Soft Fail
Secure State -> Soft Fail

Parameters:

base – SNVS peripheral base address

static inline void SNVS_HP_SetSoftwareSecurityViolation(SNVS_Type *base)

Trigger Software Security Violation.

The result SSM state transition is:

Check -> Non-Secure
Trusted -> Soft Fail
Secure -> Soft Fail

Parameters:

base – SNVS peripheral base address

static inline snvs_hp_ssm_state_t SNVS_HP_GetSSMState(SNVS_Type *base)

Get current SSM State.

Parameters:

base – SNVS peripheral base address

Returns:

Current SSM state

static inline void SNVS_HP_ResetLP(SNVS_Type *base)

Reset the SNVS LP section.

Reset the LP section except SRTC and Time alarm.

Parameters:

base – SNVS peripheral base address

static inline uint32_t SNVS_HP_GetStatusFlags(SNVS_Type *base)

Get the SNVS HP status flags.

The flags are returned as the OR’ed value f the enumeration :: _snvs_hp_status_flags_t.

Parameters:

base – SNVS peripheral base address

Returns:

The OR’ed value of status flags.

static inline void SNVS_HP_ClearStatusFlags(SNVS_Type *base, uint32_t mask)

Clear the SNVS HP status flags.

The flags to clear are passed in as the OR’ed value of the enumeration :: _snvs_hp_status_flags_t. Only these flags could be cleared using this API.

kSNVS_RTC_PeriodicInterruptFlag
kSNVS_RTC_AlarmInterruptFlag

Parameters:

base – SNVS peripheral base address
mask – OR’ed value of the flags to clear.

static inline uint32_t SNVS_HP_GetSecurityViolationStatusFlags(SNVS_Type *base)

Get the SNVS HP security violation status flags.

The flags are returned as the OR’ed value of the enumeration :: _snvs_hp_sv_status_flags_t.

Parameters:

base – SNVS peripheral base address

Returns:

The OR’ed value of security violation status flags.

static inline void SNVS_HP_ClearSecurityViolationStatusFlags(SNVS_Type *base, uint32_t mask)

Clear the SNVS HP security violation status flags.

The flags to clear are passed in as the OR’ed value of the enumeration :: _snvs_hp_sv_status_flags_t. Only these flags could be cleared using this API.

kSNVS_ZMK_EccFailFlag
kSNVS_Violation0Flag
kSNVS_Violation1Flag
kSNVS_Violation2Flag
kSNVS_Violation3Flag
kSNVS_Violation4Flag
kSNVS_Violation5Flag

Parameters:

base – SNVS peripheral base address
mask – OR’ed value of the flags to clear.

SNVS_HPSVSR_SV0_MASK

SNVS_HPSVSR_SV1_MASK

SNVS_HPSVSR_SV2_MASK

SNVS_HPSVSR_SV4_MASK

SNVS_HPSVSR_SV5_MASK

SNVS_MAKE_HP_SV_FLAG(x)

Macro to make security violation flag.

Macro help to make security violation flag kSNVS_Violation0Flag to kSNVS_Violation5Flag, For example, SNVS_MAKE_HP_SV_FLAG(0) is kSNVS_Violation0Flag.

struct _snvs_hp_rtc_datetime

#include <fsl_snvs_hp.h>

Structure is used to hold the date and time.

Public Members

uint16_t year: Range from 1970 to 2099.

uint8_t month: Range from 1 to 12.

uint8_t day: Range from 1 to 31 (depending on month).

uint8_t hour: Range from 0 to 23.

uint8_t minute: Range from 0 to 59.

uint8_t second: Range from 0 to 59.

struct _snvs_hp_rtc_config

#include <fsl_snvs_hp.h>

SNVS config structure.

The config struct can be made const so it resides in flash

Public Members

bool rtcCalEnable: true: RTC calibration mechanism is enabled; false:No calibration is used

uint32_t rtcCalValue: Defines signed calibration value for nonsecure RTC; This is a 5-bit 2’s complement value, range from -16 to +15

uint32_t periodicInterruptFreq: Defines frequency of the periodic interrupt; Range from 0 to 15

Secure Non-Volatile Storage Low-Power#

void SNVS_LP_Init(SNVS_Type *base)

Ungates the SNVS clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

base – SNVS peripheral base address

void SNVS_LP_Deinit(SNVS_Type *base)

Deinit the SNVS LP section.

Parameters:

base – SNVS peripheral base address

status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime)

Sets the SNVS SRTC date and time according to the given time structure.

Parameters:

base – SNVS peripheral base address
datetime – Pointer to the structure where the date and time details are stored.

Returns:

kStatus_Success: Success in setting the time and starting the SNVS SRTC kStatus_InvalidArgument: Error because the datetime format is incorrect

void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)

Gets the SNVS SRTC time and stores it in the given time structure.

Parameters:

base – SNVS peripheral base address
datetime – Pointer to the structure where the date and time details are stored.

status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime)

Sets the SNVS SRTC alarm time.

The function sets the SRTC alarm. It also checks whether the specified alarm time is greater than the present time. If not, the function does not set the alarm and returns an error. Please note, that SRTC alarm has limited resolution because only 32 most significant bits of SRTC counter are compared to SRTC Alarm register. If the alarm time is beyond SRTC resolution, the function does not set the alarm and returns an error.

Parameters:

base – SNVS peripheral base address
alarmTime – Pointer to the structure where the alarm time is stored.

Returns:

kStatus_Success: success in setting the SNVS SRTC alarm kStatus_InvalidArgument: Error because the alarm datetime format is incorrect kStatus_Fail: Error because the alarm time has already passed or is beyond resolution

void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime)

Returns the SNVS SRTC alarm time.

Parameters:

base – SNVS peripheral base address
datetime – Pointer to the structure where the alarm date and time details are stored.

static inline void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask)

Enables the selected SNVS interrupts.

Parameters:

base – SNVS peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration :: _snvs_lp_srtc_interrupts

static inline void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask)

Disables the selected SNVS interrupts.

Parameters:

base – SNVS peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration :: _snvs_lp_srtc_interrupts

uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base)

Gets the enabled SNVS interrupts.

Parameters:

base – SNVS peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration :: _snvs_lp_srtc_interrupts

uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base)

Gets the SNVS status flags.

Parameters:

base – SNVS peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration :: _snvs_lp_srtc_status_flags

static inline void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask)

Clears the SNVS status flags.

Parameters:

base – SNVS peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration :: _snvs_lp_srtc_status_flags

static inline void SNVS_LP_SRTC_StartTimer(SNVS_Type *base)

Starts the SNVS SRTC time counter.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_LP_SRTC_StopTimer(SNVS_Type *base)

Stops the SNVS SRTC time counter.

Parameters:

base – SNVS peripheral base address

void SNVS_LP_EnablePassiveTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin, snvs_lp_passive_tamper_t config)

Enables the specified SNVS external tamper.

Parameters:

base – SNVS peripheral base address
pin – SNVS external tamper pin
config – Configuration structure of external passive tamper

status_t SNVS_LP_EnableTxActiveTamper(SNVS_Type *base, snvs_lp_active_tx_tamper_t pin, tamper_active_tx_config_t config)

Enable active tamper tx external pad.

Parameters:

base – SNVS peripheral base address
pin – SNVS active tamper pin
config – Configuration structure of external active tamper

status_t SNVS_LP_EnableRxActiveTamper(SNVS_Type *base, snvs_lp_external_tamper_t rx, tamper_active_rx_config_t config)

Enable active tamper rx external pad.

Parameters:

base – SNVS peripheral base address
rx – SNVS external RX tamper pin
config – SNVS RX tamper config structure

status_t SNVS_LP_SetVoltageTamper(SNVS_Type *base, bool enable)

Sets voltage tamper detect.

Parameters:

base – SNVS peripheral base address
enable – True if enable false if disable

status_t SNVS_LP_SetTemperatureTamper(SNVS_Type *base, bool enable)

Sets temperature tamper detect.

Parameters:

base – SNVS peripheral base address
enable – True if enable false if disable

status_t SNVS_LP_SetClockTamper(SNVS_Type *base, bool enable)

Sets clock tamper detect.

Parameters:

base – SNVS peripheral base address
enable – True if enable false if disable

snvs_lp_external_tamper_status_t SNVS_LP_CheckVoltageTamper(SNVS_Type *base)

brief Check voltage tamper

param base SNVS peripheral base address

snvs_lp_external_tamper_status_t SNVS_LP_CheckTemperatureTamper(SNVS_Type *base)

Check temperature tamper.

Parameters:

base – SNVS peripheral base address

snvs_lp_external_tamper_status_t SNVS_LP_CheckClockTamper(SNVS_Type *base)

brief Check clock tamper

param base SNVS peripheral base address

void SNVS_LP_TamperPinTx_GetDefaultConfig(tamper_active_tx_config_t *config)

Fills in the SNVS tamper pin config struct with the default settings.

The default values are as follows. code config->clock = kSNVS_ActiveTamper16HZ; config->seed = 0U; config->polynomial = 0U; endcode

Parameters:

config – Pointer to the user’s SNVS configuration structure.

void SNVS_LP_TamperPinRx_GetDefaultConfig(tamper_active_rx_config_t *config)

brief Fills in the SNVS tamper pin config struct with the default settings.

The default values are as follows. code config->filterenable = 0U; config->filter = 0U; config->tx = kSNVS_ActiveTamper1; endcode param config Pointer to the user’s SNVS configuration structure.

void SNVS_LP_PassiveTamperPin_GetDefaultConfig(snvs_lp_passive_tamper_t *config)

Fills in the SNVS tamper pin config struct with the default settings.

The default values are as follows. code config->polarity = 0U; config->filterenable = 0U; if available on SoC config->filter = 0U; if available on SoC endcode

Parameters:

config – Pointer to the user’s SNVS configuration structure.

void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin)

Disables the specified SNVS external tamper.

Parameters:

base – SNVS peripheral base address
pin – SNVS external tamper pin

void SNVS_LP_DisableAllExternalTamper(SNVS_Type *base)

Disable all external tamper.

Parameters:

base – SNVS peripheral base address

snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin)

Returns status of the specified external tamper.

Parameters:

base – SNVS peripheral base address
pin – SNVS external tamper pin

Returns:

The status flag. This is the enumeration :: _snvs_lp_external_tamper_status

void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin)

Clears status of the specified external tamper.

Parameters:

base – SNVS peripheral base address
pin – SNVS external tamper pin

void SNVS_LP_ClearAllExternalTamperStatus(SNVS_Type *base)

Clears status of the all external tamper.

Parameters:

base – SNVS peripheral base address

static inline void SNVS_LP_EnableMonotonicCounter(SNVS_Type *base, bool enable)

Enable or disable the Monotonic Counter.

Parameters:

base – SNVS peripheral base address
enable – Pass true to enable, false to disable.

uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base)

Get the current Monotonic Counter.

Parameters:

base – SNVS peripheral base address

Returns:

Current Monotonic Counter value.

static inline void SNVS_LP_IncreaseMonotonicCounter(SNVS_Type *base)

Increase the Monotonic Counter.

Increase the Monotonic Counter by 1.

Parameters:

base – SNVS peripheral base address

void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[8U])

Write Zeroizable Master Key (ZMK) to the SNVS registers.

Parameters:

base – SNVS peripheral base address
ZMKey – The ZMK write to the SNVS register.

static inline void SNVS_LP_SetZeroizableMasterKeyValid(SNVS_Type *base, bool valid)

Set Zeroizable Master Key valid.

This API could only be called when using software programming mode. After writing ZMK using SNVS_LP_WriteZeroizableMasterKey, call this API to make the ZMK valid.

Parameters:

base – SNVS peripheral base address
valid – Pass true to set valid, false to set invalid.

static inline bool SNVS_LP_GetZeroizableMasterKeyValid(SNVS_Type *base)

Get Zeroizable Master Key valid status.

In hardware programming mode, call this API to check whether the ZMK is valid.

Parameters:

base – SNVS peripheral base address

Returns:

true if valid, false if invalid.

static inline void SNVS_LP_SetZeroizableMasterKeyProgramMode(SNVS_Type *base, snvs_lp_zmk_program_mode_t mode)

Set Zeroizable Master Key programming mode.

Parameters:

base – SNVS peripheral base address
mode – ZMK programming mode.

static inline void SNVS_LP_EnableZeroizableMasterKeyECC(SNVS_Type *base, bool enable)

Enable or disable Zeroizable Master Key ECC.

Parameters:

base – SNVS peripheral base address
enable – Pass true to enable, false to disable.

static inline void SNVS_LP_SetMasterKeyMode(SNVS_Type *base, snvs_lp_master_key_mode_t mode)

Set SNVS Master Key mode.

Note

When kSNVS_ZMK or kSNVS_CMK used, the SNVS_HP must be configured to enable the master key selection.

Parameters:

base – SNVS peripheral base address
mode – Master Key mode.

FSL_SNVS_LP_DRIVER_VERSION: Version 2.4.6

enum _snvs_lp_srtc_interrupts

List of SNVS_LP interrupts.

Values:

enumerator kSNVS_SRTC_AlarmInterrupt: SRTC time alarm.

enum _snvs_lp_srtc_status_flags

List of SNVS_LP flags.

Values:

enumerator kSNVS_SRTC_AlarmInterruptFlag: SRTC time alarm flag

enum _snvs_lp_external_tamper

List of SNVS_LP external tampers.

Values:

enumerator kSNVS_ExternalTamper1

enum _snvs_lp_active_tamper

List of SNVS_LP active tampers.

Values:

enumerator kSNVS_ActiveTamper1

enumerator kSNVS_ActiveTamper2

enumerator kSNVS_ActiveTamper3

enumerator kSNVS_ActiveTamper4

enumerator kSNVS_ActiveTamper5

enum _snvs_lp_active_clock

List of SNVS_LP external tampers.

Values:

enumerator kSNVS_ActiveTamper16HZ

enumerator kSNVS_ActiveTamper8HZ

enumerator kSNVS_ActiveTamper4HZ

enumerator kSNVS_ActiveTamper2HZ

enum _snvs_lp_external_tamper_status

List of SNVS_LP external tampers status.

Values:

enumerator kSNVS_TamperNotDetected

enumerator kSNVS_TamperDetected

enum _snvs_lp_external_tamper_polarity

SNVS_LP external tamper polarity.

Values:

enumerator kSNVS_ExternalTamperActiveLow

enumerator kSNVS_ExternalTamperActiveHigh

enum _snvs_lp_zmk_program_mode

SNVS_LP Zeroizable Master Key programming mode.

Values:

enumerator kSNVS_ZMKSoftwareProgram: Software programming mode.

enumerator kSNVS_ZMKHardwareProgram: Hardware programming mode.

enum _snvs_lp_master_key_mode

SNVS_LP Master Key mode.

Values:

enumerator kSNVS_OTPMK: One Time Programmable Master Key.

enumerator kSNVS_ZMK: Zeroizable Master Key.

enumerator kSNVS_CMK: Combined Master Key, it is XOR of OPTMK and ZMK.

typedef enum _snvs_lp_srtc_interrupts snvs_lp_srtc_interrupts_t: List of SNVS_LP interrupts.

typedef enum _snvs_lp_srtc_status_flags snvs_lp_srtc_status_flags_t: List of SNVS_LP flags.

typedef enum _snvs_lp_external_tamper snvs_lp_external_tamper_t: List of SNVS_LP external tampers.

typedef enum _snvs_lp_active_tamper snvs_lp_active_tx_tamper_t: List of SNVS_LP active tampers.

typedef enum _snvs_lp_active_clock snvs_lp_active_clock_t: List of SNVS_LP external tampers.

typedef enum _snvs_lp_external_tamper_status snvs_lp_external_tamper_status_t: List of SNVS_LP external tampers status.

typedef enum _snvs_lp_external_tamper_polarity snvs_lp_external_tamper_polarity_t: SNVS_LP external tamper polarity.

typedef struct _snvs_lp_srtc_datetime snvs_lp_srtc_datetime_t: Structure is used to hold the date and time.

typedef struct _snvs_lp_srtc_config snvs_lp_srtc_config_t

SNVS_LP config structure.

This structure holds the configuration settings for the SNVS_LP peripheral. To initialize this structure to reasonable defaults, call the SNVS_LP_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

typedef enum _snvs_lp_zmk_program_mode snvs_lp_zmk_program_mode_t: SNVS_LP Zeroizable Master Key programming mode.

typedef enum _snvs_lp_master_key_mode snvs_lp_master_key_mode_t: SNVS_LP Master Key mode.

void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config)

Ungates the SNVS clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the SNVS driver.

Parameters:

base – SNVS peripheral base address
config – Pointer to the user’s SNVS configuration structure.

void SNVS_LP_SRTC_Deinit(SNVS_Type *base)

Stops the SRTC timer.

Parameters:

base – SNVS peripheral base address

void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config)

Fills in the SNVS_LP config struct with the default settings.

The default values are as follows.

config->srtccalenable = false;
config->srtccalvalue = 0U;

Parameters:

config – Pointer to the user’s SNVS configuration structure.

SNVS_ZMK_REG_COUNT: Define of SNVS_LP Zeroizable Master Key registers.

SNVS_LP_MAX_TAMPER: Define of SNVS_LP Max possible tamper.

struct tamper_active_tx_config_t: #include <fsl_snvs_lp.h>

Structure is used to configure SNVS LP active TX tamper pins.

struct tamper_active_rx_config_t: #include <fsl_snvs_lp.h>

Structure is used to configure SNVS LP active RX tamper pins.

struct snvs_lp_passive_tamper_t: #include <fsl_snvs_lp.h>

Structure is used to configure SNVS LP passive tamper pins.

struct _snvs_lp_srtc_datetime

#include <fsl_snvs_lp.h>

Structure is used to hold the date and time.

Public Members

uint16_t year: Range from 1970 to 2099.

uint8_t month: Range from 1 to 12.

uint8_t day: Range from 1 to 31 (depending on month).

uint8_t hour: Range from 0 to 23.

uint8_t minute: Range from 0 to 59.

uint8_t second: Range from 0 to 59.

struct _snvs_lp_srtc_config

#include <fsl_snvs_lp.h>

SNVS_LP config structure.

The config struct can be made const so it resides in flash

Public Members

bool srtcCalEnable: true: SRTC calibration mechanism is enabled; false: No calibration is used

uint32_t srtcCalValue: Defines signed calibration value for SRTC; This is a 5-bit 2’s complement value, range from -16 to +15

TMU: Thermal Management Unit Driver#

enum _tmu_monitor_site

Values:

enumerator kTMU_MonitorSite0

enumerator kTMU_MonitorSite1

enumerator kTMU_MonitorSite2

enumerator kTMU_MonitorSite3

enumerator kTMU_MonitorSite4

enumerator kTMU_MonitorSite5

enumerator kTMU_MonitorSite6

enumerator kTMU_MonitorSite7

enumerator kTMU_MonitorSite8

enumerator kTMU_MonitorSite9

enumerator kTMU_MonitorSite10

enumerator kTMU_MonitorSite11

enumerator kTMU_MonitorSite12

enumerator kTMU_MonitorSite13

enumerator kTMU_MonitorSite14

enumerator kTMU_MonitorSite15

enum _tmu_interrupt_enable

TMU interrupt enable.

Values:

enumerator kTMU_ImmediateTemperatureInterruptEnable: Immediate temperature threshold exceeded interrupt enable.

enumerator kTMU_AverageTemperatureInterruptEnable: Average temperature threshold exceeded interrupt enable.

enumerator kTMU_AverageTemperatureCriticalInterruptEnable: Average temperature critical threshold exceeded interrupt enable. >

enum _tmu_interrupt_status_flags

TMU interrupt status flags.

Values:

enumerator kTMU_ImmediateTemperatureStatusFlags: Immediate temperature threshold exceeded(ITTE).

enumerator kTMU_AverageTemperatureStatusFlags: Average temperature threshold exceeded(ATTE).

enumerator kTMU_AverageTemperatureCriticalStatusFlags: Average temperature critical threshold exceeded.(ATCTE)

enum _tmu_status_flags

TMU status flags.

Values:

enumerator kTMU_IntervalExceededStatusFlags: Monitoring interval exceeded. The time required to perform measurement of all monitored sites has exceeded the monitoring interval as defined by TMTMIR.

enumerator kTMU_OutOfLowRangeStatusFlags: Out-of-range low temperature measurement detected. A temperature sensor detected a temperature reading below the lowest measurable temperature of 0 °C.

enumerator kTMU_OutOfHighRangeStatusFlags: Out-of-range high temperature measurement detected. A temperature sensor detected a temperature reading above the highest measurable temperature of 125 °C.

enum _tmu_average_low_pass_filter

Average low pass filter setting.

Values:

enumerator kTMU_AverageLowPassFilter1_0: Average low pass filter = 1.

enumerator kTMU_AverageLowPassFilter0_5: Average low pass filter = 0.5.

enumerator kTMU_AverageLowPassFilter0_25: Average low pass filter = 0.25.

enumerator kTMU_AverageLowPassFilter0_125: Average low pass filter = 0.125.

typedef struct _tmu_thresold_config tmu_thresold_config_t: configuration for TMU thresold.

typedef struct _tmu_interrupt_status tmu_interrupt_status_t: TMU interrupt status.

typedef enum _tmu_average_low_pass_filter tmu_average_low_pass_filter_t: Average low pass filter setting.

typedef struct _tmu_config tmu_config_t: Configuration for TMU module.

void TMU_Init(TMU_Type *base, const tmu_config_t *config)

Enable the access to TMU registers and Initialize TMU module.

Parameters:

base – TMU peripheral base address.
config – Pointer to configuration structure. Refer to “tmu_config_t” structure.

void TMU_Deinit(TMU_Type *base)

De-initialize TMU module and Disable the access to DCDC registers.

Parameters:

base – TMU peripheral base address.

void TMU_GetDefaultConfig(tmu_config_t *config)

Gets the default configuration for TMU.

This function initializes the user configuration structure to default value. The default value are:

Example:

config->monitorInterval = 0U;
config->monitorSiteSelection = 0U;
config->averageLPF = kTMU_AverageLowPassFilter1_0;

Parameters:

config – Pointer to TMU configuration structure.

static inline void TMU_Enable(TMU_Type *base, bool enable)

Enable/Disable the TMU module.

Parameters:

base – TMU peripheral base address.
enable – Switcher to enable/disable TMU.

static inline void TMU_EnableInterrupts(TMU_Type *base, uint32_t mask)

Enable the TMU interrupts.

Parameters:

base – TMU peripheral base address.
mask – The interrupt mask. Refer to “_tmu_interrupt_enable” enumeration.

static inline void TMU_DisableInterrupts(TMU_Type *base, uint32_t mask)

Disable the TMU interrupts.

Parameters:

base – TMU peripheral base address.
mask – The interrupt mask. Refer to “_tmu_interrupt_enable” enumeration.

void TMU_GetInterruptStatusFlags(TMU_Type *base, tmu_interrupt_status_t *status)

Get interrupt status flags.

Parameters:

base – TMU peripheral base address.
status – The pointer to interrupt status structure. Record the current interrupt status. Please refer to “tmu_interrupt_status_t” structure.

void TMU_ClearInterruptStatusFlags(TMU_Type *base, uint32_t mask)

Clear interrupt status flags and corresponding interrupt critical site capture register.

Parameters:

base – TMU peripheral base address.
mask – The mask of interrupt status flags. Refer to “_tmu_interrupt_status_flags” enumeration.

static inline uint32_t TMU_GetStatusFlags(TMU_Type *base)

Get TMU status flags.

Parameters:

base – TMU peripheral base address.

Returns:

The mask of status flags. Refer to “_tmu_status_flags” enumeration.

status_t TMU_GetHighestTemperature(TMU_Type *base, uint32_t *temperature)

Get the highest temperature reached for any enabled monitored site within the temperature sensor range.

Parameters:

base – TMU peripheral base address.
temperature – Highest temperature recorded in degrees Celsius by any enabled monitored site.

Return values:

kStatus_Success – Temperature reading is valid.
kStatus_Fail – Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 °C for an enabled monitored site.

Returns:

Execution status.

status_t TMU_GetLowestTemperature(TMU_Type *base, uint32_t *temperature)

Get the lowest temperature reached for any enabled monitored site within the temperature sensor range.

Parameters:

base – TMU peripheral base address.
temperature – Lowest temperature recorded in degrees Celsius by any enabled monitored site.

Return values:

kStatus_Success – Temperature reading is valid.
kStatus_Fail – Temperature reading is not valid due to no measured temperature within the sensor range of 0-125 °C for an enabled monitored site.

Returns:

Execution status.

status_t TMU_GetImmediateTemperature(TMU_Type *base, uint32_t siteIndex, uint32_t *temperature)

Get the last immediate temperature at site n. The site must be part of the list of enabled monitored sites as defined by monitorSiteSelection in “tmu_config_t” structure.

Parameters:

base – TMU peripheral base address.
siteIndex – The index of the site user want to read. 0U: site0 ~ 15U: site15.
temperature – Last immediate temperature reading at site n .

Return values:

kStatus_Success – Temperature reading is valid.
kStatus_Fail – Temperature reading is not valid because temperature out of sensor range or first measurement still pending.

Returns:

Execution status.

status_t TMU_GetAverageTemperature(TMU_Type *base, uint32_t siteIndex, uint32_t *temperature)

Get the last average temperature at site n. The site must be part of the list of enabled monitored sites as defined by monitorSiteSelection in “tmu_config_t” structure.

Parameters:

base – TMU peripheral base address.
siteIndex – The index of the site user want to read. 0U: site0 ~ 15U: site15.
temperature – Last average temperature reading at site n .

Return values:

kStatus_Success – Temperature reading is valid.
kStatus_Fail – Temperature reading is not valid because temperature out of sensor range or first measurement still pending.

Returns:

Execution status.

void TMU_SetHighTemperatureThresold(TMU_Type *base, const tmu_thresold_config_t *config)

Configure the high temperature thresold value and enable/disable relevant thresold.

Parameters:

base – TMU peripheral base address.
config – Pointer to configuration structure. Refer to “tmu_thresold_config_t” structure.

FSL_TMU_DRIVER_VERSION

TMU driver version.

Version 2.0.3.

struct _tmu_thresold_config

#include <fsl_tmu.h>

configuration for TMU thresold.

Public Members

bool immediateThresoldEnable: Enable high temperature immediate threshold.

bool AverageThresoldEnable: Enable high temperature average threshold.

bool AverageCriticalThresoldEnable: Enable high temperature average critical threshold.

uint8_t immediateThresoldValue: Range:0U-125U. Valid when corresponding thresold is enabled. High temperature immediate threshold value. Determines the current upper temperature threshold, for anyenabled monitored site.

uint8_t averageThresoldValue: Range:0U-125U. Valid when corresponding thresold is enabled. High temperature average threshold value. Determines the average upper temperature threshold, for any enabled monitored site.

uint8_t averageCriticalThresoldValue: Range:0U-125U. Valid when corresponding thresold is enabled. High temperature average critical threshold value. Determines the average upper critical temperature threshold, for any enabled monitored site.

struct _tmu_interrupt_status

#include <fsl_tmu.h>

TMU interrupt status.

Public Members

uint32_t interruptDetectMask: The mask of interrupt status flags. Refer to “_tmu_interrupt_status_flags” enumeration.

uint16_t immediateInterruptsSiteMask: The mask of the temperature sensor site associated with a detected ITTE event. Please refer to “_tmu_monitor_site” enumeration.

uint16_t AverageInterruptsSiteMask: The mask of the temperature sensor site associated with a detected ATTE event. Please refer to “_tmu_monitor_site” enumeration.

uint16_t AverageCriticalInterruptsSiteMask: The mask of the temperature sensor site associated with a detected ATCTE event. Please refer to “_tmu_monitor_site” enumeration.

struct _tmu_config

#include <fsl_tmu.h>

Configuration for TMU module.

Public Members

uint8_t monitorInterval: Temperature monitoring interval in seconds. Please refer to specific table in RM.

uint16_t monitorSiteSelection: By setting the select bit for a temperature sensor site, it is enabled and included in all monitoring functions. If no site is selected, site 0 is monitored by default. Refer to “_tmu_monitor_site” enumeration. Please look up relevant table in reference manual.

tmu_average_low_pass_filter_t averageLPF: The average temperature is calculated as: ALPF x Current_Temp + (1 - ALPF) x Average_Temp. For proper operation, this field should only change when monitoring is disabled.

UART: Universal Asynchronous Receiver/Transmitter Driver#

UART Driver#

static inline void UART_SoftwareReset(UART_Type *base)

Resets the UART using software.

This function resets the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]

Parameters:

base – UART peripheral base address.

status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)

Initializes an UART instance with the user configuration structure and the peripheral clock.

This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the UART.

uart_config_t uartConfig;
uartConfig.baudRate_Bps = 115200U;
uartConfig.parityMode = kUART_ParityDisabled;
uartConfig.dataBitsCount = kUART_EightDataBits;
uartConfig.stopBitCount = kUART_OneStopBit;
uartConfig.txFifoWatermark = 2;
uartConfig.rxFifoWatermark = 1;
uartConfig.enableAutoBaudrate = false;
uartConfig.enableTx = true;
uartConfig.enableRx = true;
UART_Init(UART1, &uartConfig, 24000000U);

Parameters:

base – UART peripheral base address.
config – Pointer to a user-defined configuration structure.
srcClock_Hz – UART clock source frequency in HZ.

Return values:

kStatus_Success – UART initialize succeed

void UART_Deinit(UART_Type *base)

Deinitializes a UART instance.

This function waits for transmit to complete, disables TX and RX, and disables the UART clock.

Parameters:

base – UART peripheral base address.

void UART_GetDefaultConfig(uart_config_t *config)

Gets the default configuration structure.

This function initializes the UART configuration structure to a default value. The default values are: uartConfig->baudRate_Bps = 115200U; uartConfig->parityMode = kUART_ParityDisabled; uartConfig->dataBitsCount = kUART_EightDataBits; uartConfig->stopBitCount = kUART_OneStopBit; uartConfig->txFifoWatermark = 2; uartConfig->rxFifoWatermark = 1; uartConfig->enableAutoBaudrate = flase; uartConfig->enableTx = false; uartConfig->enableRx = false;

Parameters:

config – Pointer to a configuration structure.

status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the UART instance baud rate.

This function configures the UART module baud rate. This function is used to update the UART module baud rate after the UART module is initialized by the UART_Init.

UART_SetBaudRate(UART1, 115200U, 20000000U);

Parameters:

base – UART peripheral base address.
baudRate_Bps – UART baudrate to be set.
srcClock_Hz – UART clock source frequency in Hz.

Return values:

kStatus_UART_BaudrateNotSupport – Baudrate is not support in the current clock source.
kStatus_Success – Set baudrate succeeded.

void UART_Enable9bitMode(UART_Type *base, bool enable)

Enable 9-bit mode for UART.

This function set the 9-bit mode for UART module.

Parameters:

base – UART peripheral base address.
enable – true to enable, flase to disable.

void UART_SendAddress(UART_Type *base, uint8_t address)

Transmit an address frame in 9-bit data mode.

Parameters:

base – UART peripheral base address.
address – UART slave address.

static inline void UART_SetMatchAddress(UART_Type *base, uint8_t address)

Set the 9bit slave address character.

This function configures the address for UART module that works as slave in 9-bit RS-485 mode.

Parameters:

base – UART peripheral base address.
address – 9bit slave address character.

static inline void UART_Set9bitAddressDetectMode(UART_Type *base, uint8_t mode)

Set 9bit Slave Address Detect Mode. Mode: Normal - In this mode, once the UART has detected a 9th bit is equal to ‘1’, it will always save the subsequent frames to RxFIFO. So the software must decide whether the address and data in RxFIFO are needed or not. Automtic - In this mode, If the address byte is received and it does not match SLADDR character, the receiver will discard the address byte and subsequent data byte.If the address byte again matches SLADDR character, the receiver will put this address byte and subsequent data byte in the RxFIFO along with their 9th bit.

kUART_9BitNormalMode for Normal mode kUART_9BitAutoMode for Automtic mode.

Parameters:

base – UART peripheral base address.
mode – 9bit Slave Address Detect Mode Selection.

static inline void UART_Set9bitAddressDetectInterrput(UART_Type *base, bool enable)

Set 9bit Slave Address Detected Interrupt Enable.

Parameters:

base – UART peripheral base address.
enable – true to enable, flase to disable.

static inline void UART_Set9thTransmitBit(UART_Type *base)

Set UART 9th transmit bit.

Parameters:

base – UART peripheral base address.

static inline void UART_Clear9thTransmitBit(UART_Type *base)

Clear UART 9th transmit bit.

Parameters:

base – UART peripheral base address.

static inline void UART_Enable(UART_Type *base)

This function is used to Enable the UART Module.

Parameters:

base – UART base pointer.

static inline void UART_SetIdleCondition(UART_Type *base, uart_idle_condition_t condition)

This function is used to configure the IDLE line condition.

Parameters:

base – UART base pointer.
condition – IDLE line detect condition of the enumerators in uart_idle_condition_t.

static inline void UART_Disable(UART_Type *base)

This function is used to Disable the UART Module.

Parameters:

base – UART base pointer.

bool UART_GetStatusFlag(UART_Type *base, uint32_t flag)

This function is used to get the current status of specific UART status flag(including interrupt flag). The available status flag can be select from uart_status_flag_t enumeration.

Parameters:

base – UART base pointer.
flag – Status flag to check.

Return values:

current – state of corresponding status flag.

void UART_ClearStatusFlag(UART_Type *base, uint32_t flag)

This function is used to clear the current status of specific UART status flag. The available status flag can be select from uart_status_flag_t enumeration.

Parameters:

base – UART base pointer.
flag – Status flag to clear.

void UART_EnableInterrupts(UART_Type *base, uint32_t mask)

Enables UART interrupts according to the provided mask.

This function enables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _uart_interrupt_enable. For example, to enable TX empty interrupt and RX data ready interrupt, do the following.

UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable);

Parameters:

base – UART peripheral base address.
mask – The interrupts to enable. Logical OR of _uart_interrupt_enable.

void UART_DisableInterrupts(UART_Type *base, uint32_t mask)

Disables the UART interrupts according to the provided mask.

This function disables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration members. See _uart_interrupt_enable. For example, to disable TX empty interrupt and RX data ready interrupt do the following.

UART_EnableInterrupts(UART1,kUART_TxEmptyEnable | kUART_RxDataReadyEnable);

Parameters:

base – UART peripheral base address.
mask – The interrupts to disable. Logical OR of _uart_interrupt_enable.

uint32_t UART_GetEnabledInterrupts(UART_Type *base)

Gets enabled UART interrupts.

This function gets the enabled UART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _uart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _uart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:

uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);

if (kUART_TxEmptyEnable & enabledInterrupts)
{
    ...
}

Parameters:

base – UART peripheral base address.

Returns:

UART interrupt flags which are logical OR of the enumerators in _uart_interrupt_enable.

static inline void UART_EnableTx(UART_Type *base, bool enable)

Enables or disables the UART transmitter.

This function enables or disables the UART transmitter.

Parameters:

base – UART peripheral base address.
enable – True to enable, false to disable.

static inline void UART_EnableRx(UART_Type *base, bool enable)

Enables or disables the UART receiver.

This function enables or disables the UART receiver.

Parameters:

base – UART peripheral base address.
enable – True to enable, false to disable.

static inline void UART_WriteByte(UART_Type *base, uint8_t data)

Writes to the transmitter register.

This function is used to write data to transmitter register. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

base – UART peripheral base address.
data – Data write to the TX register.

static inline uint8_t UART_ReadByte(UART_Type *base)

Reads the receiver register.

This function is used to read data from receiver register. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

base – UART peripheral base address.

Returns:

Data read from data register.

status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length)

Writes to the TX register using a blocking method.

This function polls the TX register, waits for the TX register to be empty or for the TX FIFO to have room and writes data to the TX buffer.

Parameters:

base – UART peripheral base address.
data – Start address of the data to write.
length – Size of the data to write.

Return values:

kStatus_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)

Read RX data register using a blocking method.

This function polls the RX register, waits for the RX register to be full or for RX FIFO to have data, and reads data from the TX register.

Parameters:

base – UART peripheral base address.
data – Start address of the buffer to store the received data.
length – Size of the buffer.

Return values:

kStatus_UART_RxHardwareOverrun – Receiver overrun occurred while receiving data.
kStatus_UART_NoiseError – A noise error occurred while receiving data.
kStatus_UART_FramingError – A framing error occurred while receiving data.
kStatus_UART_ParityError – A parity error occurred while receiving data.
kStatus_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

void UART_TransferCreateHandle(UART_Type *base, uart_handle_t *handle, uart_transfer_callback_t callback, void *userData)

Initializes the UART handle.

This function initializes the UART handle which can be used for other UART transactional APIs. Usually, for a specified UART instance, call this API once to get the initialized handle.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.
callback – The callback function.
userData – The parameter of the callback function.

void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received are stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If data is already received in the ring buffer, the user can get the received data from the ring buffer directly.

Note

When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.
ringBuffer – Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.

size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)

Get the length of received data in RX ring buffer.

Parameters:

handle – UART handle pointer.

Returns:

Length of received data in RX ring buffer.

status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in the ISR, the UART driver calls the callback function and passes the kStatus_UART_TxIdle as status parameter.

Note

The kStatus_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.
xfer – UART transfer structure. See uart_transfer_t.

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_UART_TxBusy – Previous transmission still not finished; data not all written to TX register yet.
kStatus_InvalidArgument – Invalid argument.

void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out how many bytes are not sent out.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.

status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)

Gets the number of bytes written to the UART TX register.

This function gets the number of bytes written to the UART TX register by using the interrupt method.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.
count – Send bytes count.

Return values:

kStatus_NoTransferInProgress – No send in progress.
kStatus_InvalidArgument – The parameter is invalid.
kStatus_Success – Get successfully through the parameter count;

status_t UART_TransferReceiveNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using an interrupt method.

This function receives data using an interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough to read, the receive request is saved by the UART driver. When the new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. The 5 bytes are copied to the xfer->data and this function returns with the parameter receivedBytes set to 5. For the left 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to the xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.
xfer – UART transfer structure, see uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into transmit queue.
kStatus_UART_RxBusy – Previous receive request is not finished.
kStatus_InvalidArgument – Invalid argument.

void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)

Aborts the interrupt-driven data receiving.

This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know how many bytes are not received yet.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.

status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been received.

This function gets the number of bytes that have been received.

Parameters:

base – UART peripheral base address.
handle – UART handle pointer.
count – Receive bytes count.

Return values:

kStatus_NoTransferInProgress – No receive in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter count;

void UART_TransferHandleIRQ(UART_Type *base, void *irqHandle)

UART IRQ handle function.

This function handles the UART transmit and receive IRQ request.

Parameters:

base – UART peripheral base address.
irqHandle – UART handle pointer.

static inline void UART_EnableTxDMA(UART_Type *base, bool enable)

Enables or disables the UART transmitter DMA request.

This function enables or disables the transmit request when the transmitter has one or more slots available in the TxFIFO. The fill level in the TxFIFO that generates the DMA request is controlled by the TXTL bits.

Parameters:

base – UART peripheral base address.
enable – True to enable, false to disable.

static inline void UART_EnableRxDMA(UART_Type *base, bool enable)

Enables or disables the UART receiver DMA request.

This function enables or disables the receive request when the receiver has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request is generated is controlled by the RXTL bits .

Parameters:

base – UART peripheral base address.
enable – True to enable, false to disable.

static inline void UART_SetTxFifoWatermark(UART_Type *base, uint8_t watermark)

This function is used to set the watermark of UART Tx FIFO. A maskable interrupt is generated whenever the data level in the TxFIFO falls below the Tx FIFO watermark.

Parameters:

base – UART base pointer.
watermark – The Tx FIFO watermark.

static inline void UART_SetRxRTSWatermark(UART_Type *base, uint8_t watermark)

This function is used to set the watermark of UART RTS deassertion.

The RTS signal deasserts whenever the data count in RxFIFO reaches the Rx RTS watermark.

Parameters:

base – UART base pointer.
watermark – The Rx RTS watermark.

static inline void UART_SetRxFifoWatermark(UART_Type *base, uint8_t watermark)

This function is used to set the watermark of UART Rx FIFO. A maskable interrupt is generated whenever the data level in the RxFIFO reaches the Rx FIFO watermark.

Parameters:

base – UART base pointer.
watermark – The Rx FIFO watermark.

static inline void UART_EnableAutoBaudRate(UART_Type *base, bool enable)

This function is used to set the enable condition of Automatic Baud Rate Detection feature.

Parameters:

base – UART base pointer.
enable – Enable/Disable Automatic Baud Rate Detection feature.
- true: Enable Automatic Baud Rate Detection feature.
- false: Disable Automatic Baud Rate Detection feature.

static inline bool UART_IsAutoBaudRateComplete(UART_Type *base)

This function is used to read if the automatic baud rate detection has finished.

Parameters:

base – UART base pointer.

Returns:

- true: Automatic baud rate detection has finished.

false: Automatic baud rate detection has not finished.

FSL_UART_DRIVER_VERSION: UART driver version.

Error codes for the UART driver.

Values:

enumerator kStatus_UART_TxBusy: Transmitter is busy.

enumerator kStatus_UART_RxBusy: Receiver is busy.

enumerator kStatus_UART_TxIdle: UART transmitter is idle.

enumerator kStatus_UART_RxIdle: UART receiver is idle.

enumerator kStatus_UART_TxWatermarkTooLarge: TX FIFO watermark too large

enumerator kStatus_UART_RxWatermarkTooLarge: RX FIFO watermark too large

enumerator kStatus_UART_FlagCannotClearManually: UART flag can’t be manually cleared.

enumerator kStatus_UART_Error: Error happens on UART.

enumerator kStatus_UART_RxRingBufferOverrun: UART RX software ring buffer overrun.

enumerator kStatus_UART_RxHardwareOverrun: UART RX receiver overrun.

enumerator kStatus_UART_NoiseError: UART noise error.

enumerator kStatus_UART_FramingError: UART framing error.

enumerator kStatus_UART_ParityError: UART parity error.

enumerator kStatus_UART_BaudrateNotSupport: Baudrate is not support in current clock source

enumerator kStatus_UART_BreakDetect: Receiver detect BREAK signal

enumerator kStatus_UART_Timeout: UART times out.

enumerator kStatus_UART_9bitSlaveAddressDetected: Receiver detect 9bit slave address.

enum _uart_data_bits

UART data bits count.

Values:

enumerator kUART_SevenDataBits: Seven data bit

enumerator kUART_EightDataBits: Eight data bit

enum _uart_parity_mode

UART parity mode.

Values:

enumerator kUART_ParityDisabled: Parity disabled

enumerator kUART_ParityEven: Even error check is selected

enumerator kUART_ParityOdd: Odd error check is selected

enum _uart_stop_bit_count

UART stop bit count.

Values:

enumerator kUART_OneStopBit: One stop bit

enumerator kUART_TwoStopBit: Two stop bits

enum _uart_9bit_detect_mode

UART 9bit address detect mode.

Values:

enumerator kUART_9BitNormalMode: 9Bit normal mode

enumerator kUART_9BitAutoMode: 9Bit automatic mode

enum _uart_idle_condition

UART idle condition detect.

Values:

enumerator kUART_IdleFor4Frames: Idle for more than 4 frames

enumerator kUART_IdleFor8Frames: Idle for more than 8 frames

enumerator kUART_IdleFor16Frames: Idle for more than 16 frames

enumerator kUART_IdleFor32Frames: Idle for more than 32 frames

enum _uart_interrupt_enable

This structure contains the settings for all of the UART interrupt configurations.

Values:

enumerator kUART_AutoBaudEnable

enumerator kUART_TxReadyEnable

enumerator kUART_IdleEnable

enumerator kUART_RxReadyEnable

enumerator kUART_TxEmptyEnable

enumerator kUART_RtsDeltaEnable

enumerator kUART_EscapeEnable

enumerator kUART_RtsEnable

enumerator kUART_AgingTimerEnable

enumerator kUART_DtrEnable

enumerator kUART_ParityErrorEnable

enumerator kUART_FrameErrorEnable

enumerator kUART_DcdEnable

enumerator kUART_RiEnable

enumerator kUART_RxDsEnable

enumerator kUART_tAirWakeEnable

enumerator kUART_AwakeEnable

enumerator kUART_DtrDeltaEnable

enumerator kUART_AutoBaudCntEnable

enumerator kUART_IrEnable

enumerator kUART_WakeEnable

enumerator kUART_TxCompleteEnable

enumerator kUART_BreakDetectEnable

enumerator kUART_RxOverrunEnable

enumerator kUART_RxDataReadyEnable

enumerator kUART_RxDmaIdleEnable

enumerator kUART_AllInterruptsEnable

UART status flags.

This provides constants for the UART status flags for use in the UART functions.

Values:

enumerator kUART_RxCharReadyFlag: Rx Character Ready Flag.

enumerator kUART_RxErrorFlag: Rx Error Detect Flag.

enumerator kUART_RxOverrunErrorFlag: Rx Overrun Flag.

enumerator kUART_RxFrameErrorFlag: Rx Frame Error Flag.

enumerator kUART_RxBreakDetectFlag: Rx Break Detect Flag.

enumerator kUART_RxParityErrorFlag: Rx Parity Error Flag.

enumerator kUART_ParityErrorFlag: Parity Error Interrupt Flag.

enumerator kUART_RtsStatusFlag: RTS_B Pin Status Flag.

enumerator kUART_TxReadyFlag: Transmitter Ready Interrupt/DMA Flag.

enumerator kUART_RtsDeltaFlag: RTS Delta Flag.

enumerator kUART_EscapeFlag: Escape Sequence Interrupt Flag.

enumerator kUART_FrameErrorFlag: Frame Error Interrupt Flag.

enumerator kUART_RxReadyFlag: Receiver Ready Interrupt/DMA Flag.

enumerator kUART_AgingTimerFlag: Aging Timer Interrupt Flag.

enumerator kUART_DtrDeltaFlag: DTR Delta Flag.

enumerator kUART_RxDsFlag: Receiver IDLE Interrupt Flag.

enumerator kUART_tAirWakeFlag: Asynchronous IR WAKE Interrupt Flag.

enumerator kUART_AwakeFlag: Asynchronous WAKE Interrupt Flag.

enumerator kUART_Rs485SlaveAddrMatchFlag: RS-485 Slave Address Detected Interrupt Flag.

enumerator kUART_AutoBaudFlag: Automatic Baud Rate Detect Complete Flag.

enumerator kUART_TxEmptyFlag: Transmit Buffer FIFO Empty.

enumerator kUART_DtrFlag: DTR edge triggered interrupt flag.

enumerator kUART_IdleFlag: Idle Condition Flag.

enumerator kUART_AutoBaudCntStopFlag: Auto-baud Counter Stopped Flag.

enumerator kUART_RiDeltaFlag: Ring Indicator Delta Flag.

enumerator kUART_RiFlag: Ring Indicator Input Flag.

enumerator kUART_IrFlag: Serial Infrared Interrupt Flag.

enumerator kUART_WakeFlag: Wake Flag.

enumerator kUART_DcdDeltaFlag: Data Carrier Detect Delta Flag.

enumerator kUART_DcdFlag: Data Carrier Detect Input Flag.

enumerator kUART_RtsFlag: RTS Edge Triggered Interrupt Flag.

enumerator kUART_TxCompleteFlag: Transmitter Complete Flag.

enumerator kUART_BreakDetectFlag: BREAK Condition Detected Flag.

enumerator kUART_RxOverrunFlag: Overrun Error Flag.

enumerator kUART_RxDataReadyFlag: Receive Data Ready Flag.

typedef enum _uart_data_bits uart_data_bits_t: UART data bits count.

typedef enum _uart_parity_mode uart_parity_mode_t: UART parity mode.

typedef enum _uart_stop_bit_count uart_stop_bit_count_t: UART stop bit count.

typedef enum _uart_9bit_detect_mode uart_9bit_detect_mode_t: UART 9bit address detect mode.

typedef enum _uart_idle_condition uart_idle_condition_t: UART idle condition detect.

typedef struct _uart_config uart_config_t: UART configuration structure.

typedef struct _uart_transfer uart_transfer_t: UART transfer structure.

typedef struct _uart_handle uart_handle_t: Forward declaration of the handle typedef.

typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData): UART transfer callback function.

typedef void (*uart_isr_t)(UART_Type *base, void *handle)

const IRQn_Type s_uartIRQ[]

uart_isr_t s_uartIsr

void *s_uartHandle[]: Pointers to uart handles for each instance.

uint32_t UART_GetInstance(UART_Type *base)

Get the UART instance from peripheral base address.

Parameters:

base – UART peripheral base address.

Returns:

UART instance.

UART_RETRY_TIMES: Retry times for waiting flag.

struct _uart_config

#include <fsl_uart.h>

UART configuration structure.

Public Members

uint32_t baudRate_Bps: UART baud rate.

uart_parity_mode_t parityMode: Parity error check mode of this module.

uart_data_bits_t dataBitsCount: Data bits count, eight (default), seven

uart_stop_bit_count_t stopBitCount: Number of stop bits in one frame.

uint8_t txFifoWatermark: TX FIFO watermark

uint8_t rxFifoWatermark: RX FIFO watermark

uint8_t rxRTSWatermark: RX RTS watermark, RX FIFO data count being larger than this triggers RTS deassertion

bool enableAutoBaudRate: Enable automatic baud rate detection

bool enableTx: Enable TX

bool enableRx: Enable RX

bool enableRxRTS: RX RTS enable

bool enableTxCTS: TX CTS enable

struct _uart_transfer

#include <fsl_uart.h>

UART transfer structure.

Public Members

size_t dataSize: The byte count to be transfer.

struct _uart_handle

#include <fsl_uart.h>

UART handle structure.

Public Members

const uint8_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize: Size of the remaining data to send.

size_t txDataSizeAll: Size of the data to send out.

uint8_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize: Size of the remaining data to receive.

size_t rxDataSizeAll: Size of the data to receive.

uint8_t *rxRingBuffer: Start address of the receiver ring buffer.

size_t rxRingBufferSize: Size of the ring buffer.

volatile uint16_t rxRingBufferHead: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail: Index for the user to get data from the ring buffer.

uart_transfer_callback_t callback: Callback function.

void *userData: UART callback function parameter.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

union __unnamed9__

Public Members

uint8_t *data: The buffer of data to be transfer.

uint8_t *rxData: The buffer to receive data.

const uint8_t *txData: The buffer of data to be sent.

UART FreeRTOS Driver#

WDOG: Watchdog Timer Driver#

void WDOG_GetDefaultConfig(wdog_config_t *config)

Initializes the WDOG configuration structure.

This function initializes the WDOG configuration structure to default values. The default values are as follows.

wdogConfig->enableWdog = true;
wdogConfig->workMode.enableWait = true;
wdogConfig->workMode.enableStop = true;
wdogConfig->workMode.enableDebug = true;
wdogConfig->enableInterrupt = false;
wdogConfig->enablePowerdown = false;
wdogConfig->resetExtension = flase;
wdogConfig->timeoutValue = 0xFFU;
wdogConfig->interruptTimeValue = 0x04u;
wdogConfig->enableTimeOutAssert = false;