MCXL255

ADVC

enum _advc_result

The enumeration of ADVC operation result.

Values:

enumerator kADVC_Stat_Ok

ADVC Run Well.

enumerator kADVC_Stat_Init

ADVC is initialized.

enumerator kADVC_Stat_SafeDoneFailed

Fail to set ADVC as safe mode.

enumerator kADVC_Stat_Timeout

ADVC status done condition was not set before timeout

enumerator kADVC_Stat_RingoMeasureFailed

Fail to measure ringo.

enumerator kADVC_Stat_FFMeasureFailed

First fail measurement failed.

enumerator kADVC_Stat_OptimalFailed

ADVC set optimal ended with error.

enumerator kADVC_Stat_BadSignature

Wrong ADVC table.

enumerator kADVC_Stat_NotEnabled

when trying to manipulate advc frequencies before it’s enabled.

enumerator kADVC_Stat_PreVoltageReqestFailed

when pre-voltage request change is reaching timeout.

enumerator kADVC_Stat_IllegalOperation

When using illegal operation mode in ADVC_ENABLE.

enumerator kADVC_Stat_IllegalClockConfiguration

CGU clock is not configured to be any of supported frequencies.

enum _advc_mode

The enumeration of ADVC mode.

Values:

enumerator kADVC_ModeSafe

Set ADVC work as safe mode.

enumerator kADVC_ModeOptimal

Set ADVC work as optimal mode.

typedef enum _advc_result advc_result_t

The enumeration of ADVC operation result.

typedef enum _advc_mode advc_mode_t

The enumeration of ADVC mode.

bool ADVC_IsInitialized(void)

Check if ADVC is initialized.

Return values:

• false – ADVC is not initialized.

• true – ADVC is initialized.

advc_result_t ADVC_Enable(advc_mode_t mode, uint8_t *vddCode)

Enable ADVC.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

Parameters:

• mode – [in] Specify the mode of advc, please refer to advc_mode_t.

• vddCode – [out] The value of VDD_AON, NULL means do not care voltage of VDD_AON.

Returns:

The result outcome with enabling ADVC.

bool ADVC_IsEnabled(void)

Check if ADVC is enabled.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

Return values:

• false – ADVC is not enabled.

• true – ADVC is enabled.

void ADVC_Disable(void)

Disable ADVC.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

bool ADVC_IsDisabled(void)

Check if ADVC is disabled.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

Return values:

• true – ADVC is not disabled.

• false – ADVC is enabled.

advc_result_t ADVC_PreVoltageChangeRequest(uint32_t aonCpuFreq)

Request to change frequency.

Note

This should be done every time we want to change frequency of any ADVC related clock.

Note

Pre Voltage request should be called before any clock change which is derived from CGU. The paramter we pass is the the future cpu frequency, since we move to safe voltage according to that.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

Parameters:

• aonCpuFreq – The frequency of AON CPU, only 10MHz, 5MHz, 3.3MHz, 3MHz, 2.5MHz, 2.5MHz, 1.5MHz, 0.75MHz, 32768 are allowed.

Returns:

The result outcome with requesting to change frequency.

advc_result_t ADVC_PostVoltageChangeRequest(void)

Post voltage change request with Non-blocking.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

Returns:

The observed result following the post-frequency change.

advc_result_t ADVC_PostVoltageChangeRequestBlocking(void)

Post voltage change request with blocking until the change is done.

Note

This function checks if SysTick is enabled. If not, it temporarily enables SysTick and disables it before exiting.

Returns:

The result outcome with requesting to change frequency and waiting for completion.

FSL_ADVC_DRIVER_VERSION

advc driver version 2.1.0.

ADVC Driver

AOI: Crossbar AND/OR/INVERT Driver

void AOI_Init(AOI_Type *base)

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

• base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

• base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

• base – AOI peripheral address.

• event – Index of the event which will be set of type aoi_event_t.

• config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

• base – AOI peripheral address.

• event – Event which will be configured of type aoi_event_t.

• eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION

Version 2.0.2.

enum _aoi_input_config

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero

Forces the input to logical zero.

enumerator kAOI_InputSignal

Passes the input signal.

enumerator kAOI_InvInputSignal

Inverts the input signal.

enumerator kAOI_LogicOne

Forces the input to logical one.

enum _aoi_event

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0

Event 0 index

enumerator kAOI_Event1

Event 1 index

enumerator kAOI_Event2

Event 2 index

enumerator kAOI_Event3

Event 3 index

typedef enum _aoi_input_config aoi_input_config_t

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI

AOI peripheral address

struct _aoi_event_config

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC

Product term 0 input A

aoi_input_config_t PT0BC

Product term 0 input B

aoi_input_config_t PT0CC

Product term 0 input C

aoi_input_config_t PT0DC

Product term 0 input D

aoi_input_config_t PT1AC

Product term 1 input A

aoi_input_config_t PT1BC

Product term 1 input B

aoi_input_config_t PT1CC

Product term 1 input C

aoi_input_config_t PT1DC

Product term 1 input D

aoi_input_config_t PT2AC

Product term 2 input A

aoi_input_config_t PT2BC

Product term 2 input B

aoi_input_config_t PT2CC

Product term 2 input C

aoi_input_config_t PT2DC

Product term 2 input D

aoi_input_config_t PT3AC

Product term 3 input A

aoi_input_config_t PT3BC

Product term 3 input B

aoi_input_config_t PT3CC

Product term 3 input C

aoi_input_config_t PT3DC

Product term 3 input D

AON_LPADC: 12-bit single-ended SAR Analog-to-Digital Converter Driver

void ADC_GetDefaultConfig(adc_config_t *config)

Gets an available pre-defined settings for ADC configuration.

Parameters:

• config – Pointer to ADC configuration structure, adc_config_t.

void ADC_Init(LPADC_Type *base, const adc_config_t *config)

Initializes the ADC module.

Parameters:

• base – ADC peripheral base address.

• config – Pointer to configuration structure, adc_config_t.

void ADC_Deinit(LPADC_Type *base)

De-initializes the ADC module.

Parameters:

• base – ADC peripheral base address.

static inline void ADC_Enable(LPADC_Type *base, bool enable)

Enable/disable the ADC module.

Parameters:

• base – ADC peripheral base address.

• enable – Indicates whether to enable the ADC module. - true Enable the ADC module. - false Disable the ADC module.

static inline void ADC_DoFifoRst(LPADC_Type *base, adc_fifo_index_t index)

Reset ADC FIFO.

Parameters:

• base – ADC peripheral base address.

• index – ADC FIFO index, adc_fifo_index_t

static inline void ADC_DoSoftWareRst(LPADC_Type *base)

Software reset ADC module.

Parameters:

• base – ADC peripheral base address.

static inline uint32_t ADC_GetStatusFlags(LPADC_Type *base)

Get ADC status flags.

Parameters:

• base – ADC peripheral base address.

Returns:

Mask value for ADC status flags to be got, should be the OR’ed value of _adc_status_flags.

static inline void ADC_ClearStatusFlags(LPADC_Type *base, uint32_t mask)

Clear ADC status flags.

Note

Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.

Parameters:

• base – ADC peripheral base address.

• mask – Mask value for ADC status flags to be cleared, should be the OR’ed value of _adc_status_flags.

static inline uint32_t ADC_GetTriggerStatusFlags(LPADC_Type *base)

Get ADC trigger status flags.

Parameters:

• base – ADC peripheral base address.

Returns:

Mask value for ADC trigger status flags to be got, should be the OR’ed value of _adc_trig_status_flags.

static inline void ADC_ClearTriggerStatusFlags(LPADC_Type *base, uint32_t mask)

Clear ADC trigger status flags.

Parameters:

• base – ADC peripheral base address.

• mask – Mask value for ADC trigger status flags to be cleared, should be the OR’ed value of _adc_trig_status_flags.

static inline void ADC_EnableInt(LPADC_Type *base, uint32_t mask)

Enable interrupts.

Parameters:

• base – ADC peripheral base address.

• mask – Mask value for interrupt events to be enabled, should be the OR’ed value of _adc_int_en.

static inline void ADC_DisableInt(LPADC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – ADC peripheral base address.

• mask – Mask value for interrupt events to be disabled, should be the OR’ed value of _adc_int_en.

static inline void ADC_EnableFifoWatermarkDma(LPADC_Type *base, adc_fifo_index_t index, bool enable)

Enable/disable the specified ADC FIFO watermark DAM transfer.

Parameters:

• base – ADC peripheral base address.

• index – ADC FIFO index, adc_fifo_index_t

• enable – Indicates whether to enable the specified ADC FIFO watermark DAM transfer. true Enable the specified ADC FIFO watermark DMA transfer. false Disable the specified ADC FIFO watermark DMA transfer.

void ADC_GetDefaultTrigConfig(adc_trig_config_t *config)

Gets an available pre-defined settings for ADC trigger’s configuration.

Parameters:

• config – Pointer to ADC trigger configuration structure, adc_trig_config_t.

void ADC_SetTrigConfig(LPADC_Type *base, adc_trig_index_t index, const adc_trig_config_t *config)

Configure the ADC trigger source.

Parameters:

• base – ADC peripheral base address.

• index – ADC trigger index, adc_trig_index_t.

• config – Pointer to ADC trigger configuration structure, adc_trig_config_t.

static inline void ADC_DoSoftwareTrig(LPADC_Type *base, adc_trig_index_t index)

Do software trigger.

Parameters:

• base – ADC peripheral base address.

• index – ADC trigger index, adc_trig_index_t.

static inline uint32_t ADC_GetResFifoCnt(LPADC_Type *base, adc_fifo_index_t index)

Get the count of result kept in specified ADC conversion result FIFO.

Parameters:

• base – ADC peripheral base address.

• index – ADC FIFO index, adc_fifo_index_t

Returns:

The count of result kept in specified ADC conversion result FIFO.

bool ADC_GetConvRes(LPADC_Type *base, adc_conv_res_t *result, adc_fifo_index_t index)

Get the result in specified conversion FIFO.

Parameters:

• base – ADC peripheral base address.

• result – Pointer to ADC result structure, adc_conv_res_t.

• index – ADC FIFO index, adc_fifo_index_t

Returns:

Status whether FIFO entry is valid. - true Conversion FIFO result is valid. - false Conversion FIFO result is invalid.

void ADC_GetDefaultCmdConfig(adc_cmd_config_t *config)

Gets an available pre-defined settings for ADC command’s configuration.

Parameters:

• config – Pointer to ADC command configuration structure, adc_cmd_config_t.

void ADC_SetCmdConfig(LPADC_Type *base, adc_cmd_index_t index, const adc_cmd_config_t *config)

Do ADC command configuration.

Parameters:

• base – ADC peripheral base address.

• index – ADC command index, adc_cmd_index_t.

• config – Pointer to ADC commad configuration structure, adc_cmd_config_t.

static inline void ADC_SetOffsetTrimVal(LPADC_Type *base, uint8_t value)

Set trim value for offset.

Parameters:

• base – ADC peripheral base address.

• value – 8-bit unsigned value that should be limited to values between 0h to A0h, with a nominal value of 50h.

static inline void ADC_GetOffsetTrimVal(LPADC_Type *base, uint8_t *pValue)

Get trim value of offset.

Parameters:

• base – ADC peripheral base address.

• pValue – Pointer to the variable in type of uint8_t to store offset value.

void ADC_DoOffsetCal(LPADC_Type *base)

Do offset calibration.

Parameters:

• base – ADC peripheral base address.

FSL_AON_LPADC_DRIVER_VERSION

AON_LPADC driver version 2.0.1.

enum _adc_status_flags

ADC status flags enumeration.

Values:

enumerator kADC_ResFifo0RdyFlag

Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level.

enumerator kADC_ResFifo0OverflowFlag

Indicates that more data has been written to the result FIFO 0 than it can hold.

enumerator kADC_ResFifo1RdyFlag

Indicates when the number of valid datawords in the result FIFO 1 is greater than the setting watermark level.

enumerator kADC_ResFifo1OverflowFlag

Indicates that more data has been written to the result FIFO 1 than it can hold.

enumerator kADC_TrigExcFlag

Indicates that a high priority trigger exception event has occurred.

enumerator kADC_TrigCompFlag

Indicates that a trigger sequence has occurred.

enumerator kADC_CalRdyFlag

Indicates that the calibration process is done.

enumerator kADC_ActFlag

Indicates that the ADC is in active state.

enumerator kADC_TrigAct

Indicates that the trigger is actively being processed.

enumerator kADC_CmdAct

Indicates that the command is actively being processed.

enum _adc_trig_status_flags

ADC trigger status flags enumeration.

Values:

enumerator kADC_Trig0IntFlag

Indicates trigger 0 is interrupted by a high priority exception.

enumerator kADC_Trig1IntFlag

Indicates trigger 1 is interrupted by a high priority exception.

enumerator kADC_Trig2IntFlag

Indicates trigger 2 is interrupted by a high priority exception.

enumerator kADC_Trig3IntFlag

Indicates trigger 3 is interrupted by a high priority exception.

enumerator kADC_Trig0CompFlag

Indicates trigger 0 is completed and trigger 0 has enabled completion interrupts.

enumerator kADC_Trig1CompFlag

Indicates trigger 1 is completed and trigger 1 has enabled completion interrupts.

enumerator kADC_Trig2CompFlag

Indicates trigger 2 is completed and trigger 2 has enabled completion interrupts.

enumerator kADC_Trig3CompFlag

Indicates trigger 3 is completed and trigger 3 has enabled completion interrupts.

enum _adc_int_en

ADC interrupt enablement mask enumeration.

Values:

enumerator kADC_ResFifo0WatermarkIntEn

Configures ADC to generate overflow interrupt requests when FIFO0 ready flag is asserted.

enumerator kADC_ResFifo0OverflowIntEn

Configures ADC to generate overflow interrupt requests when FIFO0 overflow flag is asserted.

enumerator kADC_ResFifo1WatermarkIntEn

Configures ADC to generate overflow interrupt requests when FIFO1 ready flag is asserted.

enumerator kADC_ResFifo1OverflowIntEn

Configures ADC to generate overflow interrupt requests when FIFO1 overflow flag is asserted.

enumerator kADC_TrigExcIntEn

Configures ADC to generate trigger exception interrupt.

enumerator kADC_Trig0CompIntEn

Configures ADC to generate interrupt when trigger 0 completion.

enumerator kADC_Trig1CompIntEn

Configures ADC to generate interrupt when trigger 1 completion.

enumerator kADC_Trig2CompIntEn

Configures ADC to generate interrupt when trigger 2 completion.

enumerator kADC_Trig3CompIntEn

Configures ADC to generate interrupt when trigger 3 completion.

enum _adc_cal_conv_avg

ADC calibration conversion averages enumeration.

Values:

enumerator kADC_CalConvAvg0

Single conversion.

enumerator kADC_CalConvAvg2

2 conversions averaged.

enumerator kADC_CalConvAvg4

4 conversions averaged.

enumerator kADC_CalConvAvg8

8 conversions averaged.

enumerator kADC_CalConvAvg16

16 conversions averaged.

enumerator kADC_CalConvAvg32

32 conversions averaged.

enumerator kADC_CalConvAvg64

64 conversions averaged.

enumerator kADC_CalConvAvg128

128 conversions averaged.

enumerator kADC_CalConvAvg256

256 conversions averaged.

enumerator kADC_CalConvAvg512

512 conversions averaged.

enumerator kADC_CalConvAvg1024

1024 conversions averaged.

enum _adc_cal_conv_sample_time

ADC calibration conversion sample time enumeration.

Values:

enumerator kADC_CalConvSampTime_AdckCycle0

1 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle1

2 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle2

3 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle3

4 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle4

5 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle5

6 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle6

7 ADCK cycles sample time.

enumerator kADC_CalConvSampTime_AdckCycle7

8 ADCK cycles sample time.

enum _adc_fifo_index

ADC FIFO enumeration.

Values:

enumerator kADC_Fifo0

FIFO 0.

enumerator kADC_Fifo1

FIFO 1.

enum _adc_trig_index

ADC trigger enumeration.

Values:

enumerator kADC_Trig0

Trigger 0.

enumerator kADC_Trig1

Trigger 1.

enumerator kADC_Trig2

Trigger 2.

enumerator kADC_Trig3

Trigger 3.

enum _adc_trig_cmd_index

ADC trigger command enumeration.

Values:

enumerator kADC_CmdNone

Not a valid selection from the command buffer, trigger event is ignored.

enumerator kADC_Cmd1

Trigger commad 1.

enumerator kADC_Cmd2

Trigger commad 2.

enumerator kADC_Cmd3

Trigger commad 3.

enumerator kADC_Cmd4

Trigger commad 4.

enumerator kADC_Cmd5

Trigger commad 5.

enumerator kADC_Cmd6

Trigger commad 6.

enumerator kADC_Cmd7

Trigger commad 7.

enum _adc_conv_avg

ADC hardware conversion averages enumeration.

Values:

enumerator kADC_ConvAvg1

Single conversion.

enumerator kADC_ConvAvg2

2 conversions averaged.

enumerator kADC_ConvAvg4

4 conversions averaged.

enumerator kADC_ConvAvg8

8 conversions averaged.

enumerator kADC_ConvAvg16

16 conversions averaged.

enumerator kADC_ConvAvg32

32 conversions averaged.

enumerator kADC_ConvAvg64

64 conversions averaged.

enumerator kADC_ConvAvg128

128 conversions averaged.

enumerator kADC_ConvAvg256

256 conversions averaged.

enumerator kADC_ConvAvg512

512 conversions averaged.

enumerator kADC_ConvAvg1024

1024 conversions averaged.

enum _adc_sample_time

ADC conversion sample time enumeration.

Values:

enumerator kADC_ConvSampleTime_AdcCycle1

1 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle2

2 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle3

3 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle4

4 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle5

5 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle6

6 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle7

7 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle8

8 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle10

10 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle12

12 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle16

16 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle24

24 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle40

40 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle72

72 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle136

136 ADCK cycles.

enumerator kADC_ConvSampleTime_AdcCycle264

264 ADCK cycles.

enum _adc_comp_mode

ADC hardware compare mode enumeration.

Note

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

Values:

enumerator kADC_CompareDisabled

Compare disabled.

enumerator kADC_CompareStoreOnTrue

Compare enabled. Store on true.

enumerator kADC_CompareRepeatUntilTrue

Compare enabled. Repeat channel acquisition until true.

enum _adc_ref_voltage_src

ADC reference voltage source enumeration.

Values:

enumerator kADC_RefVoltageAlt1

Option 1 setting.

enumerator kADC_RefVoltageAlt2

Option 2 setting.

enum _adc_dac_settle_delay

ADC DAC settle time enumeration.

Values:

enumerator kADC_FastDacSettleTime

Fastest settling

enumerator kADC_SlowDacSettleTime

Slowest settling

enum _adc_trig_priority_policy

ADC trigger priority exception handle policy enumeration.

Values:

enumerator kADC_ConvPreemptImmedNotAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion is not automatically resumed or restarted.

enumerator kADC_ConvPreemptSoftlyNotAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion is not resumed or restarted.

enumerator kADC_ConvPreemptImmedAutoRestarted

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kADC_ConvPreemptSoftlyAutoRestarted

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kADC_ConvPreemptImmedAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be resumed.

enumerator kADC_ConvPreemptSoftlyAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will be automatically be resumed.

enumerator kADC_ConvPreemptSubsequentlyNotAutoResumed

If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger, when higher priority conversion finishes, the preempted conversion will not automatically be restarted or resumed.

enumerator kADC_ConvPreemptSubsequentlyAutoRestarted

If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger, when higher priority conversion finishes, the preempted conversion will be automatically restarted.

enumerator kADC_ConvPreemptSubsequentlyAutoResumed

If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger, when higher priority conversion finishes, the preempted conversion will be automatically resumed.

enumerator kADC_TriggerPriorityExceptionDisabled

High priority trigger exception disabled.

typedef enum _adc_cal_conv_avg adc_cal_conv_avg_t

ADC calibration conversion averages enumeration.

typedef enum _adc_cal_conv_sample_time adc_cal_conv_sample_time_t

ADC calibration conversion sample time enumeration.

typedef enum _adc_fifo_index adc_fifo_index_t

ADC FIFO enumeration.

typedef enum _adc_trig_index adc_trig_index_t

ADC trigger enumeration.

typedef enum _adc_trig_cmd_index adc_cmd_index_t

ADC trigger command enumeration.

typedef enum _adc_conv_avg adc_conv_avg_t

ADC hardware conversion averages enumeration.

typedef enum _adc_sample_time adc_conv_sample_time_t

ADC conversion sample time enumeration.

typedef enum _adc_comp_mode adc_comp_mode_t

ADC hardware compare mode enumeration.

Note

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

typedef enum _adc_ref_voltage_src adc_ref_voltage_src_t

ADC reference voltage source enumeration.

typedef enum _adc_dac_settle_delay adc_dac_settle_delay_t

ADC DAC settle time enumeration.

typedef enum _adc_trig_priority_policy adc_trig_priority_policy_t

ADC trigger priority exception handle policy enumeration.

typedef struct _adc_conv_res adc_conv_res_t

ADC conversion result structure.

typedef struct _adc_trig_config adc_trig_config_t

ADC trigger configuration structure.

typedef struct _adc_cmd_config adc_cmd_config_t

ADC command configuration structure.

typedef struct _adc_config adc_config_t

ADC configuration structure.

ADC_TRIG_PRIORITY_EXC_HANDLE_POLICY_EN(tprictrl, tres, tcmdres, hpted)

Trigger priority exception handle policy helper macro.

tprictrl: ADC Trigger Priority Control. 00b - If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. 01b - If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. 10b - If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger.

tres: Trigger Resume Enable. 0b - Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. 1b - Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.

tcmdres: Trigger Command Resume, tres must be asserted for tcmdres to be used. 0b - Trigger sequences interrupted by a high priority trigger exception is automatically restarted. 1b - Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.

hpted: High Priority Trigger Exception Disable 0b - High priority trigger exceptions are enabled. 1b - High priority trigger exceptions are disabled.

ADC_TRIG_PRIORITY_EXC_HANDLE_POLICY_DE(policy)

struct _adc_conv_res

#include <fsl_aon_lpadc.h>

ADC conversion result structure.

Public Members

uint8_t trigSrc

Indicate the trigger source that initiated a conversion and generated this result.

uint8_t cmdSrc

Indicate the command buffer being executed that generated this result.

uint8_t loopCnt

Indicate the loop count value during command execution that generated this result.

uint16_t convVal

ADC conversion result.

struct _adc_trig_config

#include <fsl_aon_lpadc.h>

ADC trigger configuration structure.

Public Members

bool trigEn

Controls hardware trigger source to initiate conversion on the rising edge of the input trigger source.

uint8_t trigDelay

Sets the trigger delay duration to wait at the start of servicing a trigger event.

uint8_t trigPriority

Sets the priority of the associated trigger source.

adc_fifo_index_t resFifo

Selects the FIFO to store the conversion result.

adc_cmd_index_t cmdIndex

Selects the trigger command from command buffer to execute upon detect of the associated trigger event.

struct _adc_cmd_config

#include <fsl_aon_lpadc.h>

ADC command configuration structure.

Public Members

bool waitTrigEn

Controls whether commands are automatically executed or a trigger must be received before execution.

bool autoChanIncEn

Controls whether enable automatic channel incrementing.

uint8_t loopCnt

Sets how many times this command executes (and stores conversion result to RESFIFO) before finish and transition to the next command or Idle state.

uint8_t chanIndex

Sets conversion channel.

uint16_t compValLow

Sets compare low value.

uint16_t compValHigh

Sets compare high value.

adc_conv_avg_t convAvg

Selects hardware average value.

adc_comp_mode_t compMode

Selects hardware compare mode.

adc_cmd_index_t nextCmdIndex

Selects the next command to execute after this command completes.

adc_conv_sample_time_t convSampleTime

Selects sample time value.

struct _adc_config

#include <fsl_aon_lpadc.h>

ADC configuration structure.

Public Members

bool dozeModeEn

Controls system transition to low power modes while ADC is converting.

bool convPauseEn

Controls whether to enable the ADC pause function.

bool dynamicEleMatchEn

Controls whether to enable dynamic element match.

uint8_t compTime

Sets a configurable number of ADCK cycles to complete the compare phase of a conversion.

uint8_t convPauseDelay

Sets the duration of pausing during command execution sequencing.

uint8_t fifo0Watermark

Sets FIFO 0 watermark value.

adc_cal_conv_avg_t calConvAvg

Selects calibration conversion averages.

adc_ref_voltage_src_t refVoltageSrc

Selects the reference voltage source.

adc_dac_settle_delay_t dacSettleTime

Selects DAC settle delay.

adc_cal_conv_sample_time_t calConvSampTime

Selects calibration conversion sample time.

adc_trig_priority_policy_t trigPriorityPolicy

Selects trigger priority exception handle policy.

CDOG

status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)

Initialize CDOG.

This function initializes CDOG block and setting.

Parameters:

• base – CDOG peripheral base address

• conf – CDOG configuration structure

Returns:

Status of the init operation

void CDOG_Deinit(CDOG_Type *base)

Deinitialize CDOG.

This function deinitializes CDOG secure counter.

Parameters:

• base – CDOG peripheral base address

void CDOG_GetDefaultConfig(cdog_config_t *conf)

Sets the default configuration of CDOG.

This function initialize CDOG config structure to default values.

Parameters:

• conf – CDOG configuration structure

void CDOG_Stop(CDOG_Type *base, uint32_t stop)

Stops secure counter and instruction timer.

This function stops instruction timer and secure counter. This also change state od CDOG to IDLE.

Parameters:

• base – CDOG peripheral base address

• stop – expected value which will be compared with value of secure counter

void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)

Sets secure counter and instruction timer values.

This function sets value in RELOAD and START registers for instruction timer and secure counter

Parameters:

• base – CDOG peripheral base address

• reload – reload value

• start – start value

void CDOG_Check(CDOG_Type *base, uint32_t check)

Checks secure counter.

This function compares stop value in handler with secure counter value by writting to RELOAD refister.

Parameters:

• base – CDOG peripheral base address

• check – expected (stop) value

void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)

Sets secure counter and instruction timer values.

This function sets value in STOP, RELOAD and START registers for instruction timer and secure counter.

Parameters:

• base – CDOG peripheral base address

• stop – expected value which will be compared with value of secure counter

• reload – reload value for instruction timer

• start – start value for secure timer

void CDOG_Add(CDOG_Type *base, uint32_t add)

Add value to secure counter.

This function add specified value to secure counter.

Parameters:

• base – CDOG peripheral base address.

• add – Value to be added.

void CDOG_Add1(CDOG_Type *base)

Add 1 to secure counter.

This function add 1 to secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Add16(CDOG_Type *base)

Add 16 to secure counter.

This function add 16 to secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Add256(CDOG_Type *base)

Add 256 to secure counter.

This function add 256 to secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Sub(CDOG_Type *base, uint32_t sub)

brief Substract value to secure counter

This function substract specified value to secure counter.

param base CDOG peripheral base address. param sub Value to be substracted.

void CDOG_Sub1(CDOG_Type *base)

Substract 1 from secure counter.

This function substract specified 1 from secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Sub16(CDOG_Type *base)

Substract 16 from secure counter.

This function substract specified 16 from secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_Sub256(CDOG_Type *base)

Substract 256 from secure counter.

This function substract specified 256 from secure counter.

Parameters:

• base – CDOG peripheral base address.

void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)

Set the CDOG persistent word.

Parameters:

• base – CDOG peripheral base address.

• value – The value to be written.

uint32_t CDOG_ReadPersistent(CDOG_Type *base)

Get the CDOG persistent word.

Parameters:

• base – CDOG peripheral base address.

Returns:

The persistent word.

FSL_CDOG_DRIVER_VERSION

Defines CDOG driver version 2.1.3.

Change log:

• Version 2.1.3

  • Re-design multiple instance IRQs and Clocks

  • Add fix for RESTART command errata

• Version 2.1.2

  • Support multiple IRQs

  • Fix default CONTROL values

• Version 2.1.1

  • Remove bit CONTROL[CONTROL_CTRL]

• Version 2.1.0

  • Rename CWT to CDOG

• Version 2.0.2

  • Fix MISRA-2012 issues

• Version 2.0.1

  • Fix doxygen issues

• Version 2.0.0

  • initial version

enum __cdog_debug_Action_ctrl_enum

Values:

enumerator kCDOG_DebugHaltCtrl_Run

enumerator kCDOG_DebugHaltCtrl_Pause

enum __cdog_irq_pause_ctrl_enum

Values:

enumerator kCDOG_IrqPauseCtrl_Run

enumerator kCDOG_IrqPauseCtrl_Pause

enum __cdog_fault_ctrl_enum

Values:

enumerator kCDOG_FaultCtrl_EnableReset

enumerator kCDOG_FaultCtrl_EnableInterrupt

enumerator kCDOG_FaultCtrl_NoAction

enum __code_lock_ctrl_enum

Values:

enumerator kCDOG_LockCtrl_Lock

enumerator kCDOG_LockCtrl_Unlock

typedef uint32_t secure_counter_t

SC_ADD(add)

SC_ADD1

SC_ADD16

SC_ADD256

SC_SUB(sub)

SC_SUB1

SC_SUB16

SC_SUB256

SC_CHECK(val)

struct cdog_config_t

Clock Driver

enum _clock_ip_name

Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

Values:

enumerator kCLOCK_GateAonUART

Clock gate name: AON UART

enumerator kCLOCK_GateAonI2C

Clock gate name: AON I2C

enumerator kCLOCK_GateAonAPB

Clock gate name: AON APB

enumerator kCLOCK_GateAonPORT

Clock gate name: AON PORT

enumerator kCLOCK_GateAonGPIO

Clock gate name: AON GPIO

enumerator kCLOCK_GateAonQTMR0

Clock gate name: AON QTMR0

enumerator kCLOCK_GateAonLPTMR

Clock gate name: AON LPTMR

enumerator kCLOCK_GateAonKPP

Clock gate name: AON KPP

enumerator kCLOCK_GateAonLPADC

Clock gate name: AON LPADC

enumerator kCLOCK_GateAonSYS

Clock gate name: AON SYS (tick)

enumerator kCLOCK_GateAonLPACMP

Clock gate name: AON LPACMP

enumerator kCLOCK_GateAonLCD

Clock gate name: AON LCD

enumerator kCLOCK_GateAonADVC2P0

Clock gate name: AON ADVC2P0

enumerator kCLOCK_GateAonINPUTMUX1

Clock gate name: AON INPUTMUX

enumerator kCLOCK_GateXTAL32Clk

Clock gate name: XTAL32K clock

enumerator kCLOCK_GateAonRootAux

Clock gate name: AON Root Aux CLK

enumerator kCLOCK_GateXTAL32Out

Clock gate name: XTAL32K[1] Output Enable

enumerator kCLOCK_GateXTAL32ToCGU

Clock gate name: XTAL32K Enable towards CGU

enumerator kCLOCK_GateNotAvail

Clock gate name: None

enum _clock_name

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_RtcOscClk

RTC OSC clock.

enumerator kCLOCK_Fro16k

AON PAC and SMM clock.

enumerator kCLOCK_FroAON

AON free running clock.

enum _clock_select_name

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_SelAonROOT_AUX

AON ROOT_AUX clock selection

enumerator kCLOCK_SelAonROOT

AON ROOT clock selection

enumerator kCLOCK_SelAonLCD

AON LCD clock selection

enumerator kCLOCK_SelAonLPADC

AON LPADC clock selection

enumerator kCLOCK_SelAonSYSTICK

AON SYS tick clock selection

enumerator kCLOCK_SelAonKPP

AON KPP clock selection

enumerator kCLOCK_SelAonLPTMR

AON LPTMR GRP clock selection

enumerator kCLOCK_SelAonTMR

AON TMR GRP clock selection

enumerator kCLOCK_SelAonCOM

AON COM comaprator (aon_per_clk) clock selection

enum _clock_attach_id

The enumerator of clock attach Id.

Values:

enumerator kXTAL32K_to_AON_ROOT_AUX

Attach XTAL32K to AON AUX.

enumerator kAUX_to_AON_ROOT_AUX

Attach AUX to AON AUX.

enumerator kFROdiv1_to_AON_CPU

Attach FRO div 1 to AON_CPU.

enumerator kFROdiv2_to_AON_CPU

Attach FRO div 2 to AON_CPU.

enumerator kFROdiv4_to_AON_CPU

Attach FRO div 4 to AON_CPU.

enumerator kROOT_AUX_to_AON_CPU

Attach ROOT AUX to AON_CPU.

Attach XTAL32K to AON_CPU including control of kCLOCK_SelAonROOT_AUX mux.

enumerator kXTAL32K_to_AON_CPU

Attach AON_AUX to AON_CPU including control of kCLOCK_SelAonROOT_AUX mux.

enumerator kAUX_to_AON_CPU

enumerator kCLK_16K_to_AON_LCD

Attach FRO clk_16k to AON LCD.

enumerator kFRO16K_to_AON_LCD

Attach FRO fro16k to AON LCD.

enumerator kFROdiv1_to_AON_LPADC

Attach FRO div 1 to AON LPADC.

enumerator kFROdiv2_to_AON_LPADC

Attach FRO div 2 to AON LPADC.

enumerator kFROdiv4_to_AON_LPADC

Attach FRO div 4 to AON LPADC.

enumerator kROOT_AUX_to_AON_LPADC

Attach ROOT AUX to AON LPADC.

enumerator kXTAL32K_to_AON_LPADC

Attach FRO RTC to AON LPADC.

enumerator kFRO16K_to_AON_LPADC

Attach FRO fro16k to AON LPADC.

enumerator kFROdiv1_to_AON_SYSTICK

Attach FRO div 1 to AON SYSTICK.

enumerator kFROdiv2_to_AON_SYSTICK

Attach FRO div 2 to AON SYSTICK.

enumerator kFROdiv4_to_AON_SYSTICK

Attach FRO div 4 to AON SYSTICK.

enumerator kROOT_AUX_to_AON_SYSTICK

Attach ROOT AUX to AON SYSTICK.

enumerator kXTAL32K_to_AON_KPP

Attach XTAL32K to AON KPP.

enumerator kFRO16K_to_AON_KPP

Attach FRO fro16k to AON KPP.

enumerator AON_TMR_to_AON_LPTMR

Attach AON TIMER CLK to AON LPTMR GRP.

enumerator kFRO16K_to_AON_LPTMR

Attach FRO16K to AON LPTMR GRP.

enumerator kCLK_16K_to_AON_LPTMR

Attach CLK_16K to AON LPTMR GRP.

enumerator kFROdiv1_to_AON_TMR

Attach FRO div 1 to AON TMR GRP.

enumerator kFROdiv2_to_AON_TMR

Attach FRO div 2 to AON TMR GRP.

enumerator kFROdiv4_to_AON_TMR

Attach FRO div 4 to AON TMR GRP.

enumerator kROOT_AUX_to_AON_TMR

Attach ROOT AUX to AON TMR GRP.

enumerator kFROdiv1_to_AON_COM

Attach FRO div 1 to AON COM GRP.

enumerator kFROdiv2_to_AON_COM

Attach FRO div 2 to AON COM GRP.

enumerator kFROdiv4_to_AON_COM

Attach FRO div 4 to AON COM GRP.

enumerator kROOT_AUX_to_AON_COM

Attach ROOT AUX to AON COM GRP.

enumerator kNONE_to_NONE

Attach NONE to NONE.

enum _clock_div_name

Clock dividers.

Values:

enumerator kCLOCK_DIVAonCPU

Aon CPU clock divider

enumerator kCLOCK_DIVAonCMP

Aon Comp grp clock divider

enumerator kCLOCK_DIVAonSYS

Aon SYSTICK clock divider

enumerator kCLOCK_DivMax

MAX clock divider

enum _aon_fro_autotrim_config_t

AON FRO autotrim configuration.

Values:

enumerator kCLOCK_AonFro3M

ULPIRC target is 3MHz.

enumerator kCLOCK_AonFro10M

LPIRC target is 10MHz.

typedef enum _clock_ip_name clock_ip_name_t

Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

typedef enum _clock_name clock_name_t

Clock name used to get clock frequency.

typedef enum _clock_select_name clock_select_name_t

Clock name used to get clock frequency.

typedef enum _clock_attach_id clock_attach_id_t

The enumerator of clock attach Id.

typedef enum _clock_div_name clock_div_name_t

Clock dividers.

typedef struct _aon_fro_trim_config aon_fro_trim_config_t

AON FRO trim configuration.

typedef struct _xtal_drive_param xtal_drive_param_t

XTAL drive parameter structure containing dly_cap_sox, amp and gm values.

typedef struct _rosc_init_config rosc_init_config_t

ROSC initialization configuration structure.

typedef enum _aon_fro_autotrim_config_t aon_fro_autotrim_config_t

AON FRO autotrim configuration.

void CLOCK_EnableClock(clock_ip_name_t clk)

Enable the clock for specific IP.

Parameters:

• clk – : Clock to be enabled.

Returns:

Nothing

void CLOCK_DisableClock(clock_ip_name_t clk)

Disable the clock for specific IP.

Parameters:

• clk – : Clock to be Disabled.

Returns:

Nothing

void CLOCK_AttachClk(clock_attach_id_t connection)

Configure the clock selection muxes.

Parameters:

• connection – : Clock to be configured.

Returns:

Nothing

clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection)

Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id.

Parameters:

• connection – : Clock attach id to get.

Returns:

Clock source value.

void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value)

Set the clock select value. This fuction set the peripheral clock select value.

Parameters:

• sel_name – : Clock select.

• value – : value to be set.

uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name)

Get the clock select value. This fuction get the peripheral clock select value.

Parameters:

• sel_name – : Clock select.

Returns:

Clock source value.

void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value)

Setup peripheral clock dividers.

Parameters:

• div_name – : Clock divider name

• value – : Value to be divided

Returns:

Nothing

uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name)

Get peripheral clock dividers.

Parameters:

• div_name – : Clock divider name

Returns:

peripheral clock dividers

void CLOCK_HaltClockDiv(clock_div_name_t div_name)

Halt peripheral clock dividers.

Parameters:

• div_name – : Clock divider name

Returns:

Nothing

status_t CLOCK_SetupFROAonClocking(uint32_t iFreq)

Initialize the AON FRO to given frequency.

Initialize the AON FRO to given frequency and selects the frequency as AON Root Clock source for Root_Clock1, 2, 3 clock signals. In case of LPIRC selection, it also disables ULPIRC as it has no other usage than AON Root Clock source. In case of ULPIRC selection, LPIRC is kept running as it can be used in main domain.

Parameters:

• iFreq – : Desired frequency (10M, 3M, 0=off).

Returns:

returns success or fail status.

uint32_t CLOCK_GetAonCoreSysClkFreq(void)

Return Frequency of the AON core.

Returns:

Frequency of the core

status_t CLOCK_AonFroAutoTrimEnable(aon_fro_autotrim_config_t config, bool enable)

Enable/disable Aon LPIRC/ULPIRC auto trim feature.

Initialized ROSC (xtal32) is required.

See also

CLOCK_InitRosc()

Parameters:

• config – : Autotrim target frequency configuration.

• enable – : True to enable autotrim, false to disable it.

Returns:

kStatus_Fail on error, kStatus_Success otherwise.

void CLOCK_GetDefaultInitRoscConfig(rosc_init_config_t *config)

Fills the Rosc initialization configuration structure with default values.

The default values are chosen for safe and common startup behavior. Delays and timeouts are defined in milliseconds. For example:

config->xtal_drive_params[0].dly_cap_sox            = 0U;
config->xtal_drive_params[0].amp                    = 0U;
config->xtal_drive_params[0].gm                     = 0U;
config->detectionDelay                              = 2000U;
config->detectionTimeout                            = 0U;
config->detectionDelaySwitchedMode                  = 500U;
config->detectionTimeoutSwitchedMode                = 0U;
config->cbXo                                        = 3U;
config->cbXi                                        = 3U;
config->vbatOver3V                                  = true;

This function should be called before CLOCK_InitRosc if custom configuration is not fully provided.

Parameters:

• config – Pointer to the rosc_init_config_t structure to be filled.

bool CLOCK_IsRoscInitialized(void)

Checks if ROSC (xtal32k) is initialized.

This function enables the RTC alive detector temporarily to check if the ROSC (32kHz crystal oscillator) is properly initialized and running.

Returns:

true if ROSC is initialized and running properly, false if ROSC is not initialized or not running properly.

status_t CLOCK_InitRosc(const rosc_init_config_t *config)

Initializes the ROSC (xtal32k).

Parameters:

• config – Pointer to the user-defined rosc_init_config_t structure.

Returns:

kStatus_Success ROSC is initialized. kStatus_Fail ROSC init failed. kStatus_Busy ROSC is used as core clock.

status_t CLOCK_DeinitRosc(void)

brief De-initializes the SCG ROSC.

This function disables the SCG ROSC clock.

retval kStatus_Success System OSC is deinitialized. retval kStatus_Busy ROSC is used by core.

uint32_t CLOCK_GetFreq(clock_name_t clockName)

Return Frequency of selected clock.

Returns:

Frequency of selected clock

uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id)

Return Frequency of LPI2C functional Clock.

Returns:

Frequency of LPI2C functional Clock

uint32_t CLOCK_GetQtmrClkFreq(void)

Return Frequency of QTMR functional Clock.

Returns:

Frequency of QTMR functional Clock

uint32_t CLOCK_GetLptmrClkFreq(void)

Return Frequency of LPTMR functional Clock.

Returns:

Frequency of LPTMR functional Clock

uint32_t CLOCK_GetLpuartClkFreq(uint32_t id)

Return Frequency of LPUART functional Clock.

Returns:

Frequency of LPUART functional Clock

FSL_CLOCK_DRIVER_VERSION

CLOCK driver version 1.7.0.

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY

IFR1_VDD_CORE_MAIN_1P0_TRIM

IFR1_VDD_CORE_MAIN_1P1_TRIM

IFR1_VDD_CORE_MAIN_MASK

IFR1_VDD_CORE_MAIN_LPWR_MASK

IFR1_VDD_CORE_MAIN_LPWR_SHIFT

IFR1_LVD_HVD_TRIM_0

IFR1_LVD_HVD_TRIM_1

IFR1_LVD_LV_1P0_TRIM_SHIFT

IFR1_LVD_LV_1P1_TRIM_SHIFT

IFR1_HVD_LV_1P0_TRIM_SHIFT

IFR1_HVD_LV_1P1_TRIM_SHIFT

IFR1_LVD_HVD_TRIM_MASK

AON_FRO_AUTO_CAL_INT

AON_FRO_AUTO_CAL_3M_CAL_DWN_CNT

AON_FRO_AUTO_CAL_3M_TGT_LSB

AON_FRO_AUTO_CAL_10M_CAL_DWN_CNT

AON_FRO_AUTO_CAL_10M_TGT_LSB

CLK_GATE_REG_ACC_OFFSET(value)

Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

The offset of the registers MRCC_GLB_ACC0 and MRCC_GLB_ACC1.

CLK_GATE_REG_PR_OFFSET(value)

The offset of the registers MRCC_GLB_PR0 and MRCC_GLB_PR1.

CLK_GATE_REG_CC_OFFSET(value)

The offset of the registers MRCC_GLB_CC0 and MRCC_GLB_CC1.

CLK_PERIPHERAL_BIT_SHIFT(value)

Bit definitions for the peripherals in MRCC_GLB_PR, MRCC_GLB_CC and MRCC_GLB_ACC.

CLK_OF_AON(value)

True when clock gate belongs to AON domain.

SLCD_FAULT_DETECT_CLOCKS

Clock ip name array for SLCD.

SLCD_CONTROL_CLOCKS

LPACMP_CLOCKS

Clock ip name array for LPACMP.

AOI_CLOCKS

Clock ip name array for AOI.

ATX_CLOCKS

Clock ip name array for ATX.

CRC_CLOCKS

Clock ip name array for CRC.

CTIMER_CLOCKS

Clock ip name array for CTIMER.

CTIMER2 register access is only available when CTIMER1 clock is enabled and CTIMER1 is released from reset.

DMA_CLOCKS

Clock ip name array for DMA.

ERM_CLOCKS

EDMA_CLOCKS

Clock gate name array for EDMA.

EZRAMC_CLOCKS

Clock ip name array for EZRAMC_RAMA.

FREQME_CLOCKS

Clock ip name array for FREQME.

GPIO_CLOCKS

Clock ip name array for GPIO.

INPUTMUX_CLOCKS

Clock ip name array for INPUTMUX.

AON_LPADC_CLOCKS

Clock ip name array for LPCMP.

Clock ip name array for LPADC.

Clock ip name array for LPADC.

LPUART_CLOCKS

Clock ip name array for LPUART.

LPI2C_CLOCKS

Clock ip name array for LPI2C.

LPSPI_CLOCKS

Clock ip name array for LPSPI.

MTR_CLOCKS

Clock ip name array for MTR.

OSTIMER_CLOCKS

Clock ip name array for OSTIMER.

PERIPHGROUP_CLOCKS

Clock ip name array for PERIPH_GROUP.

PORT_CLOCKS

Clock ip name array for PORT.

ROMCP_CLOCKS

Clock ip name array for ROMCP.

TCU_CLOCKS

Clock ip name array for TCU.

TRNG_CLOCKS

Clock ip name array for TRNG.

UTICK_CLOCKS

Clock ip name array for UTICK.

WWDT_CLOCKS

Clock ip name array for WWDT.

BUS_CLK

Peripherals clock source definition.

TMR_CLOCKS

Clock ip name array for QTMRs.

LPTMR_CLOCKS

Clock ip name array for AON LPTMRs.

KPP_CLOCKS

Clock ip name array for QTMRs.

CLK_ATTACH_REG_OFFSET(value)

Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards.

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

CLK_ATTACH_CLK_SEL(value)

CLK_ATTACH_MUX(reg, sel)

CLK_OF_AON_SEL(value)

CLK_AON_SEL_REG_OFFSET(value)

CLK_AON_SEL_SHIFT(value)

CLK_AON_SEL_MASK(value)

CLK_AON_SEL(reg, shift, mask)

uint8_t fs_bp

Replica voltage fs_bp. 0-7

uint8_t fs_vcco

Replica voltage fs_vcco. 0-3

uint8_t tf

Relationship between the frequency and temperature. 0-7

uint8_t cltrim

Trim coarse freq value; 0-63

uint8_t ccotrim

Trim fine freq value; 0-63

uint8_t dly_cap_sox

Pulse location

uint8_t amp

Amplitude control

uint8_t gm

GM setting

uint8_t xtalDriveParamsSize

Size of xtal_drive_params array

xtal_drive_param_t (*xtal_drive_params)[]

Pointer to array of dly_cap_sox, amp and gm parameters

uint32_t detectionDelay

Delay before start of rosc initialization detection

uint32_t detectionTimeout

Timeout for detection of rosc initialization

uint32_t detectionDelaySwitchedMode

Delay before start of rosc initialization detection in switched mode

uint32_t detectionTimeoutSwitchedMode

Timeout for detection of rosc initialization in switched mode

uint8_t cbXo

Selects the internal capacitance on XO or XTAL pin

uint8_t cbXi

Selects the internal capacitance on XI or XTAL pin

bool vbatOver3V

Initialization configuration for vbat voltage value

struct _aon_fro_trim_config

#include <fsl_clock.h>

AON FRO trim configuration.

struct _xtal_drive_param

#include <fsl_clock.h>

XTAL drive parameter structure containing dly_cap_sox, amp and gm values.

struct _rosc_init_config

#include <fsl_clock.h>

ROSC initialization configuration structure.

CRC: Cyclic Redundancy Check Driver

FSL_CRC_DRIVER_VERSION

CRC driver version. Version 2.1.0.

Current version: 2.1.0

Change log:

• Version 2.1.0

  • Choosing CRC clocks from CRC clock array according to instance instead of hardcoded value.

• Version 2.0.5

  • Fix CERT-C issue with boolean-to-unsigned integer conversion.

• Version 2.0.4

  • Release peripheral from reset if necessary in init function.

• Version 2.0.3

  • Fix MISRA issues

• Version 2.0.2

  • Fix MISRA issues

• Version 2.0.1

  • move DATA and DATALL macro definition from header file to source file

enum _crc_bits

CRC bit width.

Values:

enumerator kCrcBits16

Generate 16-bit CRC code

enumerator kCrcBits32

Generate 32-bit CRC code

enum _crc_result

CRC result type.

Values:

enumerator kCrcFinalChecksum

CRC data register read value is the final checksum. Reflect out and final xor protocol features are applied.

enumerator kCrcIntermediateChecksum

CRC data register read value is intermediate checksum (raw value). Reflect out and final xor protocol feature are not applied. Intermediate checksum can be used as a seed for CRC_Init() to continue adding data to this checksum.

typedef enum _crc_bits crc_bits_t

CRC bit width.

typedef enum _crc_result crc_result_t

CRC result type.

typedef struct _crc_config crc_config_t

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

void CRC_Init(CRC_Type *base, const crc_config_t *config)

Enables and configures the CRC peripheral module.

This function enables the clock gate in the SIM module for the CRC peripheral. It also configures the CRC module and starts a checksum computation by writing the seed.

Parameters:

• base – CRC peripheral address.

• config – CRC module configuration structure.

void CRC_Deinit(CRC_Type *base)

Disables the CRC peripheral module.

This function disables the clock gate in the SIM module for the CRC peripheral.

Parameters:

• base – CRC peripheral address.

void CRC_GetDefaultConfig(crc_config_t *config)

Loads default values to the CRC protocol configuration structure.

Loads default values to the CRC protocol configuration structure. The default values are as follows.

config->polynomial = 0x1021;
config->seed = 0xFFFF;
config->reflectIn = false;
config->reflectOut = false;
config->complementChecksum = false;
config->crcBits = kCrcBits16;
config->crcResult = kCrcFinalChecksum;

Parameters:

• config – CRC protocol configuration structure.

void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)

Writes data to the CRC module.

Writes input data buffer bytes to the CRC data register. The configured type of transpose is applied.

Parameters:

• base – CRC peripheral address.

• data – Input data stream, MSByte in data[0].

• dataSize – Size in bytes of the input data buffer.

uint32_t CRC_Get32bitResult(CRC_Type *base)

Reads the 32-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

• base – CRC peripheral address.

Returns:

An intermediate or the final 32-bit checksum, after configured transpose and complement operations.

uint16_t CRC_Get16bitResult(CRC_Type *base)

Reads a 16-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

• base – CRC peripheral address.

Returns:

An intermediate or the final 16-bit checksum, after configured transpose and complement operations.

CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT

Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault.

struct _crc_config

#include <fsl_crc.h>

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

Public Members

uint32_t polynomial

CRC Polynomial, MSBit first. Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1

uint32_t seed

Starting checksum value

bool reflectIn

Reflect bits on input.

bool reflectOut

Reflect bits on output.

bool complementChecksum

True if the result shall be complement of the actual checksum.

crc_bits_t crcBits

Selects 16- or 32- bit CRC protocol.

crc_result_t crcResult

Selects final or intermediate checksum return from CRC_Get16bitResult() or CRC_Get32bitResult()

CTIMER: Standard counter/timers

void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)

Ungates the clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application before using the driver.

Parameters:

• base – Ctimer peripheral base address

• config – Pointer to the user configuration structure.

void CTIMER_Deinit(CTIMER_Type *base)

Gates the timer clock.

Parameters:

• base – Ctimer peripheral base address

void CTIMER_GetDefaultConfig(ctimer_config_t *config)

Fills in the timers configuration structure with the default settings.

The default values are:

config->mode = kCTIMER_TimerMode;
config->input = kCTIMER_Capture_0;
config->prescale = 0;

Parameters:

• config – Pointer to the user configuration structure.

status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM period

Parameters:

• base – Ctimer peripheral base address

• pwmPeriodChannel – Specify the channel to control the PWM period

• matchChannel – Match pin to be used to output the PWM signal

• pwmPeriod – PWM period match value

• pulsePeriod – Pulse width match value

• enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

Returns:

kStatus_Success on success kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle If PWM pulse width register value is larger than 0xFFFFFFFF.

status_t CTIMER_SetupPwm(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool enableInt)

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.

Parameters:

• base – Ctimer peripheral base address

• pwmPeriodChannel – Specify the channel to control the PWM period

• matchChannel – Match pin to be used to output the PWM signal

• dutyCyclePercent – PWM pulse width; the value should be between 0 to 100

• pwmFreq_Hz – PWM signal frequency in Hz

• srcClock_Hz – Timer counter clock in Hz

• enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)

Updates the pulse period of an active PWM signal.

Parameters:

• base – Ctimer peripheral base address

• matchChannel – Match pin to be used to output the PWM signal

• pulsePeriod – New PWM pulse width match value

status_t CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)

Updates the duty cycle of an active PWM signal.

Note

Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. This function can manually assign the specified channel to set the PWM cycle.

Parameters:

• base – Ctimer peripheral base address

• pwmPeriodChannel – Specify the channel to control the PWM period

• matchChannel – Match pin to be used to output the PWM signal

• dutyCyclePercent – New PWM pulse width; the value should be between 0 to 100

Returns:

kStatus_Success on success kStatus_Fail If PWM pulse width register value is larger than 0xFFFFFFFF.

static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)

Enables the selected Timer interrupts.

Parameters:

• base – Ctimer peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)

Disables the selected Timer interrupts.

Parameters:

• base – Ctimer peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)

Gets the enabled Timer interrupts.

Parameters:

• base – Ctimer peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)

Gets the Timer status flags.

Parameters:

• base – Ctimer peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)

Clears the Timer status flags.

Parameters:

• base – Ctimer peripheral base address

• mask – The status flags to clear. This is a logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_StartTimer(CTIMER_Type *base)

Starts the Timer counter.

Parameters:

• base – Ctimer peripheral base address

static inline void CTIMER_StopTimer(CTIMER_Type *base)

Stops the Timer counter.

Parameters:

• base – Ctimer peripheral base address

FSL_CTIMER_DRIVER_VERSION

Version 2.3.6

enum _ctimer_capture_channel

List of Timer capture channels.

Values:

enumerator kCTIMER_Capture_0

Timer capture channel 0

enumerator kCTIMER_Capture_1

Timer capture channel 1

enumerator kCTIMER_Capture_3

Timer capture channel 3

enum _ctimer_capture_edge

List of capture edge options.

Values:

enumerator kCTIMER_Capture_RiseEdge

Capture on rising edge

enumerator kCTIMER_Capture_FallEdge

Capture on falling edge

enumerator kCTIMER_Capture_BothEdge

Capture on rising and falling edge

enum _ctimer_match

List of Timer match registers.

Values:

enumerator kCTIMER_Match_0

Timer match register 0

enumerator kCTIMER_Match_1

Timer match register 1

enumerator kCTIMER_Match_2

Timer match register 2

enumerator kCTIMER_Match_3

Timer match register 3

enum _ctimer_external_match

List of external match.

Values:

enumerator kCTIMER_External_Match_0

External match 0

enumerator kCTIMER_External_Match_1

External match 1

enumerator kCTIMER_External_Match_2

External match 2

enumerator kCTIMER_External_Match_3

External match 3

enum _ctimer_match_output_control

List of output control options.

Values:

enumerator kCTIMER_Output_NoAction

No action is taken

enumerator kCTIMER_Output_Clear

Clear the EM bit/output to 0

enumerator kCTIMER_Output_Set

Set the EM bit/output to 1

enumerator kCTIMER_Output_Toggle

Toggle the EM bit/output

enum _ctimer_timer_mode

List of Timer modes.

Values:

enumerator kCTIMER_TimerMode

enumerator kCTIMER_IncreaseOnRiseEdge

enumerator kCTIMER_IncreaseOnFallEdge

enumerator kCTIMER_IncreaseOnBothEdge

enum _ctimer_interrupt_enable

List of Timer interrupts.

Values:

enumerator kCTIMER_Match0InterruptEnable

Match 0 interrupt

enumerator kCTIMER_Match1InterruptEnable

Match 1 interrupt

enumerator kCTIMER_Match2InterruptEnable

Match 2 interrupt

enumerator kCTIMER_Match3InterruptEnable

Match 3 interrupt

enum _ctimer_status_flags

List of Timer flags.

Values:

enumerator kCTIMER_Match0Flag

Match 0 interrupt flag

enumerator kCTIMER_Match1Flag

Match 1 interrupt flag

enumerator kCTIMER_Match2Flag

Match 2 interrupt flag

enumerator kCTIMER_Match3Flag

Match 3 interrupt flag

enum ctimer_callback_type_t

Callback type when registering for a callback. When registering a callback an array of function pointers is passed the size could be 1 or 8, the callback type will tell that.

Values:

enumerator kCTIMER_SingleCallback

Single Callback type where there is only one callback for the timer. based on the status flags different channels needs to be handled differently

enumerator kCTIMER_MultipleCallback

Multiple Callback type where there can be 8 valid callbacks, one per channel. for both match/capture

typedef enum _ctimer_capture_channel ctimer_capture_channel_t

List of Timer capture channels.

typedef enum _ctimer_capture_edge ctimer_capture_edge_t

List of capture edge options.

typedef enum _ctimer_match ctimer_match_t

List of Timer match registers.

typedef enum _ctimer_external_match ctimer_external_match_t

List of external match.

typedef enum _ctimer_match_output_control ctimer_match_output_control_t

List of output control options.

typedef enum _ctimer_timer_mode ctimer_timer_mode_t

List of Timer modes.

typedef enum _ctimer_interrupt_enable ctimer_interrupt_enable_t

List of Timer interrupts.

typedef enum _ctimer_status_flags ctimer_status_flags_t

List of Timer flags.

typedef void (*ctimer_callback_t)(uint32_t flags)

typedef struct _ctimer_match_config ctimer_match_config_t

Match configuration.

This structure holds the configuration settings for each match register.

typedef struct _ctimer_config ctimer_config_t

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)

Setup the match register.

User configuration is used to setup the match value and action to be taken when a match occurs.

Parameters:

• base – Ctimer peripheral base address

• matchChannel – Match register to configure

• config – Pointer to the match configuration structure

uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel)

Get the status of output match.

This function gets the status of output MAT, whether or not this output is connected to a pin. This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

Parameters:

• base – Ctimer peripheral base address

• matchChannel – External match channel, user can obtain the status of multiple match channels at the same time by using the logic of “|” enumeration ctimer_external_match_t

Returns:

The mask of external match channel status flags. Users need to use the _ctimer_external_match type to decode the return variables.

void CTIMER_SetupCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, ctimer_capture_edge_t edge, bool enableInt)

Setup the capture.

Parameters:

• base – Ctimer peripheral base address

• capture – Capture channel to configure

• edge – Edge on the channel that will trigger a capture

• enableInt – Flag to enable channel interrupts, if enabled then the registered call back is called upon capture

static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)

Get the timer count value from TC register.

Parameters:

• base – Ctimer peripheral base address.

Returns:

return the timer count value.

void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)

Register callback.

This function configures CTimer Callback in following modes:

• Single Callback: cb_func should be pointer to callback function pointer For example: ctimer_callback_t ctimer_callback = pwm_match_callback; CTIMER_RegisterCallBack(CTIMER, &ctimer_callback, kCTIMER_SingleCallback);

• Multiple Callback: cb_func should be pointer to array of callback function pointers Each element corresponds to Interrupt Flag in IR register. For example: ctimer_callback_t ctimer_callback_table[] = { ctimer_match0_callback, NULL, NULL, ctimer_match3_callback, NULL, NULL, NULL, NULL}; CTIMER_RegisterCallBack(CTIMER, &ctimer_callback_table[0], kCTIMER_MultipleCallback);

Parameters:

• base – Ctimer peripheral base address

• cb_func – Pointer to callback function pointer

• cb_type – callback function type, singular or multiple

static inline void CTIMER_Reset(CTIMER_Type *base)

Reset the counter.

The timer counter and prescale counter are reset on the next positive edge of the APB clock.

Parameters:

• base – Ctimer peripheral base address

static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale)

Setup the timer prescale value.

Specifies the maximum value for the Prescale Counter.

Parameters:

• base – Ctimer peripheral base address

• prescale – Prescale value

static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture)

Get capture channel value.

Get the counter/timer value on the corresponding capture channel.

Parameters:

• base – Ctimer peripheral base address

• capture – Select capture channel

Returns:

The timer count capture value.

static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable reset match channel.

Set the specified match channel reset operation.

Parameters:

• base – Ctimer peripheral base address

• match – match channel used

• enable – Enable match channel reset operation.

static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable stop match channel.

Set the specified match channel stop operation.

Parameters:

• base – Ctimer peripheral base address.

• match – match channel used.

• enable – Enable match channel stop operation.

static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable reload channel falling edge.

Enable the specified match channel reload match shadow value.

Parameters:

• base – Ctimer peripheral base address.

• match – match channel used.

• enable – Enable .

static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)

Enable capture channel rising edge.

Sets the specified capture channel for rising edge capture.

Parameters:

• base – Ctimer peripheral base address.

• capture – capture channel used.

• enable – Enable rising edge capture.

static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)

Enable capture channel falling edge.

Sets the specified capture channel for falling edge capture.

Parameters:

• base – Ctimer peripheral base address.

• capture – capture channel used.

• enable – Enable falling edge capture.

static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue)

Set the specified match shadow channel.

Parameters:

• base – Ctimer peripheral base address.

• match – match channel used.

• matchvalue – Reload the value of the corresponding match register.

struct _ctimer_match_config

#include <fsl_ctimer.h>

Match configuration.

This structure holds the configuration settings for each match register.

Public Members

uint32_t matchValue

This is stored in the match register

bool enableCounterReset

true: Match will reset the counter false: Match will not reser the counter

bool enableCounterStop

true: Match will stop the counter false: Match will not stop the counter

ctimer_match_output_control_t outControl

Action to be taken on a match on the EM bit/output

bool outPinInitState

Initial value of the EM bit/output

bool enableInterrupt

true: Generate interrupt upon match false: Do not generate interrupt on match

struct _ctimer_config

#include <fsl_ctimer.h>

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

Public Members

ctimer_timer_mode_t mode

Timer mode

ctimer_capture_channel_t input

Input channel to increment the timer, used only in timer modes that rely on this input signal to increment TC

uint32_t prescale

Prescale value

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

• base – eDMA peripheral base address.

• config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

• base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)

Push content of TCD structure into hardware TCD register.

Parameters:

• base – EDMA peripheral base address.

• channel – EDMA channel number.

• tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

• config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)

EDMA Channel initialization.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)

Set channel memory attribute.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• writeAttribute – Attributes associated with a write transaction.

• readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)

Set channel sign extension.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)

Set channel swap size.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)

Set channel access type.

Parameters:

• base – eDMA4 peripheral base address.

• channel – eDMA4 channel number.

• channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)

Set channel request source.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)

Gets the channel identification and attribute information on the system bus interface.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)

Set channel master ID replication.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – true is enable, false is disable.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)

Set channel security level.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number

• config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• type – A channel link type, which can be one of the following:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an async request for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Enables the interrupt source for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)

Disables the interrupt source for the eDMA transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• base – eDMA peripheral base address.

• channel – edma channel number.

• sourceOffset – source address offset will be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

• For the platform has cache, the software TCD should be put in non cache section

• The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

• tcd – Pointer to the TCD structure.

• transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

• tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

• tcd – Pointer to the TCD structure.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

• tcd – A point to the TCD structure.

• config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• tcd – Point to the TCD structure.

• type – Channel link type, it can be one of:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• tcd – A pointer to the TCD structure.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• tcd – A pointer to the TCD structure.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• tcd – A pointer to the TCD structure.

• enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• tcd – A point to the TCD structure.

• sourceOffset – source address offset wiil be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

• For the platform has cache, the software TCD should be put in non cache section

• The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

• transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)

Configures the eDMA TCD transfer attribute.

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

• config – Pointer to eDMA transfer configuration structure.

• nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

• base – eDMA peripheral base address.

• tcd – A point to the TCD structure.

• config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)

Sets the channel link for the eDMA TCD.

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

• base – eDMA peripheral base address.

• tcd – Point to the TCD structure.

• type – Channel link type, it can be one of:

  • kEDMA_LinkNone

  • kEDMA_MinorLink

  • kEDMA_MajorLink

• linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)

Sets the bandwidth for the eDMA TCD.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

• base – eDMA peripheral base address.

• tcd – A pointer to the TCD structure.

• bandWidth – A bandwidth setting, which can be one of the following:

  • kEDMABandwidthStallNone

  • kEDMABandwidthStall4Cycle

  • kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)

Sets the source modulo and the destination modulo for the eDMA TCD.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

• base – eDMA peripheral base address.

• tcd – A pointer to the TCD structure.

• srcModulo – A source modulo value.

• destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• tcd – A pointer to the TCD structure.

• enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Enables the interrupt source for the eDMA TCD.

Parameters:

• base – eDMA peripheral base address.

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)

Disables the interrupt source for the eDMA TCD.

Parameters:

• base – eDMA peripheral base address.

• tcd – Point to the TCD structure.

• mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

• base – eDMA peripheral base address.

• tcd – A point to the TCD structure.

• sourceOffset – source address offset wiil be applied to source address after major loop done.

• destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

1. The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)

Gets the eDMA channel error status flags.

Parameters:

• base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)

Gets the eDMA channel status flags.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)

Clears the eDMA channel status flags.

Parameters:

• base – eDMA peripheral base address.

• channel – eDMA channel number.

• mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

• handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.

• base – eDMA peripheral base address.

• channel – eDMA channel number.

Return values:

• kStatus_Success –

• kStatus_InvalidArgument –

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

• handle – eDMA handle pointer.

• tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.

• tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

• handle – eDMA handle pointer.

• callback – eDMA callback function pointer.

• userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

• config – The user configuration structure of type edma_transfer_t.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• srcOffset – source address offset.

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• destOffset – destination address offset.

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

• config – The user configuration structure of type edma_transfer_t.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

• type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

• handle – eDMA handle pointer.

• tcd – Pointer to eDMA transfer content descriptor structure.

• srcAddr – eDMA transfer source address.

• srcWidth – eDMA transfer source address width(bytes).

• srcOffset – source address offset.

• destAddr – eDMA transfer destination address.

• destWidth – eDMA transfer destination address width(bytes).

• destOffset – destination address offset.

• bytesEachRequest – eDMA transfer bytes per channel request.

• transferBytes – eDMA transfer bytes to be transferred.

• nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

1. submit single transfer

   edma_tcd_t tcd;
   EDMA_PrepareTransferTCD(handle, tcd, ....)
   EDMA_SubmitTransferTCD(handle, tcd)
   EDMA_StartTransfer(handle)
   

2. submit static link transfer,

   edma_tcd_t tcd[2];
   EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
   EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
   EDMA_SubmitTransferTCD(handle, &tcd[0])
   EDMA_StartTransfer(handle)
   

3. submit dynamic link transfer

   edma_tcd_t tcdpool[2];
   EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
   edma_tcd_t tcd;
   EDMA_PrepareTransferTCD(handle, tcd, ....)
   EDMA_SubmitTransferTCD(handle, tcd)
   EDMA_PrepareTransferTCD(handle, tcd, ....)
   EDMA_SubmitTransferTCD(handle, tcd)
   EDMA_StartTransfer(handle)
   

4. submit loop transfer

   edma_tcd_t tcd[2];
   EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
   EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
   EDMA_SubmitTransferTCD(handle, &tcd[0])
   EDMA_StartTransfer(handle)
   

Parameters:

• handle – eDMA handle pointer.

• tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

• kStatus_EDMA_Success – It means submit transfer request succeed.

• kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.

• kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

• handle – eDMA handle pointer.

• config – Pointer to eDMA transfer configuration structure.

Return values:

• kStatus_EDMA_Success – It means submit transfer request succeed.

• kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.

• kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

• handle – eDMA handle pointer

• transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail

• transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

• kStatus_Success – It means submit transfer request succeed

• kStatus_EDMA_Busy – channel is in busy status

• kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

• handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

• handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

• handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

• handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

• handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

• handle – eDMA handle pointer.

void EDMA_TcdInit(EDMA_Type *base, edma_tcd_t *tcdRegs)

Initialize all fields to 0 for the TCD structure.

This function initialize all fields for this TCD structure to 0.

Parameters:

• base – eDMA peripheral base address.

• tcd – Pointer to the TCD structure.

FSL_EDMA_DRIVER_VERSION

eDMA driver version

Version 2.10.14.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull

TCD queue is full.

enumerator kStatus_EDMA_Busy

Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes

Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes

Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes

Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes

Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes

Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes

Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes

Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes

Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable

Disable modulo

enumerator kEDMA_Modulo2bytes

Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes

Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes

Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes

Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes

Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes

Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes

Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes

Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes

Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes

Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes

Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes

Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes

Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes

Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes

Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes

Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes

Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes

Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes

Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes

Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes

Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes

Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes

Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes

Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes

Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes

Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes

Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes

Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes

Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes

Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes

Circular buffer size is 2 G bytes.

enum _edma_bandwidth

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone

No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle

eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle

eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type

Channel link type.

Values:

enumerator kEDMA_LinkNone

No channel link

enumerator kEDMA_MinorLink

Channel link after each minor loop

enumerator kEDMA_MajorLink

Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag

DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag

eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag

eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag

Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag

Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag

Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag

NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag

Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag

Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag

Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag

Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag

Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag

Transfer cancelled

enumerator kEDMA_ValidFlag

No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable

Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable

Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable

Enable interrupt while major count to half value.

enum _edma_transfer_type

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory

Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory

Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral

Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral

Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer

No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable

No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer

No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable

No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer

No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable

No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer

No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable

No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer

write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable

write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer

write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable

write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer

write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable

write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer

write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable

write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled

Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap

Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap

Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap

Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap

Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap

Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap

Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel

Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId

DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess

Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess

Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser

user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged

Privileged protection level eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t

eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t

eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t

Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t

Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t

eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t

eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t

eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t

eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t

eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t

eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t

eDMA4 channel protection level

typedef struct _edma_channel_config edma_channel_config_t

eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t

eDMA channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0

2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width

3. the totalBytes should align with the bytesEachRequest

4. the srcAddr should align with the srcWidthOfEachTransfer

5. the dstAddr should align with the dstWidthOfEachTransfer

6. the srcAddr should align with srcAddrModulo if modulo feature is enabled

7. the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the eDMA interfaces will generate assert error.

typedef struct _edma_config edma_config_t

eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:

EDMA handle pointer, users shall not touch the values inside.

Param userData:

The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.

Param transferDone:

If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.

Param tcds:

How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t

eDMA transfer handle structure

FSL_EDMA_DRIVER_UNIFIED

eDMA driver name.

This is the unified eDMA driver serving the eDMA3, eDMA4 and eDMA5 IP versions. Its Kconfig component is driver.edma_unified; the historical driver.edma4 component and the FSL_EDMA_DRIVER_EDMA4 macro are retained as deprecated aliases for backward compatibility. The version-specific edma4_* / edma5_* identifiers inside this driver refer to the corresponding IP TCD layout, not to the component name.

FSL_EDMA_DRIVER_EDMA4

Deprecated alias of FSL_EDMA_DRIVER_UNIFIED; use FSL_EDMA_DRIVER_UNIFIED.

EDMA_ALLOCATE_TCD(name, number)

Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel)

Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption

If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility

If true: a channel can suspend other channel with low priority

uint8_t channelPriority

Channel priority

struct _edma_minor_offset_config

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset

Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset

Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset

Offset for a minor loop mapping.

struct _edma_channel_config

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig

channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute

channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute

channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize

channel swap size configuration

edma_channel_access_type_t channelAccessType

channel access type configuration

uint8_t channelDataSignExtensionBitPosition

channel data sign extension bit psition configuration

uint32_t channelRequestSource

hardware service request source for the channel

bool enableMasterIDReplication

enable master ID replication

edma_channel_protection_level_t protectionLevel

protection level

struct _edma_transfer_config

#include <fsl_edma.h>

eDMA channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0

2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width

3. the totalBytes should align with the bytesEachRequest

4. the srcAddr should align with the srcWidthOfEachTransfer

5. the dstAddr should align with the dstWidthOfEachTransfer

6. the srcAddr should align with srcAddrModulo if modulo feature is enabled

7. the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the eDMA interfaces will generate assert error.

Public Members

uint32_t srcAddr

Source data address.

uint32_t destAddr

Destination data address.

edma_transfer_size_t srcTransferSize

Source data transfer size.

edma_transfer_size_t destTransferSize

Destination data transfer size.

int16_t srcOffset

Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset

Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes

bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts

minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask

channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo

source circular data queue range

int32_t srcMajorLoopOffset

source major loop offset

edma_modulo_t dstAddrModulo

destination circular data queue range

int32_t dstMajorLoopOffset

destination major loop offset

bool enableSrcMinorLoopOffset

enable source minor loop offset

bool enableDstMinorLoopOffset

enable dest minor loop offset

int32_t minorLoopOffset

burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink

channel link when major loop complete

uint32_t majorLoopLinkChannel

major loop link channel number

bool enableChannelMinorLoopLink

channel link when minor loop complete

uint32_t minorLoopLinkChannel

minor loop link channel number

edma_tcd_t *linkTCD

pointer to the link transfer control descriptor

struct _edma_config

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableMasterIdReplication

Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink

Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError

Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode

Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration

Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]

channel preemption configuration

struct _edma_handle

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback

Callback function for major count exhausted.

void *userData

Callback function parameter.

EDMA_ChannelType *channelBase

eDMA peripheral channel base address.

EDMA_Type *base

eDMA peripheral base address

EDMA_TCDType *tcdBase

eDMA peripheral tcd base address.

edma_tcd_t *tcdPool

Pointer to memory stored TCDs.

uint32_t channel

eDMA channel number.

volatile int8_t header

The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail

The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed

The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize

The total number of TCD slots in the queue.

eDMA core Driver

enum _edma_tcd_type

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag

Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag

Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t

edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t

edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t

eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t

edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t

edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t

edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType

EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType

typedef void EDMA_Type

DMA_CORE_MP_CSR_EDBG_MASK

DMA_CORE_MP_CSR_ERCA_MASK

DMA_CORE_MP_CSR_HAE_MASK

DMA_CORE_MP_CSR_HALT_MASK

DMA_CORE_MP_CSR_GCLC_MASK

DMA_CORE_MP_CSR_GMRC_MASK

DMA_CORE_MP_CSR_EDBG(x)

DMA_CORE_MP_CSR_ERCA(x)

DMA_CORE_MP_CSR_HAE(x)

DMA_CORE_MP_CSR_HALT(x)

DMA_CORE_MP_CSR_GCLC(x)

DMA_CORE_MP_CSR_GMRC(x)

DMA_CSR_INTMAJOR_MASK

DMA_CSR_INTHALF_MASK

DMA_CSR_DREQ_MASK

DMA_CSR_ESG_MASK

DMA_CSR_BWC_MASK

DMA_CSR_BWC(x)

DMA_CSR_START_MASK

DMA_CITER_ELINKNO_CITER_MASK

DMA_BITER_ELINKNO_BITER_MASK

DMA_CITER_ELINKNO_CITER_SHIFT

DMA_CITER_ELINKYES_CITER_MASK

DMA_CITER_ELINKYES_CITER_SHIFT

DMA_ATTR_SMOD_MASK

DMA_ATTR_DMOD_MASK

DMA_ATTR_SSIZE_MASK

DMA_ATTR_SSIZE_SHIFT

DMA_ATTR_DSIZE_MASK

DMA_ATTR_DSIZE_SHIFT

DMA_CITER_ELINKNO_ELINK_MASK

DMA_CSR_MAJORELINK_MASK

DMA_BITER_ELINKYES_ELINK_MASK

DMA_CITER_ELINKYES_ELINK_MASK

DMA_CSR_MAJORLINKCH_MASK

DMA_BITER_ELINKYES_LINKCH_MASK

DMA_CITER_ELINKYES_LINKCH_MASK

DMA_NBYTES_MLOFFYES_MLOFF_MASK

DMA_NBYTES_MLOFFYES_DMLOE_MASK

DMA_NBYTES_MLOFFYES_SMLOE_MASK

DMA_NBYTES_MLOFFNO_NBYTES_MASK

DMA_ATTR_DMOD(x)

DMA_ATTR_SMOD(x)

DMA_BITER_ELINKYES_LINKCH(x)

DMA_CITER_ELINKYES_LINKCH(x)

DMA_NBYTES_MLOFFYES_MLOFF(x)

DMA_NBYTES_MLOFFYES_DMLOE(x)

DMA_NBYTES_MLOFFYES_SMLOE(x)

DMA_NBYTES_MLOFFNO_NBYTES(x)

DMA_NBYTES_MLOFFYES_NBYTES(x)

DMA_ATTR_DSIZE(x)

DMA_ATTR_SSIZE(x)

DMA_CSR_DREQ(x)

DMA_CSR_MAJORLINKCH(x)

DMA_CH_MATTR_WCACHE(x)

DMA_CH_MATTR_RCACHE(x)

DMA_CH_CSR_SIGNEXT_MASK

DMA_CH_CSR_SIGNEXT_SHIFT

DMA_CH_CSR_SWAP_MASK

DMA_CH_CSR_SWAP_SHIFT

DMA_CH_SBR_INSTR_MASK

DMA_CH_SBR_INSTR_SHIFT

DMA_CH_SBR_EMI_MASK

DMA_CH_SBR_EMI_SHIFT

DMA_CH_MUX_SOURCE(x)

DMA_ERR_DBE_FLAG

DMA error flag.

DMA_ERR_SBE_FLAG

DMA_ERR_SGE_FLAG

DMA_ERR_NCE_FLAG

DMA_ERR_DOE_FLAG

DMA_ERR_DAE_FLAG

DMA_ERR_SOE_FLAG

DMA_ERR_SAE_FLAG

DMA_ERR_ERRCHAN_FLAG

DMA_ERR_ECX_FLAG

DMA_ERR_FLAG

DMA_CLEAR_DONE_STATUS(base, channel)

get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)

DMA_ENABLE_ERROR_INT(base, channel)

enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)

DMA_CLEAR_ERROR_STATUS(base, channel)

get/clear error status

DMA_GET_ERROR_STATUS(base, channel)

DMA_CLEAR_INT_STATUS(base, channel)

get/clear INT status

DMA_GET_INT_STATUS(base, channel)

DMA_ENABLE_MAJOR_INT(base, channel)

enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)

DMA_DISABLE_MAJOR_INT(base, channel)

DMA_DISABLE_HALF_INT(base, channel)

EDMA_TCD_ALIGN_SIZE

EDMA tcd align size.

EDMA_CORE_BASE(base)

EDMA base address convert macro.

EDMA_MP_BASE(base)

EDMA_CHANNEL_BASE(base, channel)

EDMA_TCD_BASE(base, channel)

EDMA_TCD_TYPE(x)

EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag)

EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)

EDMA_TCD_ATTR(tcd, flag)

EDMA_TCD_NBYTES(tcd, flag)

EDMA_TCD_SLAST(tcd, flag)

EDMA_TCD_DADDR(tcd, flag)

EDMA_TCD_DOFF(tcd, flag)

EDMA_TCD_CITER(tcd, flag)

EDMA_TCD_DLAST_SGA(tcd, flag)

EDMA_TCD_CSR(tcd, flag)

EDMA_TCD_BITER(tcd, flag)

struct _edma_core_mp

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR

Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES

Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR

Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES

Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT

Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR

Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI

Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR

SADDR register, used to save source address

__IO uint32_t SADDR_HIGH

SADDR HIGH register, used to save source address

__IO uint16_t SOFF

SOFF register, save offset bytes every transfer

__IO uint16_t ATTR

ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES

Nbytes register, minor loop length in bytes

__IO uint32_t SLAST

SLAST register

__IO uint32_t SLAST_SDA_HIGH

SLAST SDA HIGH register

__IO uint32_t DADDR

DADDR register, used for destination address

__IO uint32_t DADDR_HIGH

DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA

DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH

DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF

DOFF register, used for destination offset

__IO uint16_t CITER

CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR

CSR register, for TCD control status

__IO uint16_t BITER

BITER register, begin minor loop count.

uint8_t RESERVED[16]

Aligned 64 bytes

struct _edma4_core_tcd

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR

SADDR register, used to save source address

__IO uint16_t SOFF

SOFF register, save offset bytes every transfer

__IO uint16_t ATTR

ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES

Nbytes register, minor loop length in bytes

__IO uint32_t SLAST

SLAST register

__IO uint32_t DADDR

DADDR register, used for destination address

__IO uint16_t DOFF

DOFF register, used for destination offset

__IO uint16_t CITER

CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA

DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR

CSR register, for TCD control status

__IO uint16_t BITER

BITER register, begin minor loop count.

struct _edma_core_tcd

#include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS

Public Members

struct _edma_core_mp EDMA5_REG

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW

Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH

Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW

Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH

Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH

Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW

Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH

Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]

Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]

Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]

Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS

Public Members

struct _edma_core_channel EDMA5_REG

struct _edma_core_channel EDMA4_REG

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR

Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX

Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR

Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS

Public Members

edma4_core_tcd_t edma4_tcd

eDMA soc Driver

FSL_EDMA_SOC_DRIVER_VERSION

Driver version 1.0.0.

FSL_EDMA_SOC_IP_DMA3

DMA IP version.

FSL_EDMA_SOC_IP_DMA4

EDMA_BASE_PTRS

DMA base table.

EDMA_CHN_IRQS

FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION

FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE

FSL_FEATURE_EDMA_MODULE_COUNT

FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG

FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE

FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE

FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE

FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION

FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base)

FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base)

FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base)

FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base)

EDMA_CHANNEL_OFFSET

EDMA base address convert macro.

EDMA_CHANNEL_ARRAY_STEP(base)

ERM: error recording module

void ERM_Init(ERM_Type *base)

ERM module initialization function.

Parameters:

• base – ERM base address.

void ERM_Deinit(ERM_Type *base)

De-initializes the ERM.

static inline void ERM_EnableInterrupts(ERM_Type *base, uint32_t channel, uint32_t mask)

ERM enable interrupts.

Parameters:

• base – ERM peripheral base address.

• channel – memory channel.

• mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline void ERM_DisableInterrupts(ERM_Type *base, uint32_t channel, uint32_t mask)

ERM module disable interrupts.

Parameters:

• base – ERM base address.

• channel – memory channel.

• mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, uint32_t channel)

Gets ERM interrupt flags.

Parameters:

• base – ERM peripheral base address.

Returns:

ERM event flags.

static inline void ERM_ClearInterruptStatus(ERM_Type *base, uint32_t channel, uint32_t mask)

ERM module clear interrupt status flag.

Parameters:

• base – ERM base address.

• mask – event flag to clear. Refer to “_erm_interrupt_flag” enumeration.

uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, uint32_t channel)

ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n.

Parameters:

• base – ERM base address.

• channel – memory channel.

Return values:

memory – error absolute address.

FSL_ERM_DRIVER_VERSION

Driver version.

ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.

This structure contains the settings for all of the ERM interrupt configurations.

Values:

enumerator kERM_SingleCorrectionIntEnable

Single Correction Interrupt Notification enable.

enumerator kERM_NonCorrectableIntEnable

Non-Correction Interrupt Notification enable.

enumerator kERM_AllInterruptsEnable

All Interrupts enable

ERM interrupt status, _erm_interrupt_flag.

This provides constants for the ERM event status for use in the ERM functions.

Values:

enumerator kERM_SingleBitCorrectionIntFlag

Single-Bit Correction Event.

enumerator kERM_NonCorrectableErrorIntFlag

Non-Correctable Error Event.

enumerator kERM_AllIntsFlag

All Events.

FGPIO Driver

FREQME: Frequency Measurement

GLIKEY

Values:

enumerator kStatus_GLIKEY_LockedError

GLIKEY status for locked SFR registers (unexpected) .

enumerator kStatus_GLIKEY_NotLocked

GLIKEY status for unlocked SFR registers.

enumerator kStatus_GLIKEY_Locked

GLIKEY status for locked SFR registers.

enumerator kStatus_GLIKEY_DisabledError

GLIKEY status for disabled error.

FSL_GLIKEY_DRIVER_VERSION

Defines GLIKEY driver version 2.0.1.

Change log:

• Version 2.0.1

  • Implement INIT state recovery from the LOCKED state after a reset when the previous index was locked.

• Version 2.0.0

  • Initial version

GLIKEY_CODEWORD_STEP1

GLIKEY_CODEWORD_STEP2

GLIKEY_CODEWORD_STEP3

GLIKEY_CODEWORD_STEP4

GLIKEY_CODEWORD_STEP5

GLIKEY_CODEWORD_STEP6

GLIKEY_CODEWORD_STEP7

GLIKEY_CODEWORD_STEP_EN

GLIKEY_FSM_WR_DIS

GLIKEY_FSM_INIT

GLIKEY_FSM_STEP1

GLIKEY_FSM_STEP2

GLIKEY_FSM_STEP3

GLIKEY_FSM_STEP4

GLIKEY_FSM_LOCKED

GLIKEY_FSM_WR_EN

GLIKEY_FSM_SSR_RESET

uint32_t GLIKEY_GetStatus(GLIKEY_Type *base)

Retreives the current status of Glikey.

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

Glikey status information

status_t GLIKEY_IsLocked(GLIKEY_Type *base)

Get if Glikey is locked.

This operation returns the locking status of Glikey.

Return values:

• kStatus_GLIKEY_Locked – if locked

• kStatus_GLIKEY_NotLocked – if unlocked

Returns:

Status

status_t GLIKEY_CheckLock(GLIKEY_Type *base)

Check if Glikey is locked.

This operation returns the locking status of Glikey.

Return values:

• kStatus_GLIKEY_LockedError – if locked

• kStatus_GLIKEY_NotLocked – if unlocked

Returns:

Status kStatus_Success if success

status_t GLIKEY_SyncReset(GLIKEY_Type *base)

Perform a synchronous reset of Glikey.

This function performs a synchrounous reset of the Glikey. This results in:

• Glikey will return to the INIT state, unless it is in the LOCK state

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value)

Set interrupt enable flag of Glikey.

Parameters:

• base – [in] The base address of the Glikey instance

• value – [in] Value to set the interrupt enable flag to, see #[TODO: add reference to constants]

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value)

Get interrupt enable flag of Glikey.

Parameters:

• base – [in] The base address of the Glikey instance

• value – [out] Pointer which will be filled with the interrupt enable status, see #[TODO: add reference to constants]

Returns:

Status kStatus_Success if success

status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)

Clear the interrupt status flag of Glikey.

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)

Set the interrupt status flag of Glikey.

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_Lock(GLIKEY_Type *base)

Lock Glikey SFR (Special Function Registers) interface.

This operation locks the Glikey SFR interface if it is not locked yet.

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success

status_t GLIKEY_LockIndex(GLIKEY_Type *base)

Lock Glikey index.

This operation is used to lock a Glikey index. It can only be executed from the WR_EN state, executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. If the Glikey SFR lock is active this operation will return an error.

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index)

Check if Glikey index is locked.

This operation returns the locking status of Glikey index.

Parameters:

• base – [in] The base address of the Glikey instance

• index – [in] The index of the Glikey instance

Returns:

kStatus_GLIKEY_Locked if locked, kStatus_GLIKEY_NotLocked if unlocked Possible errors: kStatus_Fail

status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)

Start Glikey enable.

This operation is used to set a new index and start a the sequence to enable it. It needs to be started from the INIT state. If the new index is already locked Glikey will go to LOCKED state, otherwise it will go to STEP1 state. If this operation is used when Glikey is in any state other than INIT Glikey will go to WR_DIS state. It can only recover from this state through a reset (synchrounous or asyncrhonous). If the Glikey SFR lock is active this operation will return an error.

Parameters:

• base – [in] The base address of the Glikey instance

• index – [in] The index of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail

status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)

Continue Glikey enable.

This operation is used to progress through the different states of the state machine, starting from STEP1 until the state WR_EN is reached. Each next state of the state machine can only be reached by providing the right codeword to this function. If anything goes wrong the state machine will go to WR_DIS state and can only recover from it through a reset (synchrous or asynchronous). If the Glikey SFR lock is active this operation will return an error.

Parameters:

• base – [in] The base address of the Glikey instance

• codeword – [in] Encoded word for progressing to next FSM state (see GLIKEY_CODEWORD_STEPx/EN)

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail, kStatus_GLIKEY_DisabledError

status_t GLIKEY_EndOperation(GLIKEY_Type *base)

End Glikey operation.

This operation is used to end a Glikey operation. It can only be executed from the WR_EN, LOCKED and RESET states. Executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. After this operation Glikey will go to INIT state or stay in LOCKED state when the index was locked. If the Glikey SFR lock is active this operation will return an error.

Parameters:

• base – [in] The base address of the Glikey instance

Returns:

A code-flow protected error code (see nxpCsslFlowProtection)

Returns:

Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index)

Reset Glikey index.

This operation is used to reset a Glikey index. It can only be executed from the INIT state, executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. If the Glikey SFR lock is active or the index is locked this operation will return an error.

Returns:

A code-flow protected error code (see nxpCsslFlowProtection)

Returns:

Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

GLIKEY

GPIO: General-Purpose Input/Output Driver

FSL_GPIO_DRIVER_VERSION

GPIO driver version.

enum _gpio_pin_direction

GPIO direction definition.

Values:

enumerator kGPIO_DigitalInput

Set current pin as digital input

enumerator kGPIO_DigitalOutput

Set current pin as digital output

enum _gpio_checker_attribute

GPIO checker attribute.

Values:

enumerator kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW

User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW

User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW

User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW

User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW

User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW

User nonsecure:None; User Secure:None; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR

User nonsecure:None; User Secure:None; Privileged Secure:Read

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN

User nonsecure:None; User Secure:None; Privileged Secure:None

enumerator kGPIO_IgnoreAttributeCheck

Ignores the attribute check

enum _gpio_interrupt_config

Configures the interrupt generation condition.

Values:

enumerator kGPIO_InterruptStatusFlagDisabled

Interrupt status flag is disabled.

enumerator kGPIO_DMARisingEdge

ISF flag and DMA request on rising edge.

enumerator kGPIO_DMAFallingEdge

ISF flag and DMA request on falling edge.

enumerator kGPIO_DMAEitherEdge

ISF flag and DMA request on either edge.

enumerator kGPIO_FlagRisingEdge

Flag sets on rising edge.

enumerator kGPIO_FlagFallingEdge

Flag sets on falling edge.

enumerator kGPIO_FlagEitherEdge

Flag sets on either edge.

enumerator kGPIO_InterruptLogicZero

Interrupt when logic zero.

enumerator kGPIO_InterruptRisingEdge

Interrupt on rising edge.

enumerator kGPIO_InterruptFallingEdge

Interrupt on falling edge.

enumerator kGPIO_InterruptEitherEdge

Interrupt on either edge.

enumerator kGPIO_InterruptLogicOne

Interrupt when logic one.

enumerator kGPIO_ActiveHighTriggerOutputEnable

Enable active high-trigger output.

enumerator kGPIO_ActiveLowTriggerOutputEnable

Enable active low-trigger output.

enum _gpio_interrupt_selection

Configures the selection of interrupt/DMA request/trigger output.

Values:

enumerator kGPIO_InterruptOutput0

Interrupt/DMA request/trigger output 0.

enumerator kGPIO_InterruptOutput1

Interrupt/DMA request/trigger output 1.

enum gpio_pin_interrupt_control_t

GPIO pin and interrupt control.

Values:

enumerator kGPIO_PinControlNonSecure

Pin Control Non-Secure.

enumerator kGPIO_InterruptControlNonSecure

Interrupt Control Non-Secure.

enumerator kGPIO_PinControlNonPrivilege

Pin Control Non-Privilege.

enumerator kGPIO_InterruptControlNonPrivilege

Interrupt Control Non-Privilege.

typedef enum _gpio_pin_direction gpio_pin_direction_t

GPIO direction definition.

typedef enum _gpio_checker_attribute gpio_checker_attribute_t

GPIO checker attribute.

typedef struct _gpio_pin_config gpio_pin_config_t

The GPIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().

typedef enum _gpio_interrupt_config gpio_interrupt_config_t

Configures the interrupt generation condition.

typedef enum _gpio_interrupt_selection gpio_interrupt_selection_t

Configures the selection of interrupt/DMA request/trigger output.

typedef struct _gpio_version_info gpio_version_info_t

GPIO version information.

GPIO_FIT_REG(value)

struct _gpio_pin_config

#include <fsl_gpio.h>

The GPIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().

Public Members

gpio_pin_direction_t pinDirection

GPIO direction, input or output

uint8_t outputLogic

Set a default output logic, which has no use in input

struct _gpio_version_info

#include <fsl_gpio.h>

GPIO version information.

Public Members

uint16_t feature

Feature Specification Number.

uint8_t minor

Minor Version Number.

uint8_t major

Major Version Number.

GPIO Driver

void GPIO_PortInit(GPIO_Type *base)

Initializes the GPIO peripheral.

This function ungates the GPIO clock.

Parameters:

• base – GPIO peripheral base pointer.

void GPIO_PortDenit(GPIO_Type *base)

Denitializes the GPIO peripheral.

Parameters:

• base – GPIO peripheral base pointer.

void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)

Initializes a GPIO pin used by the board.

To initialize the GPIO, define a pin configuration, as either input or output, in the user file. Then, call the GPIO_PinInit() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalInput,
  0,
}
Define a digital output pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalOutput,
  0,
}

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• pin – GPIO port pin number

• config – GPIO pin configuration pointer

void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *verInfo)

Get GPIO version information.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• verInfo – GPIO version information

static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)

lock or unlock secure privilege.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – pin or interrupt macro

static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)

Enable Pin Control Non-Secure.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)

Disable Pin Control Non-Secure.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Enable Pin Control Non-Privilege.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Disable Pin Control Non-Privilege.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)

Enable Interrupt Control Non-Secure.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)

Disable Interrupt Control Non-Secure.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Enable Interrupt Control Non-Privilege.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)

Disable Interrupt Control Non-Privilege.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)

Enable port input.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)

Disable port input.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)

Sets the output level of the multiple GPIO pins to the logic 1 or 0.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• pin – GPIO pin number

• output – GPIO pin output logic level.

  • 0: corresponding pin output low-logic level.

  • 1: corresponding pin output high-logic level.

static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 1.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)

Sets the output level of the multiple GPIO pins to the logic 0.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)

Reverses the current output logic of the multiple GPIO pins.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)

Reads the current input value of the GPIO port.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• pin – GPIO pin number

Return values:

GPIO – port input value

• 0: corresponding pin input low-logic level.

• 1: corresponding pin input high-logic level.

static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)

Configures the gpio pin interrupt/DMA request.

Parameters:

• base – GPIO peripheral base pointer.

• pin – GPIO pin number.

• config – GPIO pin interrupt configuration.

  • kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.

  • kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).

  • kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).

  • kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).

  • kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).

  • kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).

  • kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).

  • kGPIO_InterruptLogicZero : Interrupt when logic zero.

  • kGPIO_InterruptRisingEdge : Interrupt on rising edge.

  • kGPIO_InterruptFallingEdge: Interrupt on falling edge.

  • kGPIO_InterruptEitherEdge : Interrupt on either edge.

  • kGPIO_InterruptLogicOne : Interrupt when logic one.

  • kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).

  • kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).

static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)

Configures the gpio pin interrupt/DMA request/trigger output channel selection.

Parameters:

• base – GPIO peripheral base pointer.

• pin – GPIO pin number.

• selection – GPIO pin interrupt output selection.

  • kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.

  • kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.

uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)

Read the GPIO interrupt status flags.

Parameters:

• base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)

Returns:

The current GPIO’s interrupt status flag. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)

Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

• base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)

• channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

Returns:

The current GPIO’s interrupt status flag based on the selected interrupt channel. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)

Read individual pin’s interrupt status flag.

Parameters:

• base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)

• pin – GPIO specific pin number.

Returns:

The current selected pin’s interrupt status flag.

void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)

Clears GPIO pin interrupt status flags.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)

Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• mask – GPIO pin number macro

• channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)

Clear GPIO individual pin’s interrupt status flag.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).

• pin – GPIO specific pin number.

static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)

Sets the GPIO interrupt configuration in PCR register for multiple pins.

Parameters:

• base – GPIO peripheral base pointer.

• mask – GPIO pin number macro.

• config – GPIO pin interrupt configuration.

  • kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.

  • kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).

  • kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).

  • kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).

  • kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).

  • kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).

  • kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).

  • kGPIO_InterruptLogicZero : Interrupt when logic zero.

  • kGPIO_InterruptRisingEdge : Interrupt on rising edge.

  • kGPIO_InterruptFallingEdge: Interrupt on falling edge.

  • kGPIO_InterruptEitherEdge : Interrupt on either edge.

  • kGPIO_InterruptLogicOne : Interrupt when logic one.

  • kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).

  • kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..

void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)

brief The GPIO module supports a device-specific number of data ports, organized as 32-bit words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the GPIO programming model. If the GPIO module’s GACR register organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention.

Parameters:

• base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)

• attribute – GPIO checker attribute

GPIO_PortGetInterruptFlags(base)

GPIO_PortClearInterruptFlags(base, mask)

INPUTMUX: Input Multiplexing Driver

enum _inputmux_index_t

Values:

enumerator kINPUTMUXAON_INDEX_QTMR0_TMR0

enumerator kINPUTMUXAON_INDEX_QTMR0_TMR1

enumerator kINPUTMUXAON_INDEX_QTMR0_TMR2

enumerator kINPUTMUXAON_INDEX_QTMR0_TMR3

enumerator kINPUTMUXAON_INDEX_SOC_GLUE_XOR0_IN0

enumerator kINPUTMUXAON_INDEX_SOC_GLUE_XOR0_IN1

enumerator kINPUTMUXAON_INDEX_QTMR1_TMR0

enumerator kINPUTMUXAON_INDEX_QTMR1_TMR1

enumerator kINPUTMUXAON_INDEX_QTMR1_TMR2

enumerator kINPUTMUXAON_INDEX_QTMR1_TMR3

enumerator kINPUTMUXAON_INDEX_LPACMP0_TRIG0

enumerator kINPUTMUXAON_INDEX_LPACMP0_TRIG1

enumerator kINPUTMUXAON_INDEX_LPACMP0_TRIG2

enumerator kINPUTMUXAON_INDEX_LPACMP0_TRIG3

enumerator kINPUTMUXAON_INDEX_LPADC0_TRIG0

enumerator kINPUTMUXAON_INDEX_LPADC0_TRIG1

enumerator kINPUTMUXAON_INDEX_LPADC0_TRIG2

enumerator kINPUTMUXAON_INDEX_LPADC0_TRIG3

enumerator kINPUTMUXAON_INDEX_AON_TRIG_OUT0

enumerator kINPUTMUXAON_INDEX_AON_TRIG_OUT1

enumerator kINPUTMUXAON_INDEX_SOC_GLUE_CMPPADS_PCTRL_XOR_IN0

enumerator kINPUTMUXAON_INDEX_SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0

enumerator kINPUTMUXAON_INDEX_LC_ROT_SOC_LOGIC_IN

enumerator kINPUTMUXAON_INDEX_LCSENSE_SEQ_PTRIG_GLUE_IN

enumerator kINPUTMUXAON_INDEX_LCSENSE_SEQ_TICKS_GLUE_IN

enumerator kINPUTMUXAON_INDEX_ACMP0_SAMPLE

enumerator kINPUTMUXAON_INDEX_ACMP0_RR_TRIG

enumerator kINPUTMUXAON_INDEX_LPI2C0_TRIG

enumerator kINPUTMUXAON_INDEX_LPUART0

enum _inputmux_connection_t

INPUTMUX connections type.

Values:

enumerator kINPUTMUXAON_AonTrigIn0ToQtmr0Tmrn

QTMR0_TMRn: QTMR0 Input Connections aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToQtmr0Tmrn

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToQtmr0Tmrn

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToQtmr0Tmrn

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToQtmr0Tmrn

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToQtmr0Tmrn

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToQtmr0Tmrn

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToQtmr0Tmrn

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToQtmr0Tmrn

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToQtmr0Tmrn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToQtmr0Tmrn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToQtmr0Tmrn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToQtmr0Tmrn

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToQtmr0Tmrn

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToQtmr0Tmrn

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToQtmr0Tmrn

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToQtmr0Tmrn

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToQtmr0Tmrn

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToQtmr0Tmrn

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToQtmr0Tmrn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToQtmr0Tmrn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToQtmr0Tmrn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToQtmr0Tmrn

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_Lptmr0OToQtmr0Tmrn

lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToQtmr0Tmrn

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToQtmr0Tmrn

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToQtmr0Tmrn

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToQtmr0Tmrn

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToQtmr0Tmrn

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToQtmr0Tmrn

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToQtmr0Tmrn

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToQtmr0Tmrn

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToQtmr0Tmrn

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToQtmr0Tmrn

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToQtmr0Tmrn

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToQtmr0Tmrn

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToQtmr0Tmrn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToQtmr0Tmrn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToQtmr0Tmrn

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToQtmr0Tmrn

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToQtmr0Tmrn

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToQtmr0Tmrn

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToQtmr0Tmrn

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToQtmr0Tmrn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToQtmr0Tmrn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToQtmr0Tmrn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToQtmr0Tmrn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToQtmr0Tmrn

lcsense_sequencer_primary_trigger_glue_out is selected SOC_GLUE_XOR0_INn: SOC_GLUE_XOR0 trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToSocGlueXor0Inn

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToSocGlueXor0Inn

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToSocGlueXor0Inn

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToSocGlueXor0Inn

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToSocGlueXor0Inn

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToSocGlueXor0Inn

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToSocGlueXor0Inn

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToSocGlueXor0Inn

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToSocGlueXor0Inn

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToSocGlueXor0Inn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToSocGlueXor0Inn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToSocGlueXor0Inn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToSocGlueXor0Inn

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToSocGlueXor0Inn

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToSocGlueXor0Inn

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToSocGlueXor0Inn

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToSocGlueXor0Inn

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToSocGlueXor0Inn

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToSocGlueXor0Inn

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToSocGlueXor0Inn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToSocGlueXor0Inn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToSocGlueXor0Inn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToSocGlueXor0Inn

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToSocGlueXor0Inn

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToSocGlueXor0Inn

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToSocGlueXor0Inn

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToSocGlueXor0Inn

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToSocGlueXor0Inn

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToSocGlueXor0Inn

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToSocGlueXor0Inn

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToSocGlueXor0Inn

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToSocGlueXor0Inn

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToSocGlueXor0Inn

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToSocGlueXor0Inn

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToSocGlueXor0Inn

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToSocGlueXor0Inn

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToSocGlueXor0Inn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToSocGlueXor0Inn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToSocGlueXor0Inn

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToSocGlueXor0Inn

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToSocGlueXor0Inn

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToSocGlueXor0Inn

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToSocGlueXor0Inn

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToSocGlueXor0Inn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToSocGlueXor0Inn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToSocGlueXor0Inn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToSocGlueXor0Inn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToSocGlueXor0Inn

lcsense_sequencer_primary_trigger_glue_out is selected QTMR1_TMRn: QTMR1 Input Connections

enumerator kINPUTMUXAON_AonTrigIn0ToQtmr1Tmrn

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToQtmr1Tmrn

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToQtmr1Tmrn

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToQtmr1Tmrn

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToQtmr1Tmrn

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToQtmr1Tmrn

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToQtmr1Tmrn

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToQtmr1Tmrn

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToQtmr1Tmrn

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToQtmr1Tmrn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToQtmr1Tmrn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToQtmr1Tmrn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToQtmr1Tmrn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToQtmr1Tmrn

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToQtmr1Tmrn

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToQtmr1Tmrn

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToQtmr1Tmrn

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToQtmr1Tmrn

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToQtmr1Tmrn

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToQtmr1Tmrn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToQtmr1Tmrn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToQtmr1Tmrn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToQtmr1Tmrn

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToQtmr1Tmrn

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToQtmr1Tmrn

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToQtmr1Tmrn

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToQtmr1Tmrn

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToQtmr1Tmrn

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToQtmr1Tmrn

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToQtmr1Tmrn

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToQtmr1Tmrn

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToQtmr1Tmrn

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToQtmr1Tmrn

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToQtmr1Tmrn

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToQtmr1Tmrn

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToQtmr1Tmrn

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToQtmr1Tmrn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToQtmr1Tmrn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToQtmr1Tmrn

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToQtmr1Tmrn

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToQtmr1Tmrn

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToQtmr1Tmrn

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToQtmr1Tmrn

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToQtmr1Tmrn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToQtmr1Tmrn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToQtmr1Tmrn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToQtmr1Tmrn

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToQtmr1Tmrn

lcsense_sequencer_primary_trigger_glue_out is selected LPACMP0_TRIGn: LPACMP0 Input Connections

enumerator kINPUTMUXAON_AonTrigIn0ToLpacmp0Trign

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLpacmp0Trign

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLpacmp0Trign

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToLpacmp0Trign

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToLpacmp0Trign

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLpacmp0Trign

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLpacmp0Trign

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLpacmp0Trign

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToLpacmp0Trign

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLpacmp0Trign

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLpacmp0Trign

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLpacmp0Trign

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLpacmp0Trign

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_AonLptmr0OToLpacmp0Trign

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLpacmp0Trign

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLpacmp0Trign

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLpacmp0Trign

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLpacmp0Trign

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_WuuOToLpacmp0Trign

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLpacmp0Trign

gpio (aon) pin event trig 0 is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToLpacmp0Trign

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToLpacmp0Trign

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToLpacmp0Trign

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToLpacmp0Trign

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_Acmp0RacoToLpacmp0Trign

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLpacmp0Trign

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLpacmp0Trign

soc_glue_xor0_out is selected LPADC0_TRIGn: LPADC trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToLpadc0Trign

aon_trig_in0 is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLpadc0Trign

aon_trig_in1 is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLpadc0Trign

aon_trig_in2 is selected

enumerator kINPUTMUXAON_AonTrigIn03ToLpadc0Trign

aon_trig_in03 is selected

enumerator kINPUTMUXAON_AonTrigIn04ToLpadc0Trign

aon_trig_in04 is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLpadc0Trign

aon_trig_in5 is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLpadc0Trign

aon_trig_in6 is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLpadc0Trign

aon_trig_in7 is selected

enumerator kINPUTMUXAON_Cm33TeToLpadc0Trign

cm33 transmit event is selected

enumerator kINPUTMUXAON_AonAcmpOutToLpadc0Trign

aon.acmp_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLpadc0Trign

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLpadc0Trign

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLpadc0Trign

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLpadc0Trign

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_AonLptmr0OToLpadc0Trign

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLpadc0Trign

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLpadc0Trign

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLpadc0Trign

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLpadc0Trign

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_WuuOToLpadc0Trign

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLpadc0Trign

gpio (aon) pin event trig 0 is selected

enumerator kINPUTMUXAON_Acmp0RacoToLpadc0Trign

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLpadc0Trign

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLpadc0Trign

soc_glue_xor0_out is selected AON_TRIG_OUTn: AON Trigger Output Connections

enumerator kINPUTMUXAON_Cm33TeToAonTrigOutn

cm33 transmit event is selected

enumerator kINPUTMUXAON_AonLpuart0ToAonTrigOutn

aon_lpuart0

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToAonTrigOutn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToAonTrigOutn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToAonTrigOutn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_ParkedOutIntvertedToAonTrigOutn

parked_out_intverted is selected

enumerator kINPUTMUXAON_AonLptmr0OToAonTrigOutn

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Lpcomp0OutToAonTrigOutn

lpcomp0_out is selected

enumerator kINPUTMUXAON_Acmp0RacoToAonTrigOutn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToAonTrigOutn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToAonTrigOutn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToAonTrigOutn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToAonTrigOutn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToAonTrigOutn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToAonTrigOutn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToAonTrigOutn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToAonTrigOutn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToAonTrigOutn

qtmr1 channel[3] output is selected SOC_GLUE_CMPPADS_PCTRL_XOR_IN0: SOC_GLUE_CMPPADS_PCTRL_XOR_IN0 trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToSocGlueCmppadsPctrlXorIn0

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToSocGlueCmppadsPctrlXorIn0

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToSocGlueCmppadsPctrlXorIn0

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToSocGlueCmppadsPctrlXorIn0

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToSocGlueCmppadsPctrlXorIn0

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToSocGlueCmppadsPctrlXorIn0

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToSocGlueCmppadsPctrlXorIn0

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToSocGlueCmppadsPctrlXorIn0

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToSocGlueCmppadsPctrlXorIn0

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToSocGlueCmppadsPctrlXorIn0

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToSocGlueCmppadsPctrlXorIn0

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToSocGlueCmppadsPctrlXorIn0

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToSocGlueCmppadsPctrlXorIn0

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToSocGlueCmppadsPctrlXorIn0

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToSocGlueCmppadsPctrlXorIn0

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToSocGlueCmppadsPctrlXorIn0

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToSocGlueCmppadsPctrlXorIn0

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToSocGlueCmppadsPctrlXorIn0

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToSocGlueCmppadsPctrlXorIn0

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToSocGlueCmppadsPctrlXorIn0

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToSocGlueCmppadsPctrlXorIn0

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToSocGlueCmppadsPctrlXorIn0

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToSocGlueCmppadsPctrlXorIn0

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToSocGlueCmppadsPctrlXorIn0

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToSocGlueCmppadsPctrlXorIn0

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToSocGlueCmppadsPctrlXorIn0

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToSocGlueCmppadsPctrlXorIn0

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToSocGlueCmppadsPctrlXorIn0

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToSocGlueCmppadsPctrlXorIn0

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToSocGlueCmppadsPctrlXorIn0

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToSocGlueCmppadsPctrlXorIn0

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToSocGlueCmppadsPctrlXorIn0

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToSocGlueCmppadsPctrlXorIn0

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToSocGlueCmppadsPctrlXorIn0

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToSocGlueCmppadsPctrlXorIn0

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToSocGlueCmppadsPctrlXorIn0

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToSocGlueCmppadsPctrlXorIn0

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToSocGlueCmppadsPctrlXorIn0

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToSocGlueCmppadsPctrlXorIn0

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToSocGlueCmppadsPctrlXorIn0

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToSocGlueCmppadsPctrlXorIn0

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToSocGlueCmppadsPctrlXorIn0

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToSocGlueCmppadsPctrlXorIn0

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToSocGlueCmppadsPctrlXorIn0

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToSocGlueCmppadsPctrlXorIn0

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToSocGlueCmppadsPctrlXorIn0

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToSocGlueCmppadsPctrlXorIn0

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToSocGlueCmppadsPctrlXorIn0

lcsense_sequencer_primary_trigger_glue_out is selected SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0: SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0 trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToSocGlueCtrlpadsPctrlXorIn0

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToSocGlueCtrlpadsPctrlXorIn0

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToSocGlueCtrlpadsPctrlXorIn0

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToSocGlueCtrlpadsPctrlXorIn0

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToSocGlueCtrlpadsPctrlXorIn0

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToSocGlueCtrlpadsPctrlXorIn0

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToSocGlueCtrlpadsPctrlXorIn0

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToSocGlueCtrlpadsPctrlXorIn0

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToSocGlueCtrlpadsPctrlXorIn0

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToSocGlueCtrlpadsPctrlXorIn0

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToSocGlueCtrlpadsPctrlXorIn0

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToSocGlueCtrlpadsPctrlXorIn0

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToSocGlueCtrlpadsPctrlXorIn0

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToSocGlueCtrlpadsPctrlXorIn0

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToSocGlueCtrlpadsPctrlXorIn0

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToSocGlueCtrlpadsPctrlXorIn0

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToSocGlueCtrlpadsPctrlXorIn0

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToSocGlueCtrlpadsPctrlXorIn0

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToSocGlueCtrlpadsPctrlXorIn0

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToSocGlueCtrlpadsPctrlXorIn0

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToSocGlueCtrlpadsPctrlXorIn0

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToSocGlueCtrlpadsPctrlXorIn0

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToSocGlueCtrlpadsPctrlXorIn0

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToSocGlueCtrlpadsPctrlXorIn0

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToSocGlueCtrlpadsPctrlXorIn0

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToSocGlueCtrlpadsPctrlXorIn0

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToSocGlueCtrlpadsPctrlXorIn0

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToSocGlueCtrlpadsPctrlXorIn0

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToSocGlueCtrlpadsPctrlXorIn0

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToSocGlueCtrlpadsPctrlXorIn0

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToSocGlueCtrlpadsPctrlXorIn0

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToSocGlueCtrlpadsPctrlXorIn0

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToSocGlueCtrlpadsPctrlXorIn0

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToSocGlueCtrlpadsPctrlXorIn0

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToSocGlueCtrlpadsPctrlXorIn0

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToSocGlueCtrlpadsPctrlXorIn0

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToSocGlueCtrlpadsPctrlXorIn0

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToSocGlueCtrlpadsPctrlXorIn0

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToSocGlueCtrlpadsPctrlXorIn0

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToSocGlueCtrlpadsPctrlXorIn0

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToSocGlueCtrlpadsPctrlXorIn0

lcsense_sequencer_primary_trigger_glue_out is selected LC_ROT_SOC_LOGIC_IN: LC_ROT_SOC_LOGIC_IN trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToLcRotSocLogicIn

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLcRotSocLogicIn

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLcRotSocLogicIn

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToLcRotSocLogicIn

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToLcRotSocLogicIn

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLcRotSocLogicIn

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLcRotSocLogicIn

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLcRotSocLogicIn

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToLcRotSocLogicIn

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLcRotSocLogicIn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLcRotSocLogicIn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLcRotSocLogicIn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLcRotSocLogicIn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToLcRotSocLogicIn

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToLcRotSocLogicIn

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToLcRotSocLogicIn

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToLcRotSocLogicIn

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToLcRotSocLogicIn

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToLcRotSocLogicIn

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToLcRotSocLogicIn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToLcRotSocLogicIn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToLcRotSocLogicIn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToLcRotSocLogicIn

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToLcRotSocLogicIn

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToLcRotSocLogicIn

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToLcRotSocLogicIn

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToLcRotSocLogicIn

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToLcRotSocLogicIn

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToLcRotSocLogicIn

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToLcRotSocLogicIn

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToLcRotSocLogicIn

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToLcRotSocLogicIn

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToLcRotSocLogicIn

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToLcRotSocLogicIn

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToLcRotSocLogicIn

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToLcRotSocLogicIn

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToLcRotSocLogicIn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLcRotSocLogicIn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToLcRotSocLogicIn

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToLcRotSocLogicIn

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToLcRotSocLogicIn

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLcRotSocLogicIn

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLcRotSocLogicIn

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLcRotSocLogicIn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLcRotSocLogicIn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLcRotSocLogicIn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLcRotSocLogicIn

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToLcRotSocLogicIn

lcsense_sequencer_primary_trigger_glue_out is selected LCSENSE_SEQ_PTRIG_GLUE_IN: LCSENSE_SEQ_PTRIG_GLUE_IN trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToLcsenseSeqPtrigGlueIn

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLcsenseSeqPtrigGlueIn

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLcsenseSeqPtrigGlueIn

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToLcsenseSeqPtrigGlueIn

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToLcsenseSeqPtrigGlueIn

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLcsenseSeqPtrigGlueIn

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLcsenseSeqPtrigGlueIn

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLcsenseSeqPtrigGlueIn

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToLcsenseSeqPtrigGlueIn

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLcsenseSeqPtrigGlueIn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLcsenseSeqPtrigGlueIn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLcsenseSeqPtrigGlueIn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLcsenseSeqPtrigGlueIn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToLcsenseSeqPtrigGlueIn

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToLcsenseSeqPtrigGlueIn

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToLcsenseSeqPtrigGlueIn

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToLcsenseSeqPtrigGlueIn

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToLcsenseSeqPtrigGlueIn

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToLcsenseSeqPtrigGlueIn

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToLcsenseSeqPtrigGlueIn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToLcsenseSeqPtrigGlueIn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToLcsenseSeqPtrigGlueIn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToLcsenseSeqPtrigGlueIn

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToLcsenseSeqPtrigGlueIn

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToLcsenseSeqPtrigGlueIn

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToLcsenseSeqPtrigGlueIn

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToLcsenseSeqPtrigGlueIn

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToLcsenseSeqPtrigGlueIn

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToLcsenseSeqPtrigGlueIn

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToLcsenseSeqPtrigGlueIn

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToLcsenseSeqPtrigGlueIn

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToLcsenseSeqPtrigGlueIn

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToLcsenseSeqPtrigGlueIn

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToLcsenseSeqPtrigGlueIn

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToLcsenseSeqPtrigGlueIn

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToLcsenseSeqPtrigGlueIn

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToLcsenseSeqPtrigGlueIn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLcsenseSeqPtrigGlueIn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToLcsenseSeqPtrigGlueIn

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToLcsenseSeqPtrigGlueIn

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToLcsenseSeqPtrigGlueIn

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLcsenseSeqPtrigGlueIn

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLcsenseSeqPtrigGlueIn

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLcsenseSeqPtrigGlueIn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLcsenseSeqPtrigGlueIn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLcsenseSeqPtrigGlueIn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLcsenseSeqPtrigGlueIn

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToLcsenseSeqPtrigGlueIn

lcsense_sequencer_primary_trigger_glue_out is selected LCSENSE_SEQ_TICKS_GLUE_IN: LCSENSE_SEQ_TICKS_GLUE_IN trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToLcsenseSeqTicksGlueIn

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLcsenseSeqTicksGlueIn

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLcsenseSeqTicksGlueIn

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToLcsenseSeqTicksGlueIn

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToLcsenseSeqTicksGlueIn

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLcsenseSeqTicksGlueIn

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLcsenseSeqTicksGlueIn

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLcsenseSeqTicksGlueIn

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToLcsenseSeqTicksGlueIn

cm33 transmit event is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLcsenseSeqTicksGlueIn

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLcsenseSeqTicksGlueIn

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLcsenseSeqTicksGlueIn

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLcsenseSeqTicksGlueIn

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_Cmp0OutToLcsenseSeqTicksGlueIn

cmp0_out is selected

enumerator kINPUTMUXAON_Lpi2c0CeopToLcsenseSeqTicksGlueIn

lpi2c0 controller end of packet is selected

enumerator kINPUTMUXAON_Lpi2c0TeopToLcsenseSeqTicksGlueIn

lpi2c0 target end of packet is selected

enumerator kINPUTMUXAON_Lpuart0RdwToLcsenseSeqTicksGlueIn

lpuart0 received data word is selected

enumerator kINPUTMUXAON_Lpuart0TdwToLcsenseSeqTicksGlueIn

lpuart0 transmitted data word is selected

enumerator kINPUTMUXAON_Lpuart0RliToLcsenseSeqTicksGlueIn

lpuart0 receive line idle is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToLcsenseSeqTicksGlueIn

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToLcsenseSeqTicksGlueIn

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToLcsenseSeqTicksGlueIn

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToLcsenseSeqTicksGlueIn

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_AonLptmr0OToLcsenseSeqTicksGlueIn

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut1ToLcsenseSeqTicksGlueIn

lc_rot_soc_logic_out1 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut2ToLcsenseSeqTicksGlueIn

lc_rot_soc_logic_out2 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut3ToLcsenseSeqTicksGlueIn

lc_rot_soc_logic_out3 is selected

enumerator kINPUTMUXAON_LcRotSocLogicOut4ToLcsenseSeqTicksGlueIn

lc_rot_soc_logic_out4 is selected

enumerator kINPUTMUXAON_Qtmr0Counter0dirToLcsenseSeqTicksGlueIn

qtmr0 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter1dirToLcsenseSeqTicksGlueIn

qtmr0 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter2dirToLcsenseSeqTicksGlueIn

qtmr0 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr0Counter3dirToLcsenseSeqTicksGlueIn

qtmr0 counter[3] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter0dirToLcsenseSeqTicksGlueIn

qtmr1 counter[0] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter1dirToLcsenseSeqTicksGlueIn

qtmr1 counter[1] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter2dirToLcsenseSeqTicksGlueIn

qtmr1 counter[2] direction is selected

enumerator kINPUTMUXAON_Qtmr1Counter3dirToLcsenseSeqTicksGlueIn

qtmr1 counter[3] direction is selected

enumerator kINPUTMUXAON_Acmp0RacoToLcsenseSeqTicksGlueIn

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLcsenseSeqTicksGlueIn

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_Logic0ToLcsenseSeqTicksGlueIn

logic_0 is selected

enumerator kINPUTMUXAON_Logic1ToLcsenseSeqTicksGlueIn

logic_1 is selected

enumerator kINPUTMUXAON_WuuOToLcsenseSeqTicksGlueIn

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLcsenseSeqTicksGlueIn

gpio (aon) pin event trig 0 input is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLcsenseSeqTicksGlueIn

soc_glue_xor0_out is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLcsenseSeqTicksGlueIn

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLcsenseSeqTicksGlueIn

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLcsenseSeqTicksGlueIn

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLcsenseSeqTicksGlueIn

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_LcsenseSequencerPrimaryTriggerGlueOutToLcsenseSeqTicksGlueIn

lcsense_sequencer_primary_trigger_glue_out is selected ACMP0_SAMPLE: ACMP0 SAMPLE trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToAcmp0Sample

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToAcmp0Sample

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToAcmp0Sample

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToAcmp0Sample

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToAcmp0Sample

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToAcmp0Sample

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToAcmp0Sample

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToAcmp0Sample

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToAcmp0Sample

cm33 transmit event is selected

enumerator kINPUTMUXAON_AonAcmpOutToAcmp0Sample

aon.acmp_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToAcmp0Sample

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToAcmp0Sample

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToAcmp0Sample

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToAcmp0Sample

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_AonLptmr0OToAcmp0Sample

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToAcmp0Sample

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToAcmp0Sample

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToAcmp0Sample

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToAcmp0Sample

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_WuuOToAcmp0Sample

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToAcmp0Sample

gpio (aon) pin event trig 0 is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToAcmp0Sample

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToAcmp0Sample

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToAcmp0Sample

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToAcmp0Sample

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToAcmp0Sample

soc_glue_xor0_out is selected ACMP0_RR_TRIG: ACMP0 RR trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToAcmp0RrTrig

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToAcmp0RrTrig

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToAcmp0RrTrig

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToAcmp0RrTrig

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToAcmp0RrTrig

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToAcmp0RrTrig

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToAcmp0RrTrig

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToAcmp0RrTrig

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToAcmp0RrTrig

cm33 transmit event is selected

enumerator kINPUTMUXAON_AonAcmpOutToAcmp0RrTrig

aon.acmp_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToAcmp0RrTrig

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToAcmp0RrTrig

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToAcmp0RrTrig

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToAcmp0RrTrig

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_AonLptmr0OToAcmp0RrTrig

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToAcmp0RrTrig

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToAcmp0RrTrig

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToAcmp0RrTrig

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToAcmp0RrTrig

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_WuuOToAcmp0RrTrig

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToAcmp0RrTrig

gpio (aon) pin event trig 0 is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToAcmp0RrTrig

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToAcmp0RrTrig

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToAcmp0RrTrig

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToAcmp0RrTrig

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToAcmp0RrTrig

soc_glue_xor0_out is selected LPI2C0_TRIG: LPI2C0 trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToLpi2c0Trig

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLpi2c0Trig

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLpi2c0Trig

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToLpi2c0Trig

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToLpi2c0Trig

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLpi2c0Trig

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLpi2c0Trig

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLpi2c0Trig

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToLpi2c0Trig

cm33 transmit event is selected

enumerator kINPUTMUXAON_AonAcmpOutToLpi2c0Trig

aon.acmp_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLpi2c0Trig

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLpi2c0Trig

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLpi2c0Trig

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLpi2c0Trig

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_AonLptmr0OToLpi2c0Trig

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLpi2c0Trig

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLpi2c0Trig

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLpi2c0Trig

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLpi2c0Trig

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_WuuOToLpi2c0Trig

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLpi2c0Trig

gpio (aon) pin event trig 0 is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToLpi2c0Trig

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToLpi2c0Trig

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToLpi2c0Trig

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToLpi2c0Trig

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_Acmp0RacoToLpi2c0Trig

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLpi2c0Trig

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLpi2c0Trig

soc_glue_xor0_out is selected LPUART0: LPUART0 trigger input connections

enumerator kINPUTMUXAON_AonTrigIn0ToLPUART0

aon_trig_in0 input is selected

enumerator kINPUTMUXAON_AonTrigIn1ToLPUART0

aon_trig_in1 input is selected

enumerator kINPUTMUXAON_AonTrigIn2ToLPUART0

aon_trig_in2 input is selected

enumerator kINPUTMUXAON_AonTrigIn3ToLPUART0

aon_trig_in3 input is selected

enumerator kINPUTMUXAON_AonTrigIn4ToLPUART0

aon_trig_in4 input is selected

enumerator kINPUTMUXAON_AonTrigIn5ToLPUART0

aon_trig_in5 input is selected

enumerator kINPUTMUXAON_AonTrigIn6ToLPUART0

aon_trig_in6 input is selected

enumerator kINPUTMUXAON_AonTrigIn7ToLPUART0

aon_trig_in7 input is selected

enumerator kINPUTMUXAON_Cm33TeToLPUART0

cm33 transmit event is selected

enumerator kINPUTMUXAON_AonAcmpOutToLPUART0

aon.acmp_out is selected

enumerator kINPUTMUXAON_Qtmr0Channel0ToLPUART0

qtmr0 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel1ToLPUART0

qtmr0 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel2ToLPUART0

qtmr0 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr0Channel3ToLPUART0

qtmr0 channel[3] output is selected

enumerator kINPUTMUXAON_AonLptmr0OToLPUART0

aon.lptmr0 output is selected

enumerator kINPUTMUXAON_Qtmr1Channel0ToLPUART0

qtmr1 channel[0] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel1ToLPUART0

qtmr1 channel[1] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel2ToLPUART0

qtmr1 channel[2] output is selected

enumerator kINPUTMUXAON_Qtmr1Channel3ToLPUART0

qtmr1 channel[3] output is selected

enumerator kINPUTMUXAON_WuuOToLPUART0

wuu output is selected

enumerator kINPUTMUXAON_GpioApet0ToLPUART0

gpio (aon) pin event trig 0 is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput0ToLPUART0

lpadc trigger complete pulse output[0] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput1ToLPUART0

lpadc trigger complete pulse output[1] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput2ToLPUART0

lpadc trigger complete pulse output[2] is selected

enumerator kINPUTMUXAON_LpadcTriggerCompletePulseOutput3ToLPUART0

lpadc trigger complete pulse output[3] is selected

enumerator kINPUTMUXAON_Acmp0RacoToLPUART0

acmp0 raw analog comparator output

enumerator kINPUTMUXAON_Acmp0AonCoutToLPUART0

acmp0_aon_cout is selected

enumerator kINPUTMUXAON_SocGlueXor0OutToLPUART0

soc_glue_xor0_out is selected

typedef enum _inputmux_index_t inputmux_index_t

typedef enum _inputmux_connection_t inputmux_connection_t

INPUTMUX connections type.

QTMR0_TMRn_REG

Periphinmux IDs.

SOC_GLUE_XOR0_INn_REG

QTMR1_TMRn_REG

LPACMP0_TRIGn_REG

LPADC0_TRIGn_REG

AON_TRIG_OUTn_REG

SOC_GLUE_CMPPADS_PCTRL_XOR_IN0_REG

SOC_GLUE_CTRLPADS_PCTRL_XOR_IN0_REG

LC_ROT_SOC_LOGIC_IN_REG

LCSENSE_SEQ_PTRIG_GLUE_IN_REG

LCSENSE_SEQ_TICKS_GLUE_IN_REG

ACMP0_SAMPLE_REG

ACMP0_RR_TRIG_REG

LPI2C0_TRIG_REG

LPUART0_REG

PMUX_SHIFT

FSL_INPUTMUX_DRIVER_VERSION

Group interrupt driver version for SDK.

void INPUTMUX_Init(void *base)

Initialize INPUTMUX peripheral.

This function enables the INPUTMUX clock.

Parameters:

• base – Base address of the INPUTMUX peripheral.

void INPUTMUX_AttachSignal(void *base, uint16_t index, inputmux_connection_t connection)

Attaches a signal.

This function writes a source signal selection into an INPUTMUX multiplexer register. The target register address is computed as:

target address = base + pmux_id + index * 4

Each inputmux_connection_t enum value encodes two fields via PMUX_SHIFT (20):

31          20 19                    0
+------------+------------------------+
|  pmux_id   |       output_id        |
+------------+------------------------+
     |                   |
group base          signal value
addr offset         to write

When N consecutive registers all accept the same set of source signals (same pmux_id), only one set of enum values is defined for the whole group; index (0 ~ N-1) selects which register to write, avoiding duplicate enum entries.

Example: SCT0 has 8 input mux registers sharing SCT0_INMUX0 = 0x000 as the group base:

base
 |
 +--[+0x000] SCT0_INMUX0  <-- index=0
 +--[+0x004] SCT0_INMUX1  <-- index=1
 +--[+0x008] SCT0_INMUX2  <-- index=2
 :   ...
 +--[+0x014] SCT0_INMUX5  <-- index=5  (write target for the call below)
 :   ...
 +--[+0x01C] SCT0_INMUX7  <-- index=7

To connect CMP0 output to SCT0 input 5:

INPUTMUX_AttachSignal(INPUTMUX, 5, kINPUTMUX_Cmp0OutToSct0);
// write address = base + 0x000 + 5*4 = base + 0x014  (SCT0_INMUX5)

For peripherals with only a single register per function (e.g. FREQMEAS_REF_REG = 0x180, FREQMEAS_TAR_REG = 0x184), each register has its own unique pmux_id and index must be 0. The two registers are distinguished by their different pmux_id values, not by index:

base
 |
 +--[+0x180] FREQMEAS_REF_REG  (pmux_id=0x180, index=0)
 +--[+0x184] FREQMEAS_TAR_REG  (pmux_id=0x184, index=0)

Parameters:

• base – Base address of the INPUTMUX peripheral.

• index – Zero-based index of the destination register within its group. Each increment advances the address by 4 bytes. Use 0 for single-register groups.

• connection – Encodes the group base offset (bits [31:PMUX_SHIFT]) and the source signal value (bits [PMUX_SHIFT-1:0]).

void INPUTMUX_Deinit(void *base)

Deinitialize INPUTMUX peripheral.

This function disables the INPUTMUX clock.

Parameters:

• base – Base address of the INPUTMUX peripheral.

KPP: KeyPad Port Driver

void KPP_Init(KPP_Type *base, kpp_config_t *configure)

KPP initialize. This function ungates the KPP clock and initializes KPP. This function must be called before calling any other KPP driver functions.

Parameters:

• base – KPP peripheral base address.

• configure – The KPP configuration structure pointer.

void KPP_Deinit(KPP_Type *base)

Deinitializes the KPP module and gates the clock. This function gates the KPP clock. As a result, the KPP module doesn’t work after calling this function.

Parameters:

• base – KPP peripheral base address.

static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask)

Enable the interrupt.

Parameters:

• base – KPP peripheral base address.

• mask – KPP interrupts to enable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask)

Disable the interrupt.

Parameters:

• base – KPP peripheral base address.

• mask – KPP interrupts to disable. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline uint16_t KPP_GetStatusFlag(KPP_Type *base)

Gets the KPP interrupt event status.

Parameters:

• base – KPP peripheral base address.

Returns:

The status of the KPP. Application can use the enum type in the “kpp_interrupt_enable_t” to get the right status of the related event.

static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask)

Clears KPP status flag.

Parameters:

• base – KPP peripheral base address.

• mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_interrupt_enable_t.

static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask)

Set KPP synchronization chain.

Parameters:

• base – KPP peripheral base address.

• mask – KPP mask to be cleared. This is a logical OR of the enumeration :: kpp_sync_operation_t.

status_t KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz)

Keypad press scanning.

This function will scanning all columns and rows. so all scanning data will be stored in the data pointer.

Parameters:

• base – KPP peripheral base address.

• data – KPP key press scanning data. The data buffer should be prepared with length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. for example the data[2] = 4, that means in column 1 row 2 has a key press event.

• clockSrc_Hz – Source clock.

Return values:

kStatus_Success – kpp press scan succeed.

FSL_KPP_DRIVER_VERSION

KPP driver version.

enum _kpp_interrupt_enable

List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

Values:

enumerator kKPP_keyDepressInterrupt

Keypad depress interrupt source

enumerator kKPP_keyReleaseInterrupt

Keypad release interrupt source

enum _kpp_sync_operation

Lists of KPP synchronize chain operation.

Values:

enumerator kKPP_ClearKeyDepressSyncChain

Keypad depress interrupt status.

enumerator kKPP_SetKeyReleasesSyncChain

Keypad release interrupt status.

typedef enum _kpp_interrupt_enable kpp_interrupt_enable_t

List of interrupts supported by the peripheral. This enumeration uses one-bot encoding to allow a logical OR of multiple members. Members usually map to interrupt enable bits in one or more peripheral registers.

typedef enum _kpp_sync_operation kpp_sync_operation_t

Lists of KPP synchronize chain operation.

typedef struct _kpp_config kpp_config_t

Lists of KPP status.

KPP_KEYPAD_COLUMNNUM_MAX

KPP_KEYPAD_ROWNUM_MAX

struct _kpp_config

#include <fsl_kpp.h>

Lists of KPP status.

Public Members

uint8_t activeRow

The row number: bit 7 ~ 0 represents the row 7 ~ 0.

uint8_t activeColumn

The column number: bit 7 ~ 0 represents the column 7 ~ 0.

uint16_t interrupt

KPP interrupt source. A logical OR of “kpp_interrupt_enable_t”.

Common Driver

FSL_COMMON_DRIVER_VERSION

common driver version.

DEBUG_CONSOLE_DEVICE_TYPE_NONE

No debug console.

DEBUG_CONSOLE_DEVICE_TYPE_UART

Debug console based on UART.

DEBUG_CONSOLE_DEVICE_TYPE_LPUART

Debug console based on LPUART.

DEBUG_CONSOLE_DEVICE_TYPE_LPSCI

Debug console based on LPSCI.

DEBUG_CONSOLE_DEVICE_TYPE_USBCDC

Debug console based on USBCDC.

DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM

Debug console based on FLEXCOMM.

DEBUG_CONSOLE_DEVICE_TYPE_IUART

Debug console based on i.MX UART.

DEBUG_CONSOLE_DEVICE_TYPE_VUSART

Debug console based on LPC_VUSART.

DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART

Debug console based on LPC_USART.

DEBUG_CONSOLE_DEVICE_TYPE_SWO

Debug console based on SWO.

DEBUG_CONSOLE_DEVICE_TYPE_QSCI

Debug console based on QSCI.

MIN(a, b)

Computes the minimum of a and b.

MAX(a, b)

Computes the maximum of a and b.

UINT16_MAX

Max value of uint16_t type.

UINT32_MAX

Max value of uint32_t type.

UINTPTR_SIZE

UINT64_H(X)

Macro to get upper 32 bits of a 64-bit value

UINT64_L(X)

Macro to get lower 32 bits of a 64-bit value

MCUX_MASK_INVERT_8(mask)

8-bit mask inversion.

MCUX_MASK_INVERT_16(mask)

16-bit mask inversion.

MCUX_MASK_INVERT_32(mask)

32-bit mask inversion for completeness.

MCUX_REG_WRITE8(reg, value)

8-bit register write macro

MCUX_REG_WRITE16(reg, value)

16-bit register write macro

MCUX_REG_WRITE32(reg, value)

32-bit register write macro

MCUX_REG_READ8(reg)

8-bit register read macro

MCUX_REG_READ16(reg)

16-bit register read macro

MCUX_REG_READ32(reg)

32-bit register read macro

MCUX_REG_BIT_SET8(reg, mask)

8-bit register bit set macro

MCUX_REG_BIT_SET16(reg, mask)

16-bit register bit set macro

MCUX_REG_BIT_SET32(reg, mask)

32-bit register bit set macro

MCUX_REG_BIT_CLEAR8(reg, mask)

8-bit register bit clear macro

MCUX_REG_BIT_CLEAR16(reg, mask)

16-bit register bit clear macro

MCUX_REG_BIT_CLEAR32(reg, mask)

32-bit register bit clear macro

MCUX_REG_BIT_GET8(reg, mask)

8-bit register bit get macro

MCUX_REG_BIT_GET16(reg, mask)

16-bit register bit get macro

MCUX_REG_BIT_GET32(reg, mask)

32-bit register bit get macro

MCUX_REG_MODIFY8(reg, mask, value)

32-bit register read-modify-write macro

MCUX_REG_MODIFY16(reg, mask, value)

16-bit register read-modify-write macro

MCUX_REG_MODIFY32(reg, mask, value)

32-bit register read-modify-write macro

SDK_ATOMIC_LOCAL_ADD(addr, val)

Add value val from the variable at address address.

SDK_ATOMIC_LOCAL_SUB(addr, val)

Subtract value val to the variable at address address.

SDK_ATOMIC_LOCAL_SET(addr, bits)

Set the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR(addr, bits)

Clear the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)

Toggle the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)

For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits.

SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)

For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false .

SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)

For the variable at address address, set as newValue value and return old value.

USEC_TO_COUNT(us, clockFreqInHz)

Macro to convert a microsecond period to raw count value

COUNT_TO_USEC(count, clockFreqInHz)

Macro to convert a raw count value to microsecond

MSEC_TO_COUNT(ms, clockFreqInHz)

Macro to convert a millisecond period to raw count value

COUNT_TO_MSEC(count, clockFreqInHz)

Macro to convert a raw count value to millisecond

SDK_ISR_EXIT_BARRIER

SDK_ALIGN(var, alignbytes)

Macro to define a variable with alignbytes alignment

SDK_SIZEALIGN(var, alignbytes)

Macro to define a variable with L1 d-cache line size alignment

Macro to define a variable with L2 cache line size alignment

Macro to change a value to a given size aligned value (rounded up)

SDK_SIZEALIGN_UP(var, alignbytes)

Macro to change a value to a given size aligned value (rounded up), the wrapper of SDK_SIZEALIGN

SDK_SIZEALIGN_DOWN(var, alignbytes)

Macro to change a value to a given size aligned value (rounded down)

SDK_IS_ALIGNED(var, alignbytes)

Macro to check if a value is aligned to a given size

AT_NONCACHEABLE_SECTION(var)

Define a variable var, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)

Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_NONCACHEABLE_SECTION_INIT(var)

Define a variable var with initial value, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)

Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_CACHE_LINE_SECTION(var)

Define a variable var, which is cache line size aligned and be placed in CacheLineData section.

AT_CACHE_LINE_SECTION_INIT(var)

Define a variable var with initial value, which is cache line size aligned and be placed in CacheLineData.init section.

AT_QUICKACCESS_SECTION_CODE(func)

Place function in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA(var)

Place data in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)

Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes.

MCUX_RAMFUNC

Function attribute to place function in RAM. For example, to place function my_func in ram, use like:

MCUX_RAMFUNC my_func

RAMFUNCTION_SECTION_CODE(func)

Place function in ram.

MCUX_DEPRECATED

Deprecated APIs.

MCUX_DEPRECATED_MACRO

Deprecated macros.

MCUX_EXPERIMENTAL

Experimental APIs.

MCUX_EXPERIMENTAL_MACRO

Experimental macros.

enum _status_groups

Status group numbers.

Values:

enumerator kStatusGroup_Generic

Group number for generic status codes.

enumerator kStatusGroup_FLASH

Group number for FLASH status codes.

enumerator kStatusGroup_LPSPI

Group number for LPSPI status codes.

enumerator kStatusGroup_FLEXIO_SPI

Group number for FLEXIO SPI status codes.

enumerator kStatusGroup_DSPI

Group number for DSPI status codes.

enumerator kStatusGroup_FLEXIO_UART

Group number for FLEXIO UART status codes.

enumerator kStatusGroup_FLEXIO_I2C

Group number for FLEXIO I2C status codes.

enumerator kStatusGroup_LPI2C

Group number for LPI2C status codes.

enumerator kStatusGroup_UART

Group number for UART status codes.

enumerator kStatusGroup_I2C

Group number for UART status codes.

enumerator kStatusGroup_LPSCI

Group number for LPSCI status codes.

enumerator kStatusGroup_LPUART

Group number for LPUART status codes.

enumerator kStatusGroup_SPI

Group number for SPI status code.

enumerator kStatusGroup_XRDC

Group number for XRDC status code.

enumerator kStatusGroup_SEMA42

Group number for SEMA42 status code.

enumerator kStatusGroup_SDHC

Group number for SDHC status code

enumerator kStatusGroup_SDMMC

Group number for SDMMC status code

enumerator kStatusGroup_SAI

Group number for SAI status code

enumerator kStatusGroup_MCG

Group number for MCG status codes.

enumerator kStatusGroup_SCG

Group number for SCG status codes.

enumerator kStatusGroup_SDSPI

Group number for SDSPI status codes.

enumerator kStatusGroup_FLEXIO_I2S

Group number for FLEXIO I2S status codes

enumerator kStatusGroup_FLEXIO_MCULCD

Group number for FLEXIO LCD status codes

enumerator kStatusGroup_FLASHIAP

Group number for FLASHIAP status codes

enumerator kStatusGroup_FLEXCOMM_I2C

Group number for FLEXCOMM I2C status codes

enumerator kStatusGroup_I2S

Group number for I2S status codes

enumerator kStatusGroup_IUART

Group number for IUART status codes

enumerator kStatusGroup_CSI

Group number for CSI status codes

enumerator kStatusGroup_MIPI_DSI

Group number for MIPI DSI status codes

enumerator kStatusGroup_SDRAMC

Group number for SDRAMC status codes.

enumerator kStatusGroup_POWER

Group number for POWER status codes.

enumerator kStatusGroup_ENET

Group number for ENET status codes.

enumerator kStatusGroup_PHY

Group number for PHY status codes.

enumerator kStatusGroup_TRGMUX

Group number for TRGMUX status codes.

enumerator kStatusGroup_SMARTCARD

Group number for SMARTCARD status codes.

enumerator kStatusGroup_LMEM

Group number for LMEM status codes.

enumerator kStatusGroup_QSPI

Group number for QSPI status codes.

enumerator kStatusGroup_DMA

Group number for DMA status codes.

enumerator kStatusGroup_EDMA

Group number for EDMA status codes.

enumerator kStatusGroup_DMAMGR

Group number for DMAMGR status codes.

enumerator kStatusGroup_FLEXCAN

Group number for FlexCAN status codes.

enumerator kStatusGroup_LTC

Group number for LTC status codes.

enumerator kStatusGroup_FLEXIO_CAMERA

Group number for FLEXIO CAMERA status codes.

enumerator kStatusGroup_LPC_SPI

Group number for LPC_SPI status codes.

enumerator kStatusGroup_LPC_USART

Group number for LPC_USART status codes.

enumerator kStatusGroup_DMIC

Group number for DMIC status codes.

enumerator kStatusGroup_SDIF

Group number for SDIF status codes.

enumerator kStatusGroup_SPIFI

Group number for SPIFI status codes.

enumerator kStatusGroup_OTP

Group number for OTP status codes.

enumerator kStatusGroup_MCAN

Group number for MCAN status codes.

enumerator kStatusGroup_CAAM

Group number for CAAM status codes.

enumerator kStatusGroup_ECSPI

Group number for ECSPI status codes.

enumerator kStatusGroup_USDHC

Group number for USDHC status codes.

enumerator kStatusGroup_LPC_I2C

Group number for LPC_I2C status codes.

enumerator kStatusGroup_DCP

Group number for DCP status codes.

enumerator kStatusGroup_MSCAN

Group number for MSCAN status codes.

enumerator kStatusGroup_ESAI

Group number for ESAI status codes.

enumerator kStatusGroup_FLEXSPI

Group number for FLEXSPI status codes.

enumerator kStatusGroup_MMDC

Group number for MMDC status codes.

enumerator kStatusGroup_PDM

Group number for MIC status codes.

enumerator kStatusGroup_SDMA

Group number for SDMA status codes.

enumerator kStatusGroup_ICS

Group number for ICS status codes.

enumerator kStatusGroup_SPDIF

Group number for SPDIF status codes.

enumerator kStatusGroup_LPC_MINISPI

Group number for LPC_MINISPI status codes.

enumerator kStatusGroup_HASHCRYPT

Group number for Hashcrypt status codes

enumerator kStatusGroup_LPC_SPI_SSP

Group number for LPC_SPI_SSP status codes.

enumerator kStatusGroup_I3C

Group number for I3C status codes

enumerator kStatusGroup_LPC_I2C_1

Group number for LPC_I2C_1 status codes.

enumerator kStatusGroup_NOTIFIER

Group number for NOTIFIER status codes.

enumerator kStatusGroup_DebugConsole

Group number for debug console status codes.

enumerator kStatusGroup_SEMC

Group number for SEMC status codes.

enumerator kStatusGroup_ApplicationRangeStart

Starting number for application groups.

enumerator kStatusGroup_IAP

Group number for IAP status codes

enumerator kStatusGroup_SFA

Group number for SFA status codes

enumerator kStatusGroup_SPC

Group number for SPC status codes.

enumerator kStatusGroup_PUF

Group number for PUF status codes.

enumerator kStatusGroup_TOUCH_PANEL

Group number for touch panel status codes

enumerator kStatusGroup_VBAT

Group number for VBAT status codes

enumerator kStatusGroup_XSPI

Group number for XSPI status codes

enumerator kStatusGroup_PNGDEC

Group number for PNGDEC status codes

enumerator kStatusGroup_JPEGDEC

Group number for JPEGDEC status codes

enumerator kStatusGroup_AUDMIX

Group number for AUDMIX status codes

enumerator kStatusGroup_HAL_GPIO

Group number for HAL GPIO status codes.

enumerator kStatusGroup_HAL_UART

Group number for HAL UART status codes.

enumerator kStatusGroup_HAL_TIMER

Group number for HAL TIMER status codes.

enumerator kStatusGroup_HAL_SPI

Group number for HAL SPI status codes.

enumerator kStatusGroup_HAL_I2C

Group number for HAL I2C status codes.

enumerator kStatusGroup_HAL_FLASH

Group number for HAL FLASH status codes.

enumerator kStatusGroup_HAL_PWM

Group number for HAL PWM status codes.

enumerator kStatusGroup_HAL_RNG

Group number for HAL RNG status codes.

enumerator kStatusGroup_HAL_I2S

Group number for HAL I2S status codes.

enumerator kStatusGroup_HAL_ADC_SENSOR

Group number for HAL ADC SENSOR status codes.

enumerator kStatusGroup_TIMERMANAGER

Group number for TiMER MANAGER status codes.

enumerator kStatusGroup_SERIALMANAGER

Group number for SERIAL MANAGER status codes.

enumerator kStatusGroup_LED

Group number for LED status codes.

enumerator kStatusGroup_BUTTON

Group number for BUTTON status codes.

enumerator kStatusGroup_EXTERN_EEPROM

Group number for EXTERN EEPROM status codes.

enumerator kStatusGroup_SHELL

Group number for SHELL status codes.

enumerator kStatusGroup_MEM_MANAGER

Group number for MEM MANAGER status codes.

enumerator kStatusGroup_LIST

Group number for List status codes.

enumerator kStatusGroup_OSA

Group number for OSA status codes.

enumerator kStatusGroup_COMMON_TASK

Group number for Common task status codes.

enumerator kStatusGroup_MSG

Group number for messaging status codes.

enumerator kStatusGroup_SDK_OCOTP

Group number for OCOTP status codes.

enumerator kStatusGroup_SDK_FLEXSPINOR

Group number for FLEXSPINOR status codes.

enumerator kStatusGroup_CODEC

Group number for codec status codes.

enumerator kStatusGroup_ASRC

Group number for codec status ASRC.

enumerator kStatusGroup_OTFAD

Group number for codec status codes.

enumerator kStatusGroup_SDIOSLV

Group number for SDIOSLV status codes.

enumerator kStatusGroup_MECC

Group number for MECC status codes.

enumerator kStatusGroup_ENET_QOS

Group number for ENET_QOS status codes.

enumerator kStatusGroup_LOG

Group number for LOG status codes.

enumerator kStatusGroup_I3CBUS

Group number for I3CBUS status codes.

enumerator kStatusGroup_QSCI

Group number for QSCI status codes.

enumerator kStatusGroup_ELEMU

Group number for ELEMU status codes.

enumerator kStatusGroup_QUEUEDSPI

Group number for QSPI status codes.

enumerator kStatusGroup_POWER_MANAGER

Group number for POWER_MANAGER status codes.

enumerator kStatusGroup_IPED

Group number for IPED status codes.

enumerator kStatusGroup_ELS_PKC

Group number for ELS PKC status codes.

enumerator kStatusGroup_CSS_PKC

Group number for CSS PKC status codes.

enumerator kStatusGroup_HOSTIF

Group number for HOSTIF status codes.

enumerator kStatusGroup_CLIF

Group number for CLIF status codes.

enumerator kStatusGroup_BMA

Group number for BMA status codes.

enumerator kStatusGroup_NETC

Group number for NETC status codes.

enumerator kStatusGroup_ELE

Group number for ELE status codes.

enumerator kStatusGroup_GLIKEY

Group number for GLIKEY status codes.

enumerator kStatusGroup_AON_POWER

Group number for AON_POWER status codes.

enumerator kStatusGroup_AON_COMMON

Group number for AON_COMMON status codes.

enumerator kStatusGroup_ENDAT3

Group number for ENDAT3 status codes.

enumerator kStatusGroup_HIPERFACE

Group number for HIPERFACE status codes.

enumerator kStatusGroup_NPX

Group number for NPX status codes.

enumerator kStatusGroup_ELA_CSEC

Group number for ELA_CSEC status codes.

enumerator kStatusGroup_FLEXIO_T_FORMAT

Group number for T-format status codes.

enumerator kStatusGroup_FLEXIO_A_FORMAT

Group number for A-format status codes.

enumerator kStatusGroup_LPC_QSPI

Group number for LPC QSPI status codes.

enumerator kStatusGroup_EVENT_CTRL

Group number for Event controller status codes.

Generic status return codes.

Values:

enumerator kStatus_Success

Generic status for Success.

enumerator kStatus_Fail

Generic status for Fail.

enumerator kStatus_ReadOnly

Generic status for read only failure.

enumerator kStatus_OutOfRange

Generic status for out of range access.

enumerator kStatus_InvalidArgument

Generic status for invalid argument check.

enumerator kStatus_Timeout

Generic status for timeout.

enumerator kStatus_NoTransferInProgress

Generic status for no transfer in progress.

enumerator kStatus_Busy

Generic status for module is busy.

enumerator kStatus_NoData

Generic status for no data is found for the operation.

typedef int32_t status_t

Type used for all status and error return values.

void *SDK_Malloc(size_t size, size_t alignbytes)

Allocate memory with given alignment and aligned size.

This is provided to support the dynamically allocated memory used in cache-able region.

Parameters:

• size – The length required to malloc.

• alignbytes – The alignment size.

Return values:

The – allocated memory.

void SDK_Free(void *ptr)

Free memory.

Parameters:

• ptr – The memory to be release.

void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

Parameters:

• delayTime_us – Delay time in unit of microsecond.

• coreClock_Hz – Core clock frequency with Hz.

static inline status_t EnableIRQ(IRQn_Type interrupt)

Enable specific interrupt.

Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ number.

Return values:

• kStatus_Success – Interrupt enabled successfully

• kStatus_Fail – Failed to enable the interrupt

static inline status_t DisableIRQ(IRQn_Type interrupt)

Disable specific interrupt.

Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ number.

Return values:

• kStatus_Success – Interrupt disabled successfully

• kStatus_Fail – Failed to disable the interrupt

static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)

Enable the IRQ, and also set the interrupt priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ to Enable.

• priNum – Priority number set to interrupt controller register.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)

Set the IRQ priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The IRQ to set.

• priNum – Priority number set to interrupt controller register.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)

Clear the pending IRQ flag.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

• interrupt – The flag which IRQ to clear.

Return values:

• kStatus_Success – Interrupt priority set successfully

• kStatus_Fail – Failed to set the interrupt priority.

static inline uint32_t DisableGlobalIRQ(void)

Disable the global IRQ.

Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:

Current primask value.

static inline void EnableGlobalIRQ(uint32_t primask)

Enable the global IRQ.

Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

• primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ().

static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)

static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)

FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ

Macro to use the default weak IRQ handler in drivers.

MAKE_STATUS(group, code)

Construct a status code value from a group and code number.

MAKE_VERSION(major, minor, bugfix)

Construct the version number for drivers.

The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).

| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0

ARRAY_SIZE(x)

Computes the number of elements in an array.

SUPPRESS_FALL_THROUGH_WARNING()

For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement.

MSDK_REG_SECURE_ADDR(x)

Convert the register address to the one used in secure mode.

MSDK_REG_NONSECURE_ADDR(x)

Convert the register address to the one used in non-secure mode.

MSDK_HAS_DWT_CYCCNT

The chip supports DWT CYCCNT or not.

MSDK_INVALID_IRQ_HANDLER

Invalid IRQ handler address.

LPACMP: Low-Power Analog Comparator Driver

void LPACMP_Init(LPACMP_Type *base, const lpacmp_config_t *config)

Initialize the LPACMP module.

Parameters:

• base – LPACMP peripheral base address

• config – Pointer to the LPACMP configuration structure, please refer to lpacmp_config_t for details.

void LPACMP_GetDefaultConfig(lpacmp_config_t *config)

Gets an available pre-defined settings for LPACMP configuration.

Parameters:

• config – Pointer to the LPACMP configuration structure, please refer to lpacmp_config_t for details.

void LPACMP_Deinit(LPACMP_Type *base)

De-initializes the LPACMP module.

Parameters:

• base – LPACMP peripheral base address

static inline void LPACMP_EnableComparator(LPACMP_Type *base, bool enable)

Enable/Disable comparator module.

Parameters:

• base – LPACMP peripheral base address

• enable – Indicates whether to enable the comparator module true Enable the comparator module false Disable the comparator module

static inline void LPACMP_SetComparatorMode(LPACMP_Type *base, lpacmp_mode_t mode)

Set comparator mode.

Parameters:

• base – LPACMP peripheral base address

• mode – comparator mode

static inline void LPACMP_SetIntervalTime(LPACMP_Type *base, uint16_t time)

Compare event trigger interval time.

Parameters:

• base – LPACMP peripheral base address

• time – Compare event trigger interval time

static inline void LPACMP_ChannelInputSelection(LPACMP_Type *base, uint8_t channel, lpacmp_positive_input_t positive, lpacmp_negative_input_t negative)

Channel positive and negative input selection.

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

• positive – Positive input channel selection

• negative – Negative input channel selection

static inline void LPACMP_SetComparePolarity(LPACMP_Type *base, uint8_t channel, bool polarity)

Comparison polarity configuration.

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

• polarity – Comparison polarity

  • true When the value we are checking is higher than the reference value. input parameter ‘result’.

  • false When the value we are checking is lower than the reference value.

static inline void LPACMP_SetDelayValue(LPACMP_Type *base, uint8_t channel, uint16_t delay)

Compare event sample delay value.

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

• delay – Compare event sample delay value

static inline void LPACMP_SetTriggerOutputWidth(LPACMP_Type *base, uint8_t channel, uint8_t width)

Set the trigger output width in clock units.

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

• width – trigger output width

static inline void LPACMP_EnableWakeupToSmm(LPACMP_Type *base, uint8_t channel, bool enable)

Enable/Disable wakeup to SMM.

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

• enable – Indicates whether to enable the comparator module

  • true Enable the comparator module

  • false Disable the comparator module

static inline void LPACMP_EnableTriggerOutput(LPACMP_Type *base, uint8_t channel, bool enable)

Enable/Disable trigger output.

Parameters:

• base – LPACMP peripheral base address

• channel – Channel index (0-3)

• enable – Indicates whether to enable the trigger output

  • true Enable the trigger output

  • false Disable the trigger output

static inline void LPACMP_EnableChannel(LPACMP_Type *base, uint8_t channel, bool enable)

Enable/Disable channel.

Parameters:

• base – LPACMP peripheral base address

• channel – Channel index (0-3)

• enable – Indicates whether to enable the trigger output true Enable the trigger output false Disable the trigger output

static inline void LPACMP_EnableInterrupt(LPACMP_Type *base, uint8_t channel, bool enable)

Enable/Disable match interrupt for specific channel.

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

• enable – Indicates whether to enable or disable the match interrupt true Enable the match interrupt false Disable the match interrupt

static inline void LPACMP_ClearInterruptStatusFlags(LPACMP_Type *base, uint8_t channel)

Clear comparison interrupt status flags.

Remark

Uses Write-1-to-Clear (W1C) mechanism

Parameters:

• base – LPACMP peripheral base address

• channel – Trigger channel index (0-3)

static inline uint32_t LPACMP_GetInterruptStatusFlags(LPACMP_Type *base)

Get the comparison interrupt status flag.

Parameters:

• base – LPACMP peripheral base address

Returns:

Comparison interrupt status flags

FSL_LPACMP_DRIVER_VERSION

LPACMP driver version.

enum _lpacmp_negative_input

Comparator negative input source.

Values:

enumerator kLPACMP_Negative_Input_Avdd_Divide_15

Comparator negative input source 1 x AVDD / 15

enumerator kLPACMP_Negative_Input_2Avdd_Divide_15

Comparator negative input source 2 x AVDD / 15

enumerator kLPACMP_Negative_Input_3Avdd_Divide_15

Comparator negative input source 3 x AVDD / 15

enumerator kLPACMP_Negative_Input_4Avdd_Divide_15

Comparator negative input source 4 x AVDD / 15

enumerator kLPACMP_Negative_Input_5Avdd_Divide_15

Comparator negative input source 5 x AVDD / 15

enumerator kLPACMP_Negative_Input_6Avdd_Divide_15

Comparator negative input source 6 x AVDD / 15

enumerator kLPACMP_Negative_Input_7Avdd_Divide_15

Comparator negative input source 7 x AVDD / 15

enumerator kLPACMP_Negative_Input_8Avdd_Divide_15

Comparator negative input source 8 x AVDD / 15

enumerator kLPACMP_Negative_Input_9Avdd_Divide_15

Comparator negative input source 9 x AVDD / 15

enumerator kLPACMP_Negative_Input_10Avdd_Divide_15

Comparator negative input source 10 x AVDD / 15

enumerator kLPACMP_Negative_Input_11Avdd_Divide_15

Comparator negative input source 11 x AVDD / 15

enumerator kLPACMP_Negative_Input_12Avdd_Divide_15

Comparator negative input source 12 x AVDD / 15

enumerator kLPACMP_Negative_Input_13Avdd_Divide_15

Comparator negative input source 13 x AVDD / 15

enumerator kLPACMP_Negative_Input_14Avdd_Divide_15

Comparator negative input source 14 x AVDD / 15

enumerator kLPACMP_Negative_Input_In4

Comparator negative input source 4

enumerator kLPACMP_Negative_Input_In5

Comparator negative input source 5

enum _lpacmp_positive_input

Comparator positive input source.

Values:

enumerator kLPACMP_Positive_Input_In4

Comparator positive input source 4

enumerator kLPACMP_Positive_Input_In5

Comparator positive input source 5

enumerator kLPACMP_Positive_Input_In0

Comparator positive input source 0

enumerator kLPACMP_Positive_Input_In1

Comparator positive input source 1

enumerator kLPACMP_Positive_Input_In2

Comparator positive input source 2

enumerator kLPACMP_Positive_Input_In3

Comparator positive input source 3

enum _lpacmp_mode

Comparator operation modes.

Values:

enumerator kLPACMP_Continuous_Mode

Always-on comparison

enumerator kLPACMP_Interval_Mode

Periodic sampling with internal timer

enumerator kLPACMP_Trigger_Mode

External trigger activation

typedef enum _lpacmp_negative_input lpacmp_negative_input_t

Comparator negative input source.

typedef enum _lpacmp_positive_input lpacmp_positive_input_t

Comparator positive input source.

typedef enum _lpacmp_mode lpacmp_mode_t

Comparator operation modes.

typedef struct _lpacmp_channel_config lpacmp_channel_config_t

Channel configuration structure.

typedef struct _lpacmp_config lpacmp_config_t

Comparator configuration structure.

struct _lpacmp_channel_config

#include <fsl_lpacmp.h>

Channel configuration structure.

Public Members

bool enableWakeupToSmm

Decides whether to enable wakeup to SMM

bool enableTriggerOutput

Decides whether to enable trigger output

bool enableInterrupt

Decides whether to enable match interrupt

bool comparePolarityHigher

Decides comparison polarity

uint8_t channelIndex

Indicates the channel being configured

uint8_t triggerOutputWidth

Sets trigger output width

uint16_t delay

Sets the delay value for which a compare event is sampled

lpacmp_positive_input_t positiveInput

Positive input selection (see RM SELn.INP_SEL)

lpacmp_negative_input_t negativeInput

Negative input selection (see RM SELn.INN_SEL)

struct _lpacmp_config

#include <fsl_lpacmp.h>

Comparator configuration structure.

Public Members

uint8_t channelCount

Indicates the channel counts

uint16_t intervalTime

Indicates the interval time

lpacmp_mode_t mode

Operating mode

lpacmp_channel_config_t *channelConfig

Channel configuration

LPADC: 12-bit SAR Analog-to-Digital Converter Driver

enum _lpadc_status_flags

Define hardware flags of the module.

Values:

enumerator kLPADC_ResultFIFO0OverflowFlag

Indicates that more data has been written to the Result FIFO 0 than it can hold.

enumerator kLPADC_ResultFIFO0ReadyFlag

Indicates when the number of valid datawords in the result FIFO 0 is greater than the setting watermark level.

enumerator kLPADC_TriggerExceptionFlag

Indicates that a trigger exception event has occurred.

enumerator kLPADC_TriggerCompletionFlag

Indicates that a trigger completion event has occurred.

enumerator kLPADC_CalibrationReadyFlag

Indicates that the calibration process is done.

enumerator kLPADC_ActiveFlag

Indicates that the ADC is in active state.

enumerator kLPADC_ResultFIFOOverflowFlag

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowFlag as instead.

enumerator kLPADC_ResultFIFOReadyFlag

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0ReadyFlag as instead.

enum _lpadc_interrupt_enable

Define interrupt switchers of the module.

Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.

Values:

enumerator kLPADC_ResultFIFO0OverflowInterruptEnable

Configures ADC to generate overflow interrupt requests when FOF0 flag is asserted.

enumerator kLPADC_FIFO0WatermarkInterruptEnable

Configures ADC to generate watermark interrupt requests when RDY0 flag is asserted.

enumerator kLPADC_ResultFIFOOverflowInterruptEnable

To compilitable with old version, do not recommend using this, please use kLPADC_ResultFIFO0OverflowInterruptEnable as instead.

enumerator kLPADC_FIFOWatermarkInterruptEnable

To compilitable with old version, do not recommend using this, please use kLPADC_FIFO0WatermarkInterruptEnable as instead.

enumerator kLPADC_TriggerExceptionInterruptEnable

Configures ADC to generate trigger exception interrupt.

enumerator kLPADC_Trigger0CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 0 completion.

enumerator kLPADC_Trigger1CompletionInterruptEnable

Configures ADC to generate interrupt when trigger 1 completion.

enum _lpadc_trigger_status_flags

The enumerator of lpadc trigger status flags, including interrupted flags and completed flags.

Note: LPADC of different chips supports different number of trigger sources, please check the Reference Manual for details.

Values:

enumerator kLPADC_Trigger0InterruptedFlag

Trigger 0 is interrupted by a high priority exception.

enumerator kLPADC_Trigger1InterruptedFlag

Trigger 1 is interrupted by a high priority exception.

enumerator kLPADC_Trigger0CompletedFlag

Trigger 0 is completed and trigger 0 has enabled completion interrupts.

enumerator kLPADC_Trigger1CompletedFlag

Trigger 1 is completed and trigger 1 has enabled completion interrupts.

enum _lpadc_sample_scale_mode

Define enumeration of sample scale mode.

The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.

Values:

enumerator kLPADC_SamplePartScale

Use divided input voltage signal. (For scale select,please refer to the reference manual).

enumerator kLPADC_SampleFullScale

Full scale (Factor of 1).

enum _lpadc_sample_channel_mode

Define enumeration of channel sample mode.

The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.

Values:

enumerator kLPADC_SampleChannelSingleEndSideA

Single-end mode, only A-side channel is converted.

enumerator kLPADC_SampleChannelSingleEndSideB

Single-end mode, only B-side channel is converted.

enumerator kLPADC_SampleChannelDiffBothSideAB

Differential mode, the ADC result is (CHnA-CHnB).

enumerator kLPADC_SampleChannelDiffBothSideBA

Differential mode, the ADC result is (CHnB-CHnA).

enumerator kLPADC_SampleChannelDiffBothSide

Differential mode, the ADC result is (CHnA-CHnB).

enumerator kLPADC_SampleChannelDualSingleEndBothSide

Dual-Single-Ended Mode. Both A side and B side channels are converted independently.

enum _lpadc_hardware_average_mode

Define enumeration of hardware average selection.

It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.

Note

Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.

Values:

enumerator kLPADC_HardwareAverageCount1

Single conversion.

enumerator kLPADC_HardwareAverageCount2

2 conversions averaged.

enumerator kLPADC_HardwareAverageCount4

4 conversions averaged.

enumerator kLPADC_HardwareAverageCount8

8 conversions averaged.

enumerator kLPADC_HardwareAverageCount16

16 conversions averaged.

enumerator kLPADC_HardwareAverageCount32

32 conversions averaged.

enumerator kLPADC_HardwareAverageCount64

64 conversions averaged.

enumerator kLPADC_HardwareAverageCount128

128 conversions averaged.

enum _lpadc_sample_time_mode

Define enumeration of sample time selection.

The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.

Values:

enumerator kLPADC_SampleTimeADCK3

3 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK5

5 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK7

7 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK11

11 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK19

19 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK35

35 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK67

69 ADCK cycles total sample time.

enumerator kLPADC_SampleTimeADCK131

131 ADCK cycles total sample time.

enum _lpadc_hardware_compare_mode

Define enumeration of hardware compare mode.

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

Values:

enumerator kLPADC_HardwareCompareDisabled

Compare disabled.

enumerator kLPADC_HardwareCompareStoreOnTrue

Compare enabled. Store on true.

enumerator kLPADC_HardwareCompareRepeatUntilTrue

Compare enabled. Repeat channel acquisition until true.

enum _lpadc_conversion_resolution_mode

Define enumeration of conversion resolution mode.

Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t

Values:

enumerator kLPADC_ConversionResolutionStandard

Standard resolution. Single-ended 12-bit conversion, Differential 13-bit conversion with 2’s complement output.

enumerator kLPADC_ConversionResolutionHigh

High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2’s complement output.

enum _lpadc_conversion_average_mode

Define enumeration of conversion averages mode.

Configure the converion average number for auto-calibration.

Note

Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.

Values:

enumerator kLPADC_ConversionAverage1

Single conversion.

enumerator kLPADC_ConversionAverage2

2 conversions averaged.

enumerator kLPADC_ConversionAverage4

4 conversions averaged.

enumerator kLPADC_ConversionAverage8

8 conversions averaged.

enumerator kLPADC_ConversionAverage16

16 conversions averaged.

enumerator kLPADC_ConversionAverage32

32 conversions averaged.

enumerator kLPADC_ConversionAverage64

64 conversions averaged.

enumerator kLPADC_ConversionAverage128

128 conversions averaged.

enumerator kLPADC_ConversionAverageMax

enum _lpadc_reference_voltage_mode

Define enumeration of reference voltage source.

For detail information, need to check the SoC’s specification.

Values:

enumerator kLPADC_ReferenceVoltageAlt1

Option 1 setting.

enumerator kLPADC_ReferenceVoltageAlt2

Option 2 setting.

enumerator kLPADC_ReferenceVoltageAlt3

Option 3 setting.

enum _lpadc_power_level_mode

Define enumeration of power configuration.

Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.

Values:

enumerator kLPADC_PowerLevelAlt1

Lowest power setting.

enumerator kLPADC_PowerLevelAlt2

Next lowest power setting.

enumerator kLPADC_PowerLevelAlt3

…

enumerator kLPADC_PowerLevelAlt4

Highest power setting.

enum _lpadc_offset_calibration_mode

Define enumeration of offset calibration mode.

Values:

enumerator kLPADC_OffsetCalibration12bitMode

12 bit offset calibration mode.

enumerator kLPADC_OffsetCalibration16bitMode

16 bit offset calibration mode.

enum _lpadc_trigger_priority_policy

Define enumeration of trigger priority policy.

This selection controls how higher priority triggers are handled.

Note

kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.

Values:

enumerator kLPADC_ConvPreemptImmediatelyNotAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion is not automatically resumed or restarted.

enumerator kLPADC_ConvPreemptSoftlyNotAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion is not resumed or restarted.

enumerator kLPADC_ConvPreemptImmediatelyAutoRestarted

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kLPADC_ConvPreemptSoftlyAutoRestarted

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will automatically be restarted.

enumerator kLPADC_ConvPreemptImmediatelyAutoResumed

If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started, when higher priority conversion finishes, the preempted conversion will automatically be resumed.

enumerator kLPADC_ConvPreemptSoftlyAutoResumed

If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the result FIFO before the higher priority trigger/command is initiated, when higher priority conversion finishes, the preempted conversion will be automatically be resumed.

enumerator kLPADC_TriggerPriorityPreemptImmediately

Legacy support is not recommended as it only ensures compatibility with older versions.

enumerator kLPADC_TriggerPriorityPreemptSoftly

Legacy support is not recommended as it only ensures compatibility with older versions.

enumerator kLPADC_TriggerPriorityExceptionDisabled

High priority trigger exception disabled.

enum _lpadc_tune_value

Define enumeration of tune value.

Values:

enumerator kLPADC_TuneValue0

Tune value 0.

enumerator kLPADC_TuneValue1

Tune value 1.

enumerator kLPADC_TuneValue2

Tune value 2.

enumerator kLPADC_TuneValue3

Tune value 3.

typedef enum _lpadc_sample_scale_mode lpadc_sample_scale_mode_t

Define enumeration of sample scale mode.

The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.

typedef enum _lpadc_sample_channel_mode lpadc_sample_channel_mode_t

Define enumeration of channel sample mode.

The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.

typedef enum _lpadc_hardware_average_mode lpadc_hardware_average_mode_t

Define enumeration of hardware average selection.

It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to capture temporary results while the averaging iterations are executed.

Note

Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH register.

typedef enum _lpadc_sample_time_mode lpadc_sample_time_mode_t

Define enumeration of sample time selection.

The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption when command looping and sequencing is configured and high conversion rates are not required.

typedef enum _lpadc_hardware_compare_mode lpadc_hardware_compare_mode_t

Define enumeration of hardware compare mode.

After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting guides operation of the automatic compare function to optionally only store when the compare operation is true. When compare is enabled, the conversion result is compared to the compare values.

typedef enum _lpadc_conversion_resolution_mode lpadc_conversion_resolution_mode_t

Define enumeration of conversion resolution mode.

Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to lpadc_sample_channel_mode_t

typedef enum _lpadc_conversion_average_mode lpadc_conversion_average_mode_t

Define enumeration of conversion averages mode.

Configure the converion average number for auto-calibration.

Note

Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL register.

typedef enum _lpadc_reference_voltage_mode lpadc_reference_voltage_source_t

Define enumeration of reference voltage source.

For detail information, need to check the SoC’s specification.

typedef enum _lpadc_power_level_mode lpadc_power_level_mode_t

Define enumeration of power configuration.

Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be possible. Refer to the device data sheet for power and performance capabilities for each setting.

typedef enum _lpadc_offset_calibration_mode lpadc_offset_calibration_mode_t

Define enumeration of offset calibration mode.

typedef enum _lpadc_trigger_priority_policy lpadc_trigger_priority_policy_t

Define enumeration of trigger priority policy.

This selection controls how higher priority triggers are handled.

Note

kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of TPRICTRL field in CFG register.

typedef enum _lpadc_tune_value lpadc_tune_value_t

Define enumeration of tune value.

typedef struct _lpadc_calibration_value lpadc_calibration_value_t

A structure of calibration value.

LPADC_CONVERSION_COMPLETE_TIMEOUT

Max loops to wait for LPADC conversion complete.

When doing calibration, driver will wait for the completion of conversion. This parameter defines how many loops to check completion before return timeout. If defined as 0, driver will wait forever until completion.

LPADC_CALIBRATION_READY_TIMEOUT

Max loops to wait for LPADC calibration ready.

Before doing calibration, driver will wait for the calibration ready. This parameter defines how many loops to check the calibration ready. If defined as 0, driver will wait forever until ready.

LPADC_GAIN_CAL_READY_TIMEOUT

Max loops to wait for LPADC gain calibration GAIN_CAL ready.

Before doing calibration, driver will wait for the gain calibration GAIN_CAL ready. This parameter defines how many loops to check the gain calibration GAIN_CAL ready. If defined as 0, driver will wait forever until ready.

LPADC_USE_FIXED_POINT_GAIN_CALCULATION

Use fixed point arithmetic for the auto-calibration gain calculation.

When set to 1, LPADC_FinishAutoCalibration() calculates the gain conversion result with integer-only arithmetic instead of the float/double software library, which saves several kB of flash on code size sensitive devices. The fixed point result keeps the gain fraction in Q17.14, so the two least significant bits of the gain conversion result are always zero.

ADC_OFSTRIM_OFSTRIM_MAX

ADC_OFSTRIM_OFSTRIM_SIGN

LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal)

Define the MACRO function to get command status from status value.

The statusVal is the return value from LPADC_GetStatusFlags().

LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal)

Define the MACRO function to get trigger status from status value.

The statusVal is the return value from LPADC_GetStatusFlags().

void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)

Initializes the LPADC module.

Parameters:

• base – LPADC peripheral base address.

• config – Pointer to configuration structure. See “lpadc_config_t”.

void LPADC_GetDefaultConfig(lpadc_config_t *config)

Gets an available pre-defined settings for initial configuration.

This function initializes the converter configuration structure with an available settings. The default values are:

config->enableInDozeMode        = true;
config->enableAnalogPreliminary = false;
config->powerUpDelay            = 0x80;
config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
config->powerLevelMode          = kLPADC_PowerLevelAlt1;
config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
config->enableConvPause         = false;
config->convPauseDelay          = 0U;
config->FIFOWatermark           = 0U;

Parameters:

• config – Pointer to configuration structure.

void LPADC_Deinit(ADC_Type *base)

De-initializes the LPADC module.

Parameters:

• base – LPADC peripheral base address.

static inline void LPADC_Enable(ADC_Type *base, bool enable)

Switch on/off the LPADC module.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the module.

static inline void LPADC_DoResetFIFO(ADC_Type *base)

Do reset the conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

static inline void LPADC_DoResetConfig(ADC_Type *base)

Do reset the module’s configuration.

Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).

Parameters:

• base – LPADC peripheral base address.

static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)

Get status flags.

Parameters:

• base – LPADC peripheral base address.

Returns:

status flags’ mask. See to _lpadc_status_flags.

static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)

Clear status flags.

Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for flags to be cleared. See to _lpadc_status_flags.

static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)

Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high priority trigger exception.

Note

On some devices, the trigger completion status may be asserted before the final command in a chained trigger sequence starts to execute. When using chained commands, do not rely on trigger completion status alone to guarantee that all conversion results are already available in the FIFO. Use FIFO ready indication together with result tags, or stall the last command with WAIT_TRIG when that sequencing model is acceptable for the application.

Parameters:

• base – LPADC peripheral base address.

Returns:

The OR’ed value of _lpadc_trigger_status_flags.

static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)

Clear trigger status flags.

Parameters:

• base – LPADC peripheral base address.

• mask – The mask of trigger status flags to be cleared, should be the OR’ed value of _lpadc_trigger_status_flags.

static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)

Enable interrupts.

Note

When enabling trigger completion interrupts (kLPADC_TriggerXCompletionInterruptEnable) on some devices, the interrupt may occur before the final command in a chained trigger sequence starts to execute. For multi-command trigger sequences, do not use the trigger completion interrupt alone as the indication that all expected results are already stored in the FIFO.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.

static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)

Disable interrupts.

Parameters:

• base – LPADC peripheral base address.

• mask – Mask value for interrupt events. See to _lpadc_interrupt_enable.

static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)

Switch on/off the DMA trigger for FIFO watermark event.

Parameters:

• base – LPADC peripheral base address.

• enable – Switcher to the event.

static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)

Get the count of result kept in conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

Returns:

The count of result kept in conversion FIFO.

bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)

Get the result in conversion FIFO.

Parameters:

• base – LPADC peripheral base address.

• result – Pointer to structure variable that keeps the conversion result in conversion FIFO.

Returns:

Status whether FIFO entry is valid.

void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)

Get the result in conversion FIFO using blocking method.

Parameters:

• base – LPADC peripheral base address.

• result – Pointer to structure variable that keeps the conversion result in conversion FIFO.

void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)

Configure the conversion trigger source.

Each programmable trigger can launch the conversion command in command buffer.

Parameters:

• base – LPADC peripheral base address.

• triggerId – ID for each trigger. Typically, the available value range is from 0.

• config – Pointer to configuration structure. See to lpadc_conv_trigger_config_t.

void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)

Gets an available pre-defined settings for trigger’s configuration.

This function initializes the trigger’s configuration structure with an available settings. The default values are:

config->targetCommandId        = 0U;
config->delayPower             = 0U;
config->priority               = 0U;
config->channelAFIFOSelect     = 0U;
config->channelBFIFOSelect     = 0U;
config->enableHardwareTrigger  = false;

Parameters:

• config – Pointer to configuration structure.

static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)

Do software trigger to conversion command.

Parameters:

• base – LPADC peripheral base address.

• triggerIdMask – Mask value for software trigger indexes, which count from zero.

static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable)

Enable hardware trigger command selection.

This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL].

Parameters:

• base – LPADC peripheral base address.

• triggerId – ID for each trigger. Typically, the available value range is from 0.

• enable – True to enable or flase to disable.

void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config)

Configure conversion command.

Note

The number of compare value register on different chips is different, that is mean in some chips, some command buffers do not have the compare functionality.

Parameters:

• base – LPADC peripheral base address.

• commandId – ID for command in command buffer. Typically, the available value range is 1 - 15.

• config – Pointer to configuration structure. See to lpadc_conv_command_config_t.

void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)

Gets an available pre-defined settings for conversion command’s configuration.

This function initializes the conversion command’s configuration structure with an available settings. The default values are:

config->sampleScaleMode            = kLPADC_SampleFullScale;
config->channelBScaleMode          = kLPADC_SampleFullScale;
config->sampleChannelMode          = kLPADC_SampleChannelSingleEndSideA;
config->channelNumber              = 0U;
config->channelBNumber             = 0U;
config->chainedNextCommandNumber   = 0U;
config->enableAutoChannelIncrement = false;
config->loopCount                  = 0U;
config->hardwareAverageMode        = kLPADC_HardwareAverageCount1;
config->sampleTimeMode             = kLPADC_SampleTimeADCK3;
config->hardwareCompareMode        = kLPADC_HardwareCompareDisabled;
config->hardwareCompareValueHigh   = 0U;
config->hardwareCompareValueLow    = 0U;
config->conversionResolutionMode   = kLPADC_ConversionResolutionStandard;
config->enableWaitTrigger          = false;
config->enableChannelB             = false;

Parameters:

• config – Pointer to configuration structure.

void LPADC_EnableCalibration(ADC_Type *base, bool enable)

Enable the calibration function.

When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the calibration function.

static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)

Set proper offset value to trim ADC.

To minimize the offset during normal operation, software should read the conversion result from the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.

Parameters:

• base – LPADC peripheral base address.

• value – Setting offset value.

status_t LPADC_DoAutoCalibration(ADC_Type *base)

Do auto calibration.

Calibration function should be executed before using converter in application. It used the software trigger and a dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including:

• LPADC_EnableCalibration(…)

• LPADC_SetOffsetValue(…)

• LPADC_SetConvCommandConfig(…)

• LPADC_SetConvTriggerConfig(…)

Parameters:

• base – LPADC peripheral base address.

• base – LPADC peripheral base address.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value)

Set trim value for offset.

Note

For 16-bit conversions, each increment is 1/2 LSB resulting in a programmable offset range of -256 LSB to 255.5 LSB; For 12-bit conversions, each increment is 1/32 LSB resulting in a programmable offset range of -16 LSB to 15.96875 LSB.

Parameters:

• base – LPADC peripheral base address.

• value – Offset trim value, is a 10-bit signed value between -512 and 511.

static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue)

Get trim value of offset.

Parameters:

• base – LPADC peripheral base address.

• pValue – Pointer to the variable in type of int16_t to store offset value.

static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)

Enable the offset calibration function.

Parameters:

• base – LPADC peripheral base address.

• enable – switcher to the calibration function.

static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode)

Set offset calibration mode.

Parameters:

• base – LPADC peripheral base address.

• mode – set offset calibration mode.see to lpadc_offset_calibration_mode_t .

status_t LPADC_DoOffsetCalibration(ADC_Type *base)

Do offset calibration.

Parameters:

• base – LPADC peripheral base address.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

void LPADC_PrepareAutoCalibration(ADC_Type *base)

Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function.

Parameters:

• base – LPADC peripheral base address.

status_t LPADC_FinishAutoCalibration(ADC_Type *base)

Finish auto calibration start with LPADC_PrepareAutoCalibration.

Note

This feature is used for LPADC with CTRL[CALOFSMODE].

Parameters:

• base – LPADC peripheral base address.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue)

Get calibration value into the memory which is defined by invoker.

Note

Please note the ADC will be disabled temporary.

Note

This function should be used after finish calibration.

Parameters:

• base – LPADC peripheral base address.

• ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure, this memory block should be always powered on even in low power modes.

status_t LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue)

Set calibration value into ADC calibration registers.

Note

Please note the ADC will be disabled temporary.

Parameters:

• base – LPADC peripheral base address.

• ptrCalibrationValue – Pointer to lpadc_calibration_value_t structure which contains ADC’s calibration value.

Return values:

• kStatus_Success – Successfully configured.

• kStatus_Timeout – Timeout occurs while waiting completion.

static inline void LPADC_RequestHighSpeedModeTrim(ADC_Type *base)

Request high speed mode trim calculation.

Parameters:

• base – LPADC peripheral base address.

static inline int8_t LPADC_GetHighSpeedTrimValue(ADC_Type *base)

Get high speed mode trim value, the result is a 5-bit signed value between -16 and 15.

Note

The high speed mode trim value is used to minimize offset for high speed conversion.

Parameters:

• base – LPADC peripheral base address.

Returns:

The calculated high speed mode trim value.

static inline void LPADC_SetHighSpeedTrimValue(ADC_Type *base, int8_t trimValue)

Set high speed mode trim value.

Note

If is possible to set the trim value manually, but it is recommended to use the LPADC_RequestHighSpeedModeTrim.

Parameters:

• base – LPADC peripheral base address.

• trimValue – The trim value to be set.

static inline void LPADC_EnableHighSpeedConversionMode(ADC_Type *base, bool enable)

Enable/disable high speed conversion mode, if enabled conversions complete 2 or 3 ADCK cycles sooner compared to conversion cycle counts when high speed mode is disabled.

Parameters:

• base – LPADC peripheral base address.

• enable – Used to enable/disable high speed conversion mode:

  • true Enable high speed conversion mode;

  • false Disable high speed conversion mode.

static inline void LPADC_EnableExtraCycle(ADC_Type *base, bool enable)

Enable/disable an additional ADCK cycle to conversion.

Parameters:

• base – LPADC peripheral base address.

• enable – Used to enable/disable an additional ADCK cycle to conversion:

  • true Enable an additional ADCK cycle to conversion;

  • false Disable an additional ADCK cycle to conversion.

static inline void LPADC_SetTuneValue(ADC_Type *base, lpadc_tune_value_t tuneValue)

Set tune value which provides some variability in how many cycles are needed to complete a conversion.

Parameters:

• base – LPADC peripheral base address.

• tuneValue – The tune value to be set, please refer to lpadc_tune_value_t.

static inline lpadc_tune_value_t LPADC_GetTuneValue(ADC_Type *base)

Get tune value which provides some variability in how many cycles are needed to complete a conversion.

Parameters:

• base – LPADC peripheral base address.

Returns:

The tune value, please refer to lpadc_tune_value_t.

static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable)

Enable/disable left-justify format in 12-bit single-end mode.

Parameters:

• base – LPADC peripheral base address.

• enable – Used to enable/disable left-justify format in 12-bit single-end mode:

  • true Enable left-justify format in 12-bit single-end mode;

  • false Disable left-justify format in 12-bit single-end mode.

FSL_LPADC_DRIVER_VERSION

LPADC driver version 2.10.3.

struct lpadc_config_t

#include <fsl_lpadc.h>

LPADC global configuration.

This structure would used to keep the settings for initialization.

Public Members

bool enableInternalClock

Enables the internally generated clock source. The clock source is used in clock selection logic at the chip level and is optionally used for the ADC clock source.

bool enableVref1LowVoltage

If voltage reference option1 input is below 1.8V, it should be “true”. If voltage reference option1 input is above 1.8V, it should be “false”.

bool enableInDozeMode

Control system transition to Stop and Wait power modes while ADC is converting. When enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.

lpadc_conversion_average_mode_t conversionAverageMode

Auto-Calibration Averages.

bool enableAnalogPreliminary

ADC analog circuits are pre-enabled and ready to execute conversions without startup delays(at the cost of higher DC current consumption).

uint32_t powerUpDelay

When the analog circuits are not pre-enabled, the ADC analog circuits are only powered while the ADC is active and there is a counted delay defined by this field after an initial trigger transitions the ADC from its Idle state to allow time for the analog circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must result in a longer delay than the analog startup time.

lpadc_reference_voltage_source_t referenceVoltageSource

Selects the voltage reference high used for conversions.

lpadc_power_level_mode_t powerLevelMode

Power Configuration Selection.

lpadc_trigger_priority_policy_t triggerPriorityPolicy

Control how higher priority triggers are handled, see to lpadc_trigger_priority_policy_t.

bool enableConvPause

Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations, between commands in a sequence, and between conversions when command is executing in “Compare Until True” configuration.

uint32_t convPauseDelay

Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing function is enabled. The available value range is in 9-bit.

uint32_t FIFOWatermark

FIFOWatermark is a programmable threshold setting. When the number of datawords stored in the ADC Result FIFO is greater than the value in this field, the ready flag would be asserted to indicate stored data has reached the programmable threshold.

struct lpadc_conv_command_config_t

#include <fsl_lpadc.h>

Define structure to keep the configuration for conversion command.

Public Members

lpadc_sample_scale_mode_t sampleScaleMode

Sample scale mode.

lpadc_sample_scale_mode_t channelBScaleMode

Alternate channe B Scale mode.

lpadc_sample_channel_mode_t sampleChannelMode

Channel sample mode.

uint32_t channelNumber

Channel number, select the channel or channel pair.

uint32_t channelBNumber

Alternate Channel B number, select the channel.

uint32_t chainedNextCommandNumber

Selects the next command to be executed after this command completes. 1-15 is available, 0 is to terminate the chain after this command.

bool enableAutoChannelIncrement

Loop with increment: when disabled, the “loopCount” field selects the number of times the selected channel is converted consecutively; when enabled, the “loopCount” field defines how many consecutive channels are converted as part of the command execution.

uint32_t loopCount

Selects how many times this command executes before finish and transition to the next command or Idle state. Command executes LOOP+1 times. 0-15 is available.

lpadc_hardware_average_mode_t hardwareAverageMode

Hardware average selection.

lpadc_sample_time_mode_t sampleTimeMode

Sample time selection.

lpadc_hardware_compare_mode_t hardwareCompareMode

Hardware compare selection.

uint32_t hardwareCompareValueHigh

Compare Value High. The available value range is in 16-bit.

uint32_t hardwareCompareValueLow

Compare Value Low. The available value range is in 16-bit.

lpadc_conversion_resolution_mode_t conversionResolutionMode

Conversion resolution mode.

bool enableWaitTrigger

Wait for trigger assertion before execution: when disabled, this command will be automatically executed; when enabled, the active trigger must be asserted again before executing this command.

struct lpadc_conv_trigger_config_t

#include <fsl_lpadc.h>

Define structure to keep the configuration for conversion trigger.

Public Members

uint32_t targetCommandId

Select the command from command buffer to execute upon detect of the associated trigger event.

uint32_t delayPower

Select the trigger delay duration to wait at the start of servicing a trigger event. When this field is clear, then no delay is incurred. When this field is set to a non-zero value, the duration for the delay is 2^delayPower ADCK cycles. The available value range is 4-bit.

uint32_t priority

Sets the priority of the associated trigger source. If two or more triggers have the same priority level setting, the lower order trigger event has the higher priority. The lower value for this field is for the higher priority, the available value range is 1-bit.

bool enableHardwareTrigger

Enable hardware trigger source to initiate conversion on the rising edge of the input trigger source or not. THe software trigger is always available.

struct lpadc_conv_result_t

#include <fsl_lpadc.h>

Define the structure to keep the conversion result.

Public Members

uint32_t commandIdSource

Indicate the command buffer being executed that generated this result.

uint32_t loopCountIndex

Indicate the loop count value during command execution that generated this result.

uint32_t triggerIdSource

Indicate the trigger source that initiated a conversion and generated this result.

uint16_t convValue

Data result.

struct _lpadc_calibration_value

#include <fsl_lpadc.h>

A structure of calibration value.

Lpc_freqme

void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config)

Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle.

Parameters:

• base – FREQME peripheral base address.

• config – The pointer to module basic configuration, please refer to freq_measure_config_t.

void FREQME_GetDefaultConfig(freq_measure_config_t *config)

Get default configuration.

config->operateMode = kFREQME_FreqMeasurementMode;
config->operateModeAttribute.refClkScaleFactor = 0U;
config->enableContinuousMode                   = false;
config->startMeasurement                       = false;

Parameters:

• config – The pointer to module basic configuration, please refer to freq_measure_config_t.

static inline void FREQME_StartMeasurementCycle(FREQME_Type *base)

Start frequency or pulse width measurement process.

Parameters:

• base – FREQME peripheral base address.

static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base)

Force the termination of any measurement cycle currently in progress and resets RESULT or just reset RESULT if the module in idle state.

Parameters:

• base – FREQME peripheral base address.

static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable)

Enable/disable Continuous mode.

Parameters:

• base – FREQME peripheral base address.

• enable – Used to enable/disable continuous mode,

  • true Enable Continuous mode.

  • false Disable Continuous mode.

static inline bool FREQME_CheckContinuousMode(FREQME_Type *base)

Check whether continuous mode is enabled.

Parameters:

• base – FREQME peripheral base address.

Return values:

• True – Continuous mode is enabled, the measurement is performed continuously.

• False – Continuous mode is disabled.

static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode)

Set operate mode of freqme module.

Parameters:

• base – FREQME peripheral base address.

• operateMode – The operate mode to be set, please refer to freqme_operate_mode_t.

static inline bool FREQME_CheckOperateMode(FREQME_Type *base)

Check module’s operate mode.

Parameters:

• base – FREQME peripheral base address.

Return values:

• True – Pulse width measurement mode.

• False – Frequency measurement mode.

static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue)

Set the minimum expected value for the measurement result.

Parameters:

• base – FREQME peripheral base address.

• minValue – The minimum value to set, please note that this value is 31 bits width.

static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue)

Set the maximum expected value for the measurement result.

Parameters:

• base – FREQME peripheral base address.

• maxValue – The maximum value to set, please note that this value is 31 bits width.

static inline void FREQME_SetReferenceClk(FREQME_Type *base, uint32_t referenceClk)

Set the reference clock source.

Parameters:

• base – FREQME peripheral base address.

• referenceClk – The reference clock source, see freqme_reference_clock_t in <device>_COMMON.h.

static inline void FREQME_SetTargetClk(FREQME_Type *base, uint32_t targetClk)

Set the target clock source.

Parameters:

• base – FREQME peripheral base address.

• targetClk – The target clock source, see freqme_target_clock_t in <device>_COMMON.h.

uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency)

Calculate the frequency of selected target clock.

Note

The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE or Ftarget = (RESULT + 1) * Freference / 2 ^ REF_SCALE

Note

This function only useful when the operate mode is selected as frequency measurement mode.

Parameters:

• base – FREQME peripheral base address.

• refClkFrequency – The frequency of reference clock.

Returns:

The frequency of target clock, if the output result is 0, please check the module’s operate mode.

static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base)

Get reference clock scaling factor.

Parameters:

• base – FREQME peripheral base address.

Returns:

Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale.

static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity)

Set pulse polarity when operate mode is selected as Pulse Width Measurement mode.

Parameters:

• base – FREQME peripheral base address.

• pulsePolarity – The pulse polarity to be set, please refer to freqme_pulse_polarity_t.

static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base)

Check pulse polarity when the operate mode is selected as pulse width measurement mode.

Parameters:

• base – FREQME peripheral base address.

Return values:

• True – Low period.

• False – High period.

static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base)

Get measurement result.

Parameters:

• base – FREQME peripheral base address.

Returns:

Measurement result.

static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base)

Get interrupt status flags, such as overflow interrupt status flag, underflow interrupt status flag, and so on.

Parameters:

• base – FREQME peripheral base address.

Returns:

Current interrupt status flags, should be the OR’ed value of _freqme_interrupt_status_flags.

static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags)

Clear interrupt status flags.

Parameters:

• base – FREQME peripheral base address.

• statusFlags – The combination of interrupt status flags to clear, should be the OR’ed value of _freqme_interrupt_status_flags.

static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks)

Enable interrupts, such as result ready interrupt, overflow interrupt and so on.

Parameters:

• base – FREQME peripheral base address.

• masks – The mask of interrupts to enable, should be the OR’ed value of _freqme_interrupt_enable.

static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)

Disable interrupts, such as result ready interrupt, overflow interrupt and so on.

Parameters:

• base – FREQME peripheral base address.

• masks – The mask of interrupts to disable, should be the OR’ed value of _freqme_interrupt_enable.

FSL_FREQME_DRIVER_VERSION

FREQME driver version 2.2.0.

enum _freqme_interrupt_status_flags

The enumeration of interrupt status flags. .

Values:

enumerator kFREQME_UnderflowInterruptStatusFlag

Indicate the measurement is just done and the result is less than minimum value.

enumerator kFREQME_OverflowInterruptStatusFlag

Indicate the measurement is just done and the result is greater than maximum value.

enumerator kFREQME_ReadyInterruptStatusFlag

Indicate the measurement is just done and the result is ready to read.

enumerator kFREQME_AllInterruptStatusFlags

All interrupt status flags.

enum _freqme_interrupt_enable

The enumeration of interrupts, including underflow interrupt, overflow interrupt, and result ready interrupt. .

Values:

enumerator kFREQME_UnderflowInterruptEnable

Enable interrupt when the result is less than minimum value.

enumerator kFREQME_OverflowInterruptEnable

Enable interrupt when the result is greater than maximum value.

enumerator kFREQME_ReadyInterruptEnable

Enable interrupt when a measurement completes and the result is ready.

enum _freqme_operate_mode

FREQME module operate mode enumeration, including frequency measurement mode and pulse width measurement mode.

Values:

enumerator kFREQME_FreqMeasurementMode

The module works in the frequency measurement mode.

enumerator kFREOME_PulseWidthMeasurementMode

The module works in the pulse width measurement mode.

enum _freqme_pulse_polarity

The enumeration of pulse polarity.

Values:

enumerator kFREQME_PulseHighPeriod

Select high period of the reference clock.

enumerator kFREQME_PulseLowPeriod

Select low period of the reference clock.

typedef enum _freqme_operate_mode freqme_operate_mode_t

FREQME module operate mode enumeration, including frequency measurement mode and pulse width measurement mode.

typedef enum _freqme_pulse_polarity freqme_pulse_polarity_t

The enumeration of pulse polarity.

typedef union _freqme_mode_attribute freqme_mode_attribute_t

The union of operate mode attribute.

Note

If the operate mode is selected as frequency measurement mode the member refClkScaleFactor should be used, if the operate mode is selected as pulse width measurement mode the member pulsePolarity should be used.

typedef struct _freq_measure_config freq_measure_config_t

The structure of freqme module basic configuration, including operate mode, operate mode attribute and so on.

union _freqme_mode_attribute

#include <fsl_freqme.h>

The union of operate mode attribute.

Note

If the operate mode is selected as frequency measurement mode the member refClkScaleFactor should be used, if the operate mode is selected as pulse width measurement mode the member pulsePolarity should be used.

Public Members

uint8_t refClkScaleFactor

Only useful in frequency measurement operate mode, used to set the reference clock counter scaling factor.

freqme_pulse_polarity_t pulsePolarity

Only Useful in pulse width measurement operate mode, used to set period polarity.

struct _freq_measure_config

#include <fsl_freqme.h>

The structure of freqme module basic configuration, including operate mode, operate mode attribute and so on.

Public Members

freqme_operate_mode_t operateMode

Select operate mode, please refer to freqme_operate_mode_t.

freqme_mode_attribute_t operateModeAttribute

Used to set the attribute of the selected operate mode, if the operate mode is selected as kFREQME_FreqMeasurementMode set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is selected as kFREOME_PulseWidthMeasurementMode, please set freqme_mode_attribute_t::pulsePolarity.

bool enableContinuousMode

Enable/disable continuous mode, if continuous mode is enable, the measurement is performed continuously and the result for the last completed measurement is available in the result register.

LPCMP: Low Power Analog Comparator Driver

void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config)

Initialize the LPCMP.

This function initializes the LPCMP module. The operations included are:

• Enabling the clock for LPCMP module.

• Configuring the comparator.

• Enabling the LPCMP module. Note: For some devices, multiple LPCMP instance share the same clock gate. In this case, to enable the clock for any instance enables all the LPCMPs. Check the chip reference manual for the clock assignment of the LPCMP.

Parameters:

• base – LPCMP peripheral base address.

• config – Pointer to “lpcmp_config_t” structure.

void LPCMP_Deinit(LPCMP_Type *base)

De-initializes the LPCMP module.

This function de-initializes the LPCMP module. The operations included are:

• Disabling the LPCMP module.

• Disabling the clock for LPCMP module.

This function disables the clock for the LPCMP. Note: For some devices, multiple LPCMP instance shares the same clock gate. In this case, before disabling the clock for the LPCMP, ensure that all the LPCMP instances are not used.

Parameters:

• base – LPCMP peripheral base address.

void LPCMP_GetDefaultConfig(lpcmp_config_t *config)

Gets an available pre-defined settings for the comparator’s configuration.

This function initializes the comparator configuration structure to these default values:

config->enableStopMode      = false;
config->enableOutputPin     = false;
config->enableCmpToDacLink  = false;
config->useUnfilteredOutput = false;
config->enableInvertOutput  = false;
config->hysteresisMode      = kLPCMP_HysteresisLevel0;
config->powerMode           = kLPCMP_LowSpeedPowerMode;
config->functionalSourceClock = kLPCMP_FunctionalClockSource0;
config->plusInputSrc          = kLPCMP_PlusInputSrcMux;
config->minusInputSrc         = kLPCMP_MinusInputSrcMux;

Parameters:

• config – Pointer to “lpcmp_config_t” structure.

static inline void LPCMP_Enable(LPCMP_Type *base, bool enable)

Enable/Disable LPCMP module.

Parameters:

• base – LPCMP peripheral base address.

• enable – “true” means enable the module, and “false” means disable the module.

void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel)

Select the input channels for LPCMP. This function determines which input is selected for the negative and positive mux.

Parameters:

• base – LPCMP peripheral base address.

• positiveChannel – Positive side input channel number. Available range is 0-7.

• negativeChannel – Negative side input channel number. Available range is 0-7.

static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable)

Enables/disables the DMA request for rising/falling events. Normally, the LPCMP generates a CPU interrupt if there is a rising/falling event. When DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling event forces a DMA transfer request rather than a CPU interrupt instead.

Parameters:

• base – LPCMP peripheral base address.

• enable – “true” means enable DMA support, and “false” means disable DMA support.

void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config)

Configures the filter.

Parameters:

• base – LPCMP peripheral base address.

• config – Pointer to “lpcmp_filter_config_t” structure.

void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config)

Configure the internal DAC module.

Parameters:

• base – LPCMP peripheral base address.

• config – Pointer to “lpcmp_dac_config_t” structure. If config is “NULL”, disable internal DAC.

static inline void LPCMP_EnableInterrupts(LPCMP_Type *base, uint32_t mask)

Enable the interrupts.

Parameters:

• base – LPCMP peripheral base address.

• mask – Mask value for interrupts. See “_lpcmp_interrupt_enable”.

static inline void LPCMP_DisableInterrupts(LPCMP_Type *base, uint32_t mask)

Disable the interrupts.

Parameters:

• base – LPCMP peripheral base address.

• mask – Mask value for interrupts. See “_lpcmp_interrupt_enable”.

static inline uint32_t LPCMP_GetStatusFlags(LPCMP_Type *base)

Get the LPCMP status flags.

Parameters:

• base – LPCMP peripheral base address.

Returns:

Mask value for the asserted flags. See “_lpcmp_status_flags”.

static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask)

Clear the LPCMP status flags.

Parameters:

• base – LPCMP peripheral base address.

• mask – Mask value for the flags. See “_lpcmp_status_flags”.

static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable)

Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. The optionally inverted comparator output COUT_RAW is sampled on every bus clock when WINDOW=1 to generate COUTA.

Parameters:

• base – LPCMP peripheral base address.

• enable – “true” means enable window mode, and “false” means disable window mode.

void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config)

Configure the window control, users can use this API to implement operations on the window, such as inverting the window signal, setting the window closing event(only valid in windowing mode), and setting the COUTA signal after the window is closed(only valid in windowing mode).

Parameters:

• base – LPCMP peripheral base address.

• config – Pointer “lpcmp_window_control_config_t” structure.

void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config)

Configure the roundrobin mode.

Parameters:

• base – LPCMP peripheral base address.

• config – Pointer “lpcmp_roundrobin_config_t” structure.

static inline void LPCMP_EnableRoundRobinMode(LPCMP_Type *base, bool enable)

Enable/Disable roundrobin mode.

Parameters:

• base – LPCMP peripheral base address.

• enable – “true” means enable roundrobin mode, and “false” means disable roundrobin mode.

void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value)

brief Configure the roundrobin internal timer reload value.

param base LPCMP peripheral base address. param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL.

static inline void LPCMP_EnableRoundRobinInternalTimer(LPCMP_Type *base, bool enable)

Enable/Disable roundrobin internal timer, note that this function is only valid when using the internal trigger source.

Parameters:

• base – LPCMP peripheral base address.

• enable – “true” means enable roundrobin internal timer, and “false” means disable roundrobin internal timer.

static inline void LPCMP_SetPreSetValue(LPCMP_Type *base, uint8_t mask)

Set preset value for all channels, users can set all channels’ preset vaule through this API, for example, if the mask set to 0x03U means channel0 and channel2’s preset value set to 1U and other channels’ preset value set to 0U.

Parameters:

• base – LPCMP peripheral base address.

• mask – Mask of channel index.

static inline uint8_t LPCMP_GetComparisonResult(LPCMP_Type *base)

Get comparison results for all channels, users can get all channels’ comparison results through this API.

Parameters:

• base – LPCMP peripheral base address.

Returns:

return All channels’ comparison result.

static inline void LPCMP_ClearInputChangedFlags(LPCMP_Type *base, uint8_t mask)

Clear input changed flags for single channel or multiple channels, users can clear input changed flag of a single channel or multiple channels through this API, for example, if the mask set to 0x03U means clear channel0 and channel2’s input changed flags.

Parameters:

• base – LPCMP peripheral base address.

• mask – Mask of channel index.

static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base)

Get input changed flags for all channels, Users can get all channels’ input changed flags through this API.

Parameters:

• base – LPCMP peripheral base address.

Returns:

return All channels’ changed flag.

FSL_LPCMP_DRIVER_VERSION

LPCMP driver version 2.3.2.

enum _lpcmp_status_flags

LPCMP status falgs mask.

Values:

enumerator kLPCMP_OutputRisingEventFlag

Rising-edge on the comparison output has occurred.

enumerator kLPCMP_OutputFallingEventFlag

Falling-edge on the comparison output has occurred.

enumerator kLPCMP_OutputRoundRobinEventFlag

Detects when any channel’s last comparison result is different from the pre-set value in trigger mode.

enumerator kLPCMP_OutputAssertEventFlag

Return the current value of the analog comparator output. The flag does not support W1C.

enum _lpcmp_interrupt_enable

LPCMP interrupt enable/disable mask.

Values:

enumerator kLPCMP_OutputRisingInterruptEnable

Comparator interrupt enable rising.

enumerator kLPCMP_OutputFallingInterruptEnable

Comparator interrupt enable falling.

enumerator kLPCMP_RoundRobinInterruptEnable

Comparator round robin mode interrupt occurred when the comparison result changes for a given channel.

enum _lpcmp_hysteresis_mode

LPCMP hysteresis mode. See chip data sheet to get the actual hystersis value with each level.

Values:

enumerator kLPCMP_HysteresisLevel0

The hard block output has level 0 hysteresis internally.

enumerator kLPCMP_HysteresisLevel1

The hard block output has level 1 hysteresis internally.

enumerator kLPCMP_HysteresisLevel2

The hard block output has level 2 hysteresis internally.

enumerator kLPCMP_HysteresisLevel3

The hard block output has level 3 hysteresis internally.

enum _lpcmp_power_mode

LPCMP nano mode.

Values:

enumerator kLPCMP_LowSpeedPowerMode

Low speed comparison mode is selected.

enumerator kLPCMP_HighSpeedPowerMode

High speed comparison mode is selected.

enumerator kLPCMP_NanoPowerMode

Nano power comparator is enabled.

enum _lpcmp_dac_reference_voltage_source

Internal DAC reference voltage source.

Values:

enumerator kLPCMP_VrefSourceVin1

vrefh_int is selected as resistor ladder network supply reference Vin.

enumerator kLPCMP_VrefSourceVin2

vrefh_ext is selected as resistor ladder network supply reference Vin.

enum _lpcmp_functional_source_clock

LPCMP functional mode clock source selection.

Note: In different devices, the functional mode clock source selection is different, please refer to specific device Reference Manual for details.

Values:

enumerator kLPCMP_FunctionalClockSource0

Select functional mode clock source0.

enumerator kLPCMP_FunctionalClockSource1

Select functional mode clock source1.

enumerator kLPCMP_FunctionalClockSource2

Select functional mode clock source2.

enumerator kLPCMP_FunctionalClockSource3

Select functional mode clock source3.

enum _lpcmp_couta_signal

Set the COUTA signal value when the window is closed.

Values:

enumerator kLPCMP_COUTASignalNoSet

NO set the COUTA signal value when the window is closed.

enumerator kLPCMP_COUTASignalLow

Set COUTA signal low(0) when the window is closed.

enumerator kLPCMP_COUTASignalHigh

Set COUTA signal high(1) when the window is closed.

enum _lpcmp_close_window_event

Set COUT event, which can close the active window in window mode.

Values:

enumerator kLPCMP_CLoseWindowEventNoSet

No Set COUT event, which can close the active window in window mode.

enumerator kLPCMP_CloseWindowEventRisingEdge

Set rising edge COUT signal as COUT event.

enumerator kLPCMP_CloseWindowEventFallingEdge

Set falling edge COUT signal as COUT event.

enumerator kLPCMP_CLoseWindowEventBothEdge

Set both rising and falling edge COUT signal as COUT event.

enum _lpcmp_roundrobin_fixedmuxport

LPCMP round robin mode fixed mux port.

Values:

enumerator kLPCMP_FixedPlusMuxPort

Fixed plus mux port.

enumerator kLPCMP_FixedMinusMuxPort

Fixed minus mux port.

enum _lpcmp_roundrobin_clock_source

LPCMP round robin mode clock source selection.

Note: In different devices,the round robin mode clock source selection is different, please refer to the specific device Reference Manual for details.

Values:

enumerator kLPCMP_RoundRobinClockSource0

Select roundrobin mode clock source0.

enumerator kLPCMP_RoundRobinClockSource1

Select roundrobin mode clock source1.

enumerator kLPCMP_RoundRobinClockSource2

Select roundrobin mode clock source2.

enumerator kLPCMP_RoundRobinClockSource3

Select roundrobin mode clock source3.

enum _lpcmp_roundrobin_trigger_source

LPCMP round robin mode trigger source.

Values:

enumerator kLPCMP_TriggerSourceExternally

Select external trigger source.

enumerator kLPCMP_TriggerSourceInternally

Select internal trigger source.

enum _lpcmp_plus_input_src

LPCMP plus input source.

Values:

enumerator kLPCMP_PlusInputSrcDac

LPCMP plus input source from the internal 8-bit DAC output.

enumerator kLPCMP_PlusInputSrcMux

LPCMP plus input source from the analog 8-1 mux.

enum _lpcmp_minus_input_src

LPCMP minus input source.

Values:

enumerator kLPCMP_MinusInputSrcDac

LPCMP minus input source from the internal 8-bit DAC output.

enumerator kLPCMP_MinusInputSrcMux

LPCMP minus input source from the analog 8-1 mux.

typedef enum _lpcmp_hysteresis_mode lpcmp_hysteresis_mode_t

LPCMP hysteresis mode. See chip data sheet to get the actual hystersis value with each level.

typedef enum _lpcmp_power_mode lpcmp_power_mode_t

LPCMP nano mode.

typedef enum _lpcmp_dac_reference_voltage_source lpcmp_dac_reference_voltage_source_t

Internal DAC reference voltage source.

typedef enum _lpcmp_functional_source_clock lpcmp_functional_source_clock_t

LPCMP functional mode clock source selection.

Note: In different devices, the functional mode clock source selection is different, please refer to specific device Reference Manual for details.

typedef enum _lpcmp_couta_signal lpcmp_couta_signal_t

Set the COUTA signal value when the window is closed.

typedef enum _lpcmp_close_window_event lpcmp_close_window_event_t

Set COUT event, which can close the active window in window mode.

typedef enum _lpcmp_roundrobin_fixedmuxport lpcmp_roundrobin_fixedmuxport_t

LPCMP round robin mode fixed mux port.

typedef enum _lpcmp_roundrobin_clock_source lpcmp_roundrobin_clock_source_t

LPCMP round robin mode clock source selection.

Note: In different devices,the round robin mode clock source selection is different, please refer to the specific device Reference Manual for details.

typedef enum _lpcmp_roundrobin_trigger_source lpcmp_roundrobin_trigger_source_t

LPCMP round robin mode trigger source.

typedef struct _lpcmp_filter_config lpcmp_filter_config_t

Configure the filter.

typedef enum _lpcmp_plus_input_src lpcmp_plus_input_src_t

LPCMP plus input source.

typedef enum _lpcmp_minus_input_src lpcmp_minus_input_src_t

LPCMP minus input source.

typedef struct _lpcmp_dac_config lpcmp_dac_config_t

configure the internal DAC.

typedef struct _lpcmp_config lpcmp_config_t

Configures the comparator.

typedef struct _lpcmp_window_control_config lpcmp_window_control_config_t

Configure the window mode control.

typedef struct _lpcmp_roundrobin_config lpcmp_roundrobin_config_t

Configure the round robin mode.

LPCMP_CCR1_COUTA_CFG_MASK

LPCMP_CCR1_COUTA_CFG_SHIFT

LPCMP_CCR1_COUTA_CFG(x)

LPCMP_CCR1_EVT_SEL_CFG_MASK

LPCMP_CCR1_EVT_SEL_CFG_SHIFT

LPCMP_CCR1_EVT_SEL_CFG(x)

struct _lpcmp_filter_config

#include <fsl_lpcmp.h>

Configure the filter.

Public Members

bool enableSample

Decide whether to use the external SAMPLE as a sampling clock input.

uint8_t filterSampleCount

Filter Sample Count. Available range is 1-7; 0 disables the filter.

uint8_t filterSamplePeriod

Filter Sample Period. The divider to the bus clock. Available range is 0-255. The sampling clock must be at least 4 times slower than the system clock to the comparator. So if enableSample is “false”, filterSamplePeriod should be set greater than 4.

struct _lpcmp_dac_config

#include <fsl_lpcmp.h>

configure the internal DAC.

Public Members

bool enableLowPowerMode

Decide whether to enable DAC low power mode.

lpcmp_dac_reference_voltage_source_t referenceVoltageSource

Internal DAC supply voltage reference source.

uint8_t DACValue

Value for the DAC Output Voltage. Different devices has different available range, for specific values, please refer to the reference manual.

struct _lpcmp_config

#include <fsl_lpcmp.h>

Configures the comparator.

Public Members

bool enableStopMode

Decide whether to enable the comparator when in STOP modes.

bool enableCmpToDacLink

Controls the link from the CMP enable to the DAC enable.

bool enableOutputPin

Decide whether to enable the comparator is available in selected pin.

bool useUnfilteredOutput

Decide whether to use unfiltered output.

bool enableInvertOutput

Decide whether to inverts the comparator output.

lpcmp_hysteresis_mode_t hysteresisMode

LPCMP hysteresis mode.

lpcmp_power_mode_t powerMode

LPCMP power mode.

lpcmp_functional_source_clock_t functionalSourceClock

Select LPCMP functional mode clock source.

lpcmp_plus_input_src_t plusInputSrc

Select LPCMP plus input source.

lpcmp_minus_input_src_t minusInputSrc

Select LPCMP minus input source.

struct _lpcmp_window_control_config

#include <fsl_lpcmp.h>

Configure the window mode control.

Public Members

bool enableInvertWindowSignal

True: enable invert window signal, False: disable invert window signal.

lpcmp_couta_signal_t COUTASignal

Decide whether to define the COUTA signal value when the window is closed.

lpcmp_close_window_event_t closeWindowEvent

Decide whether to select COUT event signal edge defines a COUT event to close window.

struct _lpcmp_roundrobin_config

#include <fsl_lpcmp.h>

Configure the round robin mode.

Public Members

uint8_t initDelayModules

Comparator and DAC initialization delay modulus, See Reference Manual and DataSheet for specific value.

uint8_t sampleClockNumbers

Specify the number of the round robin clock cycles(0~3) to wait after scanning the active channel before sampling the channel’s comparison result.

uint8_t channelSampleNumbers

Specify the number of samples for one channel, note that channelSampleNumbers must not smaller than sampleTimeThreshhold.

uint8_t sampleTimeThreshhold

Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are “1”,the final result is “1”, otherwise the final result is “0”, note that the sampleTimeThreshhold must not be larger than channelSampleNumbers.

lpcmp_roundrobin_clock_source_t roundrobinClockSource

Decide which clock source to choose in round robin mode.

lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource

Decide which trigger source to choose in round robin mode.

lpcmp_roundrobin_fixedmuxport_t fixedMuxPort

Decide which mux port to choose as fixed channel in round robin mode.

uint8_t fixedChannel

Indicate which channel of the fixed mux port is used in round robin mode.

uint8_t checkerChannelMask

Indicate which channel of the non-fixed mux port to check its voltage value in round robin mode, for example, if checkerChannelMask set to 0x11U means select channel 0 and channel 4 as checker channel.

LPI2C: Low Power Inter-Integrated Circuit Driver

void LPI2C_DriverIRQHandler(uint32_t instance)

LPI2C driver IRQ handler common entry.

This function provides the common IRQ request entry for LPI2C.

Parameters:

• instance – LPI2C instance.

FSL_LPI2C_DRIVER_VERSION

LPI2C driver version.

LPI2C status return codes.

Values:

enumerator kStatus_LPI2C_Busy

The master is already performing a transfer.

enumerator kStatus_LPI2C_Idle

The slave driver is idle.

enumerator kStatus_LPI2C_Nak

The slave device sent a NAK in response to a byte.

enumerator kStatus_LPI2C_FifoError

FIFO under run or overrun.

enumerator kStatus_LPI2C_BitError

Transferred bit was not seen on the bus.

enumerator kStatus_LPI2C_ArbitrationLost

Arbitration lost error.

enumerator kStatus_LPI2C_PinLowTimeout

SCL or SDA were held low longer than the timeout.

enumerator kStatus_LPI2C_NoTransferInProgress

Attempt to abort a transfer when one is not in progress.

enumerator kStatus_LPI2C_DmaRequestFail

DMA request failed.

enumerator kStatus_LPI2C_Timeout

Timeout polling status flags.

IRQn_Type const kLpi2cMasterIrqs[]

Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs.

IRQn_Type const kLpi2cSlaveIrqs[]

lpi2c_master_isr_t s_lpi2cMasterIsr

Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

void *s_lpi2cMasterHandle[]

Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

uint32_t LPI2C_GetInstance(LPI2C_Type *base)

Returns an instance number given a base address.

If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

LPI2C instance number starting from 0.

I2C_RETRY_TIMES

Retry times for waiting flag.

LPI2C Master Driver

void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)

Provides a default configuration for the LPI2C master peripheral.

This function provides the following default configuration for the LPI2C master peripheral:

masterConfig->enableMaster            = true;
masterConfig->debugEnable             = false;
masterConfig->ignoreAck               = false;
masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busIdleTimeout_ns       = 0;
masterConfig->pinLowTimeout_ns        = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable      = false;
masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().

Parameters:

• masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t.

void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C master peripheral.

This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

• base – The LPI2C peripheral base address.

• masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

void LPI2C_MasterDeinit(LPI2C_Type *base)

Deinitializes the LPI2C master peripheral.

This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)

Configures LPI2C master data match feature.

Parameters:

• base – The LPI2C peripheral base address.

• matchConfig – Settings for the data match feature.

status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)

Convert provided flags to status code, and clear any errors if present.

Parameters:

• base – The LPI2C peripheral base address.

• status – Current status flags value that will be checked.

Return values:

• kStatus_Success –

• kStatus_LPI2C_PinLowTimeout –

• kStatus_LPI2C_ArbitrationLost –

• kStatus_LPI2C_Nak –

• kStatus_LPI2C_FifoError –

status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)

Make sure the bus isn’t already busy.

A busy bus is allowed if we are the one driving it.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• kStatus_Success –

• kStatus_LPI2C_Busy –

static inline void LPI2C_MasterReset(LPI2C_Type *base)

Performs a software reset.

Restores the LPI2C master peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as master.

Parameters:

• base – The LPI2C peripheral base address.

• enable – Pass true to enable or false to disable the specified LPI2C as master.

static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C master status flags.

A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_master_flags

Parameters:

• base – The LPI2C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C master status flag state.

The following status register flags can be cleared:

• kLPI2C_MasterEndOfPacketFlag

• kLPI2C_MasterStopDetectFlag

• kLPI2C_MasterNackDetectFlag

• kLPI2C_MasterArbitrationLostFlag

• kLPI2C_MasterFifoErrFlag

• kLPI2C_MasterPinLowTimeoutFlag

• kLPI2C_MasterDataMatchFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_master_flags.

Parameters:

• base – The LPI2C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags().

static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C master interrupt requests.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)

Enables or disables LPI2C master DMA requests.

Parameters:

• base – The LPI2C peripheral base address.

• enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.

• enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)

Gets LPI2C master transmit data register address for DMA transfer.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Transmit Data Register address.

static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)

Gets LPI2C master receive data register address for DMA transfer.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Receive Data Register address.

static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)

Sets the watermarks for LPI2C master FIFOs.

Parameters:

• base – The LPI2C peripheral base address.

• txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated.

• rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of words in the LPI2C master FIFOs.

Parameters:

• base – The LPI2C peripheral base address.

• txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required.

• rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required.

void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)

Sets the I2C bus frequency for master transactions.

The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note

Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.

Parameters:

• base – The LPI2C peripheral base address.

• sourceClock_Hz – LPI2C functional clock frequency in Hertz.

• baudRate_Hz – Requested bus frequency in Hertz.

static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle.

Requires the master mode to be enabled.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a START signal and slave address on the I2C bus.

This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

• base – The LPI2C peripheral base address.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)

Sends a repeated START signal and slave address on the I2C bus.

This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.

Note

This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.

Parameters:

• base – The LPI2C peripheral base address.

• address – 7-bit slave device address, in bits [6:0].

• dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

• kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)

Performs a polling send transfer on the I2C bus.

Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.

Parameters:

• base – The LPI2C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

Return values:

• kStatus_Success – Data was sent successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or over run.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterStop(LPI2C_Type *base)

Sends a STOP signal on the I2C bus.

This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to error happens during transfer.

Parameters:

• base – The LPI2C peripheral base address.

• transfer – Pointer to the transfer structure.

Return values:

• kStatus_Success – Data was received successfully.

• kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

• kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.

• kStatus_LPI2C_FifoError – FIFO under run or overrun.

• kStatus_LPI2C_ArbitrationLost – Arbitration lost error.

• kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C master non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C master driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking transaction on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)

Reusable routine to handle master interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The LPI2C peripheral base address.

• lpi2cMasterHandle – Pointer to the LPI2C master driver handle.

enum _lpi2c_master_flags

LPI2C master peripheral flags.

The following status register flags can be cleared:

• kLPI2C_MasterEndOfPacketFlag

• kLPI2C_MasterStopDetectFlag

• kLPI2C_MasterNackDetectFlag

• kLPI2C_MasterArbitrationLostFlag

• kLPI2C_MasterFifoErrFlag

• kLPI2C_MasterPinLowTimeoutFlag

• kLPI2C_MasterDataMatchFlag

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_MasterTxReadyFlag

Transmit data flag

enumerator kLPI2C_MasterRxReadyFlag

Receive data flag

enumerator kLPI2C_MasterEndOfPacketFlag

End Packet flag

enumerator kLPI2C_MasterStopDetectFlag

Stop detect flag

enumerator kLPI2C_MasterNackDetectFlag

NACK detect flag

enumerator kLPI2C_MasterArbitrationLostFlag

Arbitration lost flag

enumerator kLPI2C_MasterFifoErrFlag

FIFO error flag

enumerator kLPI2C_MasterPinLowTimeoutFlag

Pin low timeout flag

enumerator kLPI2C_MasterDataMatchFlag

Data match flag

enumerator kLPI2C_MasterBusyFlag

Master busy flag

enumerator kLPI2C_MasterBusBusyFlag

Bus busy flag

enumerator kLPI2C_MasterClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_MasterIrqFlags

IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_MasterErrorFlags

Errors to check for.

enum _lpi2c_direction

Direction of master and slave transfers.

Values:

enumerator kLPI2C_Write

Master transmit.

enumerator kLPI2C_Read

Master receive.

enum _lpi2c_master_pin_config

LPI2C pin configuration.

Values:

enumerator kLPI2C_2PinOpenDrain

LPI2C Configured for 2-pin open drain mode

enumerator kLPI2C_2PinOutputOnly

LPI2C Configured for 2-pin output only mode (ultra-fast mode)

enumerator kLPI2C_2PinPushPull

LPI2C Configured for 2-pin push-pull mode

enumerator kLPI2C_4PinPushPull

LPI2C Configured for 4-pin push-pull mode

enumerator kLPI2C_2PinOpenDrainWithSeparateSlave

LPI2C Configured for 2-pin open drain mode with separate LPI2C slave

enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave

LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave

enumerator kLPI2C_2PinPushPullWithSeparateSlave

LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave

enumerator kLPI2C_4PinPushPullWithInvertedOutput

LPI2C Configured for 4-pin push-pull mode(inverted outputs)

enum _lpi2c_host_request_source

LPI2C master host request selection.

Values:

enumerator kLPI2C_HostRequestExternalPin

Select the LPI2C_HREQ pin as the host request input

enumerator kLPI2C_HostRequestInputTrigger

Select the input trigger as the host request input

enum _lpi2c_host_request_polarity

LPI2C master host request pin polarity configuration.

Values:

enumerator kLPI2C_HostRequestPinActiveLow

Configure the LPI2C_HREQ pin active low

enumerator kLPI2C_HostRequestPinActiveHigh

Configure the LPI2C_HREQ pin active high

enum _lpi2c_data_match_config_mode

LPI2C master data match configuration modes.

Values:

enumerator kLPI2C_MatchDisabled

LPI2C Match Disabled

enumerator kLPI2C_1stWordEqualsM0OrM1

LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1

enumerator kLPI2C_AnyWordEqualsM0OrM1

LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1

enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1

LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1

enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1

LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1

enumerator kLPI2C_1stWordAndM1EqualsM0AndM1

LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1

enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1

LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1

enum _lpi2c_master_transfer_flags

Transfer option flags.

Note

These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field.

Values:

enumerator kLPI2C_TransferDefaultFlag

Transfer starts with a start signal, stops with a stop signal.

enumerator kLPI2C_TransferNoStartFlag

Don’t send a start condition, address, and sub address

enumerator kLPI2C_TransferNoStopFlag

Don’t send a stop condition.

typedef enum _lpi2c_direction lpi2c_direction_t

Direction of master and slave transfers.

typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t

LPI2C pin configuration.

typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t

LPI2C master host request selection.

typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t

LPI2C master host request pin polarity configuration.

typedef struct _lpi2c_master_config lpi2c_master_config_t

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t

LPI2C master data match configuration modes.

typedef struct _lpi2c_match_config lpi2c_data_match_config_t

LPI2C master data match configuration structure.

typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t

LPI2C master descriptor of the transfer.

typedef struct _lpi2c_master_handle lpi2c_master_handle_t

LPI2C master handle of the transfer.

typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)

Master completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().

Param base:

The LPI2C peripheral base address.

Param handle:

Pointer to the LPI2C master driver handle.

Param completionStatus:

Either kStatus_Success or an error code describing how the transfer completed.

Param userData:

Arbitrary pointer-sized value passed from the application.

typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)

Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs.

struct _lpi2c_master_config

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableMaster

Whether to enable master mode.

bool enableDoze

Whether master is enabled in doze mode.

bool debugEnable

Enable transfers to continue when halted in debug mode.

bool ignoreAck

Whether to ignore ACK/NACK.

lpi2c_master_pin_config_t pinConfig

The pin configuration option.

uint32_t baudRate_Hz

Desired baud rate in Hertz.

uint32_t busIdleTimeout_ns

Bus idle timeout in nanoseconds. Set to 0 to disable.

uint32_t pinLowTimeout_ns

Pin low timeout in nanoseconds. Set to 0 to disable.

uint8_t sdaGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable.

uint8_t sclGlitchFilterWidth_ns

Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable.

struct _lpi2c_master_config hostRequest

Host request options.

struct _lpi2c_match_config

#include <fsl_lpi2c.h>

LPI2C master data match configuration structure.

Public Members

lpi2c_data_match_config_mode_t matchMode

Data match configuration setting.

bool rxDataMatchOnly

When set to true, received data is ignored until a successful match.

uint32_t match0

Match value 0.

uint32_t match1

Match value 1.

struct _lpi2c_master_transfer

#include <fsl_lpi2c.h>

Non-blocking transfer descriptor structure.

This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API.

Public Members

uint32_t flags

Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers.

uint16_t slaveAddress

The 7-bit slave address.

lpi2c_direction_t direction

Either kLPI2C_Read or kLPI2C_Write.

uint32_t subaddress

Sub address. Transferred MSB first.

size_t subaddressSize

Length of sub address to send in bytes. Maximum size is 4 bytes.

void *data

Pointer to data to transfer.

size_t dataSize

Number of bytes to transfer.

struct _lpi2c_master_handle

#include <fsl_lpi2c.h>

Driver handle for master non-blocking APIs.

Note

The contents of this structure are private and subject to change.

Public Members

uint8_t state

Transfer state machine current state.

uint16_t remainingBytes

Remaining byte count in current state.

uint8_t *buf

Buffer pointer for current state.

uint16_t commandBuffer[6]

LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word]

lpi2c_master_transfer_t transfer

Copy of the current transfer info.

lpi2c_master_transfer_callback_t completionCallback

Callback function pointer.

void *userData

Application data passed to callback.

uint16_t chunkSize

Remaining byte count in current chunk.

struct hostRequest

Public Members

bool enable

Enable host request.

lpi2c_host_request_source_t source

Host request source.

lpi2c_host_request_polarity_t polarity

Host request pin polarity.

LPI2C Master DMA Driver

void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)

Create a new handle for the LPI2C master DMA APIs.

The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.

For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C master driver handle.

• rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function.

• txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)

Performs a non-blocking DMA-based transaction on the I2C bus.

The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• transfer – The pointer to the transfer descriptor.

Return values:

• kStatus_Success – The transaction was started successfully.

• kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.

status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)

Returns number of bytes transferred so far.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

• count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.

status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to the LPI2C master driver handle.

Return values:

• kStatus_Success – A transaction was successfully aborted.

• kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress.

typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t

LPI2C master EDMA handle of the transfer.

typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)

Master DMA completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().

Param base:

The LPI2C peripheral base address.

Param handle:

Handle associated with the completed transfer.

Param completionStatus:

Either kStatus_Success or an error code describing how the transfer completed.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _lpi2c_master_edma_handle

#include <fsl_lpi2c_edma.h>

Driver handle for master DMA APIs.

Note

The contents of this structure are private and subject to change.

Public Members

LPI2C_Type *base

LPI2C base pointer.

bool isBusy

Transfer state machine current state.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

uint16_t commandBuffer[20U]

LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words]

lpi2c_master_transfer_t transfer

Copy of the current transfer info.

lpi2c_master_edma_transfer_callback_t completionCallback

Callback function pointer.

void *userData

Application data passed to callback.

edma_handle_t *rx

Handle for receive DMA channel.

edma_handle_t *tx

Handle for transmit DMA channel.

edma_tcd_t tcds[3]

Software TCD. Three are allocated to provide enough room to align to 32-bytes.

LPI2C Slave Driver

void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)

Provides a default configuration for the LPI2C slave peripheral.

This function provides the following default configuration for the LPI2C slave peripheral:

slaveConfig->enableSlave               = true;
slaveConfig->address0                  = 0U;
slaveConfig->address1                  = 0U;
slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable          = true;
slaveConfig->filterEnable              = true;
slaveConfig->enableGeneralCall         = false;
slaveConfig->sclStall.enableAck        = false;
slaveConfig->sclStall.enableTx         = true;
slaveConfig->sclStall.enableRx         = true;
slaveConfig->sclStall.enableAddress    = true;
slaveConfig->ignoreAck                 = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns   = 0;
slaveConfig->sclGlitchFilterWidth_ns   = 0;
slaveConfig->dataValidDelay_ns         = 0;
slaveConfig->clockHoldTime_ns          = 0;

After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.

Parameters:

• slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t.

void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)

Initializes the LPI2C slave peripheral.

This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.

Parameters:

• base – The LPI2C peripheral base address.

• slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override.

• sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time.

void LPI2C_SlaveDeinit(LPI2C_Type *base)

Deinitializes the LPI2C slave peripheral.

This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveReset(LPI2C_Type *base)

Performs a software reset of the LPI2C slave peripheral.

Parameters:

• base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)

Enables or disables the LPI2C module as slave.

Parameters:

• base – The LPI2C peripheral base address.

• enable – Pass true to enable or false to disable the specified LPI2C as slave.

static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)

Gets the LPI2C slave status flags.

A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_slave_flags

Parameters:

• base – The LPI2C peripheral base address.

Returns:

State of the status flags:

• 1: related status flag is set.

• 0: related status flag is not set.

static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)

Clears the LPI2C status flag state.

The following status register flags can be cleared:

• kLPI2C_SlaveRepeatedStartDetectFlag

• kLPI2C_SlaveStopDetectFlag

• kLPI2C_SlaveBitErrFlag

• kLPI2C_SlaveFifoErrFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_slave_flags.

Parameters:

• base – The LPI2C peripheral base address.

• statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags().

static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Enables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)

Disables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

• base – The LPI2C peripheral base address.

• interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)

Returns the set of currently enabled LPI2C slave interrupt requests.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)

Enables or disables the LPI2C slave peripheral DMA requests.

Parameters:

• base – The LPI2C peripheral base address.

• enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request.

• enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable.

• enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable.

static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)

Returns whether the bus is idle.

Requires the slave mode to be enabled.

Parameters:

• base – The LPI2C peripheral base address.

Return values:

• true – Bus is busy.

• false – Bus is idle.

static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)

Transmits either an ACK or NAK on the I2C bus in response to a byte from the master.

Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.

Parameters:

• base – The LPI2C peripheral base address.

• ackOrNack – Pass true for an ACK or false for a NAK.

static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)

Enables or disables ACKSTALL.

When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.

Parameters:

• base – The LPI2C peripheral base address.

• enable – True will enable ACKSTALL,false will disable ACKSTALL.

static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)

Returns the slave address sent by the I2C master.

This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.

Parameters:

• base – The LPI2C peripheral base address.

Returns:

The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits.

status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)

Performs a polling send transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• txBuff – The pointer to the data to be transferred.

• txSize – The length in bytes of the data to be transferred.

• actualTxSize – [out]

Returns:

Error or success status returned by API.

status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)

Performs a polling receive transfer on the I2C bus.

Parameters:

• base – The LPI2C peripheral base address.

• rxBuff – The pointer to the data to be transferred.

• rxSize – The length in bytes of the data to be transferred.

• actualRxSize – [out]

Returns:

Error or success status returned by API.

void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)

Creates a new handle for the LPI2C slave non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

• base – The LPI2C peripheral base address.

• handle – [out] Pointer to the LPI2C slave driver handle.

• callback – User provided pointer to the asynchronous callback function.

• userData – User provided pointer to the application callback data.

status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)

Starts accepting slave transfers.

Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

• eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.

Return values:

• kStatus_Success – Slave transfers were successfully started.

• kStatus_LPI2C_Busy – Slave transfers have already been started on this handle.

status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)

Gets the slave transfer status during a non-blocking transfer.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to i2c_slave_handle_t structure.

• count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.

Return values:

• kStatus_Success –

• kStatus_NoTransferInProgress –

void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Aborts the slave non-blocking transfers.

Note

This API could be called at any time to stop slave for handling the bus events.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)

Reusable routine to handle slave interrupts.

Note

This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.

Parameters:

• base – The LPI2C peripheral base address.

• handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

enum _lpi2c_slave_flags

LPI2C slave peripheral flags.

The following status register flags can be cleared:

• kLPI2C_SlaveRepeatedStartDetectFlag

• kLPI2C_SlaveStopDetectFlag

• kLPI2C_SlaveBitErrFlag

• kLPI2C_SlaveFifoErrFlag

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Note

These enumerations are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_SlaveTxReadyFlag

Transmit data flag

enumerator kLPI2C_SlaveRxReadyFlag

Receive data flag

enumerator kLPI2C_SlaveAddressValidFlag

Address valid flag

enumerator kLPI2C_SlaveTransmitAckFlag

Transmit ACK flag

enumerator kLPI2C_SlaveRepeatedStartDetectFlag

Repeated start detect flag

enumerator kLPI2C_SlaveStopDetectFlag

Stop detect flag

enumerator kLPI2C_SlaveBitErrFlag

Bit error flag

enumerator kLPI2C_SlaveFifoErrFlag

FIFO error flag

enumerator kLPI2C_SlaveAddressMatch0Flag

Address match 0 flag

enumerator kLPI2C_SlaveAddressMatch1Flag

Address match 1 flag

enumerator kLPI2C_SlaveGeneralCallFlag

General call flag

enumerator kLPI2C_SlaveBusyFlag

Master busy flag

enumerator kLPI2C_SlaveBusBusyFlag

Bus busy flag

enumerator kLPI2C_SlaveClearFlags

All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_SlaveIrqFlags

IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_SlaveErrorFlags

Errors to check for.

enum _lpi2c_slave_address_match

LPI2C slave address match options.

Values:

enumerator kLPI2C_MatchAddress0

Match only address 0.

enumerator kLPI2C_MatchAddress0OrAddress1

Match either address 0 or address 1.

enumerator kLPI2C_MatchAddress0ThroughAddress1

Match a range of slave addresses from address 0 through address 1.

enum _lpi2c_slave_transfer_event

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

Values:

enumerator kLPI2C_SlaveAddressMatchEvent

Received the slave address after a start or repeated start.

enumerator kLPI2C_SlaveTransmitEvent

Callback is requested to provide data to transmit (slave-transmitter role).

enumerator kLPI2C_SlaveReceiveEvent

Callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kLPI2C_SlaveTransmitAckEvent

Callback needs to either transmit an ACK or NACK.

enumerator kLPI2C_SlaveRepeatedStartEvent

A repeated start was detected.

enumerator kLPI2C_SlaveCompletionEvent

A stop was detected, completing the transfer.

enumerator kLPI2C_SlaveAllEvents

Bit mask of all available events.

typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t

LPI2C slave address match options.

typedef struct _lpi2c_slave_config lpi2c_slave_config_t

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t

LPI2C slave transfer structure.

typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t

LPI2C slave handle structure.

typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)

Slave event callback function pointer type.

This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.

Param base:

Base address for the LPI2C instance on which the event occurred.

Param transfer:

Pointer to transfer descriptor containing values passed to and/or from the callback.

Param userData:

Arbitrary pointer-sized value passed from the application.

struct _lpi2c_slave_config

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableSlave

Enable slave mode.

uint8_t address0

Slave’s 7-bit address.

uint8_t address1

Alternate slave 7-bit address.

lpi2c_slave_address_match_t addressMatchMode

Address matching options.

bool filterDozeEnable

Enable digital glitch filter in doze mode.

bool filterEnable

Enable digital glitch filter.

bool enableGeneralCall

Enable general call address matching.

struct _lpi2c_slave_config sclStall

SCL stall enable options.

bool ignoreAck

Continue transfers after a NACK is detected.

bool enableReceivedAddressRead

Enable reading the address received address as the first byte of data.

uint32_t sdaGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable.

uint32_t sclGlitchFilterWidth_ns

Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable.

uint32_t dataValidDelay_ns

Width in nanoseconds of the data valid delay.

uint32_t clockHoldTime_ns

Width in nanoseconds of the clock hold time.

struct _lpi2c_slave_transfer

#include <fsl_lpi2c.h>

LPI2C slave transfer structure.

Public Members

lpi2c_slave_transfer_event_t event

Reason the callback is being invoked.

uint8_t receivedAddress

Matching address send by master.

uint8_t *data

Transfer buffer

size_t dataSize

Transfer size

status_t completionStatus

Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent.

size_t transferredCount

Number of bytes actually transferred since start or last repeated start.

struct _lpi2c_slave_handle

#include <fsl_lpi2c.h>

LPI2C slave handle structure.

Note

The contents of this structure are private and subject to change.

Public Members

lpi2c_slave_transfer_t transfer

LPI2C slave transfer copy.

bool isBusy

Whether transfer is busy.

bool wasTransmit

Whether the last transfer was a transmit.

uint32_t eventMask

Mask of enabled events.

uint32_t transferredCount

Count of bytes transferred.

lpi2c_slave_transfer_callback_t callback

Callback function called at transfer event.

void *userData

Callback parameter passed to callback.

struct sclStall

Public Members

bool enableAck

Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall.

bool enableTx

Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer.

bool enableRx

Enables SCL clock stretching when receive data flag is set during a slave-receive transfer.

bool enableAddress

Enables SCL clock stretching when the address valid flag is asserted.

LPSPI: Low Power Serial Peripheral Interface

LPSPI Peripheral driver

void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the LPSPI master.

Parameters:

• base – LPSPI peripheral address.

• masterConfig – Pointer to structure lpspi_master_config_t.

• srcClock_Hz – Module source input clock in Hertz

void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)

Sets the lpspi_master_config_t structure to default values.

This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example:

lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

• masterConfig – pointer to lpspi_master_config_t structure

void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)

LPSPI slave configuration.

Parameters:

• base – LPSPI peripheral address.

• slaveConfig – Pointer to a structure lpspi_slave_config_t.

void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)

Sets the lpspi_slave_config_t structure to default values.

This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example:

lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

• slaveConfig – pointer to lpspi_slave_config_t structure.

void LPSPI_Deinit(LPSPI_Type *base)

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.

Parameters:

• base – LPSPI peripheral address.

void LPSPI_Reset(LPSPI_Type *base)

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API.

Parameters:

• base – LPSPI peripheral address.

uint32_t LPSPI_GetInstance(LPSPI_Type *base)

Get the LPSPI instance from peripheral base address.

Parameters:

• base – LPSPI peripheral base address.

Returns:

LPSPI instance.

static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)

Enables the LPSPI peripheral and sets the MCR MDIS to 0.

Parameters:

• base – LPSPI peripheral address.

• enable – Pass true to enable module, false to disable module.

static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)

Gets the LPSPI status flag state.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI status(in SR register).

static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)

Gets the LPSPI Tx FIFO size.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Tx FIFO size.

static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)

Gets the LPSPI Rx FIFO size.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Rx FIFO size.

static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)

Gets the LPSPI Tx FIFO count.

Parameters:

• base – LPSPI peripheral address.

Returns:

The number of words in the transmit FIFO.

static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)

Gets the LPSPI Rx FIFO count.

Parameters:

• base – LPSPI peripheral address.

Returns:

The number of words in the receive FIFO.

static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)

Clears the LPSPI status flag.

This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage:

LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);

Parameters:

• base – LPSPI peripheral address.

• statusFlags – The status flag used from type _lpspi_flags.

static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)

static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI interrupts.

This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.

LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI interrupts.

LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)

Enables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)

Disables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

• base – LPSPI peripheral address.

• mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Transmit Data Register address for a DMA operation.

This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Transmit Data Register address.

static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)

Gets the LPSPI Receive Data Register address for a DMA operation.

This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The LPSPI Receive Data Register address.

bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)

Check the argument for transfer .

Parameters:

• base – LPSPI peripheral address.

• transfer – the transfer struct to be used.

• isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer

Returns:

Return true for right and false for wrong.

static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)

Configures the LPSPI for either master or slave.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters:

• base – LPSPI peripheral address.

• mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t.

static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)

Configures the peripheral chip select used for the transfer.

Parameters:

• base – LPSPI peripheral address.

• select – LPSPI Peripheral Chip Select (PCS) configuration.

static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)

Set the PCS signal to continuous or uncontinuous mode.

Note

In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).

Parameters:

• base – LPSPI peripheral address.

• IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.

static inline bool LPSPI_IsMaster(LPSPI_Type *base)

Returns whether the LPSPI module is in master mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

Returns true if the module is in master mode or false if the module is in slave mode.

static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)

Flushes the LPSPI FIFOs.

Parameters:

• base – LPSPI peripheral address.

• flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.

• flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.

static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)

Sets the transmit and receive FIFO watermark values.

This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters:

• base – LPSPI peripheral address.

• txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

• rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)

Configures all LPSPI peripheral chip select polarities simultaneously.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific.

LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);

Parameters:

• base – LPSPI peripheral address.

• mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity.

static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)

Configures the frame size.

The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.

Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.

Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters:

• base – LPSPI peripheral address.

• frameSize – The frame size in number of bits.

uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)

Sets the LPSPI baud rate in bits per second.

This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• baudRate_Bps – The desired baud rate in bits per second.

• srcClock_Hz – Module source input clock in Hertz.

• tcrPrescaleValue – The TCR prescale value needed to program the TCR.

Returns:

The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.

void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).

This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• scaler – The 8-bit delay value 0x00 to 0xFF (255).

• whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.

uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).

This function configures the SCK to PCS delay, PCS to SCK delay, or the delay between transfers. The delay names are available in type lpspi_delay_type_t.

The function calculates the value needed for the desired delay parameter and returns the actual calculated delay. An exact delay match may not be possible, in which case the closest match is calculated without going below the desired delay value. If the input exceeds the maximum capability, the maximum supported delay is returned.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

• base – LPSPI peripheral address.

• delayTimeInNanoSec – The desired delay value in nanoseconds.

• whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.

• srcClock_Hz – Module source input clock in Hertz.

Returns:

Actual calculated delay value in nanoseconds.

static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)

Writes data into the transmit data buffer.

This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters:

• base – LPSPI peripheral address.

• data – The data word to be sent.

static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)

Reads data from the data buffer.

This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters:

• base – LPSPI peripheral address.

Returns:

The data read from the data buffer.

void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)

Set up the dummy data.

Parameters:

• base – LPSPI peripheral address.

• dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.

void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)

Initializes the LPSPI master handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

• base – LPSPI peripheral address.

• handle – LPSPI handle pointer to lpspi_master_handle_t.

• callback – DSPI callback.

• userData – callback function parameter.

status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)

LPSPI master transfer data using a polling method.

This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using an interrupt method.

This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)

Gets the master transfer remaining bytes.

This function gets the master transfer remaining bytes.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI master abort transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)

LPSPI Master IRQ handler function.

This function processes the LPSPI transmit and receive IRQ.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)

Initializes the LPSPI slave handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

• base – LPSPI peripheral address.

• handle – LPSPI handle pointer to lpspi_slave_handle_t.

• callback – DSPI callback.

• userData – callback function parameter.

status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfer data using an interrupt method.

This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)

Gets the slave transfer remaining bytes.

This function gets the slave transfer remaining bytes.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI slave aborts a transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)

LPSPI Slave IRQ handler function.

This function processes the LPSPI transmit and receives an IRQ.

Parameters:

• base – LPSPI peripheral address.

• handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)

Wait for tx FIFO to be empty.

This function wait the tx fifo empty

Parameters:

• base – LPSPI peripheral address.

Returns:

true for the tx FIFO is ready, false is not.

void LPSPI_DriverIRQHandler(uint32_t instance)

LPSPI driver IRQ handler common entry.

This function provides the common IRQ request entry for LPSPI.

Parameters:

• instance – LPSPI instance.

FSL_LPSPI_DRIVER_VERSION

LPSPI driver version.

Status for the LPSPI driver.

Values:

enumerator kStatus_LPSPI_Busy

LPSPI transfer is busy.

enumerator kStatus_LPSPI_Error

LPSPI driver error.

enumerator kStatus_LPSPI_Idle

LPSPI is idle.

enumerator kStatus_LPSPI_OutOfRange

LPSPI transfer out Of range.

enumerator kStatus_LPSPI_Timeout

LPSPI timeout polling status flags.

enum _lpspi_flags

LPSPI status flags in SPIx_SR register.

Values:

enumerator kLPSPI_TxDataRequestFlag

Transmit data flag

enumerator kLPSPI_RxDataReadyFlag

Receive data flag

enumerator kLPSPI_WordCompleteFlag

Word Complete flag

enumerator kLPSPI_FrameCompleteFlag

Frame Complete flag

enumerator kLPSPI_TransferCompleteFlag

Transfer Complete flag

enumerator kLPSPI_TransmitErrorFlag

Transmit Error flag (FIFO underrun)

enumerator kLPSPI_ReceiveErrorFlag

Receive Error flag (FIFO overrun)

enumerator kLPSPI_DataMatchFlag

Data Match flag

enumerator kLPSPI_ModuleBusyFlag

Module Busy flag

enumerator kLPSPI_AllStatusFlag

Used for clearing all w1c status flags

enum _lpspi_interrupt_enable

LPSPI interrupt source.

Values:

enumerator kLPSPI_TxInterruptEnable

Transmit data interrupt enable

enumerator kLPSPI_RxInterruptEnable

Receive data interrupt enable

enumerator kLPSPI_WordCompleteInterruptEnable

Word complete interrupt enable

enumerator kLPSPI_FrameCompleteInterruptEnable

Frame complete interrupt enable

enumerator kLPSPI_TransferCompleteInterruptEnable

Transfer complete interrupt enable

enumerator kLPSPI_TransmitErrorInterruptEnable

Transmit error interrupt enable(FIFO underrun)

enumerator kLPSPI_ReceiveErrorInterruptEnable

Receive Error interrupt enable (FIFO overrun)

enumerator kLPSPI_DataMatchInterruptEnable

Data Match interrupt enable

enumerator kLPSPI_AllInterruptEnable

All above interrupts enable.

enum _lpspi_dma_enable

LPSPI DMA source.

Values:

enumerator kLPSPI_TxDmaEnable

Transmit data DMA enable

enumerator kLPSPI_RxDmaEnable

Receive data DMA enable

enum _lpspi_master_slave_mode

LPSPI master or slave mode configuration.

Values:

enumerator kLPSPI_Master

LPSPI peripheral operates in master mode.

enumerator kLPSPI_Slave

LPSPI peripheral operates in slave mode.

enum _lpspi_which_pcs_config

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

Values:

enumerator kLPSPI_Pcs0

PCS[0]

enumerator kLPSPI_Pcs1

PCS[1]

enumerator kLPSPI_Pcs2

PCS[2]

enumerator kLPSPI_Pcs3

PCS[3]

enum _lpspi_pcs_polarity_config

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

Values:

enumerator kLPSPI_PcsActiveHigh

PCS Active High (idles low)

enumerator kLPSPI_PcsActiveLow

PCS Active Low (idles high)

enum _lpspi_pcs_polarity

LPSPI Peripheral Chip Select (PCS) Polarity.

Values:

enumerator kLPSPI_Pcs0ActiveLow

Pcs0 Active Low (idles high).

enumerator kLPSPI_Pcs1ActiveLow

Pcs1 Active Low (idles high).

enumerator kLPSPI_Pcs2ActiveLow

Pcs2 Active Low (idles high).

enumerator kLPSPI_Pcs3ActiveLow

Pcs3 Active Low (idles high).

enumerator kLPSPI_PcsAllActiveLow

Pcs0 to Pcs5 Active Low (idles high).

enum _lpspi_clock_polarity

LPSPI clock polarity configuration.

Values:

enumerator kLPSPI_ClockPolarityActiveHigh

CPOL=0. Active-high LPSPI clock (idles low)

enumerator kLPSPI_ClockPolarityActiveLow

CPOL=1. Active-low LPSPI clock (idles high)

enum _lpspi_clock_phase

LPSPI clock phase configuration.

Values:

enumerator kLPSPI_ClockPhaseFirstEdge

CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge.

enumerator kLPSPI_ClockPhaseSecondEdge

CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge.

enum _lpspi_shift_direction

LPSPI data shifter direction options.

Values:

enumerator kLPSPI_MsbFirst

Data transfers start with most significant bit.

enumerator kLPSPI_LsbFirst

Data transfers start with least significant bit.

enum _lpspi_host_request_select

LPSPI Host Request select configuration.

Values:

enumerator kLPSPI_HostReqExtPin

Host Request is an ext pin.

enumerator kLPSPI_HostReqInternalTrigger

Host Request is an internal trigger.

enum _lpspi_match_config

LPSPI Match configuration options.

Values:

enumerator kLPSI_MatchDisabled

LPSPI Match Disabled.

enumerator kLPSI_1stWordEqualsM0orM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0orM1

LPSPI Match Enabled.

enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1

LPSPI Match Enabled.

enumerator kLPSI_1stWordAndM1EqualsM0andM1

LPSPI Match Enabled.

enumerator kLPSI_AnyWordAndM1EqualsM0andM1

LPSPI Match Enabled.

enum _lpspi_pin_config

LPSPI pin (SDO and SDI) configuration.

Values:

enumerator kLPSPI_SdiInSdoOut

LPSPI SDI input, SDO output.

enumerator kLPSPI_SdiInSdiOut

LPSPI SDI input, SDI output.

enumerator kLPSPI_SdoInSdoOut

LPSPI SDO input, SDO output.

enumerator kLPSPI_SdoInSdiOut

LPSPI SDO input, SDI output.

enum _lpspi_data_out_config

LPSPI data output configuration.

Values:

enumerator kLpspiDataOutRetained

Data out retains last value when chip select is de-asserted

enumerator kLpspiDataOutTristate

Data out is tristated when chip select is de-asserted

enum _lpspi_transfer_width

LPSPI transfer width configuration.

Values:

enumerator kLPSPI_SingleBitXfer

1-bit shift at a time, data out on SDO, in on SDI (normal mode)

enumerator kLPSPI_TwoBitXfer

2-bits shift out on SDO/SDI and in on SDO/SDI

enumerator kLPSPI_FourBitXfer

4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2]

enum _lpspi_delay_type

LPSPI delay type selection.

Values:

enumerator kLPSPI_PcsToSck

PCS-to-SCK delay.

enumerator kLPSPI_LastSckToPcs

Last SCK edge to PCS delay.

enumerator kLPSPI_BetweenTransfer

Delay between transfers.

enum _lpspi_transfer_config_flag_for_master

Use this enumeration for LPSPI master transfer configFlags.

Values:

enumerator kLPSPI_MasterPcs0

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal

enumerator kLPSPI_MasterPcs1

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal

enumerator kLPSPI_MasterPcs2

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal

enumerator kLPSPI_MasterPcs3

LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal

enumerator kLPSPI_MasterPcsContinuous

Is PCS signal continuous

enumerator kLPSPI_MasterByteSwap

Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.

2. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

3. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

enum _lpspi_transfer_config_flag_for_slave

Use this enumeration for LPSPI slave transfer configFlags.

Values:

enumerator kLPSPI_SlavePcs0

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal

enumerator kLPSPI_SlavePcs1

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal

enumerator kLPSPI_SlavePcs2

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal

enumerator kLPSPI_SlavePcs3

LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal

enumerator kLPSPI_SlaveByteSwap

Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.

2. If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

3. If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

enum _lpspi_transfer_state

LPSPI transfer state, which is used for LPSPI transactional API state machine.

Values:

enumerator kLPSPI_Idle

Nothing in the transmitter/receiver.

enumerator kLPSPI_Busy

Transfer queue is not finished.

enumerator kLPSPI_Error

Transfer error.

typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t

LPSPI master or slave mode configuration.

typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t

LPSPI clock polarity configuration.

typedef enum _lpspi_clock_phase lpspi_clock_phase_t

LPSPI clock phase configuration.

typedef enum _lpspi_shift_direction lpspi_shift_direction_t

LPSPI data shifter direction options.

typedef enum _lpspi_host_request_select lpspi_host_request_select_t

LPSPI Host Request select configuration.

typedef enum _lpspi_match_config lpspi_match_config_t

LPSPI Match configuration options.

typedef enum _lpspi_pin_config lpspi_pin_config_t

LPSPI pin (SDO and SDI) configuration.

typedef enum _lpspi_data_out_config lpspi_data_out_config_t

LPSPI data output configuration.

typedef enum _lpspi_transfer_width lpspi_transfer_width_t

LPSPI transfer width configuration.

typedef enum _lpspi_delay_type lpspi_delay_type_t

LPSPI delay type selection.

typedef struct _lpspi_master_config lpspi_master_config_t

LPSPI master configuration structure.

typedef struct _lpspi_slave_config lpspi_slave_config_t

LPSPI slave configuration structure.

typedef struct _lpspi_master_handle lpspi_master_handle_t

Forward declaration of the _lpspi_master_handle typedefs.

typedef struct _lpspi_slave_handle lpspi_slave_handle_t

Forward declaration of the _lpspi_slave_handle typedefs.

typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)

Master completion callback function pointer type.

Param base:

LPSPI peripheral address.

Param handle:

Pointer to the handle for the LPSPI master.

Param status:

Success or error code describing whether the transfer is completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)

Slave completion callback function pointer type.

Param base:

LPSPI peripheral address.

Param handle:

Pointer to the handle for the LPSPI slave.

Param status:

Success or error code describing whether the transfer is completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef struct _lpspi_transfer lpspi_transfer_t

LPSPI master/slave transfer structure.

volatile uint8_t g_lpspiDummyData[]

Global variable for dummy data value setting.

LPSPI_DUMMY_DATA

LPSPI dummy data if no Tx data.

Dummy data used for tx if there is not txData.

SPI_RETRY_TIMES

Retry times for waiting flag.

LPSPI_MASTER_PCS_SHIFT

LPSPI master PCS shift macro , internal used.

LPSPI_MASTER_PCS_MASK

LPSPI master PCS shift macro , internal used.

LPSPI_SLAVE_PCS_SHIFT

LPSPI slave PCS shift macro , internal used.

LPSPI_SLAVE_PCS_MASK

LPSPI slave PCS shift macro , internal used.

struct _lpspi_master_config

#include <fsl_lpspi.h>

LPSPI master configuration structure.

Public Members

uint32_t baudRate

Baud Rate for LPSPI.

uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol

Clock polarity.

lpspi_clock_phase_t cpha

Clock phase.

lpspi_shift_direction_t direction

MSB or LSB data shift direction.

uint32_t pcsToSckDelayInNanoSec

PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t lastSckToPcsDelayInNanoSec

Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t betweenTransferDelayInNanoSec

After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (PCS).

lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low

lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

bool enableInputDelay

Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length.

struct _lpspi_slave_config

#include <fsl_lpspi.h>

LPSPI slave configuration structure.

Public Members

uint32_t bitsPerFrame

Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol

Clock polarity.

lpspi_clock_phase_t cpha

Clock phase.

lpspi_shift_direction_t direction

MSB or LSB data shift direction.

lpspi_which_pcs_t whichPcs

Desired Peripheral Chip Select (pcs)

lpspi_pcs_polarity_config_t pcsActiveHighOrLow

Desired PCS active high or low

lpspi_pin_config_t pinCfg

Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig

Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

struct _lpspi_transfer

#include <fsl_lpspi.h>

LPSPI master/slave transfer structure.

Public Members

const uint8_t *txData

Send buffer.

uint8_t *rxData

Receive buffer.

volatile size_t dataSize

Transfer bytes.

uint32_t configFlags

Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave.

struct _lpspi_master_handle

#include <fsl_lpspi.h>

LPSPI master transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous

Is PCS continuous in transfer.

volatile bool writeTcrInIsr

A flag that whether should write TCR in ISR.

volatile bool isByteSwap

A flag that whether should byte swap.

volatile bool isTxMask

A flag that whether TCR[TXMSK] is set.

volatile uint16_t bytesPerFrame

Number of bytes in each frame

volatile uint16_t frameSize

Backup of TCR[FRAMESZ]

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

uint32_t txBuffIfNull

Used if the txData is NULL.

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

lpspi_master_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

struct _lpspi_slave_handle

#include <fsl_lpspi.h>

LPSPI slave transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

volatile uint32_t errorCount

Error count for slave transfer.

lpspi_slave_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

LPSPI eDMA Driver

FSL_LPSPI_EDMA_DRIVER_VERSION

LPSPI EDMA driver version.

DMA_MAX_TRANSFER_COUNT

DMA max transfer size.

typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t

Forward declaration of the _lpspi_master_edma_handle typedefs.

typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t

Forward declaration of the _lpspi_slave_edma_handle typedefs.

typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type.

Param base:

LPSPI peripheral base address.

Param handle:

Pointer to the handle for the LPSPI master.

Param status:

Success or error code describing whether the transfer completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)

Completion callback function pointer type.

Param base:

LPSPI peripheral base address.

Param handle:

Pointer to the handle for the LPSPI slave.

Param status:

Success or error code describing whether the transfer completed.

Param userData:

Arbitrary pointer-dataSized value passed from the application.

void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI master eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.

Parameters:

• base – LPSPI peripheral base address.

• handle – LPSPI handle pointer to lpspi_master_edma_handle_t.

• callback – LPSPI callback.

• userData – callback function parameter.

• edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.

• edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)

LPSPI master config transfer parameter while using eDMA.

This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master.

Return values:

• kStatus_Success – Execution successfully.

• kStatus_LPSPI_Busy – The LPSPI device is busy.

Returns:

Indicates whether LPSPI master transfer was successful or not.

status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI master transfer data using eDMA without configs.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure, config field is not uesed.

Return values:

• kStatus_Success – Execution successfully.

• kStatus_LPSPI_Busy – The LPSPI device is busy.

• kStatus_InvalidArgument – The transfer structure is invalid.

Returns:

Indicates whether LPSPI master transfer was successful or not.

void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)

LPSPI master aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)

Gets the master eDMA transfer remaining bytes.

This function gets the master eDMA transfer remaining bytes.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the EDMA transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)

Initializes the LPSPI slave eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.

(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .

Parameters:

• base – LPSPI peripheral base address.

• handle – LPSPI handle pointer to lpspi_slave_edma_handle_t.

• callback – LPSPI callback.

• userData – callback function parameter.

• edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.

• edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)

LPSPI slave transfers data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

• transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)

LPSPI slave aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)

Gets the slave eDMA transfer remaining bytes.

This function gets the slave eDMA transfer remaining bytes.

Parameters:

• base – LPSPI peripheral base address.

• handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

• count – Number of bytes transferred so far by the eDMA transaction.

Returns:

status of status_t.

struct _lpspi_master_edma_handle

#include <fsl_lpspi_edma.h>

LPSPI master eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous

Is PCS continuous in transfer.

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

volatile uint8_t bytesLastRead

Bytes for last read RDR.

volatile bool isThereExtraRxBytes

Is there extra RX byte.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

edma_tcd_t *lastTimeTCD

Pointer to the lastTime TCD

bool isMultiDMATransmit

Is there multi DMA transmit

volatile uint8_t dmaTransmitTime

DMA Transfer times.

uint32_t lastTimeDataBytes

DMA transmit last Time data Bytes

uint32_t dataBytesEveryTime

Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT

edma_transfer_config_t transferConfigRx

Config of DMA rx channel.

edma_transfer_config_t transferConfigTx

Config of DMA tx channel.

uint32_t txBuffIfNull

Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose.

uint32_t transmitCommand

Used to write TCR for DMA purpose.

volatile uint8_t state

LPSPI transfer state , _lpspi_transfer_state.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

lpspi_master_edma_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg buff

edma_tcd_t lpspiSoftwareTCD[3]

SoftwareTCD, internal used

struct _lpspi_slave_edma_handle

#include <fsl_lpspi_edma.h>

LPSPI slave eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap

A flag that whether should byte swap.

volatile uint8_t fifoSize

FIFO dataSize.

volatile uint8_t rxWatermark

Rx watermark.

volatile uint8_t bytesEachWrite

Bytes for each write TDR.

volatile uint8_t bytesEachRead

Bytes for each read RDR.

volatile uint8_t bytesLastRead

Bytes for last read RDR.

volatile bool isThereExtraRxBytes

Is there extra RX byte.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

const uint8_t *volatile txData

Send buffer.

uint8_t *volatile rxData

Receive buffer.

volatile size_t txRemainingByteCount

Number of bytes remaining to send.

volatile size_t rxRemainingByteCount

Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes

Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes

Read RDR register remaining times.

uint32_t totalByteCount

Number of transfer bytes

uint32_t txBuffIfNull

Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull

Used if there is not rxData for DMA purpose.

volatile uint8_t state

LPSPI transfer state.

uint32_t errorCount

Error count for slave transfer.

lpspi_slave_edma_transfer_callback_t callback

Completion callback.

void *userData

Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle

edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle

edma_handle_t handle point used for TxData to TxReg

edma_tcd_t lpspiSoftwareTCD[2]

SoftwareTCD, internal used

LPTMR: Low-Power Timer

void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)

Ungates the LPTMR clock and configures the peripheral for a basic operation.

Note

This API should be called at the beginning of the application using the LPTMR driver.

Parameters:

• base – LPTMR peripheral base address

• config – A pointer to the LPTMR configuration structure.

void LPTMR_Deinit(LPTMR_Type *base)

Gates the LPTMR clock.

Parameters:

• base – LPTMR peripheral base address

void LPTMR_GetDefaultConfig(lptmr_config_t *config)

Fills in the LPTMR configuration structure with default settings.

The default values are as follows.

config->timerMode = kLPTMR_TimerModeTimeCounter;
config->pinSelect = kLPTMR_PinSelectInput_0;
config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
config->enableFreeRunning = false;
config->bypassPrescaler = true;
config->prescalerClockSource = kLPTMR_PrescalerClock_1;
config->value = kLPTMR_Prescale_Glitch_0;

Parameters:

• config – A pointer to the LPTMR configuration structure.

static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)

Enables the selected LPTMR interrupts.

Parameters:

• base – LPTMR peripheral base address

• mask – The interrupts to enable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t

static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)

Disables the selected LPTMR interrupts.

Parameters:

• base – LPTMR peripheral base address

• mask – The interrupts to disable. This is a logical OR of members of the enumeration lptmr_interrupt_enable_t.

static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)

Gets the enabled LPTMR interrupts.

Parameters:

• base – LPTMR peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration lptmr_interrupt_enable_t

static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)

Gets the LPTMR status flags.

Parameters:

• base – LPTMR peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration lptmr_status_flags_t

static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)

Clears the LPTMR status flags.

Parameters:

• base – LPTMR peripheral base address

• mask – The status flags to clear. This is a logical OR of members of the enumeration lptmr_status_flags_t.

static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)

Sets the timer period in units of count.

Timers counts from 0 until it equals the count value set here. The count value is written to the CMR register.

Note

1. The TCF flag is set with the CNR equals the count provided here and then increments.

2. Call the utility macros provided in the fsl_common.h to convert to ticks.

Parameters:

• base – LPTMR peripheral base address

• ticks – A timer period in units of ticks

static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)

Reads the current timer counting value.

This function returns the real-time timer counting value in a range from 0 to a timer period.

Note

Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.

Parameters:

• base – LPTMR peripheral base address

Returns:

The current counter value in ticks

static inline void LPTMR_StartTimer(LPTMR_Type *base)

Starts the timer.

After calling this function, the timer counts up to the CMR register value. Each time the timer reaches the CMR value and then increments, it generates a trigger pulse and sets the timeout interrupt flag. An interrupt is also triggered if the timer interrupt is enabled.

Parameters:

• base – LPTMR peripheral base address

static inline void LPTMR_StopTimer(LPTMR_Type *base)

Stops the timer.

This function stops the timer and resets the timer’s counter register.

Parameters:

• base – LPTMR peripheral base address

FSL_LPTMR_DRIVER_VERSION

Driver Version

enum _lptmr_pin_select

LPTMR pin selection used in pulse counter mode.

Values:

enumerator kLPTMR_PinSelectInput_0

Pulse counter input 0 is selected

enumerator kLPTMR_PinSelectInput_1

Pulse counter input 1 is selected

enumerator kLPTMR_PinSelectInput_2

Pulse counter input 2 is selected

enumerator kLPTMR_PinSelectInput_3

Pulse counter input 3 is selected

enum _lptmr_pin_polarity

LPTMR pin polarity used in pulse counter mode.

Values:

enumerator kLPTMR_PinPolarityActiveHigh

Pulse Counter input source is active-high

enumerator kLPTMR_PinPolarityActiveLow

Pulse Counter input source is active-low

enum _lptmr_timer_mode

LPTMR timer mode selection.

Values:

enumerator kLPTMR_TimerModeTimeCounter

Time Counter mode

enumerator kLPTMR_TimerModePulseCounter

Pulse Counter mode

enum _lptmr_prescaler_glitch_value

LPTMR prescaler/glitch filter values.

Values:

enumerator kLPTMR_Prescale_Glitch_0

Prescaler divide 2, glitch filter does not support this setting

enumerator kLPTMR_Prescale_Glitch_1

Prescaler divide 4, glitch filter 2

enumerator kLPTMR_Prescale_Glitch_2

Prescaler divide 8, glitch filter 4

enumerator kLPTMR_Prescale_Glitch_3

Prescaler divide 16, glitch filter 8

enumerator kLPTMR_Prescale_Glitch_4

Prescaler divide 32, glitch filter 16

enumerator kLPTMR_Prescale_Glitch_5

Prescaler divide 64, glitch filter 32

enumerator kLPTMR_Prescale_Glitch_6

Prescaler divide 128, glitch filter 64

enumerator kLPTMR_Prescale_Glitch_7

Prescaler divide 256, glitch filter 128

enumerator kLPTMR_Prescale_Glitch_8

Prescaler divide 512, glitch filter 256

enumerator kLPTMR_Prescale_Glitch_9

Prescaler divide 1024, glitch filter 512

enumerator kLPTMR_Prescale_Glitch_10

Prescaler divide 2048 glitch filter 1024

enumerator kLPTMR_Prescale_Glitch_11

Prescaler divide 4096, glitch filter 2048

enumerator kLPTMR_Prescale_Glitch_12

Prescaler divide 8192, glitch filter 4096

enumerator kLPTMR_Prescale_Glitch_13

Prescaler divide 16384, glitch filter 8192

enumerator kLPTMR_Prescale_Glitch_14

Prescaler divide 32768, glitch filter 16384

enumerator kLPTMR_Prescale_Glitch_15

Prescaler divide 65536, glitch filter 32768

enum _lptmr_prescaler_clock_select

LPTMR prescaler/glitch filter clock select.

Note

Clock connections are SoC-specific

Values:

enum _lptmr_interrupt_enable

List of the LPTMR interrupts.

Values:

enumerator kLPTMR_TimerInterruptEnable

Timer interrupt enable

enum _lptmr_status_flags

List of the LPTMR status flags.

Values:

enumerator kLPTMR_TimerCompareFlag

Timer compare flag

typedef enum _lptmr_pin_select lptmr_pin_select_t

LPTMR pin selection used in pulse counter mode.

typedef enum _lptmr_pin_polarity lptmr_pin_polarity_t

LPTMR pin polarity used in pulse counter mode.

typedef enum _lptmr_timer_mode lptmr_timer_mode_t

LPTMR timer mode selection.

typedef enum _lptmr_prescaler_glitch_value lptmr_prescaler_glitch_value_t

LPTMR prescaler/glitch filter values.

typedef enum _lptmr_prescaler_clock_select lptmr_prescaler_clock_select_t

LPTMR prescaler/glitch filter clock select.

Note

Clock connections are SoC-specific

typedef enum _lptmr_interrupt_enable lptmr_interrupt_enable_t

List of the LPTMR interrupts.

typedef enum _lptmr_status_flags lptmr_status_flags_t

List of the LPTMR status flags.

typedef struct _lptmr_config lptmr_config_t

LPTMR config structure.

This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration struct can be made constant so it resides in flash.

static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)

Enable or disable timer DMA request.

Toggles CSR[TDRE] on the LPTMR side only: when enabled, every compare event (CSR[TCF]=1) raises an LPTMR DMA request line which is auto-cleared after the DMA controller services it.

Note

LPTMR runs on a low-power clock that is asynchronous to the EDMA bus clock. On some EDMA IP variants the channel has TWO gates that must BOTH be opened for an LPTMR request to be accepted: the base hardware request gate (ERQ, opened by EDMA_EnableChannelRequest()) and an extra asynchronous-request gate (opened by EDMA_EnableAsyncRequest() on EDMA4; the classic EDMA + DMAMUX combination does not need this).

Parameters:

• base – base LPTMR peripheral base address

• enable – Switcher of timer DMA feature. “true” means to enable, “false” means to disable.

struct _lptmr_config

#include <fsl_lptmr.h>

LPTMR config structure.

This structure holds the configuration settings for the LPTMR peripheral. To initialize this structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration struct can be made constant so it resides in flash.

Public Members

lptmr_timer_mode_t timerMode

Time counter mode or pulse counter mode

lptmr_pin_select_t pinSelect

LPTMR pulse input pin select; used only in pulse counter mode

lptmr_pin_polarity_t pinPolarity

LPTMR pulse input pin polarity; used only in pulse counter mode

bool enableFreeRunning

True: enable free running, counter is reset on overflow False: counter is reset when the compare flag is set

bool bypassPrescaler

True: bypass prescaler; false: use clock from prescaler

lptmr_prescaler_clock_select_t prescalerClockSource

LPTMR clock source

lptmr_prescaler_glitch_value_t value

Prescaler or glitch filter value

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver

LPUART Driver

static inline void LPUART_SoftwareReset(LPUART_Type *base)

Resets the LPUART using software.

This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.

Parameters:

• base – LPUART peripheral base address.

status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)

Initializes an LPUART instance with the user configuration structure and the peripheral clock.

This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART.

lpuart_config_t lpuartConfig;
lpuartConfig.baudRate_Bps = 115200U;
lpuartConfig.parityMode = kLPUART_ParityDisabled;
lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
lpuartConfig.isMsb = false;
lpuartConfig.stopBitCount = kLPUART_OneStopBit;
lpuartConfig.txFifoWatermark = 0;
lpuartConfig.rxFifoWatermark = 1;
LPUART_Init(LPUART1, &lpuartConfig, 20000000U);

Parameters:

• base – LPUART peripheral base address.

• config – Pointer to a user-defined configuration structure.

• srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

• kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source.

• kStatus_Success – LPUART initialize succeed

status_t LPUART_Deinit(LPUART_Type *base)

Deinitializes a LPUART instance.

This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.

Parameters:

• base – LPUART peripheral base address.

Return values:

• kStatus_Success – Deinit is success.

• kStatus_LPUART_Timeout – Timeout during deinit.

void LPUART_GetDefaultConfig(lpuart_config_t *config)

Gets the default configuration structure.

This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;

Parameters:

• config – Pointer to a configuration structure.

status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)

Sets the LPUART instance baudrate.

This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.

LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);

Parameters:

• base – LPUART peripheral base address.

• baudRate_Bps – LPUART baudrate to be set.

• srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

• kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source.

• kStatus_Success – Set baudrate succeeded.

void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)

Enable 9-bit data mode for LPUART.

This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.

Parameters:

• base – LPUART peripheral base address.

• enable – true to enable, flase to disable.

static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)

Set the LPUART address.

This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.

Note

Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.

Parameters:

• base – LPUART peripheral base address.

• address1 – LPUART slave address1.

• address2 – LPUART slave address2.

static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)

Enable the LPUART match address feature.

Parameters:

• base – LPUART peripheral base address.

• match1 – true to enable match address1, false to disable.

• match2 – true to enable match address2, false to disable.

static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the rx FIFO watermark.

Parameters:

• base – LPUART peripheral base address.

• water – Rx FIFO watermark.

static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)

Sets the tx FIFO watermark.

Parameters:

• base – LPUART peripheral base address.

• water – Tx FIFO watermark.

static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)

Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.

This function Enable 16bit Data transmit in lpuart_handle_t.

Parameters:

• handle – LPUART handle pointer.

• enable – true to enable, false to disable.

uint32_t LPUART_GetStatusFlags(LPUART_Type *base)

Gets LPUART status flags.

This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty:

if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
{
    ...
}

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART status flags which are ORed by the enumerators in the _lpuart_flags.

status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)

Clears status flags with a provided mask.

This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.

Parameters:

• base – LPUART peripheral base address.

• mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask.

Return values:

• kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware.

• kStatus_Success – Status in the mask are cleared.

Returns:

0 succeed, others failed.

void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)

Enables LPUART interrupts according to a provided mask.

This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt:

LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

• base – LPUART peripheral base address.

• mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable.

void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)

Disables LPUART interrupts according to a provided mask.

This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt:

LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

• base – LPUART peripheral base address.

• mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable.

uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)

Gets enabled LPUART interrupts.

This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:

uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);

if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
{
    ...
}

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable.

static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)

Gets the LPUART data register address.

This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART data register addresses which are used both by the transmitter and receiver.

static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter DMA request.

This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver DMA.

This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

uint32_t LPUART_GetInstance(LPUART_Type *base)

Get the LPUART instance from peripheral base address.

Parameters:

• base – LPUART peripheral base address.

Returns:

LPUART instance.

static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)

Enables or disables the LPUART transmitter.

This function enables or disables the LPUART transmitter.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)

Enables or disables the LPUART receiver.

This function enables or disables the LPUART receiver.

Parameters:

• base – LPUART peripheral base address.

• enable – True to enable, false to disable.

static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)

Writes to the transmitter register.

This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

• base – LPUART peripheral base address.

• data – Data write to the TX register.

static inline uint8_t LPUART_ReadByte(LPUART_Type *base)

Reads the receiver register.

This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

• base – LPUART peripheral base address.

Returns:

Data read from data register.

static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)

Gets the rx FIFO data count.

Parameters:

• base – LPUART peripheral base address.

Returns:

rx FIFO data count.

static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)

Gets the tx FIFO data count.

Parameters:

• base – LPUART peripheral base address.

Returns:

tx FIFO data count.

void LPUART_SendAddress(LPUART_Type *base, uint8_t address)

Transmit an address frame in 9-bit data mode.

Parameters:

• base – LPUART peripheral base address.

• address – LPUART slave address.

status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)

Writes to the transmitter register using a blocking method.

This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the data to write.

• length – Size of the data to write.

Return values:

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)

Writes to the transmitter register using a blocking method in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the data to write.

• length – Size of the data to write.

Return values:

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully wrote all data.

status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)

Reads the receiver data register using a blocking method.

This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the buffer to store the received data.

• length – Size of the buffer.

Return values:

• kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.

• kStatus_LPUART_NoiseError – Noise error happened while receiving data.

• kStatus_LPUART_FramingError – Framing error happened while receiving data.

• kStatus_LPUART_ParityError – Parity error happened while receiving data.

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)

Reads the receiver data register in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer.

Parameters:

• base – LPUART peripheral base address.

• data – Start address of the buffer to store the received data by 16bit, only 10bit is valid.

• length – Size of the buffer.

Return values:

• kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.

• kStatus_LPUART_NoiseError – Noise error happened while receiving data.

• kStatus_LPUART_FramingError – Framing error happened while receiving data.

• kStatus_LPUART_ParityError – Parity error happened while receiving data.

• kStatus_LPUART_Timeout – Transmission timed out and was aborted.

• kStatus_Success – Successfully received all data.

void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)

Initializes the LPUART handle.

This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.

The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• callback – Callback function.

• userData – User data.

status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)

Transmits a buffer of data using the interrupt method.

This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.

Note

The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART transfer structure, see lpuart_transfer_t.

Return values:

• kStatus_Success – Successfully start the data transmission.

• kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.

Note

When using RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, then only 31 bytes are used for saving data.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.

• ringBufferSize – size of the ring buffer.

void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)

Get the length of received data in RX ring buffer.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

Returns:

Length of received data in RX ring buffer.

void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data transmit.

This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been sent out to bus.

This function gets the number of bytes that have been sent out to bus by an interrupt method.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Send bytes count.

Return values:

• kStatus_NoTransferInProgress – No send in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)

Receives a buffer of data using the interrupt method.

This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameter receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART transfer structure, see uart_transfer_t.

• receivedBytes – Bytes received from the ring buffer directly.

Return values:

• kStatus_Success – Successfully queue the transfer into the transmit queue.

• kStatus_LPUART_RxBusy – Previous receive request is not finished.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)

Aborts the interrupt-driven data receiving.

This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)

Gets the number of bytes that have been received.

This function gets the number of bytes that have been received.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Receive bytes count.

Return values:

• kStatus_NoTransferInProgress – No receive in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)

LPUART IRQ handle function.

This function handles the LPUART transmit and receive IRQ request.

Parameters:

• base – LPUART peripheral base address.

• irqHandle – LPUART handle pointer.

void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)

LPUART Error IRQ handle function.

This function handles the LPUART error IRQ request.

Parameters:

• base – LPUART peripheral base address.

• irqHandle – LPUART handle pointer.

void LPUART_DriverIRQHandler(uint32_t instance)

LPUART driver IRQ handler common entry.

This function provides the common IRQ request entry for LPUART.

Parameters:

• instance – LPUART instance.

FSL_LPUART_DRIVER_VERSION

LPUART driver version.

Error codes for the LPUART driver.

Values:

enumerator kStatus_LPUART_TxBusy

TX busy

enumerator kStatus_LPUART_RxBusy

RX busy

enumerator kStatus_LPUART_TxIdle

LPUART transmitter is idle.

enumerator kStatus_LPUART_RxIdle

LPUART receiver is idle.

enumerator kStatus_LPUART_TxWatermarkTooLarge

TX FIFO watermark too large

enumerator kStatus_LPUART_RxWatermarkTooLarge

RX FIFO watermark too large

enumerator kStatus_LPUART_FlagCannotClearManually

Some flag can’t manually clear

enumerator kStatus_LPUART_Error

Error happens on LPUART.

enumerator kStatus_LPUART_RxRingBufferOverrun

LPUART RX software ring buffer overrun.

enumerator kStatus_LPUART_RxHardwareOverrun

LPUART RX receiver overrun.

enumerator kStatus_LPUART_NoiseError

LPUART noise error.

enumerator kStatus_LPUART_FramingError

LPUART framing error.

enumerator kStatus_LPUART_ParityError

LPUART parity error.

enumerator kStatus_LPUART_BaudrateNotSupport

Baudrate is not support in current clock source

enumerator kStatus_LPUART_IdleLineDetected

IDLE flag.

enumerator kStatus_LPUART_Timeout

LPUART times out.

enum _lpuart_parity_mode

LPUART parity mode.

Values:

enumerator kLPUART_ParityDisabled

Parity disabled

enumerator kLPUART_ParityEven

Parity enabled, type even, bit setting: PE|PT = 10

enumerator kLPUART_ParityOdd

Parity enabled, type odd, bit setting: PE|PT = 11

enum _lpuart_data_bits

LPUART data bits count.

Values:

enumerator kLPUART_EightDataBits

Eight data bit

enumerator kLPUART_SevenDataBits

Seven data bit

enum _lpuart_stop_bit_count

LPUART stop bit count.

Values:

enumerator kLPUART_OneStopBit

One stop bit

enumerator kLPUART_TwoStopBit

Two stop bits

enum _lpuart_transmit_cts_source

LPUART transmit CTS source.

Values:

enumerator kLPUART_CtsSourcePin

CTS resource is the LPUART_CTS pin.

enumerator kLPUART_CtsSourceMatchResult

CTS resource is the match result.

enum _lpuart_transmit_cts_config

LPUART transmit CTS configure.

Values:

enumerator kLPUART_CtsSampleAtStart

CTS input is sampled at the start of each character.

enumerator kLPUART_CtsSampleAtIdle

CTS input is sampled when the transmitter is idle

enum _lpuart_transmit_rts_polarity

LPUART transmitter RTS polarity.

Values:

enumerator kLPUART_RtsPolarityLow

Transmitter RTS is active low.

enumerator kLPUART_RtsPolarityHigh

Transmitter RTS is active high.

enum _lpuart_idle_type_select

LPUART idle flag type defines when the receiver starts counting.

Values:

enumerator kLPUART_IdleTypeStartBit

Start counting after a valid start bit.

enumerator kLPUART_IdleTypeStopBit

Start counting after a stop bit.

enum _lpuart_idle_config

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

Values:

enumerator kLPUART_IdleCharacter1

the number of idle characters.

enumerator kLPUART_IdleCharacter2

the number of idle characters.

enumerator kLPUART_IdleCharacter4

the number of idle characters.

enumerator kLPUART_IdleCharacter8

the number of idle characters.

enumerator kLPUART_IdleCharacter16

the number of idle characters.

enumerator kLPUART_IdleCharacter32

the number of idle characters.

enumerator kLPUART_IdleCharacter64

the number of idle characters.

enumerator kLPUART_IdleCharacter128

the number of idle characters.

enum _lpuart_interrupt_enable

LPUART interrupt configuration structure, default settings all disabled.

This structure contains the settings for all LPUART interrupt configurations.

Values:

enumerator kLPUART_LinBreakInterruptEnable

LIN break detect. bit 7

enumerator kLPUART_RxActiveEdgeInterruptEnable

Receive Active Edge. bit 6

enumerator kLPUART_TxDataRegEmptyInterruptEnable

Transmit data register empty. bit 23

enumerator kLPUART_TransmissionCompleteInterruptEnable

Transmission complete. bit 22

enumerator kLPUART_RxDataRegFullInterruptEnable

Receiver data register full. bit 21

enumerator kLPUART_IdleLineInterruptEnable

Idle line. bit 20

enumerator kLPUART_RxOverrunInterruptEnable

Receiver Overrun. bit 27

enumerator kLPUART_NoiseErrorInterruptEnable

Noise error flag. bit 26

enumerator kLPUART_FramingErrorInterruptEnable

Framing error flag. bit 25

enumerator kLPUART_ParityErrorInterruptEnable

Parity error flag. bit 24

enumerator kLPUART_Match1InterruptEnable

Parity error flag. bit 15

enumerator kLPUART_Match2InterruptEnable

Parity error flag. bit 14

enumerator kLPUART_TxFifoOverflowInterruptEnable

Transmit FIFO Overflow. bit 9

enumerator kLPUART_RxFifoUnderflowInterruptEnable

Receive FIFO Underflow. bit 8

enumerator kLPUART_AllInterruptEnable

enum _lpuart_flags

LPUART status flags.

This provides constants for the LPUART status flags for use in the LPUART functions.

Values:

enumerator kLPUART_TxDataRegEmptyFlag

Transmit data register empty flag, sets when transmit buffer is empty. bit 23

enumerator kLPUART_TransmissionCompleteFlag

Transmission complete flag, sets when transmission activity complete. bit 22

enumerator kLPUART_RxDataRegFullFlag

Receive data register full flag, sets when the receive data buffer is full. bit 21

enumerator kLPUART_IdleLineFlag

Idle line detect flag, sets when idle line detected. bit 20

enumerator kLPUART_RxOverrunFlag

Receive Overrun, sets when new data is received before data is read from receive register. bit 19

enumerator kLPUART_NoiseErrorFlag

Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18

enumerator kLPUART_FramingErrorFlag

Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17

enumerator kLPUART_ParityErrorFlag

If parity enabled, sets upon parity error detection. bit 16

enumerator kLPUART_LinBreakFlag

LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31

enumerator kLPUART_RxActiveEdgeFlag

Receive pin active edge interrupt flag, sets when active edge detected. bit 30

enumerator kLPUART_RxActiveFlag

Receiver Active Flag (RAF), sets at beginning of valid start. bit 24

enumerator kLPUART_DataMatch1Flag

The next character to be read from LPUART_DATA matches MA1. bit 15

enumerator kLPUART_DataMatch2Flag

The next character to be read from LPUART_DATA matches MA2. bit 14

enumerator kLPUART_TxFifoEmptyFlag

TXEMPT bit, sets if transmit buffer is empty. bit 7

enumerator kLPUART_RxFifoEmptyFlag

RXEMPT bit, sets if receive buffer is empty. bit 6

enumerator kLPUART_TxFifoOverflowFlag

TXOF bit, sets if transmit buffer overflow occurred. bit 1

enumerator kLPUART_RxFifoUnderflowFlag

RXUF bit, sets if receive buffer underflow occurred. bit 0

enumerator kLPUART_AllClearFlags

enumerator kLPUART_AllFlags

typedef enum _lpuart_parity_mode lpuart_parity_mode_t

LPUART parity mode.

typedef enum _lpuart_data_bits lpuart_data_bits_t

LPUART data bits count.

typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t

LPUART stop bit count.

typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t

LPUART transmit CTS source.

typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t

LPUART transmit CTS configure.

typedef enum _lpuart_transmit_rts_polarity lpuart_transmit_rts_polarity_t

LPUART transmitter RTS polarity.

typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t

LPUART idle flag type defines when the receiver starts counting.

typedef enum _lpuart_idle_config lpuart_idle_config_t

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

typedef struct _lpuart_config lpuart_config_t

LPUART configuration structure.

typedef struct _lpuart_transfer lpuart_transfer_t

LPUART transfer structure.

typedef struct _lpuart_handle lpuart_handle_t

typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function.

typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)

void *s_lpuartHandle[]

const IRQn_Type s_lpuartTxIRQ[]

lpuart_isr_t s_lpuartIsr[]

UART_RETRY_TIMES

Retry times for waiting flag.

struct _lpuart_config

#include <fsl_lpuart.h>

LPUART configuration structure.

Public Members

uint32_t baudRate_Bps

LPUART baud rate

lpuart_parity_mode_t parityMode

Parity mode, disabled (default), even, odd

lpuart_data_bits_t dataBitsCount

Data bits count, eight (default), seven

bool isMsb

Data bits order, LSB (default), MSB

lpuart_stop_bit_count_t stopBitCount

Number of stop bits, 1 stop bit (default) or 2 stop bits

uint8_t txFifoWatermark

TX FIFO watermark

uint8_t rxFifoWatermark

RX FIFO watermark

bool enableRxRTS

RX RTS enable

bool enableTxRTS

TX RTS enable

bool enableTxCTS

TX CTS enable

lpuart_transmit_cts_source_t txCtsSource

TX CTS source

lpuart_transmit_cts_config_t txCtsConfig

TX CTS configure

lpuart_transmit_rts_polarity_t txRtsPolarity

TX RTS polarity

uint8_t rtsWatermark

RTS watermark

lpuart_idle_type_select_t rxIdleType

RX IDLE type.

lpuart_idle_config_t rxIdleConfig

RX IDLE configuration.

bool enableTx

Enable TX

bool enableRx

Enable RX

bool swapTxdRxd

Swap TXD and RXD pins

bool inverseTxd

Transmit Data Inversion - Setting true reverses the polarity of the transmitted data output

struct _lpuart_transfer

#include <fsl_lpuart.h>

LPUART transfer structure.

Public Members

size_t dataSize

The byte count to be transfer.

struct _lpuart_handle

#include <fsl_lpuart.h>

LPUART handle structure.

Public Members

volatile size_t txDataSize

Size of the remaining data to send.

size_t txDataSizeAll

Size of the data to send out.

volatile size_t rxDataSize

Size of the remaining data to receive.

size_t rxDataSizeAll

Size of the data to receive.

size_t rxRingBufferSize

Size of the ring buffer.

volatile uint16_t rxRingBufferHead

Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail

Index for the user to get data from the ring buffer.

lpuart_transfer_callback_t callback

Callback function.

void *userData

LPUART callback function parameter.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state.

bool isSevenDataBits

Seven data bits flag.

bool is16bitData

16bit data bits flag, only used for 9bit or 10bit data

union __unnamed26__

Public Members

uint8_t *data

The buffer of data to be transfer.

uint8_t *rxData

The buffer to receive data.

uint16_t *rxData16

The buffer to receive data.

const uint8_t *txData

The buffer of data to be sent.

const uint16_t *txData16

The buffer of data to be sent.

union __unnamed28__

Public Members

const uint8_t *volatile txData

Address of remaining data to send.

const uint16_t *volatile txData16

Address of remaining data to send.

union __unnamed30__

Public Members

uint8_t *volatile rxData

Address of remaining data to receive.

uint16_t *volatile rxData16

Address of remaining data to receive.

union __unnamed32__

Public Members

uint8_t *rxRingBuffer

Start address of the receiver ring buffer.

uint16_t *rxRingBuffer16

Start address of the receiver ring buffer.

LPUART eDMA Driver

void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)

Initializes the LPUART handle which is used in transactional functions.

Note

This function disables all LPUART interrupts.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

• callback – Callback function.

• userData – User data.

• txEdmaHandle – User requested DMA handle for TX DMA transfer.

• rxEdmaHandle – User requested DMA handle for RX DMA transfer.

status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• xfer – LPUART eDMA transfer structure. See lpuart_transfer_t.

Return values:

• kStatus_Success – if succeed, others failed.

• kStatus_LPUART_TxBusy – Previous transfer on going.

• kStatus_InvalidArgument – Invalid argument.

status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)

Receives data using eDMA.

This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

• xfer – LPUART eDMA transfer structure, see lpuart_transfer_t.

Return values:

• kStatus_Success – if succeed, others fail.

• kStatus_LPUART_RxBusy – Previous transfer ongoing.

• kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the sent data using eDMA.

This function aborts the sent data using eDMA.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)

Aborts the received data using eDMA.

This function aborts the received data using eDMA.

Parameters:

• base – LPUART peripheral base address.

• handle – Pointer to lpuart_edma_handle_t structure.

status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of bytes written to the LPUART TX register.

This function gets the number of bytes written to the LPUART TX register by DMA.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Send bytes count.

Return values:

• kStatus_NoTransferInProgress – No send in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)

Gets the number of received bytes.

This function gets the number of received bytes.

Parameters:

• base – LPUART peripheral base address.

• handle – LPUART handle pointer.

• count – Receive bytes count.

Return values:

• kStatus_NoTransferInProgress – No receive in progress.

• kStatus_InvalidArgument – Parameter is invalid.

• kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)

LPUART eDMA IRQ handle function.

This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application.

Note

This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.

Parameters:

• base – LPUART peripheral base address.

• lpuartEdmaHandle – LPUART handle pointer.

FSL_LPUART_EDMA_DRIVER_VERSION

LPUART EDMA driver version.

typedef struct _lpuart_edma_handle lpuart_edma_handle_t

typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)

LPUART transfer callback function.

struct _lpuart_edma_handle

#include <fsl_lpuart_edma.h>

LPUART eDMA handle.

Public Members

lpuart_edma_transfer_callback_t callback

Callback function.

void *userData

LPUART callback function parameter.

size_t rxDataSizeAll

Size of the data to receive.

size_t txDataSizeAll

Size of the data to send out.

edma_handle_t *txEdmaHandle

The eDMA TX channel used.

edma_handle_t *rxEdmaHandle

The eDMA RX channel used.

uint8_t nbytes

eDMA minor byte transfer count initially configured.

volatile uint8_t txState

TX transfer state.

volatile uint8_t rxState

RX transfer state

MCX_CMC: Core Mode Controller Driver

enum _cmc_power_mode_protection

CMC power mode Protection enumeration.

Values:

enumerator kCMC_AllowDeepSleepMode

Allow Deep Sleep mode.

enumerator kCMC_AllowPowerDownMode

Allow Power Down mode.

enumerator kCMC_AllowDeepPowerDownMode

Allow Deep Power Down mode.

enumerator kCMC_AllowAllLowPowerModes

Allow Deep Sleep, Power Down, Deep Power Down modes.

enum _cmc_wakeup_sources

Wake up sources from the previous low power mode entry.

Note

kCMC_WakeupFromUsbFs, kCMC_WakeupFromITRC, kCMC_WakeupFromCpu1 are not supported in MCXA family.

Values:

enumerator kCMC_WakeupFromResetInterruptOrPowerDown

Wakeup source is reset interrupt, or wake up from Deep Power Down.

enumerator kCMC_WakeupFromDebugReuqest

Wakeup source is debug request.

enumerator kCMC_WakeupFromInterrupt

Wakeup source is interrupt.

enumerator kCMC_WakeupFromDMAWakeup

Wakeup source is DMA Wakeup.

enumerator kCMC_WakeupFromWUURequest

Wakeup source is WUU request.

enumerator kCMC_WakeupFromUsbFs

Wakeup source is USBFS(USB0).

enumerator kCMC_WakeupFromITRC

Wakeup source is ITRC.

enumerator kCMC_WakeupFromCpu1

Wakeup source is CPU1.

enum _cmc_system_reset_interrupt_enable

System Reset Interrupt enable enumeration.

Values:

enumerator kCMC_PinResetInterruptEnable

Pin Reset interrupt enable.

enumerator kCMC_DAPResetInterruptEnable

DAP Reset interrupt enable.

enumerator kCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable

Low Power Acknowledge Timeout Reset interrupt enable.

enumerator kCMC_SoftwareResetInterruptEnable

Software Reset interrupt enable.

enumerator kCMC_LockupResetInterruptEnable

Lockup Reset interrupt enable.

enum _cmc_system_reset_interrupt_flag

CMC System Reset Interrupt Status flag.

Values:

enumerator kCMC_PinResetInterruptFlag

Pin Reset interrupt flag.

enumerator kCMC_DAPResetInterruptFlag

DAP Reset interrupt flag.

enumerator kCMC_LowPowerAcknowledgeTimeoutResetFlag

Low Power Acknowledge Timeout Reset interrupt flag.

enumerator kCMC_SoftwareResetInterruptFlag

Software Reset interrupt flag.

enumerator kCMC_LockupResetInterruptFlag

Lock up Reset interrupt flag.

enum _cmc_system_sram_arrays

CMC System SRAM arrays low power mode enable enumeration.

Values:

enumerator kCMC_RAMX0

Used to control RAMX0.

enumerator kCMC_RAMX1

Used to control RAMX1.

enumerator kCMC_RAMX2

Used to control RAMX2.

enumerator kCMC_RAMB

Used to control RAMB.

enumerator kCMC_RAMC0

Used to control RAMC0.

enumerator kCMC_RAMC1

Used to control RAMC1.

enumerator kCMC_RAMD0

Used to control RAMD0.

enumerator kCMC_RAMD1

Used to control RAMD1.

enumerator kCMC_RAME0

Used to control RAME0.

enumerator kCMC_RAME1

Used to control RAME1.

enumerator kCMC_RAMF0

Used to control RAMF0.

enumerator kCMC_RAMF1

Used to control RAMF1.

enumerator kCMC_RAMG0_RAMG1

Used to control RAMG0 and RAMG1.

enumerator kCMC_RAMG2_RAMG3

Used to control RAMG2 and RAMG3.

enumerator kCMC_RAMH0_RAMH1

Used to control RAMH0 and RAMH1.

enumerator kCMC_LPCAC

Used to control LPCAC.

enumerator kCMC_DMA0_DMA1_PKC

Used to control DMA0, DMA1 and PKC.

enumerator kCMC_USB0

Used to control USB0.

enumerator kCMC_PQ

Used to control PQ.

enumerator kCMC_CAN0_CAN1_ENET_USB1

Used to control CAN0, CAN1, ENET, USB1.

enumerator kCMC_FlexSPI

Used to control FlexSPI.

enumerator kCMC_AllSramArrays

Mask of all System SRAM arrays.

enum _cmc_system_reset_sources

System reset sources enumeration.

Values:

enumerator kCMC_WakeUpReset

The reset caused by a wakeup from Power Down or Deep Power Down mode.

enumerator kCMC_PORReset

The reset caused by power on reset detection logic.

enumerator kCMC_WarmReset

The last reset source is a warm reset source.

enumerator kCMC_FatalReset

The last reset source is a fatal reset source.

enumerator kCMC_PinReset

The reset caused by the RESET_b pin.

enumerator kCMC_DAPReset

The reset caused by a reset request from the Debug Access port.

enumerator kCMC_ResetTimeout

The reset caused by a timeout or other error condition in the system reset generation.

enumerator kCMC_LowPowerAcknowledgeTimeoutReset

The reset caused by a timeout in low power mode entry logic.

enumerator kCMC_SCGReset

The reset caused by a loss of clock or loss of lock event in the SCG.

enumerator kCMC_SoftwareReset

The reset caused by a software reset request.

enumerator kCMC_LockUoReset

The reset caused by the ARM core indication of a LOCKUP event.

enumerator kCMC_JTAGSystemReset

The reset caused by a JTAG system reset request.

enum _cmc_core_clock_gate_status

Indicate the core clock was gated.

Values:

enumerator kCMC_CoreClockNotGated

Core clock not gated.

enumerator kCMC_CoreClockGated

Core clock was gated due to low power mode entry.

enum _cmc_clock_mode

CMC clock mode enumeration.

Values:

enumerator kCMC_GateNoneClock

No clock gating.

enumerator kCMC_GateCoreClock

Gate Core clock.

enumerator kCMC_GateCorePlatformClock

Gate Core clock and platform clock.

enumerator kCMC_GateAllSystemClocks

Gate all System clocks, without getting core entering into low power mode.

enumerator kCMC_GateAllSystemClocksEnterLowPowerMode

Gate all System clocks, with core entering into low power mode.

enum _cmc_low_power_mode

CMC power mode enumeration.

Values:

enumerator kCMC_ActiveOrSleepMode

Select Active/Sleep mode.

enumerator kCMC_DeepSleepMode

Select Deep Sleep mode when a core executes WFI or WFE instruction.

enumerator kCMC_PowerDownMode

Select Power Down mode when a core executes WFI or WFE instruction.

enumerator kCMC_DeepPowerDown

Select Deep Power Down mode when a core executes WFI or WFE instruction.

typedef enum _cmc_core_clock_gate_status cmc_core_clock_gate_status_t

Indicate the core clock was gated.

typedef enum _cmc_clock_mode cmc_clock_mode_t

CMC clock mode enumeration.

typedef enum _cmc_low_power_mode cmc_low_power_mode_t

CMC power mode enumeration.

typedef struct _cmc_reset_pin_config cmc_reset_pin_config_t

CMC reset pin configuration.

typedef struct _cmc_power_domain_config cmc_power_domain_config_t

power mode configuration for each power domain.

FSL_CMC_DRIVER_VERSION

CMC driver version 2.5.0.

CMC_BLR_LOCK_FIELD_WIDTH

CMC_BLR_LOCK_IDX_MASK(index)

CMC_BLR_LOCK_IDX_SHIFT(index)

CMC_BLR_LOCK_IDX(index, value)

void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode)

Sets clock mode.

This function configs the amount of clock gating when the core asserts Sleeping due to WFI, WFE or SLEEPONEXIT.

Parameters:

• base – CMC peripheral base address.

• mode – System clock mode.

static inline void CMC_LockClockModeSetting(CMC_Type *base)

Locks the clock mode setting.

After invoking this function, any clock mode setting will be blocked.

Parameters:

• base – CMC peripheral base address.

static inline cmc_core_clock_gate_status_t CMC_GetCoreClockGatedStatus(CMC_Type *base)

Gets the core clock gated status.

This function get the status to indicate whether the core clock is gated. The core clock gated status can be cleared by software.

Parameters:

• base – CMC peripheral base address.

Returns:

The status to indicate whether the core clock is gated.

static inline void CMC_ClearCoreClockGatedStatus(CMC_Type *base)

Clears the core clock gated status.

This function clear clock status flag by software.

Parameters:

• base – CMC peripheral base address.

static inline uint8_t CMC_GetWakeupSource(CMC_Type *base)

Gets the Wakeup Source.

This function gets the Wakeup sources from the previous low power mode entry.

Parameters:

• base – CMC peripheral base address.

Returns:

The Wakeup sources from the previous low power mode entry. See _cmc_wakeup_sources for details.

static inline cmc_clock_mode_t CMC_GetClockMode(CMC_Type *base)

Gets the Clock mode.

This function gets the clock mode of the previous low power mode entry.

Parameters:

• base – CMC peripheral base address.

Returns:

The Low Power status.

static inline uint32_t CMC_GetSystemResetStatus(CMC_Type *base)

Gets the System reset status.

This function returns the system reset status. Those status updates on every MAIN Warm Reset to indicate the type/source of the most recent reset.

Parameters:

• base – CMC peripheral base address.

Returns:

The most recent system reset status. See _cmc_system_reset_sources for details.

static inline uint32_t CMC_GetStickySystemResetStatus(CMC_Type *base)

Gets the sticky system reset status since the last WAKE Cold Reset.

This function gets all source of system reset that have generated a system reset since the last WAKE Cold Reset, and that have not been cleared by software.

Parameters:

• base – CMC peripheral base address.

Returns:

System reset status that have not been cleared by software. See _cmc_system_reset_sources for details.

static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask)

Clears the sticky system reset status flags.

Parameters:

• base – CMC peripheral base address.

• mask – Bitmap of the sticky system reset status to be cleared.

static inline uint8_t CMC_GetResetCount(CMC_Type *base)

Gets the number of reset sequences completed since the last Cold Reset.

Parameters:

• base – CMC peripheral base address.

Returns:

The number of reset sequences.

void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes)

Configures all power mode protection settings.

This function configures the power mode protection settings for supported power modes. This should be done before set the lowPower mode for each power doamin.

The allowed lowpower modes are passed as bit map. For example, to allow Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes).

Parameters:

• base – CMC peripheral base address.

• allowedModes – Bitmaps of the allowed power modes. See _cmc_power_mode_protection for details.

static inline void CMC_LockPowerModeProtectionSetting(CMC_Type *base)

Locks the power mode protection.

This function locks the power mode protection. After invoking this function, any power mode protection setting will be ignored.

Parameters:

• base – CMC peripheral base address.

static inline void CMC_SetGlobalPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)

Config the same lowPower mode for all power domain.

This function configures the same low power mode for MAIN power domian and WAKE power domain.

Parameters:

• base – CMC peripheral base address.

• lowPowerMode – The desired lowPower mode. See cmc_low_power_mode_t for details.

static inline void CMC_SetMAINPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)

Configures entry into low power mode for the MAIN Power domain.

This function configures the low power mode for the MAIN power domian, when the core executes WFI/WFE instruction. The available lowPower modes are defined in the cmc_low_power_mode_t.

Parameters:

• base – CMC peripheral base address.

• lowPowerMode – The desired lowPower mode. See cmc_low_power_mode_t for details.

static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base)

Gets the power mode of the MAIN Power domain.

Parameters:

• base – CMC peripheral base address.

Returns:

The power mode of MAIN Power domain. See cmc_low_power_mode_t for details.

void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)

Configure reset pin.

This function configures reset pin. When enabled, the low power filter is enabled in both Active and Low power modes, the reset filter is only enabled in Active mode. When both filers are enabled, they operate in series.

Parameters:

• base – CMC peripheral base address.

• config – Pointer to the reset pin config structure.

static inline void CMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask)

Enable system reset interrupts.

This function enables the system reset interrupts. The assertion of non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock while an enabled interrupt is generated. Then Software can perform a graceful shutdown or abort the non-fatal warm reset provided the pending reset source is cleared by resetting the reset source and then clearing the pending flag.

Parameters:

• base – CMC peripheral base address.

• mask – System reset interrupts. See _cmc_system_reset_interrupt_enable for details.

static inline void CMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask)

Disable system reset interrupts.

This function disables the system reset interrupts.

Parameters:

• base – CMC peripheral base address.

• mask – System reset interrupts. See _cmc_system_reset_interrupt_enable for details.

static inline uint32_t CMC_GetSystemResetInterruptFlags(CMC_Type *base)

Gets System Reset interrupt flags.

This function returns the System reset interrupt flags.

Parameters:

• base – CMC peripheral base address.

Returns:

System reset interrupt flags. See _cmc_system_reset_interrupt_flag for details.

static inline void CMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask)

Clears System Reset interrupt flags.

This function clears system reset interrupt flags. The pending reset source can be cleared by resetting the source of the reset and then clearing the pending flags.

Parameters:

• base – CMC peripheral base address.

• mask – System Reset interrupt flags. See _cmc_system_reset_interrupt_flag for details.

static inline void CMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable)

Enable/Disable Non maskable Pin interrupt.

Parameters:

• base – CMC peripheral base address.

• enable – Enable or disable Non maskable pin interrupt. true - enable Non-maskable pin interrupt. false - disable Non-maskable pin interupt.

static inline uint8_t CMC_GetISPMODEPinLogic(CMC_Type *base)

Gets the logic state of the ISPMODE_n pin.

This function returns the logic state of the ISPMODE_n pin on the last negation of RESET_b pin.

Parameters:

• base – CMC peripheral base address.

Returns:

The logic state of the ISPMODE_n pin on the last negation of RESET_b pin.

static inline void CMC_ClearISPMODEPinLogic(CMC_Type *base)

Clears ISPMODE_n pin state.

Parameters:

• base – CMC peripheral base address.

static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert)

Set the logic state of the BOOT_CONFIGn pin.

This function force the logic state of the Boot_Confign pin to assert on next system reset.

Parameters:

• base – CMC peripheral base address.

• assert – Assert the corresponding pin or not. true - Assert corresponding pin on next system reset. false - No effect.

static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base)

Gets the status information written by the BootROM.

Parameters:

• base – CMC peripheral base address.

Returns:

The status information written by the BootROM.

static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue)

Sets the bootROM status value.

Note

This function is useful when result of CMC_CheckBootRomRegisterWrittable() is true.

Parameters:

• base – CMC peripheral base address.

• stat – The state value to set.

static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base, uint8_t index)

Gets the information written by the BootROM.

Parameters:

• base – CMC peripheral base address.

• index – The index of BootROM status register, ranges from 0.

Returns:

The status information written by the BootROM.

static inline void CMC_WriteBootRomStatusReg(CMC_Type *base, uint8_t index, uint32_t value)

Writes value to BootROM status register, in this way, BootROM status registers are used as general purpose register.

Note

Value in BootROM status registers are reset in cold reset.

Parameters:

• base – CMC peripheral base address.

• index – The index of BootROM status register, ranges from 0.

• value – Value to write.

static inline void CMC_LockWriteOperationToBootRomStatusReg(CMC_Type *base, uint8_t index)

Lock write operation to BootROM status register and BootROM Lock register.

Note

If locked, BootROM status register cannot be written.

Note

Once locked, only cold reset can reset related register.

Parameters:

• base – CMC peripheral base address.

• index – The index of BootROM status register, ranges from 0.

static inline bool CMC_CheckBootRomStatusRegWriteLocked(CMC_Type *base, uint8_t index)

Check if BootROM status register can be written.

Parameters:

• base – CMC peripheral base address.

• index – The index of BootROM status register, ranges from 0.

Return values:

• true – The selected BootRom status register is locked and cannot be written.

• false – The selected BootRom Status register is unlocked and cannot be written.

void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)

Power off the selected system SRAM always.

Note

This function power off the selected system SRAM always. The SRAM arrays should not be accessed while they are shut down. SRAM array contents are not retained if they are powered off.

Note

Once invoked, the previous settings will be overwritten.

Parameters:

• base – CMC peripheral base address.

• mask – Bitmap of the SRAM arrays to be powered off all modes. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

static inline void CMC_PowerOnSRAMAllMode(CMC_Type *base, uint32_t mask)

Power on SRAM during all mode.

Note

Once invoked, the previous settings will be overwritten.

Parameters:

• base – CMC peripheral base address.

• mask – Bitmap of the SRAM arrays to be powered on all modes. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)

Power off the selected system SRAM during low power modes only.

This function power off the selected system SRAM only during low power mode. SRAM array contents are not retained if they are power off.

Parameters:

• base – CMC peripheral base address.

• mask – Bitmap of the SRAM arrays to be power off during low power mode only. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)

Power on the selected system SRAM during low power modes only.

This function power on the selected system SRAM. The SRAM arrray contents are retained in low power modes.

Parameters:

• base – CMC peripheral base address.

• mask – Bitmap of the SRAM arrays to be power on during low power mode only. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)

Configs the low power mode of the on-chip flash memory.

This function configs the low power mode of the on-chip flash memory.

Parameters:

• base – CMC peripheral base address.

• doze – true: Flash is disabled while core is sleeping false: No effect.

• disable – true: Flash memory is placed in low power state. false: No effect.

static inline void CMC_EnableDebugOperation(CMC_Type *base, bool enable)

Enables/Disables debug Operation when the core sleep.

This function configs what happens to debug when core sleeps.

Parameters:

• base – CMC peripheral base address.

• enable – Enable or disable Debug when Core is sleeping. true - Debug remains enabled when the core is sleeping. false - Debug is disabled when the core is sleeping.

void CMC_PreEnterLowPowerMode(void)

Prepares to enter low power modes.

This function should be called before entering low power modes.

void CMC_PostExitLowPowerMode(void)

Recovers after wake up from low power modes.

This function should be called after wake up from low power modes. This function should be used with CMC_PreEnterLowPowerMode()

void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)

Configs the entry into the same low power mode for each power domains.

This function provides the feature to entry into the same low power mode for each power domains. Before invoking this function, please ensure the selected power mode have been allowed.

Parameters:

• base – CMC peripheral base address.

• lowPowerMode – The low power mode to be entered. See cmc_low_power_mode_t for the details.

void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)

Configs the entry into different low power modes for each power domains.

This function provides the feature to entry into different low power modes for each power domains. Before invoking this function please ensure the selected modes are allowed.

Parameters:

• base – CMC peripheral base address.

• config – Pointer to the cmc_power_domain_config_t structure.

bool lowpowerFilterEnable

Low Power Filter enable.

bool resetFilterEnable

Reset Filter enable.

uint8_t resetFilterWidth

Width of the Reset Filter.

cmc_clock_mode_t clock_mode

Clock mode for each power domain.

cmc_low_power_mode_t main_domain

The low power mode of the MAIN power domain.

struct _cmc_reset_pin_config

#include <fsl_cmc.h>

CMC reset pin configuration.

struct _cmc_power_domain_config

#include <fsl_cmc.h>

power mode configuration for each power domain.

MU: Messaging Unit

void MU_Init(MU_Type *base)

Initializes the MU module.

This function enables the MU clock only.

Parameters:

• base – MU peripheral base address.

void MU_Deinit(MU_Type *base)

De-initializes the MU module.

This function disables the MU clock only.

Parameters:

• base – MU peripheral base address.

static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg)

Writes a message to the TX register.

This function writes a message to the specific TX register. It does not check whether the TX register is empty or not. The upper layer should make sure the TX register is empty before calling this function. This function can be used in ISR for better performance.

while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { }  Wait for TX0 register empty.
MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL);  Write message to the TX0 register.

Parameters:

• base – MU peripheral base address.

• regIndex – TX register index, see mu_msg_reg_index_t.

• msg – Message to send.

status_t MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)

Blocks to send a message.

This function waits until the TX register is empty and sends the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and returns kStatus_Timeout.

Parameters:

• base – MU peripheral base address.

• regIndex – MU message register, see mu_msg_reg_index_t.

• msg – Message to send.

Return values:

• kStatus_Success – Message sent successfully.

• kStatus_Timeout – Timeout occurred while waiting for TX register to be empty.

Returns:

status_t

static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex)

Reads a message from the RX register.

This function reads a message from the specific RX register. It does not check whether the RX register is full or not. The upper layer should make sure the RX register is full before calling this function. This function can be used in ISR for better performance.

uint32_t msg;
while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base)))
{
}  Wait for the RX0 register full.

msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0);  Read message from RX0 register.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

status_t MU_ReceiveMsgTimeout(MU_Type *base, uint32_t regIndex, uint32_t *readValue)

Blocks to receive a message with timeout protection.

This function waits until the RX register is full and receives the message. If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

This function provides the same blocking behavior as MU_ReceiveMsg() but with additional timeout protection to prevent system hangs if the other core becomes unresponsive or if hardware issues occur.

Note

Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that this function includes timeout protection while MU_ReceiveMsg() waits indefinitely.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

• readValue – Pointer to store the received message.

Return values:

• kStatus_Success – Message received successfully.

• kStatus_InvalidArgument – Invalid readValue pointer.

• kStatus_Timeout – Timeout occurred while waiting for RX register to be full.

Returns:

status_t

uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)

Blocks to receive a message (infinite wait, no timeout protection).

This function waits until the RX register is full and receives the message. This function will wait indefinitely until a message is received.

Note

Both MU_ReceiveMsg() and MU_ReceiveMsgTimeout() are blocking functions. The difference is that MU_ReceiveMsgTimeout() includes timeout protection while this function waits indefinitely.

Warning

This function does not include timeout protection and may cause system hangs if the other core becomes unresponsive. For applications requiring timeout protection, use MU_ReceiveMsgTimeout() instead.

Parameters:

• base – MU peripheral base address.

• regIndex – RX register index, see mu_msg_reg_index_t.

Returns:

The received message.

static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags)

Sets the 3-bit MU flags reflect on the other MU side.

This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. The upper layer should make sure the status flag kMU_FlagsUpdatingFlag is cleared before calling this function.

while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base))
{
}  Wait for previous MU flags updating.

MU_SetFlagsNonBlocking(base, 0U);  Set the mU flags.

Parameters:

• base – MU peripheral base address.

• flags – The 3-bit MU flags to set.

status_t MU_SetFlags(MU_Type *base, uint32_t flags)

brief Blocks setting the 3-bit MU flags reflect on the other MU side.

This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, the status flag kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are updating to the other side. After the 3-bit MU flags are updated, the status flag kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, the flags cannot be changed. This function waits for the MU status flag kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.

If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout.

return status_t retval kStatus_Success Flags were set successfully. retval kStatus_Timeout Timeout occurred while waiting for flags to update.

Parameters:

• base – MU peripheral base address.

• flags – The 3-bit MU flags to set.

static inline uint32_t MU_GetFlags(MU_Type *base)

Gets the current value of the 3-bit MU flags set by the other side.

This function gets the current 3-bit MU flags on the current side.

Parameters:

• base – MU peripheral base address.

Returns:

flags Current value of the 3-bit flags.

uint32_t MU_GetStatusFlags(MU_Type *base)

Gets the MU status flags.

This function returns the bit mask of the MU status flags. See _mu_status_flags.

uint32_t flags;
flags = MU_GetStatusFlags(base);  Get all status flags.
if (kMU_Tx0EmptyFlag & flags)
{
    The TX0 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL);
}
if (kMU_Tx1EmptyFlag & flags)
{
    The TX1 register is empty. Message can be sent.
    MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL);
}

If there are more than 4 general purpose interrupts, use MU_GetGeneralPurposeStatusFlags.

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU status flags, see _mu_status_flags.

static inline uint32_t MU_GetInterruptsPending(MU_Type *base)

Gets the MU IRQ pending status of enabled interrupts.

This function returns the bit mask of the pending MU IRQs of enabled interrupts. Only these flags are checked. kMU_Tx0EmptyFlag kMU_Tx1EmptyFlag kMU_Tx2EmptyFlag kMU_Tx3EmptyFlag kMU_Rx0FullFlag kMU_Rx1FullFlag kMU_Rx2FullFlag kMU_Rx3FullFlag kMU_GenInt0Flag kMU_GenInt1Flag kMU_GenInt2Flag kMU_GenInt3Flag

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU IRQs pending.

static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t flags)

Clears the specific MU status flags.

This function clears the specific MU status flags. The flags to clear should be passed in as bit mask. See _mu_status_flags.

Clear general interrupt 0 and general interrupt 1 pending flags.
MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag);

If there are more than 4 general purpose interrupts, use MU_ClearGeneralPurposeStatusFlags.

Parameters:

• base – MU peripheral base address.

• flags – Bit mask of the MU status flags. See _mu_status_flags. Only the following flags can be cleared by software (if applicable for particular device), other flags are cleared by hardware:

  • kMU_GenInt0Flag

  • kMU_GenInt1Flag

  • kMU_GenInt2Flag

  • kMU_GenInt3Flag

  • kMU_MuResetInterruptFlag

  • kMU_OtherSideEnterRunInterruptFlag

  • kMU_OtherSideEnterHaltInterruptFlag

  • kMU_OtherSideEnterWaitInterruptFlag

  • kMU_OtherSideEnterStopInterruptFlag

  • kMU_OtherSideEnterPowerDownInterruptFlag

  • kMU_ResetAssertInterruptFlag

  • kMU_HardwareResetInterruptFlag

static inline void MU_EnableInterrupts(MU_Type *base, uint32_t interrupts)

Enables the specific MU interrupts.

This function enables the specific MU interrupts. The interrupts to enable should be passed in as bit mask. See _mu_interrupt_enable.

   Enable general interrupt 0 and TX0 empty interrupt.
MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

If there are more than 4 general purpose interrupts, use MU_EnableGeneralPurposeInterrupts.

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable.

static inline void MU_DisableInterrupts(MU_Type *base, uint32_t interrupts)

Disables the specific MU interrupts.

This function disables the specific MU interrupts. The interrupts to disable should be passed in as bit mask. See _mu_interrupt_enable.

   Disable general interrupt 0 and TX0 empty interrupt.
MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable);

If there are more than 4 general purpose interrupts, use MU_DisableGeneralPurposeInterrupts.

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU interrupts. See _mu_interrupt_enable.

status_t MU_TriggerInterrupts(MU_Type *base, uint32_t interrupts)

Triggers interrupts to the other core.

This function triggers the specific interrupts to the other core. The interrupts to trigger are passed in as bit mask. See _mu_interrupt_trigger. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}

If there are more than 4 general purpose interrupts, use MU_TriggerGeneralPurposeInterrupts.

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.

Return values:

• kStatus_Success – Interrupts have been triggered successfully.

• kStatus_Fail – Previous interrupts have not been accepted.

static inline void MU_EnableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Enables the MU general purpose interrupts.

This function enables the MU general purpose interrupts. The interrupts to enable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_EnableInterrupts only support general interrupt 0~3, this function supports all general interrupts.

For example, to enable general purpose interrupt 0 and 3, use like this:

MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU general purpose interrupts, see mu_general_purpose_interrupt_t.

static inline void MU_DisableGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Disables the MU general purpose interrupts.

This function disables the MU general purpose interrupts. The interrupts to disable should be passed in as bit mask of mu_general_purpose_interrupt_t. The function MU_DisableInterrupts only support general interrupt 0~3, this function supports all general interrupts.

For example, to disable general purpose interrupt 0 and 3, use like this:

MU_EnableGeneralPurposeInterrupts(MU, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt3);

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the MU general purpose interrupts. see mu_general_purpose_interrupt_t.

static inline uint32_t MU_GetGeneralPurposeStatusFlags(MU_Type *base)

Gets the MU general purpose interrupt status flags.

This function returns the bit mask of the MU general purpose interrupt status flags. MU_GetStatusFlags can only get general purpose interrupt status 0~3, this function can get all general purpose interrupts status.

This example shows to check whether general purpose interrupt 0 and 3 happened.

uint32_t flags;
flags = MU_GetGeneralPurposeStatusFlags(base);
if (kMU_GeneralPurposeInterrupt0 & flags)
{
}
if (kMU_GeneralPurposeInterrupt3 & flags)
{
}

Parameters:

• base – MU peripheral base address.

Returns:

Bit mask of the MU general purpose interrupt status flags.

static inline void MU_ClearGeneralPurposeStatusFlags(MU_Type *base, uint32_t flags)

Clear the MU general purpose interrupt status flags.

This function clears the specific MU general purpose interrupt status flags. The flags to clear should be passed in as bit mask. mu_general_purpose_interrupt_t_mu_status_flags.

Example to clear general purpose interrupt 0 and general interrupt 1 pending flags.

MU_ClearGeneralPurposeStatusFlags(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt1);

Parameters:

• base – MU peripheral base address.

• flags – Bit mask of the MU general purpose interrupt status flags. See mu_general_purpose_interrupt_t.

static inline uint32_t MU_GetRxStatusFlags(MU_Type *base)

Return the RX status flags in reverse numerical order.

This function return the RX status flags in reverse order. Note: RFn bits of SR[3-0](mu status register) are mapped in ascending numerical order: RF0 -> SR[0] RF1 -> SR[1] RF2 -> SR[2] RF3 -> SR[3] This function will return these bits in reverse numerical order(RF3->RF1) to comply with MU_GetRxStatusFlags() of mu driver. See MU_GetRxStatusFlags() from drivers/mu/fsl_mu.h

status_reg = MU_GetRxStatusFlags(base);

Parameters:

• base – MU peripheral base address.

Returns:

MU RX status flags in reverse order

status_t MU_TriggerGeneralPurposeInterrupts(MU_Type *base, uint32_t interrupts)

Triggers general purpose interrupts to the other core.

This function triggers the specific general purpose interrupts to the other core. The interrupts to trigger are passed in as bit mask. See mu_general_purpose_interrupt_t. The MU should not trigger an interrupt to the other core when the previous interrupt has not been processed by the other core. This function checks whether the previous interrupts have been processed. If not, it returns an error.

status_t status;
status = MU_TriggerGeneralPurposeInterrupts(base, kMU_GeneralPurposeInterrupt0 | kMU_GeneralPurposeInterrupt2);

if (kStatus_Success != status)
{
     Previous general purpose interrupt 0 or general purpose interrupt 2
     has not been processed by the other core.
}

Parameters:

• base – MU peripheral base address.

• interrupts – Bit mask of the interrupts to trigger. See mu_general_purpose_interrupt_t.

Return values:

• kStatus_Success – Interrupts have been triggered successfully.

• kStatus_Fail – Previous interrupts have not been accepted.

void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode)

Boots the other core.

This function boots the other core with a boot configuration.

Parameters:

• base – MU peripheral base address.

• mode – The other core boot mode.

void MU_HoldOtherCoreReset(MU_Type *base)

Holds the other core reset.

This function causes the other core to be held in reset following any reset event.

Parameters:

• base – MU peripheral base address.

static inline status_t MU_ResetBothSides(MU_Type *base)

Resets the MU for both A side and B side.

This function resets the MU for both A side and B side. Before reset, it is recommended to interrupt processor B, because this function may affect the ongoing processor B programs.

If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations if waiting for the other side to come out of reset takes too long.

Note

For some platforms, only MU side A could use this function, check reference manual for details.

Parameters:

• base – MU peripheral base address.

Return values:

• kStatus_Success – The MU was reset successfully.

• kStatus_Timeout – Timeout occurred while waiting for the other side to come out of reset.

Returns:

status_t

status_t MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)

Hardware reset the other core.

This function resets the other core, the other core could mask the hardware reset by calling MU_MaskHardwareReset. The hardware reset mask feature is only available for some platforms. This function could be used together with MU_BootOtherCore to control the other core reset workflow.

If MU1_BUSY_POLL_COUNT is defined and non-zero, the function will timeout after the specified number of polling iterations and return kStatus_Timeout if waiting for the other core to enter or exit reset takes too long.

Example 1: Reset the other core, and no hold reset

MU_HardwareResetOtherCore(MU_A, true, false, bootMode);

In this example, the core at MU side B will reset with the specified boot mode.

Example 2: Reset the other core and hold it, then boot the other core later. Here the other core enters reset, and the reset is hold

MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);

Current core boot the other core when necessary.

MU_BootOtherCore(MU_A, bootMode);

Note

The feature waitReset, holdReset, and bootMode might be not supported for some platforms. waitReset is only available for platforms that FSL_FEATURE_MU_NO_CORE_STATUS not defined as 1 and FSL_FEATURE_MU_HAS_RESET_ASSERT_INT not defined as 0. holdReset is only available for platforms that FSL_FEATURE_MU_HAS_RSTH not defined as 0. bootMode is only available for platforms that FSL_FEATURE_MU_HAS_BOOT not defined as 0.

Parameters:

• base – MU peripheral base address.

• waitReset – Wait the other core enters reset. Only work when there is CSSR0[RAIP].

  • true: Wait until the other core enters reset, if the other core has masked the hardware reset, then this function will be blocked.

  • false: Don’t wait the reset.

• holdReset – Hold the other core reset or not. Only work when there is CCR0[RSTH].

  • true: Hold the other core in reset, this function returns directly when the other core enters reset.

  • false: Don’t hold the other core in reset, this function waits until the other core out of reset.

• bootMode – Boot mode of the other core, if holdReset is true, this parameter is useless.

Return values:

• kStatus_Success – The other core was reset successfully.

• kStatus_Timeout – Timeout occurred while waiting for the other core to enter or exit reset.

Returns:

status_t

FSL_MU_DRIVER_VERSION

MU driver version.

enum _mu_status_flags

MU status flags.

Values:

enumerator kMU_Tx0EmptyFlag

TX0 empty.

enumerator kMU_Tx1EmptyFlag

TX1 empty.

enumerator kMU_Tx2EmptyFlag

TX2 empty.

enumerator kMU_Tx3EmptyFlag

TX3 empty.

enumerator kMU_Rx0FullFlag

RX0 full.

enumerator kMU_Rx1FullFlag

RX1 full.

enumerator kMU_Rx2FullFlag

RX2 full.

enumerator kMU_Rx3FullFlag

RX3 full.

enumerator kMU_GenInt0Flag

General purpose interrupt 0 pending.

enumerator kMU_GenInt1Flag

General purpose interrupt 1 pending.

enumerator kMU_GenInt2Flag

General purpose interrupt 2 pending.

enumerator kMU_GenInt3Flag

General purpose interrupt 3 pending.

enumerator kMU_RxFullPendingFlag

Any RX full flag is pending.

enumerator kMU_TxEmptyPendingFlag

Any TX empty flag is pending.

enumerator kMU_GenIntPendingFlag

Any general interrupt flag is pending.

enumerator kMU_EventPendingFlag

MU event pending.

enumerator kMU_FlagsUpdatingFlag

MU flags update is on-going.

enumerator kMU_MuInResetFlag

MU of any side is in reset.

enumerator kMU_MuResetInterruptFlag

The other side initializes MU reset.

enum _mu_interrupt_enable

MU interrupt source to enable.

Values:

enumerator kMU_Tx0EmptyInterruptEnable

TX0 empty.

enumerator kMU_Tx1EmptyInterruptEnable

TX1 empty.

enumerator kMU_Tx2EmptyInterruptEnable

TX2 empty.

enumerator kMU_Tx3EmptyInterruptEnable

TX3 empty.

enumerator kMU_Rx0FullInterruptEnable

RX0 full.

enumerator kMU_Rx1FullInterruptEnable

RX1 full.

enumerator kMU_Rx2FullInterruptEnable

RX2 full.

enumerator kMU_Rx3FullInterruptEnable

RX3 full.

enumerator kMU_GenInt0InterruptEnable

General purpose interrupt 0.

enumerator kMU_GenInt1InterruptEnable

General purpose interrupt 1.

enumerator kMU_GenInt2InterruptEnable

General purpose interrupt 2.

enumerator kMU_GenInt3InterruptEnable

General purpose interrupt 3.

enumerator kMU_MuResetInterruptEnable

The other side initializes MU reset.

enum _mu_interrupt_trigger

MU interrupt that could be triggered to the other core.

Values:

enumerator kMU_GenInt0InterruptTrigger

General purpose interrupt 0.

enumerator kMU_GenInt1InterruptTrigger

General purpose interrupt 1.

enumerator kMU_GenInt2InterruptTrigger

General purpose interrupt 2.

enumerator kMU_GenInt3InterruptTrigger

General purpose interrupt 3.

enum _mu_msg_reg_index

MU message register index.

Values:

enumerator kMU_MsgReg0

Message register 0.

enumerator kMU_MsgReg1

Message register 1.

enumerator kMU_MsgReg2

Message register 2.

enumerator kMU_MsgReg3

Message register 3.

enum _mu_general_purpose_interrupt

MU general purpose interrupts.

Values:

enumerator kMU_GeneralPurposeInterrupt0

General purpose interrupt 0

enumerator kMU_GeneralPurposeInterrupt1

General purpose interrupt 1

enumerator kMU_GeneralPurposeInterrupt2

General purpose interrupt 2

enumerator kMU_GeneralPurposeInterrupt3

General purpose interrupt 3

typedef enum _mu_msg_reg_index mu_msg_reg_index_t

MU message register index.

typedef enum _mu_general_purpose_interrupt mu_general_purpose_interrupt_t

MU general purpose interrupts.

MU_CORE_INTR(intr)

MU_MISC_INTR(intr)

MU_TX_INTR(intr)

MU_RX_INTR(intr)

MU_GI_INTR(intr)

MU_GET_CORE_INTR(intrs)

MU_GET_TX_INTR(intrs)

MU_GET_RX_INTR(intrs)

MU_GET_GI_INTR(intrs)

MU_CORE_FLAG(flag)

MU_STAT_FLAG(flag)

MU_TX_FLAG(flag)

MU_RX_FLAG(flag)

MU_GI_FLAG(flag)

MU_GET_CORE_FLAG(flags)

MU_GET_STAT_FLAG(flags)

MU_GET_TX_FLAG(flags)

MU_GET_RX_FLAG(flags)

MU_GET_GI_FLAG(flags)

MU1_BUSY_POLL_COUNT

Maximum polling iterations for MU waiting loops.

This parameter defines the maximum number of iterations for any polling loop in the MU code before timing out and returning an error.

It applies to all waiting loops in MU driver, such as waiting for TX register to be empty or waiting for RX register to be full.

This is a count of loop iterations, not a time-based value.

If defined as 0, polling loops will continue indefinitely until their exit condition is met, which could potentially cause the system to hang if a core becomes unresponsive.

OSTIMER: OS Event Timer Driver

void OSTIMER_Init(OSTIMER_Type *base)

Initializes an OSTIMER by turning its bus clock on.

void OSTIMER_Deinit(OSTIMER_Type *base)

Deinitializes a OSTIMER instance.

This function shuts down OSTIMER bus clock

Parameters:

• base – OSTIMER peripheral base address.

uint64_t OSTIMER_GrayToDecimal(uint64_t gray)

Translate the value from gray-code to decimal.

Parameters:

• gray – The gray value input.

Returns:

The decimal value.

static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec)

Translate the value from decimal to gray-code.

Parameters:

• dec – The decimal value.

Returns:

The gray code of the input value.

uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base)

Get OSTIMER status Flags.

This returns the status flag. Currently, only match interrupt flag can be got.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

status register value

void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask)

Clear Status Interrupt Flags.

This clears interrupt status flag. Currently, only match interrupt flag can be cleared.

Parameters:

• base – OSTIMER peripheral base address.

• mask – Clear bit mask.

Returns:

none

status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)

Set the match raw value for OSTIMER.

This function will set a match value for OSTIMER with an optional callback. And this callback will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. Please note that, the data format may be gray-code, if so, please use OSTIMER_SetMatchValue().

Parameters:

• base – OSTIMER peripheral base address.

• count – OSTIMER timer match value.(Value may be gray-code format)

• cb – OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).

Return values:

kStatus_Success – Match raw value written and interrupt enabled successfully.

status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)

Set the match value for OSTIMER.

This function will set a match value for OSTIMER with an optional callback. And this callback will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.

The function disables the match interrupt before writing the match registers and re-enables it immediately after. This function is suitable when the delta between the current timer value and count is comfortably larger than the match-register synchronisation latency (more than 7 OSTimer ticks). However, it does NOT wait for OSEVENT_CTRL[MATCH_WR_RDY]) after writing MATCH, and it does NOT check whether the requested match time has already passed. If there is any possibility that count is close to or has already passed the current timer value, use OSTIMER_SetMatchValueSafe() instead, which polls MATCH_WR_RDY and checks whether the match moment has been missed.

Parameters:

• base – OSTIMER peripheral base address.

• count – Match value in decimal (binary) format. The driver converts to Gray code internally when the hardware counter is Gray-encoded.

• cb – OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).

Return values:

kStatus_Success – Match value written and interrupt enabled successfully.

status_t OSTIMER_SetMatchValueSafe(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)

Set the match value for OSTIMER with full synchronisation and missed-event detection.

This function will set a match value for OSTIMER with an optional callback. And this callback will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.

Unlike OSTIMER_SetMatchValue(), this function performs the following additional steps after writing the match registers:

1. Wait for write synchronisation (MATCH_WR_RDY). On devices that expose OSEVENT_CTRL[MATCH_WR_RDY], the function spins until that bit is cleared, which indicates that the written value has been transferred from the shadow registers to the active compare registers in the OSTimer clock domain. This eliminates the race condition where the timer advances past the match value before the hardware has latched it.

2. Check whether the match moment has already been missed. After MATCH_WR_RDY clears, the function reads the current timer value and compares it with count:

   • If the current timer value is still below count, the match has not yet occurred. The interrupt is enabled and the function returns kStatus_Success.

   • If the current timer value has reached or passed count:

     • If the hardware interrupt flag (OSTIMER_INTRFLAG) is already set, the match event was captured by hardware. The interrupt is enabled so the pending flag triggers the ISR, and the function returns kStatus_Success.

     • If the interrupt flag is NOT set, the match moment passed without the hardware capturing it (the compare logic had not yet latched the value when the timer advanced). The interrupt is left DISABLED and the function returns kStatus_Fail. The caller is responsible for handling this missed event, for example by scheduling a new match immediately or executing the intended action directly.

Note

This function is recommended whenever the requested match delta is small or unpredictable relative to the OSTimer source clock period. If the overhead of polling MATCH_WR_RDY is unacceptable (e.g. at 32 KHz with tight real-time constraints), use OSTIMER_SetMatchValue() and ensure the match delta is always large enough.

Parameters:

• base – OSTIMER peripheral base address.

• count – Match value in decimal (binary) format. The driver converts to Gray code internally when the hardware counter is Gray-encoded.

• cb – OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).

Return values:

• kStatus_Success – Match value written and interrupt enabled. The match event will occur in the future, or the hardware interrupt flag was already set and the pending interrupt will fire immediately upon enabling.

• kStatus_Fail – Match time already passed and the hardware interrupt flag was not set. The interrupt remains disabled. The caller must handle the missed event.

static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value)

Set value to OSTIMER MATCH register directly.

This function writes the input value to OSTIMER MATCH register directly, it does not touch any other registers. Note that, the data format is gray-code if the hardware register is gray-encoded. The function OSTIMER_DecimalToGray could convert decimal value to gray code.

Parameters:

• base – OSTIMER peripheral base address.

• value – OSTIMER timer match value (Value is gray-code format if the hardware register is gray-encoded).

static inline uint64_t OSTIMER_GetMatchRegister(OSTIMER_Type *base)

Get the match value from OSTIMER.

This function will get the match value from OSTIMER. The value of timer match is gray code format if the hardware is Gray-encoded.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

Value of match register, data format is gray code if the register is Gray-encoded.

static inline uint64_t OSTIMER_GetMatchValue(OSTIMER_Type *base)

Get the match value from OSTIMER.

This function will get a match value from OSTIMER.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

Value of match register in decimal format.

static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base)

Enable the OSTIMER counter match interrupt.

Enable the timer counter match interrupt. The interrupt happens when OSTIMER counter matches the value in MATCH registers.

Parameters:

• base – OSTIMER peripheral base address.

static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base)

Disable the OSTIMER counter match interrupt.

Disable the timer counter match interrupt. The interrupt happens when OSTIMER counter matches the value in MATCH registers.

Parameters:

• base – OSTIMER peripheral base address.

static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base)

Get current timer raw count value from OSTIMER.

This function will get the timer count value from OS timer register. The raw value of timer count may be gray code format.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

Raw value of OSTIMER, may be gray code format if the hardware register is Gray-encoded.

uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base)

Get current timer count value from OSTIMER.

This function will get a decimal timer count value. If the RAW value of timer count is gray code format, it will be translated to decimal data internally.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

Value of OSTIMER which will be formated to decimal value.

static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base)

Get the capture value from OSTIMER.

This function will get a captured value from OSTIMER. The Raw value of timer capture may be gray code format if the hardware register is Gray-encoded.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

Raw value of capture register, data format may be gray code if the hardware register is Gray-encoded.

uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base)

Get the capture value from OSTIMER.

This function will get a capture decimal-value from OSTIMER. If the RAW value of timer count is gray code format, it will be translated to decimal data internally.

Parameters:

• base – OSTIMER peripheral base address.

Returns:

Value of capture register, data format is decimal.

void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb)

OS timer interrupt Service Handler.

This function handles the interrupt and refers to the callback array in the driver to callback user (as per request in OSTIMER_SetMatchValue()). if no user callback is scheduled, the interrupt will simply be cleared.

Parameters:

• base – OS timer peripheral base address.

• cb – callback scheduled for this instance of OS timer

Returns:

none

void OSTIMER_DriverIRQHandler(uint32_t instance)

OSTIMER parameterized IRQ handler entry.

Parameters:

• instance – OSTIMER instance index.

FSL_OSTIMER_DRIVER_VERSION

OSTIMER driver version.

enum _ostimer_flags

OSTIMER status flags.

Values:

enumerator kOSTIMER_MatchInterruptFlag

Match interrupt flag bit, sets if the match value was reached.

typedef void (*ostimer_callback_t)(void)

ostimer callback function.

Pls_pmu

enum _pmu_fro16k_output_freq

The enumeration of FRO16K output frequency.

Values:

enumerator kPMU_FRO16KOutput16KHz

FRM16K output 16KHz.

enumerator kPMU_FRO16KOutput8KHz

FRM16K output 8KHz.

enum _pmu_dcdc_main_power_mode

The enumeration of main DCDC power modes.

Values:

enumerator kPMU_DcdcMain_NormalPowerMode

DCDC main in normal power mode.

enumerator kPMU_DcdcMain_LowPowerMode

DCDC main in low power mode.

typedef enum _pmu_fro16k_output_freq pmu_fro16k_output_freq_t

The enumeration of FRO16K output frequency.

typedef enum _pmu_dcdc_main_power_mode pmu_dcdc_main_power_mode_t

The enumeration of main DCDC power modes.

static inline void PMU_EnableFixedDCDC(PMU_Type *base, bool enable)

Enable/disable Fixed DCDC in active mode.

Parameters:

• base – PMU peripheral base address.

• enable – Specify the behavior of Fixed DCDC, true to enable, false to disable.

static inline void PMU_UpdateDCDCMainMode(PMU_Type *base, pmu_dcdc_main_power_mode_t mode)

Update the power mode of the main DCDC.

Parameters:

• base – PMU peripheral base address.

• mode – Power mode to set for the main DCDC.

static inline pmu_dcdc_main_power_mode_t PMU_GetDCDCMainMode(PMU_Type *base)

Get the current power mode of the main DCDC.

Parameters:

• base – PMU peripheral base address.

Returns:

pmu_dcdc_main_power_mode_t Current power mode of the main DCDC.

static inline void PMU_UpdateVDDCoreInActiveMode(PMU_Type *base, uint8_t value)

Update voltage of VDD_CORE in active mode.

Parameters:

• base – PMU peripheral base address.

• value – Value to update, LSB is 9.5mV.

static inline void PMU_UpdateVDDCoreInLpMode(PMU_Type *base, uint8_t value)

Update voltage of VDD_CORE in low power modes.

Parameters:

• base – PMU peripheral base address.

• value – Value to update, LSB is 9.5mV.

static inline void PMU_UpdateVDDCore1P1InActiveMode(PMU_Type *base, uint8_t value)

Update voltage of VDD_CORE_1P1 in active mode.

Parameters:

• base – PMU peripheral base address.

• value – Value to update.

static inline void PMU_UpdateVDDCore1P1InLpMode(PMU_Type *base, uint8_t value)

Update voltage of VDD_CORE_1P1 in low power modes.

Parameters:

• base – PMU peripheral base address.

• value – Value to update.

static inline void PMU_EnableFRO16K(PMU_Type *base, bool enable)

Enable/disable FRO16K.

Deprecated:

Will be removed in next release.

Parameters:

• base – PMU peripheral base address.

• enable – Specify the behavior of FRO16K, true to enable FRO16K, false to disable FRO16K.

static inline void PMU_UpdateFRO16KFreq(PMU_Type *base, pmu_fro16k_output_freq_t freq)

Update FRO16K output frequency.

Parameters:

• base – PMU peripheral base address.

• freq – The target frequency to update, please refer to pmu_fro16k_output_freq_t for details.

static inline void PMU_KeepFRO16KActiveInDpd3AndSD(PMU_Type *base, bool keepActive)

Keep FRO16K active in DPD3 and SD modes.

Parameters:

• base – PMU peripheral base address.

• keepActive – Specify whether to keep FRO16K active, true to keep active, false otherwise.

static inline void PMU_UpdateDCDCWakeupWatchdogCounterValue(PMU_Type *base, uint16_t timeoutValue)

Update DCDC watchdog counter value.

Deprecated:

Will be removed in next release.

Parameters:

• base – PMU peripheral base address.

• timeoutValue – DCDC watchdog counter value.

static inline void PMU_UpdateWakeupTime(PMU_Type *base, uint16_t wakeupTime)

Update wakeup time of the PMU analog from POR reset to ext_reset release.

Parameters:

• base – PMU peripheral base address.

• wakeupTime – Specify the wakeup time.

static inline uint32_t PMU_GetWakeupTime(PMU_Type *base)

Get wakeup time of the PMU analog from POR reset to ext_reset release.

Parameters:

• base – PMU peripheral base address.

Returns:

The wakeup time of the PMU analog from POR reset to ext_reset release.

static inline void PMU_UpdateHvdLvTrim(PMU_Type *base, uint8_t value)

Update PMU_TRIM4 HVD_LV_TRIM bitfield.

This function writes the HVD (High Voltage Detect) low voltage trim value to PMU_TRIM4 register. The trim value should be obtained from IFR1 (Information Flash Region 1) by the caller. This function is typically used during CLOCK mode configuration (standard/mid drive strength).

Note

This function uses read-modify-write operation to preserve other bitfields in PMU_TRIM4.

Note

The caller is responsible for reading the trim value from IFR1.

Parameters:

• base – PMU peripheral base address.

• value – HVD low voltage trim value to write (4-bit value, 0x0-0xF).

static inline void PMU_UpdateLvdLvTrim(PMU_Type *base, uint8_t value)

Update PMU_TRIM4 LVD_LV_TRIM bitfield.

This function writes the LVD (Low Voltage Detect) low voltage trim value to PMU_TRIM4 register. The trim value should be obtained from IFR1 (Information Flash Region 1) by the caller. This function is typically used during CLOCK mode configuration (standard/mid drive strength).

Note

This function uses read-modify-write operation to preserve other bitfields in PMU_TRIM4.

Note

The caller is responsible for reading the trim value from IFR1.

Parameters:

• base – PMU peripheral base address.

• value – LVD low voltage trim value to write (4-bit value, 0x0-0xF).

static inline void PMU_EnableHighVolGlitchDetect(PMU_Type *base, bool enable)

Enable or disable high voltage glitch detection.

This function enables or disables the high voltage glitch detector by setting or clearing the AGDET_HV_EN bit in the AGDET_HV_CTRL register.

Note

This function includes a delay after the register write if CONFIG_PLS_PMU_REG_WRITE_DELAY_VAL is configured.

Parameters:

• base – PMU peripheral base address.

• enable – True to enable high voltage glitch detection, false to disable.

static inline void PMU_CleanHighVolGlitchDetectReset(PMU_Type *base)

Clear the high voltage glitch detection reset flag.

This function clears the high voltage glitch detector reset flag by toggling the AGDET_HV_RES bit in the AGDET_HV_CTRL register. The bit is first set and then cleared to reset the detection status.

Note

This function includes delays after register writes if CONFIG_PLS_PMU_REG_WRITE_DELAY_VAL is configured.

Parameters:

• base – PMU peripheral base address.

static inline bool PMU_IsHighVolGlitchDetectResetAsserted(PMU_Type *base)

Check if the high voltage glitch detection reset flag is asserted.

This function checks whether the high voltage glitch detector reset flag is set by reading the AGDET_HV_RES bit in the AGDET_HV_CTRL register.

Parameters:

• base – PMU peripheral base address.

Return values:

• true – The high voltage glitch detection reset flag is asserted.

• false – The high voltage glitch detection reset flag is not asserted.

static inline void PMU_EnableLowVolGlitchDetect(PMU_Type *base, bool enable)

Enable or disable the low voltage glitch detection.

This function enables or disables the low voltage glitch detector by setting or clearing the AGDET_LV_EN bit in the AGDET_LV_CTRL register.

Note

This function includes a delay after register write if CONFIG_PLS_PMU_REG_WRITE_DELAY_VAL is configured.

Parameters:

• base – PMU peripheral base address.

• enable – Enable or disable the low voltage glitch detection.

  • true: Enable low voltage glitch detection.

  • false: Disable low voltage glitch detection.

static inline void PMU_CleanLowVolGlitchDetectReset(PMU_Type *base)

Clear the low voltage glitch detection reset flag.

This function clears the low voltage glitch detector reset flag by performing a write sequence to the AGDET_LV_RES bit in the AGDET_LV_CTRL register. The flag is first set and then cleared to complete the reset operation.

Note

This function includes delays after register writes if CONFIG_PLS_PMU_REG_WRITE_DELAY_VAL is configured.

Parameters:

• base – PMU peripheral base address.

static inline bool PMU_IsLowVolGlitchDetect(PMU_Type *base)

Check if low voltage glitch detection has occurred.

This function checks the low voltage glitch detector reset flag by reading the AGDET_LV_RES bit in the AGDET_LV_CTRL register.

Parameters:

• base – PMU peripheral base address.

Return values:

• true – Low voltage glitch has been detected.

• false – Low voltage glitch has not been detected.

static inline void PMU_DoHandshakeBetweenPMUAndPAC(PMU_Type *base)

Apply handshake between PMU and PAC after PMU register update.

Parameters:

• base – PMU peripheral base address.

FSL_PMU_DRIVER_VERSION

pls_pmu driver version 2.3.0.

PORT: Port Control and Interrupts

static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)

Get PORT version information.

Parameters:

• base – PORT peripheral base pointer

• info – PORT version information

static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)

Get PORT version information.

Note

: PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and PORTC_CONFIG[RANGE] does not take effect.

Parameters:

• base – PORT peripheral base pointer

• range – port voltage range

static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)

Sets the port PCR register.

This is an example to define an input pin or output pin PCR configuration.

// Define a digital input pin PCR configuration
port_pin_config_t config = {
     kPORT_PullUp,
     kPORT_FastSlewRate,
     kPORT_PassiveFilterDisable,
     kPORT_OpenDrainDisable,
     kPORT_LowDriveStrength,
     kPORT_MuxAsGpio,
     kPORT_UnLockRegister,
};

Parameters:

• base – PORT peripheral base pointer.

• pin – PORT pin number.

• config – PORT PCR register configuration structure.

static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)

Sets the port PCR register for multiple pins.

This is an example to define input pins or output pins PCR configuration.

Define a digital input pin PCR configuration
port_pin_config_t config = {
     kPORT_PullUp ,
     kPORT_PullEnable,
     kPORT_FastSlewRate,
     kPORT_PassiveFilterDisable,
     kPORT_OpenDrainDisable,
     kPORT_LowDriveStrength,
     kPORT_MuxAsGpio,
     kPORT_UnlockRegister,
};

Parameters:

• base – PORT peripheral base pointer.

• mask – PORT pin number macro.

• config – PORT PCR register configuration structure.

static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)

Configures the pin muxing.

Note

: This function is NOT recommended to use together with the PORT_SetPinsConfig, because the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is reset to zero : kPORT_PinDisabledOrAnalog). This function is recommended to use to reset the pin mux

Parameters:

• base – PORT peripheral base pointer.

• pin – PORT pin number.

• mux – pin muxing slot selection.

  • kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.

  • kPORT_MuxAsGpio : Set as GPIO.

  • kPORT_MuxAlt2 : chip-specific.

  • kPORT_MuxAlt3 : chip-specific.

  • kPORT_MuxAlt4 : chip-specific.

  • kPORT_MuxAlt5 : chip-specific.

  • kPORT_MuxAlt6 : chip-specific.

  • kPORT_MuxAlt7 : chip-specific.

static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)

Enables the digital filter in one port, each bit of the 32-bit register represents one pin.

Parameters:

• base – PORT peripheral base pointer.

• mask – PORT pin number macro.

• enable – PORT digital filter configuration.

static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)

Sets the digital filter in one port, each bit of the 32-bit register represents one pin.

Parameters:

• base – PORT peripheral base pointer.

• config – PORT digital filter configuration structure.

static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)

Configures the port pin drive strength.

Parameters:

• base – PORT peripheral base pointer.

• pin – PORT pin number.

• strength – PORT pin drive strength

  • kPORT_LowDriveStrength = 0U - Low-drive strength is configured.

  • kPORT_HighDriveStrength = 1U - High-drive strength is configured.

static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)

Enables the port pin double drive strength.

Parameters:

• base – PORT peripheral base pointer.

• pin – PORT pin number.

• enable – PORT pin drive strength configuration.

static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)

Configures the port pin pull value.

Parameters:

• base – PORT peripheral base pointer.

• pin – PORT pin number.

• value – PORT pin pull value

  • kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.

  • kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.

static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)

Get EFT detect flags.

Parameters:

• base – PORT peripheral base pointer

Returns:

EFT detect flags

static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)

Enable EFT detect interrupts.

Parameters:

• base – PORT peripheral base pointer

• interrupt – EFT detect interrupt

static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)

Disable EFT detect interrupts.

Parameters:

• base – PORT peripheral base pointer

• interrupt – EFT detect interrupt

static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)

Clear all low EFT detector.

Note

: Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the PORTB_EDCR does not take effect.

Parameters:

• base – PORT peripheral base pointer

static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)

Clear all high EFT detector.

Parameters:

• base – PORT peripheral base pointer

FSL_PORT_DRIVER_VERSION

PORT driver version.

enum _port_pull

Internal resistor pull feature selection.

Values:

enumerator kPORT_PullDisable

Internal pull-up/down resistor is disabled.

enumerator kPORT_PullDown

Internal pull-down resistor is enabled.

enumerator kPORT_PullUp

Internal pull-up resistor is enabled.

enum _port_pull_value

Internal resistor pull value selection.

Values:

enumerator kPORT_LowPullResistor

Low internal pull resistor value is selected.

enumerator kPORT_HighPullResistor

High internal pull resistor value is selected.

enum _port_slew_rate

Slew rate selection.

Values:

enumerator kPORT_FastSlewRate

Fast slew rate is configured.

enumerator kPORT_SlowSlewRate

Slow slew rate is configured.

enum _port_open_drain_enable

Open Drain feature enable/disable.

Values:

enumerator kPORT_OpenDrainDisable

Open drain output is disabled.

enumerator kPORT_OpenDrainEnable

Open drain output is enabled.

enum _port_passive_filter_enable

Passive filter feature enable/disable.

Values:

enumerator kPORT_PassiveFilterDisable

Passive input filter is disabled.

enumerator kPORT_PassiveFilterEnable

Passive input filter is enabled.

enum _port_drive_strength

Configures the drive strength.

Values:

enumerator kPORT_LowDriveStrength

Low-drive strength is configured.

enumerator kPORT_HighDriveStrength

High-drive strength is configured.

enum _port_drive_strength1

Configures the drive strength1.

Values:

enumerator kPORT_NormalDriveStrength

Normal drive strength

enumerator kPORT_DoubleDriveStrength

Double drive strength

enum _port_input_buffer

input buffer disable/enable.

Values:

enumerator kPORT_InputBufferDisable

Digital input is disabled

enumerator kPORT_InputBufferEnable

Digital input is enabled

enum _port_invet_input

Digital input is not inverted or it is inverted.

Values:

enumerator kPORT_InputNormal

Digital input is not inverted

enumerator kPORT_InputInvert

Digital input is inverted

enum _port_lock_register

Unlock/lock the pin control register field[15:0].

Values:

enumerator kPORT_UnlockRegister

Pin Control Register fields [15:0] are not locked.

enumerator kPORT_LockRegister

Pin Control Register fields [15:0] are locked.

enum _port_mux

Pin mux selection.

Values:

enumerator kPORT_PinDisabledOrAnalog

Corresponding pin is disabled, but is used as an analog pin.

enumerator kPORT_MuxAsGpio

Corresponding pin is configured as GPIO.

enumerator kPORT_MuxAlt0

Chip-specific

enumerator kPORT_MuxAlt1

Chip-specific

enumerator kPORT_MuxAlt2

Chip-specific

enumerator kPORT_MuxAlt3

Chip-specific

enumerator kPORT_MuxAlt4

Chip-specific

enumerator kPORT_MuxAlt5

Chip-specific

enumerator kPORT_MuxAlt6

Chip-specific

enumerator kPORT_MuxAlt7

Chip-specific

enumerator kPORT_MuxAlt8

Chip-specific

enumerator kPORT_MuxAlt9

Chip-specific

enumerator kPORT_MuxAlt10

Chip-specific

enumerator kPORT_MuxAlt11

Chip-specific

enumerator kPORT_MuxAlt12

Chip-specific

enumerator kPORT_MuxAlt13

Chip-specific

enumerator kPORT_MuxAlt14

Chip-specific

enumerator kPORT_MuxAlt15

Chip-specific

enum _port_digital_filter_clock_source

Digital filter clock source selection.

Values:

enumerator kPORT_BusClock

Digital filters are clocked by the bus clock.

enumerator kPORT_LpoClock

Digital filters are clocked by the 1 kHz LPO clock.

enum _port_voltage_range

PORT voltage range.

Values:

enumerator kPORT_VoltageRange1Dot71V_3Dot6V

Port voltage range is 1.71 V - 3.6 V.

enumerator kPORT_VoltageRange2Dot70V_3Dot6V

Port voltage range is 2.70 V - 3.6 V.

typedef enum _port_mux port_mux_t

Pin mux selection.

typedef enum _port_digital_filter_clock_source port_digital_filter_clock_source_t

Digital filter clock source selection.

typedef struct _port_digital_filter_config port_digital_filter_config_t

PORT digital filter feature configuration definition.

typedef struct _port_pin_config port_pin_config_t

PORT pin configuration structure.

typedef struct _port_version_info port_version_info_t

PORT version information.

typedef enum _port_voltage_range port_voltage_range_t

PORT voltage range.

FSL_COMPONENT_ID

struct _port_digital_filter_config

#include <fsl_port.h>

PORT digital filter feature configuration definition.

Public Members

uint32_t digitalFilterWidth

Set digital filter width

port_digital_filter_clock_source_t clockSource

Set digital filter clockSource

struct _port_pin_config

#include <fsl_port.h>

PORT pin configuration structure.

Public Members

uint16_t pullSelect

No-pull/pull-down/pull-up select

uint16_t pullValueSelect

Pull value select

uint16_t slewRate

Fast/slow slew rate Configure

uint16_t passiveFilterEnable

Passive filter enable/disable

uint16_t openDrainEnable

Open drain enable/disable

uint16_t driveStrength

Fast/slow drive strength configure

uint16_t driveStrength1

Normal/Double drive strength enable/disable

uint16_t inputBuffer

Input Buffer Configure

uint16_t invertInput

Invert Input Configure

uint16_t lockRegister

Lock/unlock the PCR field[15:0]

struct _port_version_info

#include <fsl_port.h>

PORT version information.

Public Members

uint16_t feature

Feature Specification Number.

uint8_t minor

Minor Version Number.

uint8_t major

Major Version Number.

POWER Driver

Values:

enumerator kStatus_POWER_MuTransferError

Failed due to MU transfer error.

enumerator kStatus_POWER_RequestNotAllowed

Request not allowed by the other core.

enumerator kStatus_Power_HandleDuplicated

Shared handle has already been created.

enumerator kStatus_Power_NotInTargetMode

Not in the target low-power mode.

enumerator kStatus_Power_NackWithMultiReasons

NACK received with multiple reasons.

enumerator kStatus_Power_SyncFailed

Failed to synchronize the two cores.

enumerator kStatus_Power_CM0PNotWFI

CM0P did not execute WFI after approval to enter the requested low-power mode.

enumerator kStatus_Power_WakeupFromDPD1

Woke up from DPD1 successfully.

enumerator kStatus_Power_WakeupFromDPD2

Woke up from DPD2 successfully.

enumerator kStatus_Power_DualCoreNotSynced

The two cores are not synchronized.

enumerator kStatus_Power_AdvcPreVoltageChangeFailed

ADVC pre-voltage change request failed.

enumerator kStatus_Power_AdvcPostVoltageChangeFailed

ADVC post-voltage change request failed.

enumerator kStatus_Power_AdvcPostSyncFailed

ADVC post-change sync failed.

enum _power_low_power_mode

The enumeration of low power modes.

Values:

enumerator kPower_Sleep

Sleep Mode.

enumerator kPower_DeepSleep

Deep Sleep Mode.

enumerator kPower_PowerDown1

Power Down 1 mode.

enumerator kPower_PowerDown2

Power Down 2 mode.

enumerator kPower_DeepPowerDown1

Deep Power Down 1 mode.

enumerator kPower_DeepPowerDown2

Deep Power Down 2 mode.

enumerator kPower_DeepPowerDown3

Deep Power Down 3 mode.

enumerator kPower_ShutDown

ShutDown Mode

enumerator kPower_Active

Active Mode.

enum _power_wakeup_source

The enumeration of wakeup sources for different low power modes.

Values:

enumerator kPower_WS_NONE

enumerator kPower_WS_Main_RtcAlarm0

RTC Alarm0 as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_RtcAlarm0

RTC Alarm0 as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_RtcAlarm0

RTC Alarm0 as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_RtcAlarm1

RTC Alarm1 as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_RtcAlarm1

RTC Alarm1 as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_RtcAlarm1

RTC Alarm1 as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_QTimerIrq

QTimer IRQ as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_QTimerIrq

QTimer IRQ as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_QTimerIrq

QTimer IRQ as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_RtcWDT

RTC watch dog as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_RtcWDT

RTC watch dog as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_RtcWDT

RTC watch dog as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_RtcXtalFail

RTC XTAL fail as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_RtcXtalFail

RTC XTAL fail as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_RtcXtalFail

RTC XTAL fail as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_ExternalINTFallEdge

External INT falling edge as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_ExternalINTFallEdge

External INT falling edge as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_ExternalINTFallEdge

External INT falling edge as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_ExternalINTRiseEdge

External INT rising edge as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_ExternalINTRiseEdge

External INT rising edge as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_ExternalINTRiseEdge

External INT rising edge as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_SMMTimer

Deep sleep counter as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_SMMTimer

Deep sleep counter as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_SMMTimer

Deep sleep counter as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_Comparator

Voltage comparator as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_Comparator

Voltage comparator as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_Comparator

Voltage comparator as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_AonHsGpioWakeup0

HS_GPIO wakeup0 as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_AonHsGpioWakeup0

HS_GPIO wakeup0 as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_AonHsGpioWakeup0

HS_GPIO wakeup0 as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_Lpuart0

LPUART0 Interrupt as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_Lpuart0

LPUART0 Interrupt as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_Lpuart0

LPUART0 Interrupt as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_AdvcOrACMP

ADVC or ACMP as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_AdvcOrACMP

ADVC or ACMP as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_AdvcOrACMP

ADVC or ACMP as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_Lpi2cInt

AON Lpi2c interrupt as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_Lpi2cInt

AON Lpi2c interrupt as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_Lpi2cInt

AON Lpi2c interrupt as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_AdcInt

ADC interrupt as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_AdcInt

ADC interrupt as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_AdcInt

ADC interrupt as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_LptmrInt

LPTMR interrupt as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_LptmrInt

LPTMR interrupt as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_LptmrInt

LPTMR interrupt as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_TamperDetect

Tamper detect as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_TamperDetect

Tamper detect as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_TamperDetect

Tamper detect as wakeup source, wakeup both Main and AON Domains

enumerator kPower_WS_Main_LcdInt

LCD interrupt as wakeup source, only wakeup Main Domain

enumerator kPower_WS_Aon_LcdInt

LCD interrupt as wakeup source, only wakeup AON Domain

enumerator kPower_WS_Both_LcdInt

LCD interrupt as wakeup source, wakeup both Main and AON Domains

enum _power_main_domain_sram_array

Values:

enumerator kPower_MainDomainNoneRams

enumerator kPower_MainDomainRamX0

Main Domain RAM X0, bitmask representation for power control

enumerator kPower_MainDomainRamX1

Main Domain RAM X1, bitmask representation for power control

enumerator kPower_MainDomainRamA0

Main Domain RAM A0, bitmask representation for power control

enumerator kPower_MainDomainRamA1

Main Domain RAM A1, bitmask representation for power control

enumerator kPower_MainDomainRamA2

Main Domain RAM A2, bitmask representation for power control

enumerator kPower_MainDomainRamA3

Main Domain RAM A3, bitmask representation for power control

enumerator kPower_MainDomainRamB0

Main Domain RAM B0, bitmask representation for power control

enumerator kPower_MainDomainRamB1

Main Domain RAM B1, bitmask representation for power control

enumerator kPower_MainDomainRamB2ToB4

Main Domain RAM B2 to B4, bitmask representation for power control

enumerator kPower_MainDomainAllRams

Represents all RAMs in the Main Domain, bitmask for power control

enum _power_vdd_core_aon_output_voltage

The enumeration of VDD_CORE_AON output voltage.

Values:

enumerator kPower_VddCoreAon_785mV

The output voltage of VDD_CORE_AON is about 785mV.

enumerator kPower_VddCoreAon_760mV

The output voltage of VDD_CORE_AON is about 760mV.

enumerator kPower_VddCoreAon_750mV

The output voltage of VDD_CORE_AON is about 750mV.

enumerator kPower_VddCoreAon_700mV

The output voltage of VDD_CORE_AON is about 700mV.

enumerator kPower_VddCoreAon_630mV

The output voltage of VDD_CORE_AON is about 630mV.

enumerator kPower_VddCoreAon_AdvcControl

The output voltage of VDD_CORE_AON is controlled by ADVC.

enum _power_aon_domain_sram_array

Values:

enumerator kPower_AonDomainNoneRams

No AON Domain RAMs.

enumerator kPower_AonDomainRam1stHalf16kB

First half (16kB) of AON Domain RAM, bitmask for power control

enumerator kPower_AonDomainRam2nd8kB

Second 8kB of AON Domain RAM, bitmask for power control

enumerator kPower_AonDomainRamLower8kB

Lower 8kB of AON Domain RAM, bitmask for power control

enumerator kPower_AonDomainAllRams

Represents all RAMs in the AON Domain, bitmask for power control

enum _power_mu_message_direction

Enumeration of power MU message directions.

Values:

enumerator kPower_MsgDirMainToAon

Message direction from Main to AON domain

enumerator kPower_MsgDirAonToMain

Message direction from AON to Main domain

enum _power_mu_message_type

Enumeration of power MU message types.

Values:

enumerator kPower_MsgTypeRequest

Message type is a request

enumerator kPower_MsgTypeACK

Message type is response with ACKnowledgment

enumerator kPower_MsgTypeNACK

Message type is response with Negative ACKnowledgment

enumerator kPower_MsgTypeSync

Message type is to sync dual cores.

enum _power_mu_nack_reason

The reason of NACK response.

Values:

enumerator kPower_MsgNACK_ChannelMisMatch

NACK response due to channel mismatch.

enumerator kPower_MsgNACK_TargetModeNotAllowed

NACK response due to target mode not allowed..

enumerator kPower_MsgNACK_WrongMsgReceived

NACK response due to wrong message.

enum _power_dpd1_transition

Enumeration of follow power transition.

Values:

enumerator kPower_Dpd1ToActive

Transition from DPD1 to Active mode

enumerator kPower_Dpd1ToDpd2WakeToDpd1

Transition from DPD1 to DPD2 wakeup to DPD1 mode

enumerator kPower_Dpd1ToDpd2WakeToActive

Transition from DPD1 to DPD2 wakeup to Active mode

enum _power_dual_core_sync_state

Dual-core synchronization state stored in power_handle_t::dualCoreSynced.

This 2-bit field acts as a lightweight state machine to coordinate CM33 and CM0+ around low-power wakeup sequences, preventing CM0+ from clearing AON__SMM->STAT while CM33 ROM is still reading it.

State	Meaning
00	Not initialised (handle not yet created on both cores)
01	CM33 ROM wakeup path active (DPD1->Active or DPD2->Active).

CM0+ must skip the STAT write in Power_ClearLpPowerSettings(). CM33 will perform the write after exiting its spin-wait. 10 | DPD2 entered with wakeToDpd1=true (DPD2->DPD1 transition). CM0+ is allowed to write STAT (CM33 ROM does not run on this path), then immediately restores state to 01 for the subsequent DPD1->Active step. 11 | MU link established; both cores are fully operational.

Values:

enumerator kPower_DualCoreNotSynced

00: handle not initialised

enumerator kPower_DualCoreAonOnly

01: CM33 ROM wakeup path active, CM0+ must defer STAT write

enumerator kPower_DualCoreDpd2ToDpd1

10: DPD2->DPD1 path, CM0+ writes STAT then restores to 01

enumerator kPower_DualCoreSynced

11: both cores operational via MU

typedef enum _power_low_power_mode power_low_power_mode_t

The enumeration of low power modes.

typedef bool (*power_user_callback_t)(power_low_power_mode_t targetPowerMode, void *ptrPowerConfig, void *userData)

typedef enum _power_wakeup_source power_wakeup_source_t

The enumeration of wakeup sources for different low power modes.

typedef enum _power_vdd_core_aon_output_voltage power_vdd_core_output_voltage_t

The enumeration of VDD_CORE_AON output voltage.

typedef enum _power_mu_message_direction power_mu_message_direction_t

Enumeration of power MU message directions.

typedef enum _power_mu_message_type power_mu_message_type_t

Enumeration of power MU message types.

typedef enum _power_mu_nack_reason power_mu_nack_reason_t

The reason of NACK response.

typedef struct _power_ds_config power_ds_config_t

Configuration structure for deep sleep mode.

typedef struct _power_pd1_config power_pd1_config_t

Configuration structure for power down 1 mode.

typedef struct _power_pd2_config power_pd2_config_t

Configuration structure for power down 2 mode.

typedef enum _power_dpd1_transition power_dpd1_transition_t

Enumeration of follow power transition.

typedef struct _power_dpd1_config power_dpd1_config_t

Configuration structure for deep power down mode 1.

typedef struct _power_dpd2_config power_dpd2_config_t

Configuration structure for deep power down mode 2.

typedef struct _power_dpd3_config power_dpd3_config_t

Configuration structure for deep power down mode 3.

typedef struct _power_sd_config power_sd_config_t

Configuration structure for shut down.

typedef struct _power_wakeup_source_info power_wakeup_source_info_t

The structure of dumped wakeup source information.

typedef enum _power_dual_core_sync_state power_dual_core_sync_state_t

Dual-core synchronization state stored in power_handle_t::dualCoreSynced.

This 2-bit field acts as a lightweight state machine to coordinate CM33 and CM0+ around low-power wakeup sequences, preventing CM0+ from clearing AON__SMM->STAT while CM33 ROM is still reading it.

State	Meaning
00	Not initialised (handle not yet created on both cores)
01	CM33 ROM wakeup path active (DPD1->Active or DPD2->Active).

CM0+ must skip the STAT write in Power_ClearLpPowerSettings(). CM33 will perform the write after exiting its spin-wait. 10 | DPD2 entered with wakeToDpd1=true (DPD2->DPD1 transition). CM0+ is allowed to write STAT (CM33 ROM does not run on this path), then immediately restores state to 01 for the subsequent DPD1->Active step. 11 | MU link established; both cores are fully operational.

typedef struct _power_handle power_handle_t

Structure to handle power management operations.

typedef struct _power_drv_config power_drv_config_t

Inform the other core that it attempts to create a handle.

status_t Power_CreateHandle(power_handle_t *handle, const power_drv_config_t *config)

Create the shared power handle.

This function initializes the shared power_handle_t in the shared RAM and, unless power_drv_config_t::noSyncCM0P is true, attempts to synchronize with the other core.

Note

Please invoke this function before using other APIs.

Parameters:

• handle – [in] Pointer to power_handle_t in shared RAM.

• config – [in] Pointer to power_drv_config_t.

Return values:

• kStatus_Success – Handle created (and cores synchronized if requested).

• kStatus_Power_HandleDuplicated – A shared handle has already been created by the peer.

• kStatus_POWER_MuTransferError – MU synchronization/transfer error.

• kStatus_Timeout – Timed out while waiting for MU response (if timeout enabled).

void Power_DumpHandleValue(power_handle_t *ptrDumpBuffer)

Dump the current shared handle into a local buffer.

Parameters:

• ptrDumpBuffer – [out] Pointer to a power_handle_t to receive the copy.

void Power_GetPowerModeConfig(void *config)

Get the configuration of the latest requested low-power mode.

Parameters:

• config – [out] Pointer to a buffer large enough to hold the configuration structure that matches Power_GetTargetLowPowerMode(). The actual type depends on the saved target mode (e.g. power_pd2_config_t).

uint32_t Power_GetHandleOffset(void)

Get the offset of shared handle in shared RAM.

Returns:

Offset of shared handle in shared RAM, in bytes.

void Power_RestoreHandleOffset(uint32_t offset)

Restore the shared handle from offset in shared RAM.

Parameters:

• offset – [in] Offset of shared handle in shared RAM, in bytes.

status_t Power_SyncDualCoreBlocking(void)

Synchronizes the two cores in a blocking manner.

Return values:

• kStatus_Success – Synchronized successfully.

• kStatus_Power_HandleDuplicated – The peer reports a duplicated handle.

• kStatus_POWER_MuTransferError – MU transfer error.

• kStatus_Timeout – Timed out while waiting for MU response (if timeout enabled).

FSL_POWER_DRIVER_VERSION

power driver version 2.3.5.

POWER_SHARED_RAM_BASE_ADDR

POWER_MU_TRANSFER_TIMEOUT

POWER_CONTEXT_SAVING_DPD2_TO_DPD1_SYNC_TIMEOUT

POWER_ENCODE_WS(wakeupDomain, pinEdge, aonIndex)

Encodes a wakeup source into a 32-bit code.

Note

Bit field layout:

• bits [7:0] : AON control-bit index.

• bits [23:20] : External pin edge (1 = rising, 2 = falling, 3 = both edges).

• bits [27:24] : Wakeup domain (0 = Main only, 1 = AON only, 2 = both Main and AON). In some low-power modes (e.g. PD2), only the AON domain can be woken.

POWER_DECODE_WS(wsCode)

void Power_EnableWakeupSource(power_wakeup_source_t ws)

Enable input wakeup source, once enabled it will be effective until disabled.

The enabled wakeup sources are recorded, and set to register before entering low power modes.

Note

There are two ways to enable wakeup source: The first one is invoking Power_EnableWakeupSource(), the way is used to enable more than one wakeup source; The second one is specify the wakeup source in configuration of low power mode.

Parameters:

• ws – [in] Specify the coded wakeup source, please refer to power_wakeup_source_t for details.

void Power_DisableWakeupSource(power_wakeup_source_t ws)

Disable input wakeup source.

Parameters:

• ws – [in] Specify the coded wakeup source, please refer to power_wakeup_source_t for details.

void Power_DisableAllWakeupSources(void)

Disable all enabled wakeup sources to both main domain and aon domain.

void Power_DumpEnabledWakeSource(power_wakeup_source_info_t *ptrWsInfo)

Dump information of all configured wakeup sources, in type of power_wakeup_source_info_t.

Parameters:

• ptrWsInfo – [out] Pointer to the variable to store dumped wakeup source information.

void Power_GetWakeupSource(uint32_t *ptrWakeupSourceMask)

Get latest mask of wakeup sources which cause the wakeup to main CPU.

Parameters:

• ptrWakeupSourceMask – [out] Pointer to the variable to store mask of wakeup sources.

void Power_CheckThenDisableWakeupSource(power_wakeup_source_t ws)

Check whether the selected wakeup source is already enabled, if it is then disable it.

Parameters:

• ws – Specify the wakeup source in type of power_wakeup_source_t.

void Power_CheckThenEnableWakeupSource(power_wakeup_source_t ws)

Check whether the selected wakeup source is disabled, if it is then enable it.

Parameters:

• ws – Specify the wakeup source in type of power_wakeup_source_t.

void Power_RegisterUserCallback(power_user_callback_t callback, void *userData)

Register user callback.

Parameters:

• callback – [in] Pointer to callback in type of power_user_callback_t.

• userData – [in] Pointer to user data.

void Power_UnRegisterUserCallback(void)

Unregister user callback.

power_low_power_mode_t Power_GetTargetLowPowerMode(void)

Get the target low power mode of latest request.

Returns:

The target low power mode power_low_power_mode_t of latest request.

power_low_power_mode_t Power_GetPreviousPowerMode(void)

Get previous power mode.

Returns:

The previous power mode.

void Power_ResetPreviousPowerMode(void)

Reset previous power mode as active mode.

void Power_UpdatePreviousPowerMode(power_low_power_mode_t lpMode)

Update previous power mode as input low power mode.

Parameters:

• lpMode – The low power mode to update, in type of power_low_power_mode_t.

status_t Power_GetCurrentPowerMode(power_low_power_mode_t *ptrCurLpMode)

Get current power mode.

Parameters:

• ptrCurLpMode – [out] Pointer to store current low power mode

Return values:

kStatus_Success – Successfully retrieved current low power mode.

power_low_power_mode_t Power_GetTargetPowerMode(void)

Get the target low power mode.

Returns:

Requested low power mode, in type of power_low_power_mode_t.

void Power_ClearTargetPowerMode(void)

Clear the target low power mode.

void Power_ClearLpPowerSettings(void)

Clear all low power settings.

status_t Power_EnterLowPowerMode(power_low_power_mode_t lowpowerMode, void *config)

Enter selected low power mode.

Parameters:

• lowpowerMode – [in] Indicate specific target low power mode.

• config – [in] Pointer to the matching configuration structure.

Return values:

• kStatus_Success – Entered the target mode (or queued the sequence on peer core).

• kStatus_POWER_MuTransferError – MU transfer error.

• kStatus_POWER_RequestNotAllowed – Request rejected by the peer.

• kStatus_Power_DualCoreNotSynced – The two cores are not synchronized (for modes requiring sync).

• kStatus_Timeout – Timed out while waiting for MU response (if timeout enabled).

status_t Power_EnterSleep(void)

Enter the sleep mode.

This function is used to put the system into sleep mode.

Return values:

• kStatus_Success – Successfully entered sleep mode.

• kStatus_POWER_MuTransferError – Something error occurs during MU transfer.

• kStatus_POWER_RequestNotAllowed – Request not allowed by another core.

status_t Power_EnterDeepSleep(power_ds_config_t *config)

Enter Deep Sleep mode.

This function attempts to put the system into Deep Sleep mode with the provided configuration.

Parameters:

• config – [in] Pointer to the Deep Sleep mode configuration.

Return values:

• kStatus_Success – Successfully entered Deep Sleep mode.

• kStatus_POWER_MuTransferError – Something error occurs during MU transfer.

• kStatus_POWER_RequestNotAllowed – Request not allowed by another core.

status_t Power_EnterPowerDown1(power_pd1_config_t *config)

Enter Power Down 1 mode.

This function attempts to put the system into Power Down 1 mode with the provided configuration.

Parameters:

• config – [in] Pointer to the Power Down 1 mode configuration.

Return values:

• kStatus_Success – Successfully entered Power Down 1 mode.

• kStatus_POWER_MuTransferError – Something error occurs during MU transfer.

• kStatus_POWER_RequestNotAllowed – Request not allowed by another core.

status_t Power_EnterPowerDown2(power_pd2_config_t *config)

Enter Power Down 2 mode.

This function attempts to put the system into Power Down 2 mode with the provided configuration.

Parameters:

• config – [in] Pointer to the Power Down 2 mode configuration.

Return values:

• kStatus_Success – Successfully entered Power Down 2 mode.

• kStatus_POWER_MuTransferError – Something error occurs during MU transfer.

• kStatus_POWER_RequestNotAllowed – Request not allowed by another core.

status_t Power_EnterDeepPowerDown1(power_dpd1_config_t *config)

Enter Deep Power Down 1 mode.

This function attempts to put the system into Deep Power Down 1 mode with the provided configuration.

Note

If attempting to enable context saving feature, please ensure RAM blocks used by stack are retained.

Parameters:

• config – [in] Pointer to the Deep Power Down 1 mode configuration.

Return values:

• kStatus_Success – Successfully entered Deep Power Down 1 mode.

• kStatus_POWER_MuTransferError – Something error occurs during MU transfer.

• kStatus_POWER_RequestNotAllowed – Request not allowed by another core.

power_dpd1_transition_t Power_GetDeepPowerDown1NextTransition(void)

Get the next transition after Deep Power Down 1 mode.

Returns:

Next transition after Deep Power Down 1 mode, in type of power_dpd1_transition_t.

status_t Power_EnterDeepPowerDown2(power_dpd2_config_t *config)

Enter Deep Power Down 2 mode.

This function attempts to put the system into Deep Power Down 2 mode with the provided configuration. The function automatically manages clock switching and voltage scaling during DPD2 entry and wakeup:

• On entry: Switches AON CPU clock to target frequency (32kHz or FRO/4 based on switchToX32K flag)

• On wakeup (with saveContext=true): Restores original clock frequency

• Voltage is automatically selected based on target frequency

• When ADVC is enabled: Uses ADVC Pre/Post VoltageChangeRequest APIs for voltage management

• When ADVC is disabled: Directly updates VddCore voltage based on frequency requirements

Note

If attempting to enable context saving feature, please ensure RAM blocks used by stack are retained.

Note

The dpd2VddCoreAonVoltage field in config is deprecated and ignored. Voltage is now automatically selected based on the target clock frequency.

Note

When disableFRO10M or disableFRO3M is set, the caller must switch all FRO-derived CGU peripheral clocks to a non-FRO source (e.g. 32 kHz) or disable them before calling this function. The power driver handles the AON CPU clock switch and FRO disable, but does not modify peripheral clock configuration (PER_CLK_CONFIG / PER_CLK_EN). Failure to do so may cause ADVC to raise VDD_CORE voltage due to undefined FRO block output after the selected FRO is disabled.

Parameters:

• config – [in] Pointer to the Deep Power Down 2 mode configuration.

Return values:

• kStatus_Success – Entered DPD2 (or completed the request sequence).

• kStatus_Power_WakeupFromDPD2 – Returned from DPD2 with context restored (when context saving enabled).

• kStatus_POWER_MuTransferError – MU transfer error.

• kStatus_POWER_RequestNotAllowed – Request rejected by the peer.

• kStatus_Power_DualCoreNotSynced – Cores are not synchronized.

• kStatus_Timeout – Timed out while waiting for MU response / cross-core sync.

status_t Power_EnterDeepPowerDown3(power_dpd3_config_t *config)

Enter Deep Power Down 3 mode.

This function attempts to put the system into Deep Power Down 3 mode with the provided configuration.

Parameters:

• config – [in] Pointer to the Deep Power Down 3 mode configuration.

Return values:

• kStatus_Success – Entered DPD3 (or completed the request sequence).

• kStatus_POWER_MuTransferError – MU transfer error.

• kStatus_POWER_RequestNotAllowed – Request rejected by the peer.

• kStatus_Power_DualCoreNotSynced – Cores are not synchronized.

• kStatus_Timeout – Timed out while waiting for MU response (if timeout enabled).

status_t Power_EnterShutDown(power_sd_config_t *config)

Enter Shutdown mode.

This function attempts to put the system into Shutdown mode with the provided configuration.

Parameters:

• config – [in] Pointer to the Shutdown mode configuration.

Return values:

• kStatus_Success – Entered Shutdown (or completed the request sequence).

• kStatus_POWER_MuTransferError – MU transfer error.

• kStatus_POWER_RequestNotAllowed – Request rejected by the peer.

• kStatus_Power_DualCoreNotSynced – Cores are not synchronized.

• kStatus_Timeout – Timed out while waiting for MU response (if timeout enabled).

uint32_t Power_PushContext(uint32_t handleAddr)

Save current context into stack. ——&#8212; <–&#8212;High address | D15 | –&#8212; ——&#8212; | | D14 | | ——&#8212; | | D13 | | ——&#8212; | | D12 | | ——&#8212; |-&#8212; Only CM33 | D11 | | ——&#8212; | | D10 | | ——&#8212; | | D9 | | ——&#8212; |.

void Power_LowPowerBoot(void)

Restore saved context from stack.

Note

User can use this function to restore context after waking up from low power modes which reset system.

void Power_NotifyCM33ToRun(void)

Notify CM33 that CM0+ is ready to proceed after DPD2 wakeup with context restore.

This function waits for CM33 to signal that it has restored context (by writing a sync pattern to SMM backup1 registers), then acknowledges by setting dualCoreSynced to kPower_DualCoreSynced, allowing both cores to continue in sync.

Note

Called from CM0+ side only after waking up from DPD2 with context saving enabled.

power_mu_message_type_t Power_GetMuMessageType(uint32_t message)

Get type of received MU message.

Parameters:

• message – The received message.

Returns:

The type of MU message.

power_mu_message_direction_t Power_GetMuMessageDir(uint32_t message)

Get direction of received MU message.

Parameters:

• message – The received message.

Returns:

The direction of MU message.

status_t Power_MuSyncCallback(uint32_t message, uint32_t channelId)

The callback when one core want to sync with another, that is when the message type is kPower_MsgTypeSync.

Parameters:

• message – Received message value.

• channelId – The channel which transfer the message.

Return values:

• kStatus_Power_SyncFailed – Failed to sync between dual cores.

• kStatus_Success – Sync dual cores successfully.

status_t Power_InterpretRequest(uint32_t message)

Interpret request message from requester.

Parameters:

• message – The message which request from requester.

Return values:

• kStatus_POWER_MuTransferError – Something wrong during transfer.

• kStatus_POWER_RequestNotAllowed – Request is not allowed.

• kStatus_Success – Interpret request message successfully.

status_t Power_InterpretResponse(uint32_t message)

Interpret a MU response message.

Parameters:

• message – [in] The response message sent to the requester.

Return values:

• kStatus_Success – The response has been interpreted successfully (ACK).

• kStatus_POWER_MuTransferError – Invalid message or MU error.

• kStatus_POWER_RequestNotAllowed – NACK due to target mode not allowed.

• kStatus_Power_NackWithMultiReasons – NACK with multiple reasons.

status_t Power_MuMessageCallback(uint32_t message, uint32_t channelId)

Callback function for handling power MU messages.

This function is called when a power MU message is received. It processes the message based on the given message content and the channel ID.

Note

This function integrate Power_MuSyncCallback(), Power_InterpretRequest(), and Power_InterpretResponse().

Parameters:

• message – [in] The received power MU message.

• channelId – [in] The ID of the channel on which the message was received.

Return values:

• kStatus_Power_SyncFailed – Failed to sync between dual cores.

• kStatus_POWER_MuTransferError – Something wrong during transfer.

• kStatus_POWER_RequestNotAllowed – Request is not allowed.

• kStatus_Success – Interpret request/response message successfully.

struct _power_ds_config

#include <fsl_power.h>

Configuration structure for deep sleep mode.

struct _power_pd1_config

#include <fsl_power.h>

Configuration structure for power down 1 mode.

Public Members

power_wakeup_source_t mainWakeupSource

Specify the wakeup source to main domain. If the selected wakeup source is not already enabled, it will be enabled before entering PD1 mode. Setting it to kPower_WS_NONE indicates that this structure does not control any wakeup source. Pre-enabled wakeup sources are not affected. Wakeup sources can also be enabled manually by invoking Power_EnableWakeupSource().

uint32_t mainRamArraysToRetain

Deprecated:

: This field is no longer used, In PD1 mode, all RAM arrays retained.

uint32_t disableBandgap

Flag to indicate whether to disable the bandgap during power down

uint32_t enableIVSMode

Enable/disable IVS mode for the Main domain SRAM retention.

pmu_fro16k_output_freq_t fro16KOutputFreq

Specify the output frequency of FRO16K

struct _power_pd2_config

#include <fsl_power.h>

Configuration structure for power down 2 mode.

Public Members

uint32_t mainRamArraysToRetain

Deprecated:

: This field is no longer used, In PD2 mode, all RAM arrays retained.

uint32_t aonRamArraysToRetain

Deprecated:

: This field is no longer used, In PD2 mode, all RAM arrays retained.

uint32_t enableIVSMode

Enable/disable IVS mode for the Main domain SRAM retention.

uint32_t disableBandgap

Flag to indicate whether to disable the bandgap during DPD2 mode

uint32_t disableFRO10M

Flag to indicate whether to disable the FRO10M clock during DPD2 mode

power_vdd_core_output_voltage_t vddCoreAonVoltage

Deprecated:

: Voltage is now automatically selected based on frequency. This field is ignored.

pmu_fro16k_output_freq_t fro16KOutputFreq

Specify the output frequency of FRO16K

struct _power_dpd1_config

#include <fsl_power.h>

Configuration structure for deep power down mode 1.

Public Members

uint32_t mainRamArraysToRetain

Bitmask representing the main domain RAM arrays to retain during power down

uint32_t disableBandgap

Flag to indicate whether to disable the bandgap during power down

uint32_t enableIVSMode

Enable/disable IVS mode for the Main domain SRAM retention.

power_dpd1_transition_t nextTrans

Next transition after DPD1 mode, refer to power_dpd1_transition_t

uint32_t saveContext

True to save basic register context into stack, false to do not save.

uint32_t disableFRO10M

Flag to indicate whether to disable the FRO10M clock during DPD1 mode

pmu_fro16k_output_freq_t fro16KOutputFreq

Specify the output frequency of FRO16K

uint32_t reserved

Reserved for using.

power_vdd_core_output_voltage_t vddCoreAonVoltage

Deprecated:

Voltage is now automatically selected based on frequency. Specify output voltage of VDD_CORE_AON

struct _power_dpd2_config

#include <fsl_power.h>

Configuration structure for deep power down mode 2.

Public Members

power_wakeup_source_t mainWakeupSource

Specify the wakeup source to main domain. If the selected wakeup source is not already enabled, it will be enabled before entering DPD2 mode. Setting it to kPower_WS_NONE indicates that this structure does not control any wakeup source. Pre-enabled wakeup sources are not affected. Wakeup sources can also be enabled manually by invoking Power_EnableWakeupSource().

power_wakeup_source_t aonWakeupSource

Specify the wakeup source to aon domain. If the selected wakeup source is not already enabled, it will be enabled before entering DPD2 mode. Setting it to kPower_WS_NONE indicates that this structure does not control any wakeup source. Pre-enabled wakeup sources are not affected. Wakeup sources can also be enabled manually by invoking Power_EnableWakeupSource().

uint32_t mainRamArraysToRetain

Bitmask representing the main domain RAM arrays to retain during DPD2 mode

uint32_t aonRamArraysToRetain

Bitmask representing the AON domain RAM arrays to retain during DPD2 mode

uint32_t enableIVSMode

Enable/disable IVS mode for the Main domain SRAM retention.

uint32_t disableBandgap

Flag to indicate whether to disable the bandgap during DPD2 mode

uint32_t switchToX32K

Flag to indicate whether to switch to X32K clock source during DPD2 mode

uint32_t disableFRO10M

Flag to indicate whether to disable the FRO10M clock during DPD2 mode. Please note, if switchToX32K is disable, FRO10M can not be disable if it is using as clock source.

Note

Before calling Power_EnterDeepPowerDown2() with this flag set, the caller must ensure all FRO-derived CGU peripheral clocks (configured via PER_CLK_CONFIG and PER_CLK_EN) are switched to a non-FRO source (e.g. 32 kHz) or disabled. When the FRO selected by SEL_MODE is disabled, the FRO block output becomes undefined, causing any remaining FROdiv-sourced clock to carry an undefined signal. ADVC may misinterpret this as a high frequency and raise VDD_CORE voltage. See ADVC document sections 1.3.2 and 3.2.4 step iii for details.

uint32_t wakeToDpd1

Flag to indicate whether to wake up to DPD1 mode after DPD2 mode

uint32_t saveContext

True to save basic register context into stack, false to do not save.

uint32_t disableFRO3M

True to disable FRO3M, false to do not disable. Please note, if switchToX32K is disable, FRO3M can not be disable if it is using as clock source. See disableFRO10M note for CGU peripheral clock requirements.

pmu_fro16k_output_freq_t fro16KOutputFreq

Specify the output frequency of FRO16K

power_vdd_core_output_voltage_t dpd2VddCoreAonVoltage

Deprecated:

Voltage is now automatically selected based on frequency. Specify output voltage of VDD_CORE AON in DPD2 mode, in type of power_vdd_core_output_voltage_t.

struct _power_dpd3_config

#include <fsl_power.h>

Configuration structure for deep power down mode 3.

Public Members

power_wakeup_source_t wakeupSource

Specify the wakeup source to main and aon domain. If the selected wakeup source is not already enabled, it will be enabled before entering DPD3 mode. Setting it to kPower_WS_NONE indicates that this structure does not control any wakeup source. Pre-enabled wakeup sources are not affected. Wakeup sources can also be enabled manually by invoking Power_EnableWakeupSource().

pmu_fro16k_output_freq_t fro16KOutputFreq

Specify the output frequency of FRO16K

bool keepFro16kActive

Flag to indicate whether to keep FRO16K active during SD mode. If false, the fro16KOutputFreq configuration is ignored.

struct _power_sd_config

#include <fsl_power.h>

Configuration structure for shut down.

Public Members

power_wakeup_source_t wakeupSource

Specify the wakeup source to main and aon domain. If the selected wakeup source is not already enabled, it will be enabled before entering SD mode. Setting it to kPower_WS_NONE indicates that this structure does not control any wakeup source. Pre-enabled wakeup sources are not affected. Wakeup sources can also be enabled manually by invoking Power_EnableWakeupSource().

pmu_fro16k_output_freq_t fro16KOutputFreq

Specify the output frequency of FRO16K

bool keepFro16kActive

Flag to indicate whether to keep FRO16K active during SD mode. If false, the fro16KOutputFreq configuration is ignored.

struct _power_wakeup_source_info

#include <fsl_power.h>

The structure of dumped wakeup source information.

Public Members

uint32_t aonWakeupSourceMask

The mask of wakeup sources in AON domain.

uint32_t mainWakeupSourceMask

The mask of wakeup sources in Main domain.

struct _power_handle

#include <fsl_power.h>

Structure to handle power management operations.

Public Members

uint32_t lpConfig[4U]

Buffer (4 x 32-bit words) for storing the most recent low-power configuration.

power_user_callback_t cm33Callback

Callback function for CM33 core operations, in type of power_user_callback_t

void *cm33UserData

User data pointer for CM33 core operations

power_user_callback_t cm0pCallback

Callback function for CM0+ core operations, in type of power_user_callback_t

void *cm0pUserData

User data pointer for CM0+ core operations

power_wakeup_source_info_t enabledWsInfo

Used to record all enabled wakeup sources.

volatile uint32_t muChannelId

MU channel ID used for power communication.

volatile power_low_power_mode_t targetPowerMode

Target low-power mode requested by this core.

volatile power_low_power_mode_t previousPowerMode

Previously entered low-power mode.

volatile power_dual_core_sync_state_t dualCoreSynced

Dual-core sync state; see power_dual_core_sync_state_t.

volatile uint32_t requestCM33Start

CM0P-side flag requesting CM33 to run the entry sequence.

volatile uint32_t cm0pWFI

CM0P has executed WFI (used for PD2/DPD2/DPD3/SD).

volatile uint32_t cm33SavedSP

CM33 saved SP for context restore (offset 44).

struct _power_drv_config

#include <fsl_power.h>

Inform the other core that it attempts to create a handle.

Public Members

uint32_t muChannelId

MU channel ID used by the power driver.

uint32_t noSyncCM0P

If true, skip synchronizing with CM0P; if false, perform blocking sync.

QTMR: Quad Timer Driver

void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)

Ungates the Quad Timer clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the Quad Timer driver.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• config – Pointer to user’s Quad Timer config structure

void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)

Stops the counter and gates the Quad Timer clock.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

void QTMR_GetDefaultConfig(qtmr_config_t *config)

Fill in the Quad Timer config struct with the default settings.

The default values are:

config->debugMode = kQTMR_RunNormalInDebug;
config->enableExternalForce = false;
config->enableMasterMode = false;
config->faultFilterCount = 0;
config->faultFilterPeriod = 0;
config->primarySource = kQTMR_ClockDivide_2;
config->secondarySource = kQTMR_Counter0InputPin;

Parameters:

• config – Pointer to user’s Quad Timer config structure.

void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Enables the selected Quad Timer interrupts.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t

void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Disables the selected Quad Timer interrupts.

Parameters:

• base – Quad Timer peripheral base addres

• channel – Quad Timer channel number

• mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t

uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)

Gets the enabled Quad Timer interrupts.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration qtmr_interrupt_enable_t

uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Gets the Quad Timer status flags.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

The status flags. This is the logical OR of members of the enumeration qtmr_status_flags_t

void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Clears the Quad Timer status flags.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• mask – The status flags to clear. This is a logical OR of members of the enumeration qtmr_status_flags_t

void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks)

Sets the timer period in ticks.

Timers counts from initial value till it equals the count value set here. The counter will then reinitialize to the value specified in the Load register.

Note

1. This function will write the time period in ticks to COMP1 or COMP2 register depending on the count direction

2. User can call the utility macros provided in fsl_common.h to convert to ticks

3. This function supports cases, providing only primary source clock without secondary source clock.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• ticks – Timer period in units of ticks

void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks)

Set compare value.

This function sets the value used for comparison with the counter value.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• ticks – Timer period in units of ticks.

static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t value)

Set load value.

This function sets the value used to initialize the counter after a counter comparison.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• value – Load register initialization value.

static inline uint32_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel)

Reads the current timer counting value.

This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note

User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

Current counter value in ticks

static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource)

Starts the Quad Timer counter.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• clockSource – Quad Timer clock source

static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel)

Stops the Quad Timer counter.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

FSL_QTMR_DRIVER_VERSION

Version

enum _qtmr_primary_count_source

Quad Timer primary clock source selection.

Values:

enumerator kQTMR_ClockCounter0InputPin

Use counter 0 input pin

enumerator kQTMR_ClockCounter1InputPin

Use counter 1 input pin

enumerator kQTMR_ClockCounter2InputPin

Use counter 2 input pin

enumerator kQTMR_ClockCounter3InputPin

Use counter 3 input pin

enumerator kQTMR_ClockCounter0Output

Use counter 0 output

enumerator kQTMR_ClockCounter1Output

Use counter 1 output

enumerator kQTMR_ClockCounter2Output

Use counter 2 output

enumerator kQTMR_ClockCounter3Output

Use counter 3 output

enumerator kQTMR_ClockDivide_1

IP bus clock divide by 1 prescaler

enumerator kQTMR_ClockDivide_2

IP bus clock divide by 2 prescaler

enumerator kQTMR_ClockDivide_4

IP bus clock divide by 4 prescaler

enumerator kQTMR_ClockDivide_8

IP bus clock divide by 8 prescaler

enumerator kQTMR_ClockDivide_16

IP bus clock divide by 16 prescaler

enumerator kQTMR_ClockDivide_32

IP bus clock divide by 32 prescaler

enumerator kQTMR_ClockDivide_64

IP bus clock divide by 64 prescaler

enumerator kQTMR_ClockDivide_128

IP bus clock divide by 128 prescaler

enum _qtmr_input_source

Quad Timer input sources selection.

Values:

enumerator kQTMR_Counter0InputPin

Use counter 0 input pin

enumerator kQTMR_Counter1InputPin

Use counter 1 input pin

enumerator kQTMR_Counter2InputPin

Use counter 2 input pin

enumerator kQTMR_Counter3InputPin

Use counter 3 input pin

enum _qtmr_counting_mode

Quad Timer counting mode selection.

Values:

enumerator kQTMR_NoOperation

No operation

enumerator kQTMR_PriSrcRiseEdge

Count rising edges of primary source

enumerator kQTMR_PriSrcRiseAndFallEdge

Count rising and falling edges of primary source

enumerator kQTMR_PriSrcRiseEdgeSecInpHigh

Count rise edges of pri SRC while sec inp high active

enumerator kQTMR_QuadCountMode

Quadrature count mode, uses pri and sec sources

enumerator kQTMR_PriSrcRiseEdgeSecDir

Count rising edges of pri SRC; sec SRC specifies dir

enumerator kQTMR_SecSrcTrigPriCnt

Edge of sec SRC trigger primary count until compare

enumerator kQTMR_CascadeCount

Cascaded count mode (up/down)

enum _qtmr_pwm_out_state

Quad Timer PWM output state.

Values:

enumerator kQTMR_PwmLow

The output state of PWM channel is low

enumerator kQTMR_PwmHigh

The output state of PWM channel is low

enum _qtmr_output_mode

Quad Timer output mode selection.

Values:

enumerator kQTMR_AssertWhenCountActive

Assert OFLAG while counter is active

enumerator kQTMR_ClearOnCompare

Clear OFLAG on successful compare

enumerator kQTMR_SetOnCompare

Set OFLAG on successful compare

enumerator kQTMR_ToggleOnCompare

Toggle OFLAG on successful compare

enumerator kQTMR_ToggleOnAltCompareReg

Toggle OFLAG using alternating compare registers

enumerator kQTMR_SetOnCompareClearOnSecSrcInp

Set OFLAG on compare, clear on sec SRC input edge

enumerator kQTMR_SetOnCompareClearOnCountRoll

Set OFLAG on compare, clear on counter rollover

enumerator kQTMR_EnableGateClock

Enable gated clock output while count is active

enum _qtmr_input_capture_edge

Quad Timer input capture edge mode, rising edge, or falling edge.

Values:

enumerator kQTMR_NoCapture

Capture is disabled

enumerator kQTMR_RisingEdge

Capture on rising edge (IPS=0) or falling edge (IPS=1)

enumerator kQTMR_FallingEdge

Capture on falling edge (IPS=0) or rising edge (IPS=1)

enumerator kQTMR_RisingAndFallingEdge

Capture on both edges

enum _qtmr_preload_control

Quad Timer input capture edge mode, rising edge, or falling edge.

Values:

enumerator kQTMR_NoPreload

Never preload

enumerator kQTMR_LoadOnComp1

Load upon successful compare with value in COMP1

enumerator kQTMR_LoadOnComp2

Load upon successful compare with value in COMP2

enum _qtmr_debug_action

List of Quad Timer run options when in Debug mode.

Values:

enumerator kQTMR_RunNormalInDebug

Continue with normal operation

enumerator kQTMR_HaltCounter

Halt counter

enumerator kQTMR_ForceOutToZero

Force output to logic 0

enumerator kQTMR_HaltCountForceOutZero

Halt counter and force output to logic 0

enum _qtmr_interrupt_enable

List of Quad Timer interrupts.

Values:

enumerator kQTMR_CompareInterruptEnable

Compare interrupt.

enumerator kQTMR_Compare1InterruptEnable

Compare 1 interrupt.

enumerator kQTMR_Compare2InterruptEnable

Compare 2 interrupt.

enumerator kQTMR_OverflowInterruptEnable

Timer overflow interrupt.

enumerator kQTMR_EdgeInterruptEnable

Input edge interrupt.

enum _qtmr_status_flags

List of Quad Timer flags.

Values:

enumerator kQTMR_CompareFlag

Compare flag

enumerator kQTMR_Compare1Flag

Compare 1 flag

enumerator kQTMR_Compare2Flag

Compare 2 flag

enumerator kQTMR_OverflowFlag

Timer overflow flag

enumerator kQTMR_EdgeFlag

Input edge flag

enum _qtmr_channel_selection

List of channel selection.

Values:

enumerator kQTMR_Channel_0

TMR Channel 0

enumerator kQTMR_Channel_1

TMR Channel 1

enumerator kQTMR_Channel_2

TMR Channel 2

enumerator kQTMR_Channel_3

TMR Channel 3

typedef uint32_t qtmrRegType

typedef enum _qtmr_primary_count_source qtmr_primary_count_source_t

Quad Timer primary clock source selection.

typedef enum _qtmr_input_source qtmr_input_source_t

Quad Timer input sources selection.

typedef enum _qtmr_counting_mode qtmr_counting_mode_t

Quad Timer counting mode selection.

typedef enum _qtmr_pwm_out_state qtmr_pwm_out_state_t

Quad Timer PWM output state.

typedef enum _qtmr_output_mode qtmr_output_mode_t

Quad Timer output mode selection.

typedef enum _qtmr_input_capture_edge qtmr_input_capture_edge_t

Quad Timer input capture edge mode, rising edge, or falling edge.

typedef enum _qtmr_preload_control qtmr_preload_control_t

Quad Timer input capture edge mode, rising edge, or falling edge.

typedef enum _qtmr_debug_action qtmr_debug_action_t

List of Quad Timer run options when in Debug mode.

typedef enum _qtmr_interrupt_enable qtmr_interrupt_enable_t

List of Quad Timer interrupts.

typedef enum _qtmr_status_flags qtmr_status_flags_t

List of Quad Timer flags.

typedef enum _qtmr_channel_selection qtmr_channel_selection_t

List of channel selection.

typedef struct _qtmr_config qtmr_config_t

Quad Timer config structure.

This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

status_t QTMR_SetupPwm(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)

Sets up Quad timer module for PWM signal output.

The function initializes the timer module according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• pwmFreqHz – PWM signal frequency in Hz

• dutyCyclePercent – PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)

• outputPolarity – true: invert polarity of the output signal, false: no inversion

• srcClock_Hz – Main counter clock in Hz.

Returns:

Returns an error if there was error setting up the signal.

void QTMR_SetupInputCapture(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_input_source_t capturePin, bool inputPolarity, bool reloadOnCapture, qtmr_input_capture_edge_t captureMode)

Allows the user to count the source clock cycles until a capture event arrives.

The count is stored in the capture register.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• capturePin – Pin through which we receive the input signal to trigger the capture

• inputPolarity – true: invert polarity of the input signal, false: no inversion

• reloadOnCapture – true: reload the counter when an input capture occurs, false: no reload

• captureMode – Specifies which edge of the input signal triggers a capture

void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus)

Set PWM output in idle status (high or low).

Note

When the PWM is set again, the counting needs to be restarted.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.

static inline qtmr_pwm_out_state_t QTMR_GetPwmOutputStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Get the channel output status.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

Current channel output status.

uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel)

Get the PWM channel dutycycle value.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

Returns:

Current channel dutycycle value.

void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_primary_count_source_t prescaler)

This function set the value of the prescaler on QTimer channels.

Parameters:

• base – Quad Timer peripheral base address

• channel – Quad Timer channel number

• prescaler – Set prescaler value

TMR_CSCTRL_OFLAG_MASK

TMR_CSCTRL_OFLAG_SHIFT

struct _qtmr_config

#include <fsl_qtmr.h>

Quad Timer config structure.

This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

Public Members

qtmr_primary_count_source_t primarySource

Specify the primary count source

qtmr_input_source_t secondarySource

Specify the secondary count source

bool enableMasterMode

true: Broadcast compare function output to other counters; false no broadcast

bool enableExternalForce

true: Compare from another counter force state of OFLAG signal false: OFLAG controlled by local counter

uint8_t faultFilterCount

Fault filter count

uint8_t faultFilterPeriod

Fault filter period;value of 0 will bypass the filter

qtmr_debug_action_t debugMode

Operation in Debug mode

Reset Driver

enum _SYSCON_RSTn

Enumeration for peripheral reset control bits.

Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers

Values:

enumerator kAonUART_RST_SHIFT_RSTn

AON UART reset control

enumerator kAonI2C_RST_SHIFT_RSTn

AON I2C reset control

enumerator kAonCAL_RST_SHIFT_RSTn

AON CAL reset control

enumerator kAonQTMR0_RST_SHIFT_RSTn

AON QTMR0 reset control

enumerator kAonLPTMR_RST_SHIFT_RSTn

AON LPTMR reset control

enumerator kAonKPP_RST_SHIFT_RSTn

AON KPP reset control

enumerator kAonLPADC_RST_SHIFT_RSTn

AON LPADC reset control

enumerator kAonLCD_RST_SHIFT_RSTn

AON LCD reset control

enumerator kAonSecurity_RST_SHIFT_RSTn

AON Security reset control

enumerator kAonADVC2P0_RST_SHIFT_RSTn

AON ADVC2P0 reset control

enumerator NotAvail_RSTn

No reset control

typedef enum _SYSCON_RSTn SYSCON_RSTn_t

Enumeration for peripheral reset control bits.

Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers

typedef SYSCON_RSTn_t reset_ip_name_t

void RESET_SetPeripheralReset(reset_ip_name_t peripheral)

Assert reset to peripheral.

Asserts reset signal to specified peripheral module.

Parameters:

• peripheral – Assert reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)

Clear reset to peripheral.

Clears reset signal to specified peripheral module, allows it to operate.

Parameters:

• peripheral – Clear reset to this peripheral. The enum argument contains encoding of reset register and reset bit position in the reset register.

void RESET_PeripheralReset(reset_ip_name_t peripheral)

Reset peripheral module.

Reset peripheral module.

Parameters:

• peripheral – Peripheral to reset. The enum argument contains encoding of reset register and reset bit position in the reset register.

static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral)

Release peripheral module.

Release peripheral module.

Parameters:

• peripheral – Peripheral to release. The enum argument contains encoding of reset register and reset bit position in the reset register.

FSL_RESET_DRIVER_VERSION

reset driver version 2.6.0

LPUART_RSTS

LPI2C_RSTS

TMR_RSTS

PORT_RSTS_N

PORT_RSTS_N

GPIO_RSTS_N

GPIO_RSTS_N

AON_LPADC_RSTS

ROMAPI Driver

enum _flash_property_tag

Enumeration for various flash properties.

Values:

enumerator kFLASH_PropertyPflashSectorSize

Pflash sector size property.

enumerator kFLASH_PropertyPflashTotalSize

Pflash total size property.

enumerator kFLASH_PropertyPflashBlockSize

Pflash block size property.

enumerator kFLASH_PropertyPflashBlockCount

Pflash block count property.

enumerator kFLASH_PropertyPflashBlockBaseAddr

Pflash block base address property.

enumerator kFLASH_PropertyPflashPageSize

Pflash page size property.

enumerator kFLASH_PropertyPflashSystemFreq

System Frequency property.

enumerator kFLASH_PropertyFfrSectorSize

FFR sector size property.

enumerator kFLASH_PropertyFfrTotalSize

FFR total size property.

enumerator kFLASH_PropertyFfrBlockBaseAddr

FFR block base address property.

enumerator kFLASH_PropertyFfrPageSize

FFR page size property.

enum _flash_driver_api_keys

Enumeration for Flash driver API keys.

Note

The resulting value is built with a byte order such that the string being readable in expected order when viewed in a hex editor, if the value is treated as a 32-bit little endian value.

Values:

enumerator kFLASH_ApiEraseKey

Key value used to validate all flash erase APIs.

typedef enum _flash_property_tag flash_property_tag_t

Enumeration for various flash properties.

typedef struct _flash_ffr_config flash_ffr_config_t

Flash controller paramter config.

typedef struct _flash_config flash_config_t

Flash driver state information.

An instance of this structure is allocated by the user of the flash driver and passed into each of the driver APIs.

typedef union StandardVersion standard_version_t

Structure of version property.

typedef struct _flash_driver_interface flash_driver_interface_t

Interface for the flash driver.

typedef struct _bootloader_tree bootloader_tree_t

Root of the bootloader API tree.

An instance of this struct resides in read-only memory in the bootloader. It provides a user application access to APIs exported by the bootloader.

FSL_ROMAPI_DRIVER_VERSION

romapi driver version 2.0.1.

FOUR_CHAR_CODE(a, b, c, d)

Constructs the four character code for the Flash driver API key.

ROM_API_BASE

ROM API base address

ROM_API

ROM API base pointer

FLASH_API

FLASH API base pointer

static inline status_t FLASH_Init(flash_config_t *config)

Initializes the global flash properties structure members.

This function checks and initializes the Flash module for the other Flash APIs.

Parameters:

• config – Pointer to the storage for the driver runtime state.

static inline status_t FLASH_EraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)

Erases the flash sectors encompassed by parameters passed into function.

This function erases the appropriate number of flash sectors based on the desired start address and length.

Parameters:

• config – The pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be erased. NOTE: The start address need to be 4 Bytes-aligned.

• lengthInBytes – The length, given in bytes need be 4 Bytes-aligned.

• key – The value used to validate all flash erase APIs.

static inline status_t FLASH_ProgramPhrase(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)

Programs flash phrases with data at locations passed in through parameters.

This function programs the flash memory with the desired data for a given flash area as determined by the start address and the length.

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be programmed. Must be word-aligned.

• src – A pointer to the source buffer of data that is to be programmed into the flash.

• lengthInBytes – The length, given in bytes (not words or long-words), to be programmed. Must be word-aligned.

static inline status_t FLASH_ProgramPage(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)

Programs flash page with data at locations passed in through parameters.

This function programs the flash memory with the desired data for a given flash area as determined by the start address and the length.

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be programmed. Must be word-aligned.

• src – A pointer to the source buffer of data that is to be programmed into the flash.

• lengthInBytes – The length, given in bytes (not words or long-words), to be programmed. Must be word-aligned.

static inline status_t FLASH_VerifyProgram(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, const uint8_t *expectedData, uint32_t *failedAddress, uint32_t *failedData)

Verifies programming of the desired flash area.

This function verifies the data programed in the flash memory using the Flash Program Check Command and compares it to the expected data for a given flash area as determined by the start address and length.

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be verified. Must be word-aligned.

• lengthInBytes – The length, given in bytes (not words or long-words), to be verified. Must be word-aligned.

• expectedData – A pointer to the expected data that is to be verified against.

• failedAddress – A pointer to the returned failing address.

• failedData – A pointer to the returned failing data. Some derivatives do not include failed data as part of the FCCOBx registers. In this case, zeros are returned upon failure.

static inline status_t FLASH_VerifyErasePhrase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)

Verify that the flash phrases are erased.

This function checks the appropriate number of flash sectors based on the desired start address and length to check whether the flash is erased

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be verified. The start address does not need to be sector-aligned but must be word-aligned.

• lengthInBytes – The length, given in bytes (not words or long-words), to be verified. Must be word-aligned.

static inline status_t FLASH_VerifyErasePage(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)

Verify that the flash pages are erased.

This function checks the appropriate number of flash sectors based on the desired start address and length to check whether the flash is erased

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be verified. The start address does not need to be sector-aligned but must be word-aligned.

• lengthInBytes – The length, given in bytes (not words or long-words), to be verified. Must be word-aligned.

static inline status_t FLASH_VerifyEraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)

Verify that the flash sectors are erased.

This function checks the appropriate number of flash sectors based on the desired start address and length to check whether the flash is erased

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be verified. The start address does not need to be sector-aligned but must be word-aligned.

• lengthInBytes – The length, given in bytes (not words or long-words), to be verified. Must be word-aligned.

static inline status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)

Returns the desired flash property.

Parameters:

• config – A pointer to the storage for the driver runtime state.

• whichProperty – The desired property from the list of properties in enum flash_property_tag_t

• value – A pointer to the value returned for the desired flash property.

static inline status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes)

Reads flash at locations passed in through parameters.

This function read the flash memory from a given flash area as determined by the start address and the length.

Parameters:

• config – A pointer to the storage for the driver runtime state.

• start – The start address of the desired flash memory to be read.

• dest – A pointer to the dest buffer of data that is to be read from the flash.

• lengthInBytes – The length, given in bytes (not words or long-words), to be read.

static inline uint32_t ROMAPI_GetVersion(void)

Get ROM API version.

This function read the ROM API version.

static inline void ROMAPI_RunBootloader(void *arg)

Run the Bootloader API to force into the ISP mode base on the user arg.

Parameters:

• arg – Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure

uint32_t ffrBlockBase

uint32_t ffrTotalSize

uint32_t ffrPageSize

uint32_t sectorSize

uint32_t cfpaPageVersion

uint32_t cfpaPageOffset

uint32_t PFlashBlockBase

A base address of the first PFlash block

uint32_t PFlashTotalSize

The size of the combined PFlash block.

uint32_t PFlashBlockCount

A number of PFlash blocks.

uint32_t PFlashPageSize

The size in bytes of a page of PFlash.

uint32_t PFlashSectorSize

The size in bytes of a sector of PFlash.

flash_ffr_config_t ffrConfig

uint8_t bugfix

bugfix version [7:0]

uint8_t minor

minor version [15:8]

uint8_t major

major version [23:16]

char name

name [31:24]

struct StandardVersion

uint32_t version

combined version numbers

status_t (*flash_init)(flash_config_t *config)

status_t (*flash_erase_sector)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)

status_t (*flash_program_phrase)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)

status_t (*flash_program_page)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)

status_t (*flash_verify_program)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, const uint8_t *expectedData, uint32_t *failedAddress, uint32_t *failedData)

status_t (*flash_verify_erase_phrase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)

status_t (*flash_verify_erase_page)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)

status_t (*flash_verify_erase_sector)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)

status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)

status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes)

standard_version_t version

uint32_t reserved

uint32_t boot_image_index

uint32_t instance

uint32_t boot_interface

uint32_t mode

uint32_t tag

struct user_app_boot_invoke_option_t B

uint32_t U

union user_app_boot_invoke_option_t option

void (*run_bootloader)(void *arg)

Function to start the bootloader executing.

const flash_driver_interface_t *flash_driver

Internal Flash driver API.

void (*jump)(void *arg)

FSL_COMPONENT_ID

struct _flash_ffr_config

#include <fsl_romapi.h>

Flash controller paramter config.

struct _flash_config

#include <fsl_romapi.h>

Flash driver state information.

An instance of this structure is allocated by the user of the flash driver and passed into each of the driver APIs.

union StandardVersion

#include <fsl_romapi.h>

Structure of version property.

struct _flash_driver_interface

#include <fsl_romapi.h>

Interface for the flash driver.

struct user_app_boot_invoke_option_t

struct _bootloader_tree

#include <fsl_romapi.h>

Root of the bootloader API tree.

An instance of this struct resides in read-only memory in the bootloader. It provides a user application access to APIs exported by the bootloader.

struct __unnamed1__

Public Members

uint8_t bugfix

bugfix version [7:0]

uint8_t minor

minor version [15:8]

uint8_t major

major version [23:16]

char name

name [31:24]

union option

Public Members

struct user_app_boot_invoke_option_t B

uint32_t U

struct B

RTC: Real Time Clock

void RTC_GetDefaultConfig(rtc_config_t *config)

Fills the RTC configuration structure with default values.

The default values are chosen for safe and common startup behavior. For example:

config->operatingMode                               = kRTC_ModeTimeDate;
config->enableXtal32                                = true;
config->enable2kHzOutputSMM                         = false;
config->alarmInitialEnable[0]                       = false;
config->alarmInitialEnable[1]                       = false;
config->alarmInitialEnable[2]                       = false;
config->enableWatchdog                              = false;
config->watchdogTimeoutValue                        = 0U;
config->tamperConfig.enableGlobalTamper             = false;
config->tamperConfig.tamperInputConfig[0].enableTamperInput = false;
config->tamperConfig.tamperInputConfig[0].polarity = kRTC_TamperPolarityLow;
config->tamperConfig.tamperInputConfig[0].pullup = kRTC_TamperPullupDisabled;
config->tamperConfig.tamperInputConfig[0].filter = kRTC_TamperFilterDisabled;
config->tamperConfig.tamperInputConfig[1].enableTamperInput = false;
config->tamperConfig.tamperInputConfig[1].polarity = kRTC_TamperPolarityLow;
config->tamperConfig.tamperInputConfig[1].pullup = kRTC_TamperPullupDisabled;
config->tamperConfig.tamperInputConfig[1].filter = kRTC_TamperFilterDisabled;
config->aliveDetectorConfig.enableAliveDetector     = false;
config->aliveDetectorConfig.bypassAnalogAliveMechanism = false;
config->aliveDetectorConfig.mechanismPeriod          = 0U;

This function should be called before RTC_Init() if custom configuration is not fully provided.

Parameters:

• config – Pointer to the rtc_config_t structure to be filled.

status_t RTC_Init(RTC_Type *base, const rtc_config_t *config)

Initializes the RTC peripheral.

This function configures the RTC module according to the settings provided in the config structure. It setups initial operating mode, watchdog, tamper detection, and alive detector.

Parameters:

• base – RTC peripheral base address.

• config – Pointer to the user-defined rtc_config_t structure.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready,

status_t RTC_Deinit(RTC_Type *base)

De-initializes the RTC peripheral.

This function resets RTC registers to a default state and stops the RTC.

Parameters:

• base – RTC peripheral base address.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_StartTimer(RTC_Type *base)

Starts the RTC time counter.

Parameters:

• base – RTC peripheral base address

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_StopTimer(RTC_Type *base)

Stops the RTC time counter.

Parameters:

• base – RTC peripheral base address

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)

Sets the current RTC date and time.

Validates the provided date and time before setting. If the input is invalid, an error status is returned.

Parameters:

• base – RTC peripheral base address.

• datetime – Pointer to the rtc_datetime_t structure containing the new date and time.

Returns:

kStatus_Success if the operation was successful, kStatus_Fail if RTC is not working in time date mode, kStatus_InvalidArgument if the input was invalid, kStatus_Timeout if the interface is not ready.

status_t RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)

Retrieves the current RTC date and time.

Parameters:

• base – RTC peripheral base address.

• datetime – Pointer to the rtc_datetime_t structure to store the current date and time.

Returns:

kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in time/date mode, kStatus_Fail if a read collision occurred, kStatus_Timeout if the interface is not ready.

status_t RTC_SetFreeRunningCounter(RTC_Type *base, uint64_t countValue)

Sets the initial value of the RTC free-running counter.

This function is applicable only when the RTC is in Free-Running Counter mode.

Parameters:

• base – RTC peripheral base address.

• countValue – The initial value to set for the counter.

Returns:

kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, or kStatus_Timeout if the interface is not ready.

status_t RTC_GetFreeRunningCounter(RTC_Type *base, uint64_t *countValue)

Retrieves the current value of the RTC free-running counter.

This function is applicable only when the RTC is in Free-Running Counter mode.

Parameters:

• base – RTC peripheral base address.

• countValue – Pointer to a variable to store the current counter value.

Returns:

kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in free-running mode, or kStatus_Fail if a read collision occurred, kStatus_Timeout if the interface is not ready.

status_t RTC_ConfigureBCDAlarm(RTC_Type *base, rtc_alarm_id_t alarmId, const rtc_bcd_alarm_config_t *alarmConfig)

Configures a specific RTC BCD alarm.

Sets the alarm time, date, mask, mode, and initial enable state. The number of alarms is MCU-dependent (e.g., 3 alarms: Alarm0, Alarm1, Alarm2).

Parameters:

• base – RTC peripheral base address.

• alarmId – The ID of the alarm to configure (e.g., kRTC_Alarm_0).

• alarmConfig – Pointer to the rtc_bcd_alarm_config_t structure with alarm settings.

Returns:

kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, or kStatus_Timeout if the interface is not ready.

status_t RTC_ConfigureFreeRunningAlarm(RTC_Type *base, rtc_alarm_id_t alarmId, const rtc_free_run_alarm_config_t *alarmConfig)

Configures a specific RTC free running mode alarm.

Select the alarm id and set the alarm counter value

Parameters:

• base – RTC peripheral base address.

• alarmId – The ID of the alarm to configure (e.g., kRTC_Alarm_0).

• alarmConfig – Pointer to the rtc_free_run_alarm_config_t structure with alarm settings.

Returns:

kStatus_Success if the operation was successful, kStatus_InvalidArgument if the input was invalid, or kStatus_Timeout if the interface is not ready.

status_t RTC_EnableAlarm(RTC_Type *base, rtc_alarm_id_t alarmId)

Enables a specific RTC alarm.

Parameters:

• base – RTC peripheral base address.

• alarmId – The ID of the alarm to enable.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_DisableAlarm(RTC_Type *base, rtc_alarm_id_t alarmId)

Disables a specific RTC alarm.

Parameters:

• base – RTC peripheral base address.

• alarmId – The ID of the alarm to disable.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)

Enables specified RTC interrupt sources.

Parameters:

• base – RTC peripheral base address.

• mask – Bitmask of interrupts to enable (see rtc_interrupt_enable_t).

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)

Disables specified RTC interrupt sources.

Parameters:

• base – RTC peripheral base address.

• mask – Bitmask of interrupts to disable (see rtc_interrupt_enable_t).

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)

Gets the enabled RTC interrupts.

Parameters:

• base – RTC peripheral base address

Returns:

enabled interrupts bitmask.

static inline uint32_t RTC_GetInterruptFlags(RTC_Type *base)

Get the RTC interrupt flags.

Parameters:

• base – RTC peripheral base address

Returns:

Occured interrupt flags bitmask.

status_t RTC_ClearInterruptFlags(RTC_Type *base, uint32_t mask)

Clears the RTC interrupt flags.

Parameters:

• base – RTC peripheral base address

• mask – The interrupt flags to clear. This is a logical OR of members of the enumeration rtc_status_flags_t

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

void RTC_RegisterCallBack(rtc_callback_t cb_func)

Register callback.

Parameters:

• cb_func – callback function

status_t RTC_EnableWatchdog(RTC_Type *base)

Enables the RTC Watchdog Timer. Assumes timeout is already configured via RTC_Init or RTC_SetWatchdogTimeout.

Parameters:

• base – RTC peripheral base address.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_DisableWatchdog(RTC_Type *base)

Disables the RTC Watchdog Timer.

Parameters:

• base – RTC peripheral base address.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_SetWatchdogTimeout(RTC_Type *base, uint32_t timeoutValue)

Sets the timeout value for the RTC Watchdog Timer.

Parameters:

• base – RTC peripheral base address.

• timeoutValue – The desired timeout value.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_RefreshWatchdog(RTC_Type *base)

Refreshes the RTC Watchdog Timer.

Parameters:

• base – RTC peripheral base address. return kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_ConfigureTamperInput(RTC_Type *base, rtc_tamper_input_id_t tamperInputId, const rtc_tamper_input_config_t *config)

Configures a specific tamper detection input.

This function sets up the tamper input configuration, including enabling/disabling the input, setting polarity, pullup and filters.

Parameters:

• base – RTC peripheral base address.

• config – Pointer to the rtc_tamper_config_t structure containing tamper input settings. This structure defines the behavior of the tamper input, such as polarity, pull-up configuration, and filtering.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_EnableTamperInputPin(RTC_Type *base, rtc_tamper_input_id_t tamperInputId)

Enables the specific tamper detection input pin.

Parameters:

• base – RTC peripheral base address.

• tamperInputId – Bitmask of tamper inputs to enable.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_DisableTamperInputPin(RTC_Type *base, rtc_tamper_input_id_t tamperInputId)

Disable the specific tamper detection input pin.

Parameters:

• base – RTC peripheral base address.

• tamperInputId – Bitmask of tamper inputs to disable.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_GetTamperTimestamp(RTC_Type *base, uint64_t *latchedCount)

Gets the latched RTC counter value at the time of the last tamper event.

Parameters:

• base – RTC peripheral base address.

• latchedCount – Pointer to a variable where the latched counter value will be stored.

Returns:

kStatus_Success if the operation was successful, kStatus_InvalidArgument if not in tamper mode,

status_t RTC_WriteKey(RTC_Type *base, const uint32_t *keyData)

Writes a key to the RTC’s non-volatile storage.

Parameters:

• base – RTC peripheral base address.

• keyData – Pointer to the key data to be written.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_ReadKey(RTC_Type *base, uint32_t *keyBuffer)

Reads a key from the RTC’s non-volatile storage.

Parameters:

• base – RTC peripheral base address.

• keyBuffer – Pointer to a buffer where the key data will be stored.

Returns:

kStatus_Success if the operation was successful, kStatus_Fail if SECURE_KEY_READY is not set.

status_t RTC_ConfigureAliveDetector(RTC_Type *base, const rtc_alive_detector_config_t *config)

Enables the RTC alive detector.

Parameters:

• base – RTC peripheral base address.

• config – Pointer to the rtc_alive_detector_config_t structure containing alive detector settings.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

FSL_RTC_DRIVER_VERSION

Version 2.0.1

RTC_SECURE_KEY_SIZE_BYTES

RTC_SECURE_KEY_REG_COUNT

RTC_MAX_TAMPER_INPUTS

enum _rtc_operating_mode

RTC operating modes.

Values:

enumerator kRTC_ModeTimeDate

RTC operates in Time/Date counting mode.

enumerator kRTC_ModeFreeRunningCounter

RTC operates as a free-running counter.

enum _rtc_alarm_id

RTC Alarm identifiers. Corresponds to Alarm 0, 1, 2.

Values:

enumerator kRTC_Alarm_0

Identifier for Alarm 0

enumerator kRTC_Alarm_1

Identifier for Alarm 1

enumerator kRTC_Alarm_2

Identifier for Alarm 2

enum _rtc_alarm_mode

RTC alarm operational modes.

Values:

enumerator kRTC_AlarmModeSingleShot

Alarm triggers once and then (typically) disables itself or requires re-arming.

enumerator kRTC_AlarmModeRepeat

Alarm triggers repeatedly based on its configuration (e.g., daily, weekly).

enum _rtc_alarm_mask_fields

RTC alarm mask fields. Used with rtc_bcd_alarm_config_t’s mask member. Set a bit to 1 to ignore the corresponding field for alarm matching.

Values:

enumerator kRTC_AlarmMaskIgnoreNothing

Match all fields specified in alarm time/date.

enumerator kRTC_AlarmMaskIgnoreSecond

Ignore seconds field for alarm match.

enumerator kRTC_AlarmMaskIgnoreMinute

Ignore minutes field for alarm match.

enumerator kRTC_AlarmMaskIgnoreHour

Ignore hours field for alarm match.

enumerator kRTC_AlarmMaskIgnoreDay

Ignore day of the month field for alarm match.

enumerator kRTC_AlarmMaskIgnoreDayOfWeek

Ignore day of the week field for alarm match.

enumerator kRTC_AlarmMaskIgnoreMonth

Ignore month field for alarm match.

enumerator kRTC_AlarmMaskIgnoreAll

Ignore all field for alarm match.

enum _rtc_tamper_input_id

RTC Tamper input identifiers. Corresponds to Tamper 0, 1.

Values:

enumerator kRTC_TamperInput0

Enable Tamper input 0.

enumerator kRTC_TamperInput1

Enable Tamper input 1.

enum _rtc_tamper_filter

RTC tamper input filter configuration.

Values:

enumerator kRTC_TamperFilterDisabled

Digital filter disabled for this tamper input.

enumerator kRTC_TamperFilterEnabled

Digital filter enabled for this tamper input.

enum _rtc_tamper_polarity

RTC tamper input trigger level.

Values:

enumerator kRTC_TamperPolarityLow

Tamper event triggered on a low level or falling edge.

enumerator kRTC_TamperPolarityHigh

Tamper event triggered on a high level or rising edge.

enum _rtc_tamper_pullup

RTC tamper input pull-up configuration.

Values:

enumerator kRTC_TamperPullupDisabled

No pull-up resistor enabled for this tamper input.

enumerator kRTC_TamperPullupEnabled

Pull-up resistor enabled for this tamper input.

enum _rtc_callback_type

Callback type identifiers for RTC events.

Values:

enumerator kRTC_Alarm0Callback

Alarm 0 interrupt callback type

enumerator kRTC_Alarm1Callback

Alarm 1 interrupt callback type

enumerator kRTC_Alarm2Callback

Alarm 2 interrupt callback type

enumerator kRTC_XtalFailCallback

XTAL Fail interrupt callback type

enumerator kRTC_WatchDogCallback

WatchDog timer timeout interrupt callback type

enumerator kRTC_Tamper0Callback

Tamper 0 detection interrupt callback type

enumerator kRTC_Tamper1Callback

Tamper 1 detection interrupt callback type

enum _rtc_interrupt_enable

RTC interrupt enable masks. Use bitwise OR to enable multiple interrupts.

Values:

enumerator kRTC_Alarm0InterruptEnable

Enable Alarm 0 interrupt.

enumerator kRTC_Alarm1InterruptEnable

Enable Alarm 1 interrupt.

enumerator kRTC_Alarm2InterruptEnable

Enable Alarm 2 interrupt.

enumerator kRTC_XtalFailInterruptEnable

Enable XTAL Fail interrupt.

enumerator kRTC_WatchdogInterruptEnable

Enable Watchdog timeout interrupt.

enumerator kRTC_Tamper0InterruptEnable

Enable Tamper 0 detection interrupt.

enumerator kRTC_Tamper1InterruptEnable

Enable Tamper 1 detection interrupt.

enumerator kRTC_AllInterruptsEnable

Enable all RTC interrupts.

enum _rtc_status_flags

RTC status flags. Use bitwise OR to check multiple flags.

Values:

enumerator kRTC_Alarm0InterruptFlag

Alarm 0 flag.

enumerator kRTC_Alarm1InterruptFlag

Alarm 1 flag.

enumerator kRTC_Alarm2InterruptFlag

Alarm 2 flag.

enumerator kRTC_XtalFailInterruptFlag

XTAL Fail flag.

enumerator kRTC_WatchdogInterruptFlag

Watchdog timeout flag.

enumerator kRTC_Tamper0InterruptFlag

Tamper 0 detection flag.

enumerator kRTC_Tamper1InterruptFlag

Tamper 1 detection flag.

enumerator kRTC_AllStatusFlags

Mask for all RTC status flags.

typedef enum _rtc_operating_mode rtc_operating_mode_t

RTC operating modes.

typedef struct _rtc_datetime rtc_datetime_t

RTC date and time structure.

typedef enum _rtc_alarm_id rtc_alarm_id_t

RTC Alarm identifiers. Corresponds to Alarm 0, 1, 2.

typedef enum _rtc_alarm_mode rtc_alarm_mode_t

RTC alarm operational modes.

typedef enum _rtc_alarm_mask_fields rtc_alarm_mask_fields_t

RTC alarm mask fields. Used with rtc_bcd_alarm_config_t’s mask member. Set a bit to 1 to ignore the corresponding field for alarm matching.

typedef struct _rtc_alarm_config rtc_bcd_alarm_config_t

RTC bcd alarm configuration structure.

typedef struct _rtc_free_run_alarm_config rtc_free_run_alarm_config_t

RTC free run mode alarm

typedef enum _rtc_tamper_input_id rtc_tamper_input_id_t

RTC Tamper input identifiers. Corresponds to Tamper 0, 1.

typedef enum _rtc_tamper_filter rtc_tamper_filter_t

RTC tamper input filter configuration.

typedef enum _rtc_tamper_polarity rtc_tamper_polarity_t

RTC tamper input trigger level.

typedef enum _rtc_tamper_pullup rtc_tamper_pullup_t

RTC tamper input pull-up configuration.

typedef struct _rtc_tamper_input_config rtc_tamper_input_config_t

RTC tamper input configuration structure.

typedef struct _rtc_tamper_config rtc_tamper_config_t

RTC global tamper detection configuration structure.

typedef struct _rtc_alive_detector_config rtc_alive_detector_config_t

RTC alive detector configuration structure.

typedef struct _rtc_config rtc_config_t

RTC general configuration structure.

typedef enum _rtc_callback_type rtc_callback_type_t

Callback type identifiers for RTC events.

typedef enum _rtc_interrupt_enable rtc_interrupt_enable_t

RTC interrupt enable masks. Use bitwise OR to enable multiple interrupts.

typedef enum _rtc_status_flags rtc_status_flags_t

RTC status flags. Use bitwise OR to check multiple flags.

typedef void (*rtc_callback_t)(rtc_callback_type_t type)

RTC callback function pointer type.

status_t RTC_EnableAliveDetector(RTC_Type *base)

Alive detector enable.

Parameters:

• base – RTC peripheral base address.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

status_t RTC_DisableAliveDetector(RTC_Type *base)

Alive detector disable.

Parameters:

• base – RTC peripheral base address.

Returns:

kStatus_Success if the operation was successful, kStatus_Timeout if the interface is not ready.

RTC_WAIT_INTERFACE_READY_TIMEOUT

RTC wait inteface ready timeout

RTC_WAIT_READ_COUNTER_LATCHED_READY

RTC wait read counter latched timeout

RTC_WAIT_SECURE_KEY_READY_TIMEOUT

RTC wait secure key ready timeout

struct _rtc_datetime

#include <fsl_rtc.h>

RTC date and time structure.

Public Members

uint16_t year

Year (e.g., 2023)

uint8_t month

Month (1-12)

uint8_t day

Day of the month (1-31)

uint8_t hour

Hour (0-23)

uint8_t minute

Minute (0-59)

uint8_t second

Second (0-59)

uint8_t hundredthOfSecond

Hundredth of a second (0-99)

uint8_t dayOfWeek

Day of the week (e.g., 0 for Sunday, 1 for Monday, etc.)

struct _rtc_alarm_config

#include <fsl_rtc.h>

RTC bcd alarm configuration structure.

Public Members

uint8_t hour

Alarm hour (0-23). Relevant if not masked.

uint8_t minute

Alarm minute (0-59). Relevant if not masked.

uint8_t second

Alarm second (0-59). Relevant if not masked.

uint8_t hundredthOfSecond

Alarm hundredth of second (0-99).

uint8_t day

Alarm day of the month (1-31). Relevant if not masked.

uint8_t dayOfWeek

Alarm day of the week. Sunday is 0, Monday is 1. Relevant if not masked.

uint8_t month

Alarm month (1-12). Relevant if not masked.

uint8_t mask

Alarm mask, it a logical OR of members of the enumeration rtc_alarm_mask_fields_t.

rtc_alarm_mode_t mode

Alarm mode: kRTC_AlarmModeSingleShot or kRTC_AlarmModeRepeat.

bool enable

Initial enable state for this alarm when configured. True to enable, false to disable.

struct _rtc_free_run_alarm_config

#include <fsl_rtc.h>

RTC free run mode alarm

Public Members

uint64_t alarmCounter

Alarm counter value.

rtc_alarm_mode_t mode

Alarm mode: kRTC_AlarmModeSingleShot or kRTC_AlarmModeRepeat.

bool enable

Initial enable state for this alarm when configured. True to enable, false to disable.

struct _rtc_tamper_input_config

#include <fsl_rtc.h>

RTC tamper input configuration structure.

Public Members

bool enableTamperInput

True to enable this tamper input, false to disable. (Maps to TAMP_CTRL[TAMP_EN] bit)

rtc_tamper_polarity_t polarity

Trigger level for this tamper input.

rtc_tamper_pullup_t pullup

Pull-up configuration for this tamper input.

rtc_tamper_filter_t filter

Digital filter configuration for this tamper input.

struct _rtc_tamper_config

#include <fsl_rtc.h>

RTC global tamper detection configuration structure.

Public Members

bool enableGlobalTamper

Master enable for the tamper detection sub-module.

rtc_tamper_input_config_t tamperInputConfig[2]

Configuration for the tamper input pins. This structure is used to configure each tamper input pin’s behavior, such as trigger level, pull-up, and filtering.

struct _rtc_alive_detector_config

#include <fsl_rtc.h>

RTC alive detector configuration structure.

Public Members

bool enableAliveDetector

True to enable the RTC alive detector, false to disable.

bool bypassAnalogAliveMechanism

Bypass the RTC analog alive mechanism, implemented at the PAC. After de-activation of the SMM reset this value is sample back value from PAC.

uint8_t mechanismPeriod

Define the length of the active period of the Alive Detector Mechanism in 2KHz clock cycles

struct _rtc_config

#include <fsl_rtc.h>

RTC general configuration structure.

Public Members

rtc_operating_mode_t operatingMode

RTC operating mode: Time/Date or Free-Running Counter.

bool enableXtal32

Enable/disable the 32kHz crystal oscillator circuitry. True to enable.

bool enable2kHzOutputSMM

Enable/disable 2kHz output towards SMM. True to enable.

bool alarmInitialEnable[3]

Initial enable state for Alarm 0, 1, 2. True to enable.

bool enableWatchdog

Initial enable state for the Watchdog Timer. True to enable.

uint32_t watchdogTimeoutValue

Watchdog Timer timeout value (units are MCU specific, e.g., seconds or RTC clock cycles).

rtc_tamper_config_t tamperConfig

Tamper detection configuration.

rtc_alive_detector_config_t aliveDetectorConfig

RTC alive detector configuration.

SLCD: Segment LCD Driver

void SLCD_Init(SLCD_Type *base, const slcd_config_t *configure)

Initializes the SLCD, ungates the module clock, initializes the power setting, enables all used plane pins, and sets with interrupt and work mode with the configuration.

Parameters:

• base – SLCD peripheral base address.

• configure – SLCD configuration pointer. For the configuration structure, many parameters have the default setting and the SGLCD_Getdefaultconfig() is provided to get them. Use it verified for their applications. The others have no default settings, such as “clkConfig”, and must be provided by the application before calling the SGLCD_Init() API.

void SLCD_Deinit(SLCD_Type *base)

Deinitializes the SLCD module, gates the module clock, disables an interrupt, and displays the SLCD.

Parameters:

• base – SLCD peripheral base address.

void SLCD_GetDefaultConfig(slcd_config_t *configure)

Gets the SLCD default configuration structure. The purpose of this API is to get default parameters of the configuration structure for the SGLCD_Init(). Use these initialized parameters unchanged in SGLCD_Init() or modify fields of the structure before the calling SGLCD_Init(). All default parameters of the configure structuration are listed.

config.displayMode        = kSLCD_NormalMode;
config.powerSupply        = kSLCD_InternalVll3UseChargePump;
config.voltageTrim        = kSLCD_RegulatedVolatgeTrim00;
config.lowPowerBehavior   = kSLCD_EnabledInWaitStop;
config.interruptSrc       = 0;
config.faultConfig        = NULL;
config.frameFreqIntEnable =  false;

Parameters:

• configure – The SLCD configuration structure pointer.

static inline void SLCD_StartDisplay(SLCD_Type *base)

Enables the SLCD controller, starts generation, and displays the front plane and back plane waveform.

Parameters:

• base – SLCD peripheral base address.

static inline void SLCD_StopDisplay(SLCD_Type *base)

Stops the SLCD controller. There is no waveform generator and all enabled pins only output a low value.

Parameters:

• base – SLCD peripheral base address.

void SLCD_StartBlinkMode(SLCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate)

Starts the SLCD blink mode.

Parameters:

• base – SLCD peripheral base address.

• mode – SLCD blink mode.

• rate – SLCD blink rate.

static inline void SLCD_StopBlinkMode(SLCD_Type *base)

Stops the SLCD blink mode.

Parameters:

• base – SLCD peripheral base address.

static inline void SLCD_SetBackPlanePhase(SLCD_Type *base, uint32_t pinIndx, slcd_phase_type_t phase)

Sets the SLCD back plane pin phase.

This function sets the SLCD back plane pin phase. “kSLCD_PhaseXActivate” setting means the phase X is active for the back plane pin. “kSLCD_NoPhaseActivate” setting means there is no phase active for the back plane pin. For example, set the back plane pin 20 for phase A.

SLCD_SetBackPlanePhase(LCD, 20, kSLCD_PhaseAActivate);

Parameters:

• base – SLCD peripheral base address.

• pinIndx – SLCD back plane pin index. Range from 0 to 63.

• phase – The phase activates for the back plane pin.

static inline void SLCD_SetFrontPlaneSegments(SLCD_Type *base, uint32_t pinIndx, uint8_t operation)

Sets the SLCD front plane segment operation for a front plane pin.

This function sets the SLCD front plane segment on or off operation. Each bit turns on or off the segments associated with the front plane pin in the following pattern: HGFEDCBA (most significant bit controls segment H and least significant bit controls segment A). For example, turn on the front plane pin 20 for phase B and phase C.

SLCD_SetFrontPlaneSegments(LCD, 20, (kSLCD_PhaseBActivate | kSLCD_PhaseCActivate));

Parameters:

• base – SLCD peripheral base address.

• pinIndx – SLCD back plane pin index. Range from 0 to 63.

• operation – The operation for the segment on the front plane pin. This is a logical OR of the enumeration :: slcd_phase_type_t.

static inline void SLCD_SetFrontPlaneOnePhase(SLCD_Type *base, uint32_t pinIndx, slcd_phase_index_t phaseIndx, bool enable)

Sets one SLCD front plane pin for one phase.

This function can be used to set one phase on or off for the front plane pin. It can be call many times to set the plane pin for different phase indexes. For example, turn on the front plane pin 20 for phase B and phase C.

SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseBIndex, true);
SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseCIndex, true);

Parameters:

• base – SLCD peripheral base address.

• pinIndx – SLCD back plane pin index. Range from 0 to 63.

• phaseIndx – The phase bit index slcd_phase_index_t.

• enable – True to turn on the segment for phaseIndx phase false to turn off the segment for phaseIndx phase.

static inline uint32_t SLCD_GetFaultDetectCounter(SLCD_Type *base)

Gets the SLCD fault detect counter.

This function gets the number of samples inside the fault detection sample window.

Parameters:

• base – SLCD peripheral base address.

Returns:

The fault detect counter. The maximum return value is 255. If the maximum 255 returns, the overflow may happen. Reconfigure the fault detect sample window and fault detect clock prescaler for proper sampling.

void SLCD_EnableInterrupts(SLCD_Type *base, uint32_t mask)

Enables the SLCD interrupt. For example, to enable fault detect complete interrupt and frame frequency interrupt, do the following.

SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);

Parameters:

• base – SLCD peripheral base address.

• mask – SLCD interrupts to enable. This is a logical OR of the enumeration :: slcd_interrupt_enable_t.

void SLCD_DisableInterrupts(SLCD_Type *base, uint32_t mask)

Disables the SLCD interrupt. For example, to disable fault detect complete interrupt and frame frequency interrupt, do the following.

SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);

Parameters:

• base – SLCD peripheral base address.

• mask – SLCD interrupts to disable. This is a logical OR of the enumeration :: slcd_interrupt_enable_t.

uint32_t SLCD_GetInterruptStatus(SLCD_Type *base)

Gets the SLCD interrupt status flag.

Parameters:

• base – SLCD peripheral base address.

Returns:

The event status of the interrupt source. This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.

void SLCD_ClearInterruptStatus(SLCD_Type *base, uint32_t mask)

Clears the SLCD interrupt events status flag.

Parameters:

• base – SLCD peripheral base address.

• mask – SLCD interrupt source to be cleared. This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.

FSL_SLCD_DRIVER_VERSION

SLCD driver version.

enum _slcd_clock_prescaler

SLCD clock prescaler to generate frame frequency.

Values:

enumerator kSLCD_ClkPrescaler00

Prescaler 0.

enumerator kSLCD_ClkPrescaler01

Prescaler 1.

enumerator kSLCD_ClkPrescaler02

Prescaler 2.

enumerator kSLCD_ClkPrescaler03

Prescaler 3.

enumerator kSLCD_ClkPrescaler04

Prescaler 4.

enumerator kSLCD_ClkPrescaler05

Prescaler 5.

enumerator kSLCD_ClkPrescaler06

Prescaler 6.

enumerator kSLCD_ClkPrescaler07

Prescaler 7.

enum _slcd_regulated_voltage_trim

SLCD regulated voltage trim parameter, be used to meet the desired contrast.

Values:

enumerator kSLCD_VolatgeTrimNo

No voltage trim.

enumerator kSLCD_VolatgeTrimIncrease50mV

Increase the voltage by 50 mV.

enumerator kSLCD_VolatgeTrimIncrease100mV

Increase the voltage by 100 mV.

enumerator kSLCD_VolatgeTrimIncrease150mV

Increase the voltage by 150 mV.

enumerator kSLCD_VolatgeTrimIncrease200mV

Increase the voltage by 200 mV.

enumerator kSLCD_VolatgeTrimIncrease250mV

Increase the voltage by 250 mV.

enumerator kSLCD_VolatgeTrimIncrease300mV

Increase the voltage by 300 mV.

enumerator kSLCD_VolatgeTrimIncrease350mV

Increase the voltage by 350 mV.

enumerator kSLCD_VolatgeTrimDecrease400mV

Decrease the voltage by 400 mV.

enumerator kSLCD_VolatgeTrimDecrease350mV

Decrease the voltage by 350 mV.

enumerator kSLCD_VolatgeTrimDecrease300mV

Decrease the voltage by 300 mV.

enumerator kSLCD_VolatgeTrimDecrease250mV

Decrease the voltage by 250 mV.

enumerator kSLCD_VolatgeTrimDecrease200mV

Decrease the voltage by 200 mV.

enumerator kSLCD_VolatgeTrimDecrease150mV

Decrease the voltage by 150 mV.

enumerator kSLCD_VolatgeTrimDecrease100mV

Decrease the voltage by 100 mV.

enumerator kSLCD_VolatgeTrimDecrease50mV

Decrease the voltage by 50 mV.

enum _slcd_sample_hold

SLCD sample&hold configuration. To save power, configure the voltage to be sampled and held periodically, during this period the phase switches are turned off.

Values:

enumerator kSLCD_SampleHoldNone

No sample&hold.

enumerator kSLCD_SampleHold64Cycle

Sample&hold each 64 function clock cycle.

enumerator kSLCD_SampleHold128Cycle

Sample&hold each 128 function clock cycle.

enum _slcd_blink_rate

SLCD blink rate.

Values:

enumerator kSLCD_BlinkRate00

SLCD blink rate is LCD clock/((2^11)).

enumerator kSLCD_BlinkRate01

SLCD blink rate is LCD clock/((2^12)).

enumerator kSLCD_BlinkRate02

SLCD blink rate is LCD clock/((2^13)).

enumerator kSLCD_BlinkRate03

SLCD blink rate is LCD clock/((2^14)).

enumerator kSLCD_BlinkRate04

SLCD blink rate is LCD clock/((2^15)).

enumerator kSLCD_BlinkRate05

SLCD blink rate is LCD clock/((2^16)).

enumerator kSLCD_BlinkRate06

SLCD blink rate is LCD clock/((2^17)).

enumerator kSLCD_BlinkRate07

SLCD blink rate is LCD clock/((2^18)).

enum _slcd_duty_cycle

SLCD duty cycle.

Values:

enumerator kSLCD_1Div1DutyCycle

LCD use 1 BP 1/1 duty cycle.

enumerator kSLCD_1Div2DutyCycle

LCD use 2 BP 1/2 duty cycle.

enumerator kSLCD_1Div3DutyCycle

LCD use 3 BP 1/3 duty cycle.

enumerator kSLCD_1Div4DutyCycle

LCD use 4 BP 1/4 duty cycle.

enumerator kSLCD_1Div5DutyCycle

LCD use 5 BP 1/5 duty cycle.

enumerator kSLCD_1Div6DutyCycle

LCD use 6 BP 1/6 duty cycle.

enumerator kSLCD_1Div7DutyCycle

LCD use 7 BP 1/7 duty cycle.

enumerator kSLCD_1Div8DutyCycle

LCD use 8 BP 1/8 duty cycle.

enum _slcd_phase_type

SLCD segment phase type.

Values:

enumerator kSLCD_NoPhaseActivate

LCD wareform no phase activates.

enumerator kSLCD_PhaseAActivate

LCD waveform phase A activates.

enumerator kSLCD_PhaseBActivate

LCD waveform phase B activates.

enumerator kSLCD_PhaseCActivate

LCD waveform phase C activates.

enumerator kSLCD_PhaseDActivate

LCD waveform phase D activates.

enumerator kSLCD_PhaseEActivate

LCD waveform phase E activates.

enumerator kSLCD_PhaseFActivate

LCD waveform phase F activates.

enumerator kSLCD_PhaseGActivate

LCD waveform phase G activates.

enumerator kSLCD_PhaseHActivate

LCD waveform phase H activates.

enum _slcd_phase_index

SLCD segment phase bit index.

Values:

enumerator kSLCD_PhaseAIndex

LCD phase A bit index.

enumerator kSLCD_PhaseBIndex

LCD phase B bit index.

enumerator kSLCD_PhaseCIndex

LCD phase C bit index.

enumerator kSLCD_PhaseDIndex

LCD phase D bit index.

enumerator kSLCD_PhaseEIndex

LCD phase E bit index.

enumerator kSLCD_PhaseFIndex

LCD phase F bit index.

enumerator kSLCD_PhaseGIndex

LCD phase G bit index.

enumerator kSLCD_PhaseHIndex

LCD phase H bit index.

enum _slcd_display_mode

SLCD display mode.

Values:

enumerator kSLCD_NormalMode

LCD Normal display mode.

enumerator kSLCD_AlternateMode

LCD Alternate display mode. For four back planes or less.

enumerator kSLCD_BlankMode

LCD Blank display mode.

enum _slcd_blink_mode

SLCD blink mode.

Values:

enumerator kSLCD_BlankDisplayBlink

Display blank during the blink period.

enumerator kSLCD_AltDisplayBlink

Display alternate display during the blink period if duty cycle is lower than 5.

enum _slcd_fault_detect_clock_prescaler

SLCD fault detect clock prescaler.

Values:

enumerator kSLCD_FaultSampleFreqDivider1

Fault detect sample clock frequency is 1/1 bus clock.

enumerator kSLCD_FaultSampleFreqDivider2

Fault detect sample clock frequency is 1/2 bus clock.

enumerator kSLCD_FaultSampleFreqDivider4

Fault detect sample clock frequency is 1/4 bus clock.

enumerator kSLCD_FaultSampleFreqDivider8

Fault detect sample clock frequency is 1/8 bus clock.

enumerator kSLCD_FaultSampleFreqDivider16

Fault detect sample clock frequency is 1/16 bus clock.

enumerator kSLCD_FaultSampleFreqDivider32

Fault detect sample clock frequency is 1/32 bus clock.

enumerator kSLCD_FaultSampleFreqDivider64

Fault detect sample clock frequency is 1/64 bus clock.

enumerator kSLCD_FaultSampleFreqDivider128

Fault detect sample clock frequency is 1/128 bus clock.

enum _slcd_fault_detect_sample_window_width

SLCD fault detect sample window width.

Values:

enumerator kSLCD_FaultDetectWindowWidth4SampleClk

Sample window width is 4 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth8SampleClk

Sample window width is 8 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth16SampleClk

Sample window width is 16 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth32SampleClk

Sample window width is 32 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth64SampleClk

Sample window width is 64 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth128SampleClk

Sample window width is 128 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth256SampleClk

Sample window width is 256 sample clock cycles.

enumerator kSLCD_FaultDetectWindowWidth512SampleClk

Sample window width is 512 sample clock cycles.

enum _slcd_interrupt_enable

SLCD interrupt source.

Values:

enumerator kSLCD_FaultDetectCompleteInterrupt

SLCD fault detection complete interrupt source.

enumerator kSLCD_FrameFreqInterrupt

SLCD frame frequency interrupt source. Not available in all low-power modes.

enum _slcd_lowpower_behavior

SLCD behavior in low power mode.

Values:

enumerator kSLCD_EnabledInWaitStop

SLCD works in wait and stop mode.

enumerator kSLCD_EnabledInWaitOnly

SLCD works in wait mode and is disabled in stop mode.

enumerator kSLCD_EnabledInStopOnly

SLCD works in stop mode and is disabled in wait mode.

enumerator kSLCD_DisabledInWaitStop

SLCD is disabled in stop mode and wait mode.

typedef enum _slcd_clock_prescaler slcd_clock_prescaler_t

SLCD clock prescaler to generate frame frequency.

typedef enum _slcd_regulated_voltage_trim slcd_regulated_voltage_trim_t

SLCD regulated voltage trim parameter, be used to meet the desired contrast.

typedef enum _slcd_sample_hold slcd_sample_hold_t

SLCD sample&hold configuration. To save power, configure the voltage to be sampled and held periodically, during this period the phase switches are turned off.

typedef enum _slcd_blink_rate slcd_blink_rate_t

SLCD blink rate.

typedef enum _slcd_duty_cycle slcd_duty_cycle_t

SLCD duty cycle.

typedef enum _slcd_phase_type slcd_phase_type_t

SLCD segment phase type.

typedef enum _slcd_phase_index slcd_phase_index_t

SLCD segment phase bit index.

typedef enum _slcd_display_mode slcd_display_mode_t

SLCD display mode.

typedef enum _slcd_blink_mode slcd_blink_mode_t

SLCD blink mode.

typedef enum _slcd_fault_detect_clock_prescaler slcd_fault_detect_clock_prescaler_t

SLCD fault detect clock prescaler.

typedef enum _slcd_fault_detect_sample_window_width slcd_fault_detect_sample_window_width_t

SLCD fault detect sample window width.

typedef struct _slcd_fault_detect_config slcd_fault_detect_config_t

SLCD fault frame detection configuration structure.

typedef enum _slcd_interrupt_enable slcd_interrupt_enable_t

SLCD interrupt source.

typedef enum _slcd_lowpower_behavior slcd_lowpower_behavior

SLCD behavior in low power mode.

typedef struct _slcd_config slcd_config_t

SLCD configuration structure.

struct SLCD_Type

#include <fsl_slcd.h>

SLCD structure definition.

Public Members

SGLCD_FAULT_DETECT_Type *fault

Pointer to fault detect registers.

SGLCD_CONTROL_Type *control

Pointer to control registers.

struct _slcd_fault_detect_config

#include <fsl_slcd.h>

SLCD fault frame detection configuration structure.

Public Members

bool faultDetectIntEnable

Fault frame detection interrupt enable flag.

bool faultDetectBackPlaneEnable

True means the pin id fault detected is back plane otherwise front plane.

uint8_t faultDetectPinIndex

Fault detected pin id from 0 to 63.

slcd_fault_detect_clock_prescaler_t faultPrescaler

Fault detect clock prescaler.

slcd_fault_detect_sample_window_width_t width

Fault detect sample window width.

struct _slcd_config

#include <fsl_slcd.h>

SLCD configuration structure.

Public Members

bool lowPowerWaveform

Generate low power waveform.

slcd_regulated_voltage_trim_t voltageTrimVLL1

Voltage trim for VLL1 output level.

slcd_regulated_voltage_trim_t voltageTrimVLL2

Voltage trim for VLL2 output level.

slcd_sample_hold_t sampleHold

Sample&hold setting.

slcd_display_mode_t displayMode

SLCD display mode.

slcd_duty_cycle_t dutyCycle

Duty cycle.

slcd_lowpower_behavior lowPowerBehavior

SLCD behavior in low power mode.

bool frameFreqIntEnable

Frame frequency interrupt enable flag.

uint32_t slcdLowPinEnabled

Setting enabled SLCD pin 0 ~ pin 31. Setting bit n to 1 means enable pin n.

uint32_t slcdHighPinEnabled

Setting enabled SLCD pin 32 ~ pin 63. Setting bit n to 1 means enable pin (n + 32).

uint32_t backPlaneLowPin

Setting back plane pin 0 ~ pin 31. Setting bit n to 1 means setting pin n as back plane. It should never have the same bit setting as the frontPlane Pin.

uint32_t backPlaneHighPin

Setting back plane pin 32 ~ pin 63. Setting bit n to 1 means setting pin (n + 32) as back plane. It should never have the same bit setting as the frontPlane Pin.

slcd_fault_detect_config_t *faultConfig

Fault frame detection configure. If not requirement, set to NULL.

SMM: Sleep Mode Manager Driver

enum _smm_interrupt_enable

The enumeration of interrupt to enable. .

Values:

enumerator kSMM_QChannelTimeoutInt

Enable or disable the QChannel timeout interrupt.

enumerator kSMM_QChannelDenyInt

Enable or disable the QChannel deny interrupt.

enumerator kSMM_DeepSleepCounterInt

Enable or disable the deep sleep counter interrupt.

enumerator kSMM_ComparatorMatchInt

Enable or disable the comparator match interrupt.

enumerator kSMM_AllSupportedInts

Enable or disable all support interrupts.

enum _smm_interrupt_flag

The enumeration of interrupt flag. .

Values:

enumerator kSMM_QChannelTimeoutIntFlag

Indicates that the QChannel timeout interrupt has occurred.

enumerator kSMM_QChannelDenyIntFlag

Indicates that the Q channel deny interrupt has occurred.

enumerator kSMM_AllIntFlags

All supported interrupt flags

enum _smm_ext_int_polarity

The enumeration of external interrupt polarity.

Values:

enumerator kSMM_ExtIntRisingEdge

Trigger on rising edge of the external interrupt pin.

enumerator kSMM_ExtIntFallingEdge

Trigger on falling edge of the external interrupt pin.

enum _smm_watchdog_alarm_use

Watchdog alarm use enumeration.

Values:

enumerator kSMM_WatchdogAlarmAsReset

Use watchdog alarm to trigger system reset.

enumerator kSMM_WatchdogAlarmAsInterrupt

Use watchdog alarm to trigger interrupt.

typedef enum _smm_ext_int_polarity smm_ext_int_polarity_t

The enumeration of external interrupt polarity.

typedef struct _smm_ext_int_config smm_ext_int_config_t

Configuration definition of external interrupt.

typedef struct _smm_backup_reg_content smm_backup_reg_content_t

The definition of backend register content.

typedef enum _smm_watchdog_alarm_use smm_watchdog_alarm_use_t

Watchdog alarm use enumeration.

void SMM_SetExtInterruptConfig(SMM_Type *base, const smm_ext_int_config_t *ptrConfig)

Set external interrupt configuration.

Parameters:

• base – SMM base address.

• ptrConfig – Pointer to configuration in type of smm_ext_int_config_t.

static inline void SMM_DisableAonCpuIsoSingal(SMM_Type *base)

Disable the AON CPU I/O signals on exit from DPD2.

Deprecated:

Please use SMM_DisableAonCpuIso() as instead.

Parameters:

• base – SMM base address.

static inline void SMM_DisableMainCpuIsoSingal(SMM_Type *base)

Disable the Main CPU I/O signals on exit from DPD1.

Deprecated:

Please use SMM_DisableMainCpuIso() as instead.

Parameters:

• base – SMM base address.

static inline void SMM_EnableWakeupSourceToMainCpu(SMM_Type *base, uint32_t wakeupSources)

Enable wakeup sources to the main CPU.

Parameters:

• base – SMM base address.

• wakeupSources – Mask value of wakeup sources.

static inline void SMM_DisableWakeupSourceToMainCpu(SMM_Type *base, uint32_t wakeupSources)

Disable wakeup sources to the main CPU.

Parameters:

• base – SMM base address.

• wakeupSources – Mask value of wakeup sources.

static inline uint32_t SMM_GetEnabledWakeupSourceToMainCpu(SMM_Type *base)

Get enabled wakeup sources to main CPU.

Parameters:

• base – SMM base address.

Returns:

Masked value of all enabled wakeup sources to main CPU.

static inline void SMM_EnableWakeupSourceToAonCpu(SMM_Type *base, uint32_t wakeupSources)

Enable wakeup sources to AON CPU.

Parameters:

• base – SMM base address.

• wakeupSources – The mask value of wakeup sources.

static inline void SMM_DisableWakeupSourceToAonCpu(SMM_Type *base, uint32_t wakeupSources)

Disable wakeup sources to AON CPU.

Parameters:

• base – SMM base address.

• wakeupSources – The mask value of wakeup sources.

static inline uint32_t SMM_GetEnabledWakeupSourceToAonCpu(SMM_Type *base)

Get enabled wakeup sources to AON CPU.

Parameters:

• base – SMM base address.

Returns:

Masked value of all enabled wakeup sources to AON CPU.

static inline uint32_t SMM_GetWakeupSourceStatus(SMM_Type *base)

Get wakeup source status.

Parameters:

• base – SMM base address.

Returns:

Masked value of all enabled wakeup sources.

static inline void SMM_ClearWakeupSourceStatus(SMM_Type *base, uint32_t wakeupSources)

Clear wakeup source status.

Parameters:

• base – SMM base address.

• wakeupSources – Mask value of wakeup sources to clear.

static inline void SMM_ShutDownBandgapInLowPowerModes(SMM_Type *base, bool shutdown)

Shutdown bangdap in low power modes.

Parameters:

• base – SMM base address.

• shutdown – True to disable bandgap, false to keep enabled.

static inline void SMM_StartPowerDownSequence(SMM_Type *base)

Start the power down sequence.

Parameters:

• base – SMM base address.

static inline void SMM_StartAonDPD2Sequence(SMM_Type *base)

Start the DPD2 sequence.

Parameters:

• base – SMM base address.

static inline void SMM_StartAonShutDownSequence(SMM_Type *base)

Start the AON shutdown/DPD3 sequence.

Parameters:

• base – SMM base address.

static inline void SMM_AbortLowPowerModeSequence(SMM_Type *base)

Abort any start of low power modes sequence.

Parameters:

• base – SMM base address.

static inline void SMM_SwitchToXTAL32(SMM_Type *base, bool enable)

Switch to XTAL32 in DPD2 mode.

Parameters:

• base – SMM base address

• enable – True means switch to 32k clock, false means remain at AON_CLK.

static inline void SMM_PowerOffAonSramManually(SMM_Type *base, uint8_t sramCuts)

Power off selected AON SRAM cuts manually.

Parameters:

• base – SMM base address.

• sramCuts – The mask of AON SRAM cuts.

static inline void SMM_PowerOnAonSramManually(SMM_Type *base, uint8_t sramCuts)

Power on selected AON SRAM cuts manually.

Parameters:

• base – SMM base address.

• sramCuts – The mask of AON SRAM cuts.

static inline void SMM_PowerOffAonSramAutomatically(SMM_Type *base, uint8_t sramCuts)

Power off selected AON SRAM cuts when enter into low power mode.

Parameters:

• base – SMM base address.

• sramCuts – The mask of AON SRAM cuts.

static inline void SMM_DisableAonSramAutoControl(SMM_Type *base, uint8_t sramCuts)

Keep selected AON SRAM keep powered when enter into low power mode.

Parameters:

• base – SMM base address.

• sramCuts – The mask of AON SRAM cuts.

void SMM_WriteToBackupReg(SMM_Type *base, const smm_backup_reg_content_t *ptrBackupRegContent)

Write data to backup registers.

Parameters:

• base – SMM base address.

• ptrBackupRegContent – [in] Pointer to the data to be written to the backup registers.

void SMM_ReadFromBackupReg(SMM_Type *base, smm_backup_reg_content_t *ptrBackupRegContent)

Read data from backup registers.

Parameters:

• base – SMM base address.

• ptrBackupRegContent – [out] Pointer of the content will read from backup registers.

void SMM_EnableMainDomainSramRetention(SMM_Type *base, uint16_t sramCuts)

Enable memory retention at low power modes for main CPU.

Parameters:

• base – SMM base address.

• sramCuts – Mask of sram cuts to retained.

static inline void SMM_DisableMainDomainSramRetention(SMM_Type *base)

Disable memory retention at low power modes for main CPU.

Parameters:

• base – SMM base address.

static inline void SMM_EnableIvsModeForSramRetention(SMM_Type *base, bool enable)

Enable/disable IVS Mode for the SRAM retention.

Parameters:

• base – SMM base address.

• enable – True to enable IVS mode, false to disable.

static inline uint8_t SMM_GetPowerState(SMM_Type *base)

Get the power state.

Parameters:

• base – SMM base address.

Returns:

Value of power state.

static inline void SMM_WakeupMainDomain(SMM_Type *base)

Wakeup the main domain CPU from low power mode.

Parameters:

• base – SMM base address.

static inline bool SMM_CheckExternalIntActive(SMM_Type *base)

Check if the external interrupt flag is asserted.

Parameters:

• base – SMM base address.

Returns:

True if external interrupt is active, false otherwise.

static inline void SMM_ClearExternalIntFlag(SMM_Type *base)

Clear the external interrupt flag.

Parameters:

• base – SMM base address.

static inline void SMM_DisableMainCpuIso(SMM_Type *base)

Disable the main CPU I/O signals.

Parameters:

• base – SMM base address.

static inline void SMM_DisableAonCpuIso(SMM_Type *base)

Disable the AON CPU I/O signals.

Parameters:

• base – SMM base address.

static inline void SMM_ClearAllLowPowerSequence(SMM_Type *base)

Clear all low power sequence settings.

Parameters:

• base – SMM base address.

static inline void SMM_ClearMainCpuWakeupSources(SMM_Type *base)

Clear all wakeup sources to main domain.

Parameters:

• base –

static inline void SMM_ClearAonCpuWakeupSources(SMM_Type *base)

Clear all wakeup sources to AON domain.

Parameters:

• base – SMM base address.

static inline void SMM_ConfigWatchdogAlarmUse(SMM_Type *base, smm_watchdog_alarm_use_t alarmUse)

Config the watchdog alarm use.

Parameters:

• base – SMM base address.

• alarmUse – The watchdog alarm use.

static inline void SMM_UseDeepSleepCounterInSoftwareMethod(SMM_Type *base)

Use the deep sleep counter for general software needs.

Parameters:

• base – SMM base address.

static inline void SMM_UseDeepSleepCounterInHardwareMethod(SMM_Type *base)

Use the deep sleep counter by hardware to wakeup from low power mode.

Parameters:

• base – SMM base address.

static inline void SMM_ResetAndDisableDeepSleepCounter(SMM_Type *base)

Reset the deep sleep counter and disable count.

Parameters:

• base – SMM base address.

static inline void SMM_StartDeepSleepCounter(SMM_Type *base)

Enable the countdown start of the deep sleep counter when at software use.

Parameters:

• base – SMM base address.

static inline void SMM_UpdateDeepSleepCounter(SMM_Type *base, uint16_t value)

Update the deep sleep counter, the counter is counting the AON clocks.

Parameters:

• base – SMM base address.

• value – Value to update the deep sleep counter.

static inline uint16_t SMM_ReadDeepSleepCounter(SMM_Type *base)

Read value of deep sleep counter.

Parameters:

• base – SMM base address.

Returns:

Count of deep sleep counter.

static inline void SMM_EnableInterrupts(SMM_Type *base, uint32_t masks)

Enable specific interrupts.

Parameters:

• base – SMM base address.

• masks – Bitmask of interrupts to enable. Use OR’ed values from s

static inline void SMM_DisableInterrupts(SMM_Type *base, uint32_t masks)

Disable specific interrupts.

Parameters:

• base – SMM base address.

• masks – Bitmask of interrupts to disable, should be OR’ed value of smm_interrupt_enable_t.

static inline uint32_t SMM_GetInterruptFlags(SMM_Type *base)

Get interrupt flags.

Parameters:

• base – SMM base address.

Returns:

The mask of all asserted interrupt flags, should be the OR’ed value of smm_interrupt_flag_t.

static inline void SMM_ClearInterruptFlags(SMM_Type *base, uint32_t flags)

Clear interrupt flags.

Parameters:

• base – SMM base address.

• flags – The mask of interrupt flags to clear, should be the OR’ed value of smm_interrupt_flag_t.

static inline bool SMM_CheckDeepSleepCounterMatch(SMM_Type *base)

Check if deep sleep counter reach zero at software use.

Parameters:

• base – SMM base address.

Return values:

• false – Deep sleep counter do not reach zero.

• true – Deep sleep counter reach zero.

static inline void SMM_ClearDeepSleepCounterMatchFlag(SMM_Type *base)

Clear deep sleep counter match flag.

Parameters:

• base – SMM base address.

static inline bool SMM_CheckComparatorMatch(SMM_Type *base)

Check if comparator match was active.

Parameters:

• base – SMM base address.

Return values:

• false – Comparator match is not active.

• true – Comparator match is active.

static inline void SMM_ClearComparatorMatchFlag(SMM_Type *base)

Clear comparator match flag.

Parameters:

• base – SMM base address.

FSL_SMM_DRIVER_VERSION

smm driver version 2.2.1.

SMM_CPU_CORE_FREQ

bool maskExtIntPin

Set to true to mask the external interrupt pin; false to unmask.

smm_ext_int_polarity_t extIntPolarity

External interrupt polarity.

uint32_t word1

uint32_t word2

struct _smm_ext_int_config

#include <fsl_smm.h>

Configuration definition of external interrupt.

struct _smm_backup_reg_content

#include <fsl_smm.h>

The definition of backend register content.

TRDC: Trusted Resource Domain Controller

void TRDC_Init(TRDC_Type *base)

Initializes the TRDC module.

This function enables the TRDC clock.

Parameters:

• base – TRDC peripheral base address.

void TRDC_Deinit(TRDC_Type *base)

De-initializes the TRDC module.

This function disables the TRDC clock.

Parameters:

• base – TRDC peripheral base address.

static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)

Gets the domain ID of the current bus master.

Parameters:

• base – TRDC peripheral base address.

Returns:

Domain ID of current bus master.

void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config)

Gets the TRDC hardware configuration.

This function gets the TRDC hardware configurations, including number of bus masters, number of domains, number of MRCs and number of PACs.

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to the structure to get the configuration.

static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)

Sets the TRDC DAC(Domain Assignment Controllers) global valid.

Once enabled, it will remain enabled until next reset.

Parameters:

• base – TRDC peripheral base address.

static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum)

Locks the bus master domain assignment register.

This function locks the master domain assignment. After it is locked, the register can’t be changed until next reset.

Parameters:

• base – TRDC peripheral base address.

• master – Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.

• regNum – Which register to configure, processor master can have more than one register for the MDAC configuration.

• assignIndex – Which assignment register to lock.

static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid)

Sets the master domain assignment as valid or invalid.

This function sets the master domain assignment as valid or invalid.

Parameters:

• base – TRDC peripheral base address.

• master – Which master to configure.

• regNum – Which register to configure, processor master can have more than one register for the MDAC configuration.

• assignIndex – Index for the domain assignment register.

• valid – True to set valid, false to set invalid.

void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment)

Gets the default master domain assignment for the processor bus master.

This function gets the default master domain assignment for the processor bus master. It should only be used for the processor bus masters, such as CORE0. This function sets the assignment as follows:

assignment->domainId           = 0U;
assignment->domainIdSelect     = kTRDC_DidMda;
assignment->lock               = 0U;

Parameters:

• domainAssignment – Pointer to the assignment structure.

void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment)

Gets the default master domain assignment for non-processor bus master.

This function gets the default master domain assignment for non-processor bus master. It should only be used for the non-processor bus masters, such as DMA. This function sets the assignment as follows:

assignment->domainId            = 0U;
assignment->privilegeAttr       = kTRDC_ForceUser;
assignment->secureAttr       = kTRDC_ForceSecure;
assignment->bypassDomainId      = 0U;
assignment->lock                = 0U;

Parameters:

• domainAssignment – Pointer to the assignment structure.

void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum, const trdc_processor_domain_assignment_t *domainAssignment)

Sets the processor bus master domain assignment.

This function sets the processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to set.

Example: Set domain assignment for core 0.

trdc_processor_domain_assignment_t processorAssignment;

TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);

processorAssignment.domainId = 0;
processorAssignment.xxx      = xxx;
TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);

Parameters:

• base – TRDC peripheral base address.

• master – Which master to configure, refer to trdc_master_t in processor header file.

• regNum – Which register to configure, processor master can have more than one register for the MDAC configuration.

• domainAssignment – Pointer to the assignment structure.

void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, uint8_t master, const trdc_non_processor_domain_assignment_t *domainAssignment)

Sets the non-processor bus master domain assignment.

This function sets the non-processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to set.

Example: Set domain assignment for DMA0.

trdc_non_processor_domain_assignment_t nonProcessorAssignment;

TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
nonProcessorAssignment.domainId = 1;
nonProcessorAssignment.xxx      = xxx;

TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);

Parameters:

• base – TRDC peripheral base address.

• master – Which master to configure, refer to trdc_master_t in processor header file.

• domainAssignment – Pointer to the assignment structure.

static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base)

Gets the bit map of the bus master(s) that is(are) sourcing a PID register.

This function sets the non-processor master domain assignment as valid.

Parameters:

• base – TRDC peripheral base address.

Returns:

the bit map of the master(s). Bit 1 sets indicates bus master 1.

void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig)

Sets the current Process identifier(PID) for processor core.

Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. Secure privileged software saves and restores the PID as part of any context switch. This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality.

Parameters:

• base – TRDC peripheral base address.

• master – Which processor master to configure, refer to trdc_master_t in processor header file.

• pidConfig – Pointer to the configuration structure.

void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration)

Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.

config->lockSecureVTOR    = false;
config->lockNonsecureVTOR = false;
config->lockSecureMPU     = false;
config->lockNonsecureMPU  = false;
config->lockSAU           = false;

Parameters:

• domainAssignment – Pointer to the configuration structure.

void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration)

Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.

Example: Lock the secure and non-secure MPU registers.

trdc_idau_config_t idauConfiguration;

TRDC_GetDefaultIDAUConfig(&idauConfiguration);

idauConfiguration.lockSecureMPU = true;
idauConfiguration.lockNonsecureMPU      = true;
TRDC_SetIDAU(TRDC, &idauConfiguration);

Parameters:

• base – TRDC peripheral base address.

• domainAssignment – Pointer to the configuration structure.

static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)

Enables/disables the FLW(flash logical window) function.

Parameters:

• base – TRDC peripheral base address.

• enable – True to enable, false to disable.

static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)

Locks FLW registers. Once locked the registers can noy be updated until next reset.

Parameters:

• base – TRDC peripheral base address.

static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)

Gets the FLW physical base address.

Parameters:

• base – TRDC peripheral base address.

Returns:

Physical address of the FLW function.

static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)

Sets the FLW size.

Parameters:

• base – TRDC peripheral base address.

• size – Size of the FLW in unit of 32k bytes.

void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration)

Gets the default FLW(Flsh Logical Window) configuration.

config->blockCount    = false;
config->arrayBaseAddr = false;
config->lock     = false;
config->enable  = false;

Parameters:

• flwConfiguration – Pointer to the configuration structure.

void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration)

Sets the FLW function’s configuration.

trdc_flw_config_t flwConfiguration;

TRDC_GetDefaultIDAUConfig(&flwConfiguration);

flwConfiguration.blockCount = 32U;
flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
TRDC_SetIDAU(TRDC, &flwConfiguration);

Parameters:

• base – TRDC peripheral base address.

• flwConfiguration – Pointer to the configuration structure.

status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error)

Gets and clears the first domain error of the current domain.

This function gets the first access violation information for the current domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.

Parameters:

• base – TRDC peripheral base address.

• error – Pointer to the error information.

Returns:

If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData.

status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId)

Gets and clears the first domain error of the specific domain.

This function gets the first access violation information for the specific domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.

Parameters:

• base – TRDC peripheral base address.

• error – Pointer to the error information.

• domainId – The error of which domain to get and clear.

Returns:

If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData.

static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)

Sets the TRDC MRC(Memory Region Checkers) global valid.

Once enabled, it will remain enabled until next reset.

Parameters:

• base – TRDC peripheral base address.

static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)

Gets the TRDC MRC(Memory Region Checkers) region number valid.

Parameters:

• base – TRDC peripheral base address.

Returns:

the region number of the given MRC instance

void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mrcIdx, uint8_t regIdx)

Sets the memory access configuration for one of the access control register of one MRC.

Example: Enable the secure operations and lock the configuration for MRC0 region 1.

trdc_memory_access_control_config_t config;

config.securePrivX = true;
config.securePrivW = true;
config.securePrivR = true;
config.lock = true;
TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to the configuration structure.

• mrcIdx – MRC index.

• regIdx – Register number.

void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable)

Enables the update of the selected domians.

After the domians’ update are enabled, their regions’ NSE bits can be set or clear.

Parameters:

• base – TRDC peripheral base address.

• mrcIdx – MRC index.

• domianMask – Bit mask of the domains to be enabled.

• enable – True to enable, false to disable.

void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)

Sets the NSE bits of the selected regions for domains.

This function sets the NSE bits for the selected regions for the domains whose update are enabled.

Parameters:

• base – TRDC peripheral base address.

• mrcIdx – MRC index.

• regionMask – Bit mask of the regions whose NSE bits to set.

void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)

Clears the NSE bits of the selected regions for domains.

This function clears the NSE bits for the selected regions for the domains whose update are enabled.

Parameters:

• base – TRDC peripheral base address.

• mrcIdx – MRC index.

• regionMask – Bit mask of the regions whose NSE bits to clear.

void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask)

Clears the NSE bits for all the regions of the selected domains.

This function clears the NSE bits for all regions of selected domains whose update are enabled.

Parameters:

• base – TRDC peripheral base address.

• mrcIdx – MRC index.

• domainMask – Bit mask of the domians whose NSE bits to clear.

void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config)

Sets the configuration for one of the region descriptor per domain per MRC instnce.

This function sets the configuration for one of the region descriptor, including the start and end address of the region, memory access control policy and valid.

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to region descriptor configuration structure.

static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)

Sets the TRDC MBC(Memory Block Checkers) global valid.

Once enabled, it will remain enabled until next reset.

Parameters:

• base – TRDC peripheral base address.

void TRDC_GetMbcHardwareConfig(TRDC_Type *base, trdc_slave_memory_hardware_config_t *config, uint8_t mbcIdx, uint8_t slvIdx)

Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to the structure to get the configuration.

• mbcIdx – MBC number.

• slvIdx – Slave number.

void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx)

Sets the NSR update configuration for one of the MBC instance.

After set the NSE configuration, the configured memory area can be updateby NSE set/clear.

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to NSE update configuration structure.

• mbcIdx – MBC index.

void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)

Sets the NSE bits of the selected configuration words according to NSE update configuration.

This function sets the NSE bits of the word for the configured regio, memory.

Parameters:

• base – TRDC peripheral base address.

• mbcIdx – MBC index.

• bitMask – Mask of the bits whose NSE bits to set.

void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)

Clears the NSE bits of the selected configuration words according to NSE update configuration.

This function sets the NSE bits of the word for the configured regio, memory.

Parameters:

• base – TRDC peripheral base address.

• mbcIdx – MBC index.

• bitMask – Mask of the bits whose NSE bits to clear.

void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave)

Clears all configuration words’ NSE bits of the selected domain and memory.

Parameters:

• base – TRDC peripheral base address.

• mbcIdx – MBC index.

• domainMask – Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.

• slaveMask – Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1’s NSE bits.

void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mbcIdx, uint8_t rgdIdx)

Sets the memory access configuration for one of the region descriptor of one MBC.

Example: Enable the secure operations and lock the configuration for MRC0 region 1.

trdc_memory_access_control_config_t config;

config.securePrivX = true;
config.securePrivW = true;
config.securePrivR = true;
config.lock = true;
TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to the configuration structure.

• mbcIdx – MBC index.

• rgdIdx – Region descriptor number.

void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config)

Sets the configuration for one of the memory block per domain per MBC instnce.

This function sets the configuration for one of the memory block, including the memory access control policy and nse enable.

Parameters:

• base – TRDC peripheral base address.

• config – Pointer to memory block configuration structure.

enum _trdc_did_sel

TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation.

Values:

enumerator kTRDC_DidMda

Use MDAn[2:0] as DID.

enumerator kTRDC_DidInput

Use the input DID (DID_in) as DID.

enumerator kTRDC_DidMdaAndInput

Use MDAn[2] concatenated with DID_in[1:0] as DID.

enumerator kTRDC_DidReserved

Reserved.

enum _trdc_secure_attr

TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment.

Values:

enumerator kTRDC_ForceSecure

Force the bus attribute for this master to secure.

enumerator kTRDC_ForceNonSecure

Force the bus attribute for this master to non-secure.

enumerator kTRDC_MasterSecure

Use the bus master’s secure/nonsecure attribute directly.

enumerator kTRDC_MasterSecure1

Use the bus master’s secure/nonsecure attribute directly.

enum _trdc_pid_domain_hit_config

The configuration of domain hit evaluation of PID.

Values:

enumerator kTRDC_pidDomainHitNone0

No PID is included in the domain hit evaluation.

enumerator kTRDC_pidDomainHitNone1

No PID is included in the domain hit evaluation.

enumerator kTRDC_pidDomainHitInclusive

The PID is included in the domain hit evaluation when (PID & ~PIDM).

enumerator kTRDC_pidDomainHitExclusive

The PID is included in the domain hit evaluation when ~(PID & ~PIDM).

enum _trdc_privilege_attr

TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment.

Values:

enumerator kTRDC_ForceUser

Force the bus attribute for this master to user.

enumerator kTRDC_ForcePrivilege

Force the bus attribute for this master to privileged.

enumerator kTRDC_MasterPrivilege

Use the bus master’s attribute directly.

enumerator kTRDC_MasterPrivilege1

Use the bus master’s attribute directly.

enum _trdc_pid_lock

PID lock configuration.

Values:

enumerator kTRDC_PidUnlocked0

The PID value can be updated by any secure priviledged write.

enumerator kTRDC_PidUnlocked1

The PID value can be updated by any secure priviledged write.

enumerator kTRDC_PidUnlocked2

The PID value can be updated by any secure priviledged write from the bus master that first configured this register.

enumerator kTRDC_PidLocked

The PID value is locked until next reset.

enum _trdc_controller

TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.

Values:

enumerator kTRDC_MemBlockController0

Memory block checker 0.

enumerator kTRDC_MemBlockController1

Memory block checker 1.

enumerator kTRDC_MemBlockController2

Memory block checker 2.

enumerator kTRDC_MemBlockController3

Memory block checker 3.

enumerator kTRDC_MemRegionChecker0

Memory region checker 0.

enumerator kTRDC_MemRegionChecker1

Memory region checker 1.

enumerator kTRDC_MemRegionChecker2

Memory region checker 2.

enumerator kTRDC_MemRegionChecker3

Memory region checker 3.

enumerator kTRDC_MemRegionChecker4

Memory region checker 4.

enumerator kTRDC_MemRegionChecker5

Memory region checker 5.

enumerator kTRDC_MemRegionChecker6

Memory region checker 6.

enum _trdc_error_state

TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].

Values:

enumerator kTRDC_ErrorStateNone

No access violation detected.

enumerator kTRDC_ErrorStateNone1

No access violation detected.

enumerator kTRDC_ErrorStateSingle

Single access violation detected.

enumerator kTRDC_ErrorStateMulti

Multiple access violation detected.

enum _trdc_error_attr

TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].

Values:

enumerator kTRDC_ErrorSecureUserInst

Secure user mode, instruction fetch access.

enumerator kTRDC_ErrorSecureUserData

Secure user mode, data access.

enumerator kTRDC_ErrorSecurePrivilegeInst

Secure privileged mode, instruction fetch access.

enumerator kTRDC_ErrorSecurePrivilegeData

Secure privileged mode, data access.

enumerator kTRDC_ErrorNonSecureUserInst

NonSecure user mode, instruction fetch access.

enumerator kTRDC_ErrorNonSecureUserData

NonSecure user mode, data access.

enumerator kTRDC_ErrorNonSecurePrivilegeInst

NonSecure privileged mode, instruction fetch access.

enumerator kTRDC_ErrorNonSecurePrivilegeData

NonSecure privileged mode, data access.

enum _trdc_error_type

TRDC domain error access type definition TRDC_DERR_W1_n[ERW].

Values:

enumerator kTRDC_ErrorTypeRead

Error occurs on read reference.

enumerator kTRDC_ErrorTypeWrite

Error occurs on write reference.

enum _trdc_region_descriptor

The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions.

Values:

enumerator kTRDC_RegionDescriptor0

Region descriptor 0.

enumerator kTRDC_RegionDescriptor1

Region descriptor 1.

enumerator kTRDC_RegionDescriptor2

Region descriptor 2.

enumerator kTRDC_RegionDescriptor3

Region descriptor 3.

enumerator kTRDC_RegionDescriptor4

Region descriptor 4.

enumerator kTRDC_RegionDescriptor5

Region descriptor 5.

enumerator kTRDC_RegionDescriptor6

Region descriptor 6.

enumerator kTRDC_RegionDescriptor7

Region descriptor 7.

enumerator kTRDC_RegionDescriptor8

Region descriptor 8.

enumerator kTRDC_RegionDescriptor9

Region descriptor 9.

enumerator kTRDC_RegionDescriptor10

Region descriptor 10.

enumerator kTRDC_RegionDescriptor11

Region descriptor 11.

enumerator kTRDC_RegionDescriptor12

Region descriptor 12.

enumerator kTRDC_RegionDescriptor13

Region descriptor 13.

enumerator kTRDC_RegionDescriptor14

Region descriptor 14.

enumerator kTRDC_RegionDescriptor15

Region descriptor 15.

enum _trdc_MRC_domain

The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or several domains.

Values:

enumerator kTRDC_MrcDomain0

Domain 0.

enumerator kTRDC_MrcDomain1

Domain 1.

enumerator kTRDC_MrcDomain2

Domain 2.

enumerator kTRDC_MrcDomain3

Domain 3.

enumerator kTRDC_MrcDomain4

Domain 4.

enumerator kTRDC_MrcDomain5

Domain 5.

enumerator kTRDC_MrcDomain6

Domain 6.

enumerator kTRDC_MrcDomain7

Domain 7.

enumerator kTRDC_MrcDomain8

Domain 8.

enumerator kTRDC_MrcDomain9

Domain 9.

enumerator kTRDC_MrcDomain10

Domain 10.

enumerator kTRDC_MrcDomain11

Domain 11.

enumerator kTRDC_MrcDomain12

Domain 12.

enumerator kTRDC_MrcDomain13

Domain 13.

enumerator kTRDC_MrcDomain14

Domain 14.

enumerator kTRDC_MrcDomain15

Domain 15.

enum _trdc_MBC_domain

The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several domains.

Values:

enumerator kTRDC_MbcDomain0

Domain 0.

enumerator kTRDC_MbcDomain1

Domain 1.

enumerator kTRDC_MbcDomain2

Domain 2.

enumerator kTRDC_MbcDomain3

Domain 3.

enumerator kTRDC_MbcDomain4

Domain 4.

enumerator kTRDC_MbcDomain5

Domain 5.

enumerator kTRDC_MbcDomain6

Domain 6.

enumerator kTRDC_MbcDomain7

Domain 7.

enum _trdc_MBC_memory

The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several memory block.

Values:

enumerator kTRDC_MbcSlaveMemory0

Memory 0.

enumerator kTRDC_MbcSlaveMemory1

Memory 1.

enumerator kTRDC_MbcSlaveMemory2

Memory 2.

enumerator kTRDC_MbcSlaveMemory3

Memory 3.

enum _trdc_MBC_bit

The MBC bit enumeration, used to form a mask to set/clear configured words’ NSE.

Values:

enumerator kTRDC_MbcBit0

Bit 0.

enumerator kTRDC_MbcBit1

Bit 1.

enumerator kTRDC_MbcBit2

Bit 2.

enumerator kTRDC_MbcBit3

Bit 3.

enumerator kTRDC_MbcBit4

Bit 4.

enumerator kTRDC_MbcBit5

Bit 5.

enumerator kTRDC_MbcBit6

Bit 6.

enumerator kTRDC_MbcBit7

Bit 7.

enumerator kTRDC_MbcBit8

Bit 8.

enumerator kTRDC_MbcBit9

Bit 9.

enumerator kTRDC_MbcBit10

Bit 10.

enumerator kTRDC_MbcBit11

Bit 11.

enumerator kTRDC_MbcBit12

Bit 12.

enumerator kTRDC_MbcBit13

Bit 13.

enumerator kTRDC_MbcBit14

Bit 14.

enumerator kTRDC_MbcBit15

Bit 15.

enumerator kTRDC_MbcBit16

Bit 16.

enumerator kTRDC_MbcBit17

Bit 17.

enumerator kTRDC_MbcBit18

Bit 18.

enumerator kTRDC_MbcBit19

Bit 19.

enumerator kTRDC_MbcBit20

Bit 20.

enumerator kTRDC_MbcBit21

Bit 21.

enumerator kTRDC_MbcBit22

Bit 22.

enumerator kTRDC_MbcBit23

Bit 23.

enumerator kTRDC_MbcBit24

Bit 24.

enumerator kTRDC_MbcBit25

Bit 25.

enumerator kTRDC_MbcBit26

Bit 26.

enumerator kTRDC_MbcBit27

Bit 27.

enumerator kTRDC_MbcBit28

Bit 28.

enumerator kTRDC_MbcBit29

Bit 29.

enumerator kTRDC_MbcBit30

Bit 30.

enumerator kTRDC_MbcBit31

Bit 31.

typedef struct _trdc_hardware_config trdc_hardware_config_t

TRDC hardware configuration.

typedef struct _trdc_slave_memory_hardware_config trdc_slave_memory_hardware_config_t

Hardware configuration of the two slave memories within each MBC(memory block checker).

typedef enum _trdc_did_sel trdc_did_sel_t

TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation.

typedef enum _trdc_secure_attr trdc_secure_attr_t

TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment.

typedef enum _trdc_pid_domain_hit_config trdc_pid_domain_hit_config_t

The configuration of domain hit evaluation of PID.

typedef struct _trdc_processor_domain_assignment trdc_processor_domain_assignment_t

Domain assignment for the processor bus master.

typedef enum _trdc_privilege_attr trdc_privilege_attr_t

TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment.

typedef struct _trdc_non_processor_domain_assignment trdc_non_processor_domain_assignment_t

Domain assignment for the non-processor bus master.

typedef enum _trdc_pid_lock trdc_pid_lock_t

PID lock configuration.

typedef struct _trdc_pid_config trdc_pid_config_t

Process identifier(PID) configuration for processor cores.

typedef struct _trdc_idau_config trdc_idau_config_t

IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.

typedef struct _trdc_flw_config trdc_flw_config_t

FLW(Flash Logical Window) configuration.

typedef enum _trdc_controller trdc_controller_t

TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.

typedef enum _trdc_error_state trdc_error_state_t

TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].

typedef enum _trdc_error_attr trdc_error_attr_t

TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].

typedef enum _trdc_error_type trdc_error_type_t

TRDC domain error access type definition TRDC_DERR_W1_n[ERW].

typedef struct _trdc_domain_error trdc_domain_error_t

TRDC domain error definition.

typedef struct _trdc_memory_access_control_config trdc_memory_access_control_config_t

Memory access control configuration for MBC/MRC.

typedef struct _trdc_mrc_region_descriptor_config trdc_mrc_region_descriptor_config_t

The configuration of each region descriptor per domain per MRC instance.

typedef struct _trdc_mbc_nse_update_config trdc_mbc_nse_update_config_t

The configuration of MBC NSE update.

typedef struct _trdc_mbc_memory_block_config trdc_mbc_memory_block_config_t

The configuration of each memory block per domain per MBC instance.

FSL_TRDC_DRIVER_VERSION

struct _trdc_hardware_config

#include <fsl_trdc.h>

TRDC hardware configuration.

Public Members

uint8_t masterNumber

Number of bus masters.

uint8_t domainNumber

Number of domains.

uint8_t mbcNumber

Number of MBCs.

uint8_t mrcNumber

Number of MRCs.

struct _trdc_slave_memory_hardware_config

#include <fsl_trdc.h>

Hardware configuration of the two slave memories within each MBC(memory block checker).

Public Members

uint32_t blockNum

Number of blocks.

uint32_t blockSize

Block size.

struct _trdc_processor_domain_assignment

#include <fsl_trdc.h>

Domain assignment for the processor bus master.

Public Members

uint32_t domainId

Domain ID.

uint32_t domainIdSelect

Domain ID select method, see trdc_did_sel_t.

uint32_t pidDomainHitConfig

The configuration of the domain hit evaluation for PID, see trdc_pid_domain_hit_config_t.

uint32_t pidMask

The mask combined with PID, so multiple PID can be included as part of the domain hit determination. Set to 0 to disable.

uint32_t secureAttr

Secure attribute, see trdc_secure_attr_t.

uint32_t pid

The process identifier, combined with pidMask to form the domain hit determination.

uint32_t __pad0__

Reserved.

uint32_t lock

Lock the register.

uint32_t __pad1__

Reserved.

struct _trdc_non_processor_domain_assignment

#include <fsl_trdc.h>

Domain assignment for the non-processor bus master.

Public Members

uint32_t domainId

Domain ID.

uint32_t privilegeAttr

Privileged attribute, see trdc_privilege_attr_t.

uint32_t secureAttr

Secure attribute, see trdc_secure_attr_t.

uint32_t bypassDomainId

Bypass domain ID.

uint32_t __pad0__

Reserved.

uint32_t lock

Lock the register.

uint32_t __pad1__

Reserved.

struct _trdc_pid_config

#include <fsl_trdc.h>

Process identifier(PID) configuration for processor cores.

Public Members

uint32_t pid

The process identifier of the executing task. The highest bit can be used to define secure/nonsecure attribute of the task.

uint32_t __pad0__

Reserved.

uint32_t lock

How to lock the register, see trdc_pid_lock_t.

uint32_t __pad1__

Reserved.

struct _trdc_idau_config

#include <fsl_trdc.h>

IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.

Public Members

uint32_t __pad0__

Reserved.

uint32_t lockSecureVTOR

Disable writes to secure VTOR(Vector Table Offset Register).

uint32_t lockNonsecureVTOR

Disable writes to non-secure VTOR, Application interrupt and Reset Control Registers.

uint32_t lockSecureMPU

Disable writes to secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor in Secure state.

uint32_t lockNonsecureMPU

Disable writes to non-secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor.

uint32_t lockSAU

Disable writes to SAU(Security Attribution Unit) registers.

uint32_t __pad1__

Reserved.

struct _trdc_flw_config

#include <fsl_trdc.h>

FLW(Flash Logical Window) configuration.

Public Members

uint16_t blockCount

Block count of the Flash Logic Window in 32KByte blocks.

uint32_t arrayBaseAddr

Flash array base address of the Flash Logical Window.

bool lock

Disable writes to FLW registers.

bool enable

Enable FLW function.

struct _trdc_domain_error

#include <fsl_trdc.h>

TRDC domain error definition.

Public Members

trdc_controller_t controller

Which controller captured access violation.

uint32_t address

Access address that generated access violation.

trdc_error_state_t errorState

Error state.

trdc_error_attr_t errorAttr

Error attribute.

trdc_error_type_t errorType

Error type.

uint8_t errorPort

Error port.

uint8_t domainId

Domain ID.

uint8_t slaveMemoryIdx

The slave memory index. Only apply when violation in MBC.

struct _trdc_memory_access_control_config

#include <fsl_trdc.h>

Memory access control configuration for MBC/MRC.

Public Members

uint32_t nonsecureUsrX

Allow nonsecure user execute access.

uint32_t nonsecureUsrW

Allow nonsecure user write access.

uint32_t nonsecureUsrR

Allow nonsecure user read access.

uint32_t __pad0__

Reserved.

uint32_t nonsecurePrivX

Allow nonsecure privilege execute access.

uint32_t nonsecurePrivW

Allow nonsecure privilege write access.

uint32_t nonsecurePrivR

Allow nonsecure privilege read access.

uint32_t __pad1__

Reserved.

uint32_t secureUsrX

Allow secure user execute access.

uint32_t secureUsrW

Allow secure user write access.

uint32_t secureUsrR

Allow secure user read access.

uint32_t __pad2__

Reserved.

uint32_t securePrivX

Allownsecure privilege execute access.

uint32_t securePrivW

Allownsecure privilege write access.

uint32_t securePrivR

Allownsecure privilege read access.

uint32_t __pad3__

Reserved.

uint32_t lock

Lock the configuration until next reset, only apply to access control register 0.

struct _trdc_mrc_region_descriptor_config

#include <fsl_trdc.h>

The configuration of each region descriptor per domain per MRC instance.

Public Members

uint8_t memoryAccessControlSelect

Select one of the 8 access control policies for this region, for access cotrol policies see trdc_memory_access_control_config_t.

uint32_t startAddr

Physical start address.

bool valid

Lock the register.

bool nseEnable

Enable non-secure accesses and disable secure accesses.

uint32_t endAddr

Physical start address.

uint8_t mrcIdx

The index of the MRC for this configuration to take effect.

uint8_t domainIdx

The index of the domain for this configuration to take effect.

uint8_t regionIdx

The index of the region for this configuration to take effect.

struct _trdc_mbc_nse_update_config

#include <fsl_trdc.h>

The configuration of MBC NSE update.

Public Members

uint32_t __pad0__

Reserved.

uint32_t wordIdx

MBC configuration word index to be updated.

uint32_t __pad1__

Reserved.

uint32_t memorySelect

Bit mask of the selected memory to be updated. _trdc_MBC_memory.

uint32_t __pad2__

Reserved.

uint32_t domianSelect

Bit mask of the selected domain to be updated. _trdc_MBC_domain.

uint32_t __pad3__

Reserved.

uint32_t autoIncrement

Whether to increment the word index after current word is updated using this configuration.

struct _trdc_mbc_memory_block_config

#include <fsl_trdc.h>

The configuration of each memory block per domain per MBC instance.

Public Members

uint32_t memoryAccessControlSelect

Select one of the 8 access control policies for this memory block, for access cotrol policies see trdc_memory_access_control_config_t.

uint32_t nseEnable

Enable non-secure accesses and disable secure accesses.

uint32_t mbcIdx

The index of the MBC for this configuration to take effect.

uint32_t domainIdx

The index of the domain for this configuration to take effect.

uint32_t slaveMemoryIdx

The index of the slave memory for this configuration to take effect.

uint32_t memoryBlockIdx

The index of the memory block for this configuration to take effect.

Trdc_core

typedef struct _TRDC_General_Type TRDC_General_Type

TRDC general configuration register definition.

typedef struct _TRDC_FLW_Type TRDC_FLW_Type

TRDC flash logical control register definition.

typedef struct _TRDC_DomainError_Type TRDC_DomainError_Type

TRDC domain error register definition.

typedef struct _TRDC_DomainAssignment_Type TRDC_DomainAssignment_Type

TRDC master domain assignment register definition.

typedef struct _TRDC_MBC_Type TRDC_MBC_Type

TRDC MBC control register definition.

typedef struct _TRDC_MRC_Type TRDC_MRC_Type

TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word].

TRDC_GENERAL_BASE(base)

TRDC base address convert macro.

TRDC_FLW_BASE(base)

TRDC_DOMAIN_ERROR_BASE(base)

TRDC_DOMAIN_ASSIGNMENT_BASE(base)

TRDC_MBC_BASE(base, instance)

TRDC_MRC_BASE(base, instance)

struct _TRDC_General_Type

#include <fsl_trdc_core.h>

TRDC general configuration register definition.

Public Members

__IO uint32_t TRDC_CR

TRDC Register, offset: 0x0

__I uint32_t TRDC_HWCFG0

TRDC Hardware Configuration Register 0, offset: 0xF0

__I uint32_t TRDC_HWCFG1

TRDC Hardware Configuration Register 1, offset: 0xF4

__I uint32_t TRDC_HWCFG2

TRDC Hardware Configuration Register 2, offset: 0xF8

__I uint32_t TRDC_HWCFG3

TRDC Hardware Configuration Register 3, offset: 0xFC

__I uint8_t DACFG [8]

Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1

__IO uint32_t TRDC_IDAU_CR

TRDC IDAU Control Register, offset: 0x1C0

struct _TRDC_FLW_Type

#include <fsl_trdc_core.h>

TRDC flash logical control register definition.

Public Members

__IO uint32_t TRDC_FLW_CTL

TRDC FLW Control, offset: 0x1E0

__I uint32_t TRDC_FLW_PBASE

TRDC FLW Physical Base, offset: 0x1E4

__IO uint32_t TRDC_FLW_ABASE

TRDC FLW Array Base, offset: 0x1E8

__IO uint32_t TRDC_FLW_BCNT

TRDC FLW Block Count, offset: 0x1EC

struct _TRDC_DomainError_Type

#include <fsl_trdc_core.h>

TRDC domain error register definition.

Public Members

__IO uint32_t TRDC_FDID

TRDC Fault Domain ID, offset: 0x1FC

__I uint32_t TRDC_DERRLOC [16]

TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4

struct _TRDC_DomainAssignment_Type

#include <fsl_trdc_core.h>

TRDC master domain assignment register definition.

Public Members

__IO uint32_t PID [8]

Process Identifier, array offset: 0x700, array step: 0x4

struct _TRDC_MBC_Type

#include <fsl_trdc_core.h>

TRDC MBC control register definition.

Public Members

__I uint32_t MBC_MEM_GLBCFG [4]

MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_NSE_BLK_INDEX

MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000

__O uint32_t MBC_NSE_BLK_SET

MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000

__O uint32_t MBC_NSE_BLK_CLR

MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000

__O uint32_t MBC_NSE_BLK_CLR_ALL

MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000

__IO uint32_t MBC_MEMN_GLBAC [8]

MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W [64]

MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W [16]

MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W [8]

MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W [2]

MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4

struct _TRDC_MRC_Type

#include <fsl_trdc_core.h>

TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word].

Public Members

__I uint32_t MRC_GLBCFG

MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000

__IO uint32_t MRC_NSE_RGN_INDIRECT

MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000

__O uint32_t MRC_NSE_RGN_SET

MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000

__O uint32_t MRC_NSE_RGN_CLR

MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000

__O uint32_t MRC_NSE_RGN_CLR_ALL

MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000

__IO uint32_t MRC_GLBAC [8]

MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4

__IO uint32_t MRC_DOM0_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM0_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000

__IO uint32_t MRC_DOM1_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14140, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM1_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000

__IO uint32_t MRC_DOM2_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14240, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM2_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000

__IO uint32_t MRC_DOM3_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14340, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM3_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000

__IO uint32_t MRC_DOM4_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14440, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM4_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000

__IO uint32_t MRC_DOM5_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14540, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM5_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000

__IO uint32_t MRC_DOM6_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14640, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM6_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000

__IO uint32_t MRC_DOM7_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14740, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM7_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000

__IO uint32_t MRC_DOM8_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14840, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM8_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000

__IO uint32_t MRC_DOM9_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14940, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM9_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000

__IO uint32_t MRC_DOM10_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM10_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000

__IO uint32_t MRC_DOM11_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM11_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000

__IO uint32_t MRC_DOM12_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM12_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000

__IO uint32_t MRC_DOM13_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM13_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000

__IO uint32_t MRC_DOM14_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM14_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000

__IO uint32_t MRC_DOM15_RGD_W [16][2]

MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM15_RGD_NSE

MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000

struct MBC_DERR

Public Members

__I uint32_t W0

MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10

__I uint32_t W1

MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10

__O uint32_t W3

MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10

struct MRC_DERR

Public Members

__I uint32_t W0

MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10

__I uint32_t W1

MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10

__O uint32_t W3

MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10

union __unnamed36__

Public Members

struct _TRDC_DomainAssignment_Type MDA_DFMT0[8]

struct _TRDC_DomainAssignment_Type MDA_DFMT1[8]

struct MDA_DFMT0

Public Members

__IO uint32_t MDA_W_DFMT0 [8]

DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4

struct MDA_DFMT1

Public Members

__IO uint32_t MDA_W_DFMT1 [1]

DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4

Trdc_soc

FSL_TRDC_SOC_DRIVER_VERSION

Driver version 1.1.0.

TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)

TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x)

FSL_FEATURE_TRDC_DOMAIN_COUNT

TRDC feature.

TRDC_MBC_COUNT

TRDC base address convert macro.

TRDC_MBC_OFFSET(x)

TRDC_MBC_ARRAY_STEP

FSL_COMPONENT_ID

TRNG: True Random Number Generator

FSL_TRNG_DRIVER_VERSION

TRNG driver version 2.0.23.

Current version: 2.0.23

Change log:

• version 2.0.23

  • Updated TRNG default values for MCXA577 devices based on silicon characterization.

• version 2.0.22

  • Added support for KW43 and MCXW70 devices.

• version 2.0.21

  • Added support for MCXC devices.

• version 2.0.20

  • Added support for MCXA devices.

• version 2.0.19

  • Added support for MCXA and MCXL.

• version 2.0.18

  • TRNG health checks now done in software on RT5xx and RT6xx.

• version 2.0.17

  • Added support for RT700.

• version 2.0.16

  • Added support for Dual oscillator mode.

• version 2.0.15

  • Changed TRNG_USER_CONFIG_DEFAULT_XXX values according to latest reccomended by design team.

• version 2.0.14

  • add support for RW610 and RW612

• version 2.0.13

  • After deepsleep it might return error, added clearing bits in TRNG_GetRandomData() and generating new entropy.

  • Modified reloading entropy in TRNG_GetRandomData(), for some data length it doesn’t reloading entropy correctly.

• version 2.0.12

  • For KW34A4_SERIES, KW35A4_SERIES, KW36A4_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv8.

• version 2.0.11

  • Add clearing pending errors in TRNG_Init().

• version 2.0.10

  • Fixed doxygen issues.

• version 2.0.9

  • Fix HIS_CCM metrics issues.

• version 2.0.8

  • For K32L2A41A_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv4.

• version 2.0.7

  • Fix MISRA 2004 issue rule 12.5.

• version 2.0.6

  • For KW35Z4_SERIES set TRNG_USER_CONFIG_DEFAULT_OSC_DIV to kTRNG_RingOscDiv8.

• version 2.0.5

  • Add possibility to define default TRNG configuration by device specific preprocessor macros for FRQMIN, FRQMAX and OSCDIV.

• version 2.0.4

  • Fix MISRA-2012 issues.

• Version 2.0.3

  • update TRNG_Init to restart entropy generation

• Version 2.0.2

  • fix MISRA issues

• Version 2.0.1

  • add support for KL8x and KL28Z

  • update default OSCDIV for K81 to divide by 2

enum _trng_sample_mode

TRNG sample mode. Used by trng_config_t.

Values:

enumerator kTRNG_SampleModeVonNeumann

Use von Neumann data in both Entropy shifter and Statistical Checker.

enumerator kTRNG_SampleModeRaw

Use raw data into both Entropy shifter and Statistical Checker.

enumerator kTRNG_SampleModeVonNeumannRaw

Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker.

enum _trng_clock_mode

TRNG clock mode. Used by trng_config_t.

Values:

enumerator kTRNG_ClockModeRingOscillator

Ring oscillator is used to operate the TRNG (default).

enumerator kTRNG_ClockModeSystem

System clock is used to operate the TRNG. This is for test use only, and indeterminate results may occur.

enum _trng_ring_osc_div

TRNG ring oscillator divide. Used by trng_config_t.

Values:

enumerator kTRNG_RingOscDiv0

Ring oscillator with no divide

enumerator kTRNG_RingOscDiv2

Ring oscillator divided-by-2.

enumerator kTRNG_RingOscDiv4

Ring oscillator divided-by-4.

enumerator kTRNG_RingOscDiv8

Ring oscillator divided-by-8.

enum trng_oscillator_mode_t

TRNG oscillator mode . Used by trng_config_t.

Values:

enumerator kTRNG_SingleOscillatorModeOsc1

Single oscillator mode, using OSC1 (default)

enumerator kTRNG_DualOscillatorMode

Dual oscillator mode

enumerator kTRNG_SingleOscillatorModeOsc2

Single oscillator mode, using OSC2

typedef enum _trng_sample_mode trng_sample_mode_t

TRNG sample mode. Used by trng_config_t.

typedef enum _trng_clock_mode trng_clock_mode_t

TRNG clock mode. Used by trng_config_t.

typedef enum _trng_ring_osc_div trng_ring_osc_div_t

TRNG ring oscillator divide. Used by trng_config_t.

typedef enum trng_oscillator_mode_t trng_oscillator_mode_t

TRNG oscillator mode . Used by trng_config_t.

typedef struct _trng_statistical_check_limit trng_statistical_check_limit_t

Data structure for definition of statistical check limits. Used by trng_config_t.

typedef struct _trng_user_config trng_config_t

Data structure for the TRNG initialization.

This structure initializes the TRNG by calling the TRNG_Init() function. It contains all TRNG configurations.

status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)

Initializes the user configuration structure to default values.

This function initializes the configuration structure to default values. The default values are platform dependent.

Parameters:

• userConfig – User configuration structure.

Returns:

If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.

status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)

Initializes the TRNG.

This function initializes the TRNG. When called, the TRNG entropy generation starts immediately.

Parameters:

• base – TRNG base address

• userConfig – Pointer to the initialization configuration structure.

Returns:

If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error.

void TRNG_Deinit(TRNG_Type *base)

Shuts down the TRNG.

This function shuts down the TRNG.

Parameters:

• base – TRNG base address.

status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)

Gets random data.

This function gets random data from the TRNG.

Parameters:

• base – TRNG base address.

• data – Pointer address used to store random data.

• dataSize – Size of the buffer pointed by the data parameter.

Returns:

random data

struct _trng_statistical_check_limit

#include <fsl_trng.h>

Data structure for definition of statistical check limits. Used by trng_config_t.

Public Members

uint32_t maximum

Maximum limit.

int32_t minimum

Minimum limit.

struct _trng_user_config

#include <fsl_trng.h>

Data structure for the TRNG initialization.

This structure initializes the TRNG by calling the TRNG_Init() function. It contains all TRNG configurations.

Public Members

bool lock

Disable programmability of TRNG registers.

trng_clock_mode_t clockMode

Clock mode used to operate TRNG.

trng_ring_osc_div_t ringOscDiv

Ring oscillator divide used by TRNG.

trng_sample_mode_t sampleMode

Sample mode of the TRNG ring oscillator.

trng_oscillator_mode_t oscillatorMode

TRNG oscillator mode .

trng_ring_osc_div_t ringOsc2Div

Divider used for Ring oscillator 2.

uint16_t entropyDelay

Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken.

uint16_t sampleSize

Sample Size. Defines the total number of Entropy samples that will be taken during Entropy generation.

uint16_t sparseBitLimit

Sparse Bit Limit which defines the maximum number of consecutive samples that may be discarded before an error is generated. This limit is used only for during von Neumann sampling (enabled by TRNG_HAL_SetSampleMode()). Samples are discarded if two consecutive raw samples are both 0 or both 1. If this discarding occurs for a long period of time, it indicates that there is insufficient Entropy.

uint8_t retryCount

Retry count. It defines the number of times a statistical check may fails during the TRNG Entropy Generation before generating an error.

uint8_t longRunMaxLimit

Largest allowable number of consecutive samples of all 1, or all 0, that is allowed during the Entropy generation.

trng_statistical_check_limit_t monobitLimit

Maximum and minimum limits for statistical check of number of ones/zero detected during entropy generation.

trng_statistical_check_limit_t runBit1Limit

Maximum and minimum limits for statistical check of number of runs of length 1 detected during entropy generation.

trng_statistical_check_limit_t runBit2Limit

Maximum and minimum limits for statistical check of number of runs of length 2 detected during entropy generation.

trng_statistical_check_limit_t runBit3Limit

Maximum and minimum limits for statistical check of number of runs of length 3 detected during entropy generation.

trng_statistical_check_limit_t runBit4Limit

Maximum and minimum limits for statistical check of number of runs of length 4 detected during entropy generation.

trng_statistical_check_limit_t runBit5Limit

Maximum and minimum limits for statistical check of number of runs of length 5 detected during entropy generation.

trng_statistical_check_limit_t runBit6PlusLimit

Maximum and minimum limits for statistical check of number of runs of length 6 or more detected during entropy generation.

trng_statistical_check_limit_t pokerLimit

Maximum and minimum limits for statistical check of “Poker Test”.

trng_statistical_check_limit_t frequencyCountLimit

Maximum and minimum limits for statistical check of entropy sample frequency count.

UTICK: MictoTick Timer Driver

void UTICK_Init(UTICK_Type *base)

Initializes an UTICK by turning its bus clock on.

void UTICK_Deinit(UTICK_Type *base)

Deinitializes a UTICK instance.

This function shuts down Utick bus clock

Parameters:

• base – UTICK peripheral base address.

uint32_t UTICK_GetStatusFlags(UTICK_Type *base)

Get Status Flags.

This returns the status flag

Parameters:

• base – UTICK peripheral base address.

Returns:

status register value

void UTICK_ClearStatusFlags(UTICK_Type *base)

Clear Status Interrupt Flags.

This clears intr status flag

Parameters:

• base – UTICK peripheral base address.

Returns:

none

void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb)

Starts UTICK.

This function starts a repeat/onetime countdown with an optional callback

Parameters:

• base – UTICK peripheral base address.

• mode – UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)

• count – UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)

• cb – UTICK callback (can be left as NULL if none, otherwise should be a void func(void))

Returns:

none

void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb)

UTICK Interrupt Service Handler.

This function handles the interrupt and refers to the callback array in the driver to callback user (as per request in UTICK_SetTick()). if no user callback is scheduled, the interrupt will simply be cleared.

Parameters:

• base – UTICK peripheral base address.

• cb – callback scheduled for this instance of UTICK

Returns:

none

FSL_UTICK_DRIVER_VERSION

UTICK driver version 2.0.6.

enum _utick_mode

UTICK timer operational mode.

Values:

enumerator kUTICK_Onetime

Trigger once

enumerator kUTICK_Repeat

Trigger repeatedly

typedef enum _utick_mode utick_mode_t

UTICK timer operational mode.

typedef void (*utick_callback_t)(void)

UTICK callback function.

WUU: Wakeup Unit driver

void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config)

Enables and Configs External WakeUp Pins.

This function enables/disables the external pin as wakeup input. What’s more this function configs pins options, including edge detection wakeup event and operate mode.

Parameters:

• base – MUU peripheral base address.

• pinIndex – The index of the external input pin. See Reference Manual for the details.

• config – Pointer to wuu_external_wakeup_pin_config_t structure.

void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex)

Disable and clear external wakeup pin settings.

Parameters:

• base – MUU peripheral base address.

• pinIndex – The index of the external input pin.

static inline uint32_t WUU_GetExternalWakeUpPinsFlag(WUU_Type *base)

Gets External Wakeup pin flags.

This function return the external wakeup pin flags.

Parameters:

• base – WUU peripheral base address.

Returns:

Wakeup flags for all external wakeup pins.

static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask)

Clears External WakeUp Pin flags.

This function clears external wakeup pins flags based on the mask.

Parameters:

• base – WUU peripheral base address.

• mask – The mask of Wakeup pin index to be cleared.

void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event)

Config Internal modules’ event as the wake up soures.

This function configs the internal modules event as the wake up sources.

Parameters:

• base – WUU peripheral base address.

• moduleIndex – The selected internal module. See the Reference Manual for the details.

• event – Select interrupt or DMA/Trigger of the internal module as the wake up source.

void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event)

Disable an on-chip internal modules’ event as the wakeup sources.

Parameters:

• base – WUU peripheral base address.

• moduleIndex – The selected internal module. See the Reference Manual for the details.

• event – The event(interrupt or DMA/trigger) of the internal module to disable.

static inline uint32_t WUU_GetModuleInterruptFlag(WUU_Type *base)

Get wakeup flags for internal wakeup modules.

Parameters:

• base – WUU peripheral base address.

Returns:

Wakeup flags for all internal wakeup modules.

static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t moduleIndex)

Gets the internal module wakeup source flag.

This function checks the flag to detect whether the system is woken up by specific on-chip module interrupt.

Parameters:

• base – WWU peripheral base address.

• moduleIndex – A module index, which starts from 0.

Returns:

True if the specific pin is a wake up source.

void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config)

Configs and Enables Pin filters.

This function configs Pin filter, including pin select, filer operate mode filer wakeup event and filter edge detection.

Parameters:

• base – WUU peripheral base address.

• filterIndex – The index of the pin filer.

• config – Pointer to wuu_pin_filter_config_t structure.

bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex)

Gets the pin filter configuration.

This function gets the pin filter flag.

Parameters:

• base – WUU peripheral base address.

• filterIndex – A pin filter index, which starts from 1.

Returns:

True if the flag is a source of the existing low-leakage power mode.

void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex)

Clears the pin filter configuration.

This function clears the pin filter flag.

Parameters:

• base – WUU peripheral base address.

• filterIndex – A pin filter index to clear the flag, starting from 1.

bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex)

brief Gets the external wakeup source flag.

This function checks the external pin flag to detect whether the MCU is woken up by the specific pin.

param base WUU peripheral base address. param pinIndex A pin index, which starts from 0. return True if the specific pin is a wakeup source.

void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex)

brief Clears the external wakeup source flag.

This function clears the external wakeup source flag for a specific pin.

param base WUU peripheral base address. param pinIndex A pin index, which starts from 0.

FSL_WUU_DRIVER_VERSION

Defines WUU driver version 2.4.2.

enum _wuu_external_pin_edge_detection

External WakeUp pin edge detection enumeration.

Values:

enumerator kWUU_ExternalPinDisable

External input Pin disabled as wake up input.

enumerator kWUU_ExternalPinRisingEdge

External input Pin enabled with the rising edge detection.

enumerator kWUU_ExternalPinFallingEdge

External input Pin enabled with the falling edge detection.

enumerator kWUU_ExternalPinAnyEdge

External input Pin enabled with any change detection.

enum _wuu_external_wakeup_pin_event

External input wake up pin event enumeration.

Values:

enumerator kWUU_ExternalPinInterrupt

External input Pin configured as interrupt.

enumerator kWUU_ExternalPinDMARequest

External input Pin configured as DMA request.

enumerator kWUU_ExternalPinTriggerEvent

External input Pin configured as Trigger event.

enum _wuu_external_wakeup_pin_mode

External input wake up pin mode enumeration.

Values:

enumerator kWUU_ExternalPinActiveDSPD

External input Pin is active only during Deep Sleep/Power Down Mode. NOTE: This enumerations has been deprecated, please switch to kWUU_ExternalPinActiveLowLeakage.

enumerator kWUU_ExternalPinActiveLowLeakageMode

External input Pin is active only during low-leakage power modes.

enumerator kWUU_ExternalPinActiveAlways

External input Pin is active during all power modes.

enum _wuu_internal_wakeup_module_event

Internal module wake up event enumeration.

Values:

enumerator kWUU_InternalModuleInterrupt

Internal modules’ interrupt as a wakeup source.

enumerator kWUU_InternalModuleDMATrigger

Internal modules’ DMA/Trigger as a wakeup source.

enum _wuu_filter_edge

Pin filter edge enumeration.

Values:

enumerator kWUU_FilterDisabled

Filter disabled.

enumerator kWUU_FilterPosedgeEnable

Filter posedge detect enabled.

enumerator kWUU_FilterNegedgeEnable

Filter negedge detect enabled.

enumerator kWUU_FilterAnyEdge

Filter any edge detect enabled.

enum _wuu_filter_event

Pin Filter event enumeration.

Values:

enumerator kWUU_FilterInterrupt

Filter output configured as interrupt.

enumerator kWUU_FilterDMARequest

Filter output configured as DMA request.

enumerator kWUU_FilterTriggerEvent

Filter output configured as Trigger event.

enum _wuu_filter_mode

Pin filter mode enumeration.

Values:

enumerator kWUU_FilterActiveDSPD

External input pin filter is active only during Deep Sleep/Power Down Mode. NOTE: This enumerations has been deprecated, please switch to kWUU_FilterActiveLowLeakage.

enumerator kWUU_FilterActiveLowLeakageMode

External input pin filter is active only during low-leakage power modes.

enumerator kWUU_FilterActiveAlways

External input Pin filter is active during all power modes.

typedef enum _wuu_external_pin_edge_detection wuu_external_pin_edge_detection_t

External WakeUp pin edge detection enumeration.

typedef enum _wuu_external_wakeup_pin_event wuu_external_wakeup_pin_event_t

External input wake up pin event enumeration.

typedef enum _wuu_external_wakeup_pin_mode wuu_external_wakeup_pin_mode_t

External input wake up pin mode enumeration.

typedef enum _wuu_internal_wakeup_module_event wuu_internal_wakeup_module_event_t

Internal module wake up event enumeration.

typedef enum _wuu_filter_edge wuu_filter_edge_t

Pin filter edge enumeration.

typedef enum _wuu_filter_event wuu_filter_event_t

Pin Filter event enumeration.

typedef enum _wuu_filter_mode wuu_filter_mode_t

Pin filter mode enumeration.

typedef struct _wuu_external_wakeup_pin_config wuu_external_wakeup_pin_config_t

External WakeUp pin configuration.

typedef struct _wuu_pin_filter_config wuu_pin_filter_config_t

Pin Filter configuration.

struct _wuu_external_wakeup_pin_config

#include <fsl_wuu.h>

External WakeUp pin configuration.

Public Members

wuu_external_pin_edge_detection_t edge

External Input pin edge detection.

wuu_external_wakeup_pin_event_t event

External Input wakeup Pin event

wuu_external_wakeup_pin_mode_t mode

External Input wakeup Pin operate mode.

struct _wuu_pin_filter_config

#include <fsl_wuu.h>

Pin Filter configuration.

Public Members

uint32_t pinIndex

The index of wakeup pin to be muxxed into filter.

wuu_filter_edge_t edge

The edge of the pin digital filter.

wuu_filter_event_t event

The event of the filter output.

wuu_filter_mode_t mode

The mode of the filter operate.

WWDT: Windowed Watchdog Timer Driver

void WWDT_GetDefaultConfig(wwdt_config_t *config)

Initializes WWDT configure structure.

This function initializes the WWDT configure structure to default value. The default value are:

config->enableWwdt = true;
config->enableWatchdogReset = false;
config->enableWatchdogProtect = false;
config->enableLockOscillator = false;
config->windowValue = 0xFFFFFFU;
config->timeoutValue = 0xFFFFFFU;
config->warningValue = 0;

See also

wwdt_config_t

Parameters:

• config – Pointer to WWDT config structure.

void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)

Initializes the WWDT.

This function initializes the WWDT. When called, the WWDT runs according to the configuration.

Example:

wwdt_config_t config;
WWDT_GetDefaultConfig(&config);
config.timeoutValue = 0x7ffU;
WWDT_Init(wwdt_base,&config);

Parameters:

• base – WWDT peripheral base address

• config – The configuration of WWDT

void WWDT_Deinit(WWDT_Type *base)

Shuts down the WWDT.

This function shuts down the WWDT.

Parameters:

• base – WWDT peripheral base address

static inline void WWDT_Enable(WWDT_Type *base)

Enables the WWDT module.

This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.

Parameters:

• base – WWDT peripheral base address

static inline void WWDT_Disable(WWDT_Type *base)

Disables the WWDT module.

Deprecated:

Do not use this function. It will be deleted in next release version, for once the bit field of WDEN written with a 1, it can not be re-written with a 0.

This function write value into WWDT_MOD register to disable the WWDT.

Parameters:

• base – WWDT peripheral base address

static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)

Gets all WWDT status flags.

This function gets all status flags.

Example for getting Timeout Flag:

uint32_t status;
status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;

Parameters:

• base – WWDT peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration _wwdt_status_flags_t

void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)

Clear WWDT flag.

This function clears WWDT status flag.

Example for clearing warning flag:

WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);

Parameters:

• base – WWDT peripheral base address

• mask – The status flags to clear. This is a logical OR of members of the enumeration _wwdt_status_flags_t

static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)

Set the WWDT warning value.

The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter is no longer greater than the value defined by WARNINT, an interrupt will be generated after the subsequent WDCLK.

Parameters:

• base – WWDT peripheral base address

• warningValue – WWDT warning value.

static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)

Set the WWDT timeout value.

This function sets the timeout value. Every time a feed sequence occurs the value in the TC register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change the timeout value before the watchdog counter is below the warning and window values will cause a watchdog reset and set the WDTOF flag.

Parameters:

• base – WWDT peripheral base address

• timeoutCount – WWDT timeout value, count of WWDT clock tick.

static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)

Sets the WWDT window value.

The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer value) so windowing is not in effect.

Parameters:

• base – WWDT peripheral base address

• windowValue – WWDT window value.

void WWDT_Refresh(WWDT_Type *base)

Refreshes the WWDT timer.

This function feeds the WWDT. This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.

Parameters:

• base – WWDT peripheral base address

FSL_WWDT_DRIVER_VERSION

Defines WWDT driver version.

WWDT_FIRST_WORD_OF_REFRESH

First word of refresh sequence

WWDT_SECOND_WORD_OF_REFRESH

Second word of refresh sequence

enum _wwdt_status_flags_t

WWDT status flags.

This structure contains the WWDT status flags for use in the WWDT functions.

Values:

enumerator kWWDT_TimeoutFlag

Time-out flag, set when the timer times out

enumerator kWWDT_WarningFlag

Warning interrupt flag, set when timer is below the value WDWARNINT

typedef struct _wwdt_config wwdt_config_t

Describes WWDT configuration structure.

struct _wwdt_config

#include <fsl_wwdt.h>

Describes WWDT configuration structure.

Public Members

bool enableWwdt

Enables or disables WWDT

bool enableWatchdogReset

true: Watchdog timeout will cause a chip reset false: Watchdog timeout will not cause a chip reset

bool enableWatchdogProtect

true: Enable watchdog protect i.e timeout value can only be changed after counter is below warning & window values false: Disable watchdog protect; timeout value can be changed at any time

uint32_t windowValue

Window value, set this to 0xFFFFFF if windowing is not in effect

uint32_t timeoutValue

Timeout value

uint32_t warningValue

Watchdog time counter value that will generate a warning interrupt. Set this to 0 for no warning

uint32_t clockFreq_Hz

Watchdog clock source frequency.