MCXC353#

AOI: Crossbar AND/OR/INVERT Driver#

void AOI_Init(AOI_Type *base)#

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)#

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)#

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Index of the event which will be set of type aoi_event_t.
config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)#

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Event which will be configured of type aoi_event_t.
eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION#: Version 2.0.2.

enum _aoi_input_config#

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero#: Forces the input to logical zero.

enumerator kAOI_InputSignal#: Passes the input signal.

enumerator kAOI_InvInputSignal#: Inverts the input signal.

enumerator kAOI_LogicOne#: Forces the input to logical one.

enum _aoi_event#

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0#: Event 0 index

enumerator kAOI_Event1#: Event 1 index

enumerator kAOI_Event2#: Event 2 index

enumerator kAOI_Event3#: Event 3 index

typedef enum _aoi_input_config aoi_input_config_t#

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t#: AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t#

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI#: AOI peripheral address

struct _aoi_event_config#

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC#: Product term 0 input A

aoi_input_config_t PT0BC#: Product term 0 input B

aoi_input_config_t PT0CC#: Product term 0 input C

aoi_input_config_t PT0DC#: Product term 0 input D

aoi_input_config_t PT1AC#: Product term 1 input A

aoi_input_config_t PT1BC#: Product term 1 input B

aoi_input_config_t PT1CC#: Product term 1 input C

aoi_input_config_t PT1DC#: Product term 1 input D

aoi_input_config_t PT2AC#: Product term 2 input A

aoi_input_config_t PT2BC#: Product term 2 input B

aoi_input_config_t PT2CC#: Product term 2 input C

aoi_input_config_t PT2DC#: Product term 2 input D

aoi_input_config_t PT3AC#: Product term 3 input A

aoi_input_config_t PT3BC#: Product term 3 input B

aoi_input_config_t PT3CC#: Product term 3 input C

aoi_input_config_t PT3DC#: Product term 3 input D

CRC: Cyclic Redundancy Check Driver#

FSL_CRC_DRIVER_VERSION#

CRC driver version. Version 2.1.0.

Current version: 2.1.0

Change log:

Version 2.1.0
- Choosing CRC clocks from CRC clock array according to instance instead of hardcoded value.
Version 2.0.5
- Fix CERT-C issue with boolean-to-unsigned integer conversion.
Version 2.0.4
- Release peripheral from reset if necessary in init function.
Version 2.0.3
- Fix MISRA issues
Version 2.0.2
- Fix MISRA issues
Version 2.0.1
- move DATA and DATALL macro definition from header file to source file

enum _crc_bits#

CRC bit width.

Values:

enumerator kCrcBits16#: Generate 16-bit CRC code

enumerator kCrcBits32#: Generate 32-bit CRC code

enum _crc_result#

CRC result type.

Values:

enumerator kCrcFinalChecksum#: CRC data register read value is the final checksum. Reflect out and final xor protocol features are applied.

enumerator kCrcIntermediateChecksum#: CRC data register read value is intermediate checksum (raw value). Reflect out and final xor protocol feature are not applied. Intermediate checksum can be used as a seed for CRC_Init() to continue adding data to this checksum.

typedef enum _crc_bits crc_bits_t#: CRC bit width.

typedef enum _crc_result crc_result_t#: CRC result type.

typedef struct _crc_config crc_config_t#

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

void CRC_Init(CRC_Type *base, const crc_config_t *config)#

Enables and configures the CRC peripheral module.

This function enables the clock gate in the SIM module for the CRC peripheral. It also configures the CRC module and starts a checksum computation by writing the seed.

Parameters:

base – CRC peripheral address.
config – CRC module configuration structure.

void CRC_Deinit(CRC_Type *base)#

Disables the CRC peripheral module.

This function disables the clock gate in the SIM module for the CRC peripheral.

Parameters:

base – CRC peripheral address.

void CRC_GetDefaultConfig(crc_config_t *config)#

Loads default values to the CRC protocol configuration structure.

Loads default values to the CRC protocol configuration structure. The default values are as follows.

config->polynomial = 0x1021;
config->seed = 0xFFFF;
config->reflectIn = false;
config->reflectOut = false;
config->complementChecksum = false;
config->crcBits = kCrcBits16;
config->crcResult = kCrcFinalChecksum;

Parameters:

config – CRC protocol configuration structure.

void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)#

Writes data to the CRC module.

Writes input data buffer bytes to the CRC data register. The configured type of transpose is applied.

Parameters:

base – CRC peripheral address.
data – Input data stream, MSByte in data[0].
dataSize – Size in bytes of the input data buffer.

uint32_t CRC_Get32bitResult(CRC_Type *base)#

Reads the 32-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

base – CRC peripheral address.

Returns:

An intermediate or the final 32-bit checksum, after configured transpose and complement operations.

uint16_t CRC_Get16bitResult(CRC_Type *base)#

Reads a 16-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

base – CRC peripheral address.

Returns:

An intermediate or the final 16-bit checksum, after configured transpose and complement operations.

CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT#: Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault.

struct _crc_config#

#include <fsl_crc.h>

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

Public Members

uint32_t polynomial#: CRC Polynomial, MSBit first. Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1

uint32_t seed#: Starting checksum value

bool reflectIn#: Reflect bits on input.

bool reflectOut#: Reflect bits on output.

bool complementChecksum#: True if the result shall be complement of the actual checksum.

crc_bits_t crcBits#: Selects 16- or 32- bit CRC protocol.

crc_result_t crcResult#: Selects final or intermediate checksum return from CRC_Get16bitResult() or CRC_Get32bitResult()

DualADC: Dual Analog-to-Digital Converter#

uint32_t DUALADC_GetInstance(DADC_Type *base)#

Get the instance for DualADC module.

Parameters:

base – DualADC base address

Returns:

Instance number if valid base address is provided, otherwise returns 0xFFFFFFFF

void DUALADC_GetDefaultConfig(dadc_config_t *config)#

Populate a dadc_config_t with reset-state defaults.

Defaults applied:

Cooperation mode
Low power (max 24 MHz ADCK)
Analog pre-enable disabled
VREFH0x reference voltage
Power-up delay count: 0x80 (adjust per device tADCSTUP specification)
Right-justified result
High-speed mode disabled
Tune mode 1
Doze: ADC continues converting through system low-power entry (DOZEN = 0)
Normal calibration sample time (3.5 ADCK cycles)
256-average calibration (RM recommended minimum)

Parameters:

config – Pointer to the configuration structure to populate. Must not be NULL.

status_t DUALADC_Init(DADC_Type *base, const dadc_config_t *config)#

Initialize the DualADC module.

Initialization sequence:

Enable the peripheral clock.
Release the peripheral reset (if supported by the platform).
Assert then release software reset for ADCA and ADCB (CTRL[RSTA]/CTRL[RSTB]).
Configure CFG0 via read-modify-write.
Configure CFG1 via read-modify-write.
Configure CTRL fields (DOZEN, CST_LONG, CAL_AVGS) via read-modify-write.

On return the ADC is enabled and ready for calibration or conversion.

Parameters:

base – DualADC peripheral base address.
config – Pointer to the initialization configuration. Must not be NULL.

Return values:

kStatus_Success – Initialization succeeded.
kStatus_InvalidArgument – base is not a valid DualADC peripheral address.
kStatus_Timeout – Reset operation times out.

status_t DUALADC_DeInit(DADC_Type *base)#

Deinitialize the DualADC module.

Clears CTRL[ADCEN] to terminate any active conversion, gates the peripheral clock, and asserts the peripheral reset (if supported by the platform).

Parameters:

base – DualADC peripheral base address.

Return values:

kStatus_Success – Deinitialization succeeded.
kStatus_InvalidArgument – base is not a valid DualADC peripheral address.

status_t DUALADC_DoCalibration(DADC_Type *base)#

Perform all DualADC calibration routines.

Executes in order:

Offset calibration (CTRL[CALOFS]) - updates OFSTRIM.
High-speed calibration (CTRL[CALHS]) - only when CFG1[HS] is set; updates HSTRIM.
Gain and linearity calibration (CTRL[CAL_REQ]) - polls GCC[0/1].RDY, computes the 17-bit fixed-point gain result, writes GCR[0/1], and waits for STAT0[CAL_RDY].

Must be called after DUALADC_Enable to ensure ADC enabled. CTRL[CAL_AVGS] (set in DUALADC_Init) applies to all three calibration steps.

Parameters:

base – DualADC peripheral base address.

Return values:

kStatus_Success – All calibration steps completed successfully.
kStatus_Timeout – A calibration poll loop exceeded DUALADC_CALIBRATION_TIMEOUT iterations (only possible when the timeout is non-zero).

void DUALADC_SetCalibrationValue(DADC_Type *base, const dadc_calibration_value_t *ptrCalibrationValue)#

Restore calibration registers from a previously saved dadc_calibration_value_t.

Writes OFSTRIM, HSTRIM, CAL_GAR[0..32], CAL_GBR[0..32], GCR[0], and GCR[1] from the supplied structure. GCR[n].RDY is set automatically so the hardware uses the restored values. CTRL[ADCEN] is cleared before writing and restored afterwards. No CAL_RDY polling is performed.

Parameters:

base – DualADC peripheral base address.
ptrCalibrationValue – Pointer to the calibration value structure to restore. Must not be NULL.

void DUALADC_GetDefaultConversionCommandConfig(dadc_cmd_config_t *config)#

Populate a dadc_cmd_config_t with reset-state defaults.

Defaults applied:

Single-ended A-side conversion
Standard resolution (12-bit)
Minimum sample time (3.5 ADCK)
No hardware averaging
Channel 0, no alternate B-channel
Compare disabled, wait-trigger disabled

Parameters:

config – Pointer to the command configuration structure. Must not be NULL.

void DUALADC_ConfigConversionCommand(DADC_Type *base, uint32_t index, const dadc_cmd_config_t *config)#

Configure a DualADC conversion command buffer entry.

CMD[CDIS] is not touched; use DUALADC_SetConversionSequenceEndCommand to set the sequence terminator separately.

Parameters:

base – DualADC peripheral base address.
index – Command buffer index, range 1-20 (maps to CMD[0]-CMD[19]).
config – Pointer to the command configuration.

static inline void DUALADC_SetConversionSequenceEndCommand(DADC_Type *base, uint32_t index)#

Mark a command buffer entry as the conversion sequence terminator.

Sets CMD[CDIS] for index. The conversion sequence ends after the previous command is executed; index itself is not executed. If CMD1 is marked as the sequence end, the sequence will not start.

Parameters:

base – DualADC peripheral base address.
index – Command buffer index, range 1-20.

void DUALADC_GetDefaultAverageTimerConfig(dadc_avgt_config_t *config)#

Populate a dadc_avgt_config_t with reset-state defaults.

Defaults: average-with-timer disabled for both ADCA and ADCB; repeat count 1; interval 0; prescaler *1.

Parameters:

config – Pointer to the configuration structure to populate. Must not be NULL.

void DUALADC_ConfigAverageTimer(DADC_Type *base, const dadc_avgt_config_t *config)#

Configure the average-with-timer feature.

Writes AVGT_CTRL and ITCFG registers via read-modify-write. In cooperation mode the ADCB fields in config are written to hardware but ignored; in independence mode both sets are independent.

Parameters:

base – DualADC peripheral base address.
config – Pointer to the average-with-timer configuration. Must not be NULL.

static inline void DUALADC_Enable(DADC_Type *base)#

Enable the DualADC module.

Call this after DUALADC_Init when the application is ready to start the ADC.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_Disable(DADC_Type *base)#

Disable the DualADC module.

The peripheral clock and configuration registers are preserved; call DUALADC_Enable to restart the ADC without re-initializing.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_GetConversionResult(DADC_Type *base, uint32_t index, dadc_conversion_result_t *result)#

Read the conversion result for a command buffer entry.

Reads RSLT[index-1] once and populates all three members of result. Reading the result register automatically clears the corresponding RSLTRDY_STAT bit.

Parameters:

base – DualADC peripheral base address.
index – Command buffer index, range 1-20.
result – Pointer to the result structure to populate. Must not be NULL.

static inline void DUALADC_SetSoftwareTrigger(DADC_Type *base, uint32_t mask)#

Assert one or both software triggers.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_software_trigger_t values.

static inline void DUALADC_EnableDmaA(DADC_Type *base)#

Enable the DMA request for ADCA.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_DisableDmaA(DADC_Type *base)#

Disable the DMA request for ADCA.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_EnableDmaB(DADC_Type *base)#

Enable the DMA request for ADCB (independence mode only).

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_DisableDmaB(DADC_Type *base)#

Disable the DMA request for ADCB.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_ResetADCA(DADC_Type *base)#

Assert the software reset for ADCA (CTRL[RSTA]).

Note

CTRL[RSTA] is NOT self-clearing. After asserting reset, the logic high level must be held for more than 2 ADC functional clock cycles before invoking DUALADC_ReleaseResetADCA to release it explicitly.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_ReleaseResetADCA(DADC_Type *base)#

Release the software reset for ADCA by clearing CTRL[RSTA].

Note

Must be called after the reset has been held for more than 2 ADC functional clock cycles, see DUALADC_ResetADCA.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_ResetADCB(DADC_Type *base)#

Assert the software reset for ADCB (CTRL[RSTB]).

Note

CTRL[RSTB] is NOT self-clearing. After asserting reset, the logic high level must be held for more than 2 ADC functional clock cycles before invoking DUALADC_ReleaseResetADCB to release it explicitly.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_ReleaseResetADCB(DADC_Type *base)#

Release the software reset for ADCB by clearing CTRL[RSTB].

Note

Must be called after the reset has been held for more than 2 ADC functional clock cycles, see DUALADC_ResetADCB.

Parameters:

base – DualADC peripheral base address.

static inline void DUALADC_EnableInterrupts(DADC_Type *base, uint32_t mask)#

Enable DualADC interrupts in the IE register.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_interrupt_t values.

static inline void DUALADC_DisableInterrupts(DADC_Type *base, uint32_t mask)#

Disable DualADC interrupts in the IE register.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_interrupt_t values.

static inline void DUALADC_EnableResultReadyInterrupts(DADC_Type *base, uint32_t mask)#

Enable result-ready interrupts for one or more command buffers.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_cmd_mask_t values.

static inline void DUALADC_DisableResultReadyInterrupts(DADC_Type *base, uint32_t mask)#

Disable result-ready interrupts for one or more command buffers.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_cmd_mask_t values.

static inline void DUALADC_EnableCompareInterrupts(DADC_Type *base, uint32_t mask)#

Enable compare interrupts for one or more command buffers.

The compare interrupt fires when a command’s conversion result satisfies the compare condition (CMD[CMPEN] must also be set for that command buffer).

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_cmd_mask_t values.

static inline void DUALADC_DisableCompareInterrupts(DADC_Type *base, uint32_t mask)#

Disable compare interrupts for one or more command buffers.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_cmd_mask_t values.

static inline uint32_t DUALADC_GetScanSequenceStatusFlags(DADC_Type *base)#

Get scan sequence completion status flags for ADCA and ADCB (STAT2[EOSI]).

Returns the OR-combination of STAT2[EOSIA] and STAT2[EOSIB]. Test the return value against kDADC_EndofScanAFlag and kDADC_EndofScanBFlag.

Parameters:

base – DualADC peripheral base address.

Returns:

OR combination of asserted end-of-scan flag bits from dadc_scan_seq_status_flag_t.

static inline void DUALADC_ClearScanSequenceStatusFlags(DADC_Type *base, uint32_t mask)#

Clear scan sequence completion status flags for ADCA and ADCB (STAT2[EOSI]).

Writes 1 to the selected STAT2[EOSIA/B] bits to clear them. Bits not present in mask are not affected.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of kDADC_EndofScanAFlag and/or kDADC_EndofScanBFlag.

static inline uint32_t DUALADC_GetErrorStatusFlags(DADC_Type *base)#

Get error status flags for ADCA and ADCB (STAT1).

Returns the OR-combination of STAT1[INTVTIMEERR_FLAGA/B] and STAT1[OVERLAP_FLAGA/B]. Test the return value against kDADC_OverlapAFlag, kDADC_OverlapBFlag, kDADC_IntervalErrAFlag, and kDADC_IntervalErrBFlag.

Parameters:

base – DualADC peripheral base address.

Returns:

OR combination of asserted error flag bits from dadc_error_status_flag_t.

static inline void DUALADC_ClearErrorStatusFlags(DADC_Type *base, uint32_t mask)#

Clear error status flags for ADCA and ADCB (STAT1).

Writes 1 to the selected STAT1[INTVTIMEERR_FLAG] and STAT1[OVERLAP_FLAG] bits to clear them. Bits not present in mask are not affected.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_error_status_flag_t values.

static inline uint32_t DUALADC_GetStatusFlags(DADC_Type *base)#

Get general read-only status flags for ADCA and ADCB (STAT0 and STAT2[STARTUPSTS]).

Returns the OR-combination of:

STAT0[ADC_ACTIVEA], STAT0[ADC_ACTIVEB] - conversion in progress indicators
STAT0[CAL_RDY] - calibration complete
STAT2[STARTUPSTSA], STAT2[STARTUPSTSB] - analog startup complete

All flags are read-only; none can be cleared by software. Test the return value against kDADC_AdcActiveAFlag, kDADC_AdcActiveBFlag, kDADC_CalibrationReadyFlag, kDADC_StartupDoneAFlag, and kDADC_StartupDoneBFlag.

Parameters:

base – DualADC peripheral base address.

Returns:

OR combination of asserted general status flag bits from dadc_status_flag_t.

static inline uint32_t DUALADC_GetActiveCommandA(DADC_Type *base)#

Get the command buffer index currently executing in ADCA (0 = idle).

Parameters:

base – DualADC peripheral base address.

Returns:

Active command index for ADCA (0~20).

static inline uint32_t DUALADC_GetActiveCommandB(DADC_Type *base)#

Get the command buffer index currently executing in ADCB (0 = idle).

Parameters:

base – DualADC peripheral base address.

Returns:

Active command index for ADCB (0~20).

static inline uint32_t DUALADC_GetAvgTimerStatusA(DADC_Type *base)#

Get the average-with-timer remaining repeat count for ADCA.

Parameters:

base – DualADC peripheral base address.

Returns:

Remaining sequence repeat count for ADCA.

static inline uint32_t DUALADC_GetAvgTimerStatusB(DADC_Type *base)#

Get the average-with-timer remaining repeat count for ADCB.

Parameters:

base – DualADC peripheral base address.

Returns:

Remaining sequence repeat count for ADCB.

static inline uint32_t DUALADC_GetOverlapCommandA(DADC_Type *base)#

Get the command index that was executing when a trigger overlap occurred for ADCA.

Note

Valid only when kDADC_OverlapAFlag is asserted.

Parameters:

base – DualADC peripheral base address.

Returns:

Command index that was active during the overlap event (1~20).

static inline uint32_t DUALADC_GetOverlapCommandB(DADC_Type *base)#

Get the command index that was executing when a trigger overlap occurred for ADCB.

Note

Valid only when kDADC_OverlapBFlag is asserted.

Parameters:

base – DualADC peripheral base address.

Returns:

Command index that was active during the overlap event (1~20).

static inline uint32_t DUALADC_GetIntervalErrCommandA(DADC_Type *base)#

Get the command index executing when an interval timer error occurred for ADCA.

Note

Valid only when kDADC_IntervalErrAFlag is asserted.

Parameters:

base – DualADC peripheral base address.

Returns:

Command index that was active during the interval error (1~20).

static inline uint32_t DUALADC_GetIntervalErrCommandB(DADC_Type *base)#

Get the command index executing when an interval timer error occurred for ADCB.

Note

Valid only when kDADC_IntervalErrBFlag is asserted.

Parameters:

base – DualADC peripheral base address.

Returns:

Command index that was active during the interval error (1~20).

static inline uint32_t DUALADC_GetCompareStatusFlags(DADC_Type *base)#

Get the compare status flags for all command buffers.

Parameters:

base – DualADC peripheral base address.

Returns:

Bitmask of compare results; use dadc_cmd_mask_t to check individual commands.

static inline void DUALADC_ClearCompareStatusFlags(DADC_Type *base, uint32_t mask)#

Clear compare status flags for one or more command buffers.

Parameters:

base – DualADC peripheral base address.
mask – OR combination of dadc_cmd_mask_t values to clear.

static inline uint32_t DUALADC_GetResultReadyFlags(DADC_Type *base)#

Get the result-ready flags for all command buffers.

Each bit indicates a conversion result is available in the corresponding RSLT register. Flags clear automatically when the associated RSLT register is read by DUALADC_GetConversionResult.

Parameters:

base – DualADC peripheral base address.

Returns:

Bitmask of ready results; use dadc_cmd_mask_t to check individual commands.

FSL_DUAL_ADC_DRIVER_VERSION#: Version 2.0.0

enum _dadc_conversion_mode#

DualADC conversion mode selection.

Controls whether ADCA and ADCB share one conversion sequence (cooperation) or run independent sequences (independence).

Values:

enumerator kDADC_CooperationMode#: Cooperation mode: ADCA and ADCB share one conversion sequence.

enumerator kDADC_IndependenceMode#: Independence mode: ADCA and ADCB run independent sequences.

enum _dadc_power_config#

DualADC power configuration.

Selects the power and maximum ADCK frequency trade-off.

Values:

enumerator kDADC_LowPowerConfig#: Low power mode: maximum ADCK frequency 24 MHz (default).

enumerator kDADC_HighPowerConfig#: High power mode: maximum ADCK frequency 64 MHz.

enum _dadc_ref_voltage_src#

DualADC voltage reference source selection.

Values:

enumerator kDADC_VrefH0#: VREFH0x - default reference.

enumerator kDADC_VrefH1#: VREFH1x.

enumerator kDADC_VrefH2#: VREFH2x.

enum _dadc_tune_mode#

DualADC tune mode selection.

Note

Consult the device-specific reference manual for the effect of each value.

Values:

enumerator kDADC_TuneMode0#: Tune mode 0.

enumerator kDADC_TuneMode1#: Tune mode 1.

enumerator kDADC_TuneMode2#: Tune mode 2.

enum _dadc_calibration_averages#

Number of ADC conversions averaged during calibration routines.

Applied to offset calibration (CTRL[CALOFS]), high-speed calibration (CTRL[CALHS]), and gain calibration (CTRL[CAL_REQ]). The recommended minimum is kDADC_CalibrationAverage256.

Values:

enumerator kDADC_CalibrationAverageSingle#: Single conversion - no averaging.

enumerator kDADC_CalibrationAverage2#: 2 conversions averaged.

enumerator kDADC_CalibrationAverage4#: 4 conversions averaged.

enumerator kDADC_CalibrationAverage8#: 8 conversions averaged.

enumerator kDADC_CalibrationAverage16#: 16 conversions averaged.

enumerator kDADC_CalibrationAverage32#: 32 conversions averaged.

enumerator kDADC_CalibrationAverage64#: 64 conversions averaged.

enumerator kDADC_CalibrationAverage128#: 128 conversions averaged.

enumerator kDADC_CalibrationAverage256#: 256 conversions averaged (RM recommended minimum).

enumerator kDADC_CalibrationAverage512#: 512 conversions averaged.

enumerator kDADC_CalibrationAverage1024#: 1024 conversions averaged.

enum _dadc_trig_sel#

DualADC trigger source selection for ADCA (CFG0[TRIGSEL]).

Values:

enumerator kDADC_TrigSelTrigger0#: Trigger0 input.

enumerator kDADC_TrigSelTriggerSyncIn#: Trigger_sync_in input.

enum _dadc_dma_src#

DualADC DMA trigger source selection (DE[DMASRCA/B]).

Values:

enumerator kDADC_DmaSrcEndOfScan#: DMA triggered by end-of-scan; cleared by DMA ack.

enumerator kDADC_DmaSrcResultReady#: DMA triggered by result-ready; cleared by reading RSLT.

enum _dadc_software_trigger#

DualADC software trigger selection mask.

Values may be OR’d together to assert Trigger0 and Trigger1 simultaneously. In cooperation mode Trigger0 starts both ADCA and ADCB; Trigger1 is unused. In independence mode Trigger0 starts ADCA and Trigger1 starts ADCB.

Values:

enumerator kDADC_SoftwareTrigger0#: Software Trigger0: ADCA (ADCA+ADCB in cooperation mode).

enumerator kDADC_SoftwareTrigger1#: Software Trigger1: ADCB (independence mode only).

enum _dadc_conversion_type#

DualADC conversion type selection (CMD[CTYPE]).

Values:

enumerator kDADC_ConversionSingleEndedA#: Single-ended, A-side channel only.

enumerator kDADC_ConversionSingleEndedB#: Single-ended, B-side channel only.

enumerator kDADC_ConversionDifferential#: Differential mode (A minus B).

enumerator kDADC_ConversionDualSingleEnded#: Dual single-ended: A and B sides converted independently.

enum _dadc_resolution#

DualADC conversion resolution selection (CMD[MODE]).

Values:

enumerator kDADC_ResolutionStandard#: Standard: 12-bit single-ended or 13-bit differential.

enumerator kDADC_ResolutionHigh#: High: 16-bit single-ended or differential.

enum _dadc_sample_time#

DualADC sample time selection in ADCK cycles (CMD[STS]).

Values:

enumerator kDADC_SampleTime3_5#: 3.5 ADCK cycles (minimum sample time).

enumerator kDADC_SampleTime5_5#: 5.5 ADCK cycles.

enumerator kDADC_SampleTime7_5#: 7.5 ADCK cycles.

enumerator kDADC_SampleTime11_5#: 11.5 ADCK cycles.

enumerator kDADC_SampleTime19_5#: 19.5 ADCK cycles.

enumerator kDADC_SampleTime35_5#: 35.5 ADCK cycles.

enumerator kDADC_SampleTime67_5#: 67.5 ADCK cycles.

enumerator kDADC_SampleTime131_5#: 131.5 ADCK cycles (maximum sample time).

enum _dadc_hardware_averages#

DualADC hardware averaging count for conversions (CMD[AVGS]).

Values:

enumerator kDADC_HardwareAverageSingle#: Single conversion, no averaging.

enumerator kDADC_HardwareAverage2#: 2 conversions averaged.

enumerator kDADC_HardwareAverage4#: 4 conversions averaged.

enumerator kDADC_HardwareAverage8#: 8 conversions averaged.

enumerator kDADC_HardwareAverage16#: 16 conversions averaged.

enumerator kDADC_HardwareAverage32#: 32 conversions averaged.

enumerator kDADC_HardwareAverage64#: 64 conversions averaged.

enumerator kDADC_HardwareAverage128#: 128 conversions averaged.

enumerator kDADC_HardwareAverage256#: 256 conversions averaged.

enumerator kDADC_HardwareAverage512#: 512 conversions averaged.

enumerator kDADC_HardwareAverage1024#: 1024 conversions averaged.

enum _dadc_interrupt#

DualADC interrupt source selection mask for the IE register.

Values may be OR’d together. ADCB interrupt sources are only generated in independence mode (CFG0[INDEP]=1).

Values:

enumerator kDADC_InterruptEndOfScanA#: End of scan sequence for ADCA.

enumerator kDADC_InterruptOverlapA#: Trigger overlap interrupt for ADCA.

enumerator kDADC_InterruptIntervalTimeErrA#: Average-with-timer interval error for ADCA.

enumerator kDADC_InterruptEndOfScanB#: End of scan sequence for ADCB.

enumerator kDADC_InterruptOverlapB#: Trigger overlap interrupt for ADCB.

enumerator kDADC_InterruptIntervalTimeErrB#: Average-with-timer interval error for ADCB.

enum _dadc_scan_seq_status_flag#

DualADC scan sequence completion status flag mask (STAT2[EOSI]).

Used with DUALADC_GetScanSequenceStatusFlags and DUALADC_ClearScanSequenceStatusFlags. Values may be OR’d together. kDADC_EndofScanBFlag is only generated in independence mode (CFG0[INDEP]=1).

Values:

enumerator kDADC_EndofScanAFlag#: ADCA scan sequence complete.

enumerator kDADC_EndofScanBFlag#: ADCB scan sequence complete.

enum _dadc_error_status_flag#

DualADC error status flag mask (STAT1).

Used with DUALADC_GetErrorStatusFlags and DUALADC_ClearErrorStatusFlags. Values may be OR’d together. ADCB flags are only generated in independence mode (CFG0[INDEP]=1).

Values:

enumerator kDADC_OverlapAFlag#: ADCA Trigger overlap detected.

enumerator kDADC_OverlapBFlag#: ADCB Trigger overlap detected.

enumerator kDADC_IntervalErrAFlag#: ADCA Average-with-timer interval too short.

enumerator kDADC_IntervalErrBFlag#: ADCB Average-with-timer interval too short.

enum _dadc_status_flag#

DualADC general read-only status flag mask (STAT0 and STAT2[STARTUPSTS]).

Used with DUALADC_GetStatusFlags. All flags are read-only and cannot be cleared by software. Values may be OR’d together to test multiple flags at once.

Values:

enumerator kDADC_AdcActiveAFlag#: ADCA is actively converting.

enumerator kDADC_AdcActiveBFlag#: ADCB is actively converting.

enumerator kDADC_CalibrationReadyFlag#: Calibration complete.

enumerator kDADC_StartupDoneAFlag#: ADCA analog startup complete.

enumerator kDADC_StartupDoneBFlag#: ADCB analog startup complete.

enum _dadc_cmd_mask#

DualADC command buffer bitmask values for RSLTRDY_IE and CMP_IE registers.

Values may be OR’d together to address multiple command buffers simultaneously.

Values:

enumerator kDADC_Cmd1Mask#: Command buffer 1.

enumerator kDADC_Cmd2Mask#: Command buffer 2.

enumerator kDADC_Cmd3Mask#: Command buffer 3.

enumerator kDADC_Cmd4Mask#: Command buffer 4.

enumerator kDADC_Cmd5Mask#: Command buffer 5.

enumerator kDADC_Cmd6Mask#: Command buffer 6.

enumerator kDADC_Cmd7Mask#: Command buffer 7.

enumerator kDADC_Cmd8Mask#: Command buffer 8.

enumerator kDADC_Cmd9Mask#: Command buffer 9.

enumerator kDADC_Cmd10Mask#: Command buffer 10.

enumerator kDADC_Cmd11Mask#: Command buffer 11.

enumerator kDADC_Cmd12Mask#: Command buffer 12.

enumerator kDADC_Cmd13Mask#: Command buffer 13.

enumerator kDADC_Cmd14Mask#: Command buffer 14.

enumerator kDADC_Cmd15Mask#: Command buffer 15.

enumerator kDADC_Cmd16Mask#: Command buffer 16.

enumerator kDADC_Cmd17Mask#: Command buffer 17.

enumerator kDADC_Cmd18Mask#: Command buffer 18.

enumerator kDADC_Cmd19Mask#: Command buffer 19.

enumerator kDADC_Cmd20Mask#: Command buffer 20.

enum _dadc_avgt_prescaler#

DualADC average-with-timer interval prescaler (ITCFG[PRESCALERA/B]).

Interval = ITCFG[INTERVAL] * ADCK_period * 2^prescaler

Values:

enumerator kDADC_AvgtPrescaler1#: Prescaled by 1.

enumerator kDADC_AvgtPrescaler2#: Prescaled by 2.

enumerator kDADC_AvgtPrescaler4#: Prescaled by 4.

enumerator kDADC_AvgtPrescaler8#: Prescaled by 8.

enumerator kDADC_AvgtPrescaler16#: Prescaled by 16.

enumerator kDADC_AvgtPrescaler32#: Prescaled by 32.

enumerator kDADC_AvgtPrescaler64#: Prescaled by 64.

enumerator kDADC_AvgtPrescaler128#: Prescaled by 128.

typedef enum _dadc_conversion_mode dadc_conversion_mode_t#

DualADC conversion mode selection.

Controls whether ADCA and ADCB share one conversion sequence (cooperation) or run independent sequences (independence).

typedef enum _dadc_power_config dadc_power_config_t#

DualADC power configuration.

Selects the power and maximum ADCK frequency trade-off.

typedef enum _dadc_ref_voltage_src dadc_ref_voltage_src_t#: DualADC voltage reference source selection.

typedef enum _dadc_tune_mode dadc_tune_mode_t#: DualADC tune mode selection.

Note

Consult the device-specific reference manual for the effect of each value.

typedef enum _dadc_calibration_averages dadc_calibration_averages_t#

Number of ADC conversions averaged during calibration routines.

Applied to offset calibration (CTRL[CALOFS]), high-speed calibration (CTRL[CALHS]), and gain calibration (CTRL[CAL_REQ]). The recommended minimum is kDADC_CalibrationAverage256.

typedef enum _dadc_trig_sel dadc_trig_sel_t#: DualADC trigger source selection for ADCA (CFG0[TRIGSEL]).

typedef enum _dadc_dma_src dadc_dma_src_t#: DualADC DMA trigger source selection (DE[DMASRCA/B]).

typedef enum _dadc_software_trigger dadc_software_trigger_t#

DualADC software trigger selection mask.

typedef enum _dadc_conversion_type dadc_conversion_type_t#: DualADC conversion type selection (CMD[CTYPE]).

typedef enum _dadc_resolution dadc_resolution_t#: DualADC conversion resolution selection (CMD[MODE]).

typedef enum _dadc_sample_time dadc_sample_time_t#: DualADC sample time selection in ADCK cycles (CMD[STS]).

typedef enum _dadc_hardware_averages dadc_hardware_averages_t#: DualADC hardware averaging count for conversions (CMD[AVGS]).

typedef enum _dadc_interrupt dadc_interrupt_t#

DualADC interrupt source selection mask for the IE register.

Values may be OR’d together. ADCB interrupt sources are only generated in independence mode (CFG0[INDEP]=1).

typedef enum _dadc_scan_seq_status_flag dadc_scan_seq_status_flag_t#

DualADC scan sequence completion status flag mask (STAT2[EOSI]).

Used with DUALADC_GetScanSequenceStatusFlags and DUALADC_ClearScanSequenceStatusFlags. Values may be OR’d together. kDADC_EndofScanBFlag is only generated in independence mode (CFG0[INDEP]=1).

typedef enum _dadc_error_status_flag dadc_error_status_flag_t#

DualADC error status flag mask (STAT1).

Used with DUALADC_GetErrorStatusFlags and DUALADC_ClearErrorStatusFlags. Values may be OR’d together. ADCB flags are only generated in independence mode (CFG0[INDEP]=1).

typedef enum _dadc_status_flag dadc_status_flag_t#

DualADC general read-only status flag mask (STAT0 and STAT2[STARTUPSTS]).

Used with DUALADC_GetStatusFlags. All flags are read-only and cannot be cleared by software. Values may be OR’d together to test multiple flags at once.

typedef enum _dadc_cmd_mask dadc_cmd_mask_t#

DualADC command buffer bitmask values for RSLTRDY_IE and CMP_IE registers.

Values may be OR’d together to address multiple command buffers simultaneously.

typedef struct _dadc_cmd_config dadc_cmd_config_t#

DualADC conversion command configuration structure.

Configure each command buffer entry and pass to DUALADC_ConfigConversionCommand. Use DUALADC_GetDefaultConvCmdConfig for safe defaults.

Note

CMD[CDIS] (sequence terminator) is not included here; use the dedicated DUALADC_SetConvSequenceEndCommand inline function instead.

typedef struct _dadc_config dadc_config_t#

DualADC initialization configuration structure.

Pass a populated instance of this structure to DUALADC_Init. Use DUALADC_GetDefaultConfig to obtain safe reset-state defaults before modifying individual fields.

Note

CTRL[ADCEN] is always asserted at the end of DUALADC_Init and must not be set by the caller beforehand.

Note

Calibration request bits (CTRL[CAL_REQ], CTRL[CALOFS], CTRL[CALHS]) are excluded from this structure and must be triggered through DUALADC_DoCalibration.

typedef enum _dadc_avgt_prescaler dadc_avgt_prescaler_t#

DualADC average-with-timer interval prescaler (ITCFG[PRESCALERA/B]).

Interval = ITCFG[INTERVAL] * ADCK_period * 2^prescaler

typedef struct _dadc_avgt_config dadc_avgt_config_t#

DualADC average-with-timer configuration structure.

The average-with-timer feature repeats a conversion sequence automatically at a configurable interval. Pass to DUALADC_ConfigAvgTimer. Use DUALADC_GetDefaultAvgTimerConfig for safe defaults.

In cooperation mode only the ADCA fields (A suffix) take effect; ADCB follows ADCA and the ADCB fields are ignored by hardware. In independence mode both sets of fields are independent.

Interval formula: Interval = interval * ADCK_period * 2^prescaler

typedef struct _dadc_calibration_value dadc_calibration_value_t#: DualADC calibration value structure.

typedef struct _dadc_conversion_result dadc_conversion_result_t#

DualADC conversion result structure.

All three members are derived from a single RSLT register read. Use the member that matches the conversion configuration.

Note

The raw values are not final ADC codes. In standard 12-bit mode (CMD[MODE]=0) the ADC code does not start at bit 0:

CFG1[JLEFT]=0: 12-bit code at bit[14:3]; right-shift by 3 to obtain the value.
CFG1[JLEFT]=1: 12-bit code at bit[15:4]; right-shift by 4 to obtain the value. In high-resolution 16-bit mode (CMD[MODE]=1) the result fills bit[15:0] and no shift is needed. When average-with-timer is enabled result32 holds the sum of raw register values; apply the same right-shift before dividing by the repeat count.

DUALADC_RESET_TIMEOUT#

NOP loop count used to hold CTRL[RSTA]/CTRL[RSTB] asserted long enough for the software reset to take effect.

CTRL[RSTA] and CTRL[RSTB] are NOT self-clearing. The logic high level must be sustained for more than 2 ADC functional clock cycles before the reset takes effect; the bits must then be cleared explicitly by software. This macro controls how many __NOP() iterations are executed between asserting and releasing the reset bits in DUALADC_Init, providing a portable hold time that scales with CPU clock speed.

The required NOP count scales with the CPU-to-ADC clock frequency ratio: min_count = ceil(2 * f_CPU / f_ADC) The default value of 20 covers ratios up to 10 (e.g., 150 MHz CPU with 16 MHz ADC clock). Increase this value via Kconfig option CONFIG_DUALADC_RESET_TIMEOUT when the CPU clock is much faster than the ADC functional clock (large f_CPU/f_ADC ratio).

DUALADC_CALIBRATION_TIMEOUT#

Max loop count waiting for each calibration step (STAT0[CAL_RDY], GCC[n][RDY]) to complete.

Set via Kconfig option CONFIG_DUALADC_CALIBRATION_TIMEOUT. Default 0 means wait forever.

struct _dadc_cmd_config#

#include <fsl_dual_adc.h>

DualADC conversion command configuration structure.

Configure each command buffer entry and pass to DUALADC_ConfigConversionCommand. Use DUALADC_GetDefaultConvCmdConfig for safe defaults.

Note

CMD[CDIS] (sequence terminator) is not included here; use the dedicated DUALADC_SetConvSequenceEndCommand inline function instead.

Public Members

dadc_conversion_type_t conversionType#: Conversion type (A-side/B-side/differential/dual).

dadc_resolution_t resolutionMode#: Conversion resolution (standard or high).

dadc_sample_time_t sampleTimeMode#: Input sample time in ADCK cycles.

dadc_hardware_averages_t hardwareAverages#: Number of conversions averaged per result.

uint8_t channelNumber#: A-side input channel select (0-31).

bool enableAltBChannel#: Use altBChannelNumber for B-side instead of channelNumber.

uint8_t altBChannelNumber#: B-side channel select when enableAltBChannel is true (0-31).

bool enableCompare#: Enable hardware compare for this command.

uint16_t compareValueHigh#: Compare value high (CVH); written to CV[n] when enableCompare is true.

uint16_t compareValueLow#: Compare value low (CVL); written to CV[n] when enableCompare is true.

bool enableWaitTrigger#: Require trigger re-assertion before this command executes.

struct _dadc_config#

#include <fsl_dual_adc.h>

DualADC initialization configuration structure.

Pass a populated instance of this structure to DUALADC_Init. Use DUALADC_GetDefaultConfig to obtain safe reset-state defaults before modifying individual fields.

Note

CTRL[ADCEN] is always asserted at the end of DUALADC_Init and must not be set by the caller beforehand.

Note

Calibration request bits (CTRL[CAL_REQ], CTRL[CALOFS], CTRL[CALHS]) are excluded from this structure and must be triggered through DUALADC_DoCalibration.

Public Members

dadc_conversion_mode_t conversionMode#: ADCA/ADCB conversion mode (cooperation or independence).

dadc_power_config_t powerConfig#: Power and maximum ADCK frequency.

bool enableAnalogPreEnable#: Pre-enable analog circuits for faster conversion startup.

dadc_ref_voltage_src_t refVoltageSource#: Voltage reference source.

uint8_t powerUpDelayCount#: Power-up delay count; must exceed device tADCSTUP.

dadc_trig_sel_t triggerSource#: Trigger source for ADCA (CFG0[TRIGSEL]).

bool enableLeftJustify#: Left-justify the 12-bit result in the result register.

bool enableHighSpeedMode#: Enable high-speed conversion mode.

bool enableHighSpeedExtra#: Add one extra conversion cycle in high-speed mode.

dadc_tune_mode_t tuneMode#: Tune mode; see device reference manual.

bool enableDoze#: ADC finishes current scan then goes inactive on doze entry.

bool enableLongCalSampleTime#: Use long (67.5 ADCK) sample time during calibration.

dadc_calibration_averages_t calibrationAverages#: Conversion averages during calibration routines.

bool enableConversionPause#: Insert a delay between consecutive conversions in a sequence.

uint16_t conversionPauseDelay#: Pause delay count (0-511); delay = conversionPauseDelay * 4 ADCK cycles.

bool enableHardwareTrigger0#: Enable hardware Trigger0 for ADCA (or both in cooperation mode).

bool enableHardwareTrigger1#: Enable hardware Trigger1 for ADCB (independence mode only).

uint8_t hardwareTrigger0Delay#: Trigger0 delay select (0-15, raw count); delay time 2^hardwareTrigger0Delay ADCK cycles.

uint8_t hardwareTrigger1Delay#: Trigger1 delay select (0-15, raw count); delay time 2^hardwareTrigger1Delay ADCK cycles.

dadc_dma_src_t dmaSourceA#: DMA trigger source for ADCA.

dadc_dma_src_t dmaSourceB#: DMA trigger source for ADCB (independence mode only).

struct _dadc_avgt_config#

#include <fsl_dual_adc.h>

DualADC average-with-timer configuration structure.

The average-with-timer feature repeats a conversion sequence automatically at a configurable interval. Pass to DUALADC_ConfigAvgTimer. Use DUALADC_GetDefaultAvgTimerConfig for safe defaults.

In cooperation mode only the ADCA fields (A suffix) take effect; ADCB follows ADCA and the ADCB fields are ignored by hardware. In independence mode both sets of fields are independent.

Interval formula: Interval = interval * ADCK_period * 2^prescaler

Public Members

bool enableAvgTimerA#: Enable average-with-timer for ADCA.

uint16_t repeatCountA#: Sequence repeat count for ADCA (1-512); stored as AVGTA_TIMES+1.

uint16_t intervalA#: ADCA timer interval raw count (ITCFG[INTERVALA]).

dadc_avgt_prescaler_t prescalerA#: ADCA interval timer prescaler.

bool enableAvgTimerB#: Enable average-with-timer for ADCB (independence mode only).

uint16_t repeatCountB#: Sequence repeat count for ADCB (1-512, independence mode only).

uint16_t intervalB#: ADCB timer interval raw count (ITCFG[INTERVALB], independence mode only).

dadc_avgt_prescaler_t prescalerB#: ADCB interval timer prescaler (independence mode only).

struct _dadc_calibration_value#

#include <fsl_dual_adc.h>

DualADC calibration value structure.

Public Members

uint16_t offsetTrimA#: OFSTRIM[OFSTRIMA]: ADCA offset trim (10-bit).

uint16_t offsetTrimB#: OFSTRIM[OFSTRIMB]: ADCB offset trim (10-bit).

uint16_t highSpeedTrimA#: HSTRIM[HSTRIMA]: ADCA high-speed trim (5-bit).

uint16_t highSpeedTrimB#: HSTRIM[HSTRIMB]: ADCB high-speed trim (5-bit).

uint32_t gcalr[DADC_GCR_COUNT]#: GCR[n].GCALR: 17-bit gain calibration result (RDY bit excluded).

uint16_t calGar[DADC_CAL_GAR_COUNT]#: CAL_GAR[0..32]: linearity calibration values for ADCA.

uint16_t calGbr[DADC_CAL_GBR_COUNT]#: CAL_GBR[0..32]: linearity calibration values for ADCB.

struct _dadc_conversion_result#

#include <fsl_dual_adc.h>

DualADC conversion result structure.

All three members are derived from a single RSLT register read. Use the member that matches the conversion configuration.

Note

The raw values are not final ADC codes. In standard 12-bit mode (CMD[MODE]=0) the ADC code does not start at bit 0:

CFG1[JLEFT]=0: 12-bit code at bit[14:3]; right-shift by 3 to obtain the value.
CFG1[JLEFT]=1: 12-bit code at bit[15:4]; right-shift by 4 to obtain the value. In high-resolution 16-bit mode (CMD[MODE]=1) the result fills bit[15:0] and no shift is needed. When average-with-timer is enabled result32 holds the sum of raw register values; apply the same right-shift before dividing by the repeat count.

Public Members

uint16_t resultLow#: bit[15:0]: single-ended or differential result; A-side result in dual single-ended mode.

uint16_t resultHigh#: bit[31:16]: B-side result in dual single-ended mode (CTYPE=3).

uint32_t result32#: bit[31:0]: full 32-bit summed result when average-with-timer is enabled.

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)#

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

base – eDMA peripheral base address.
config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)#

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)#

Push content of TCD structure into hardware TCD register.

Parameters:

base – EDMA peripheral base address.
channel – EDMA channel number.
tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)#

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)#

EDMA Channel initialization.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)#

Set channel memory attribute.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
writeAttribute – Attributes associated with a write transaction.
readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)#

Set channel sign extension.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)#

Set channel swap size.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)#

Set channel access type.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)#

Set channel request source.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)#

Gets the channel identification and attribute information on the system bus interface.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)#

Set channel master ID replication.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – true is enable, false is disable.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)#

Set channel security level.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)#

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)#

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)#

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)#

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number
config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)#

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
type – A channel link type, which can be one of the following:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)#

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)#

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)#

Enables an async request for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)#

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)#

Enables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)#

Disables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)#

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
channel – edma channel number.
sourceOffset – source address offset will be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)#

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)#

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)#

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)#

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)#

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)#

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Parameters:

tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)#

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

Parameters:

tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)#

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)#

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)#

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)#

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)#

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)#

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)#

Configures the eDMA TCD transfer attribute.

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)#

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)#

Sets the channel link for the eDMA TCD.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)#

Sets the bandwidth for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)#

Sets the source modulo and the destination modulo for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)#

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)#

Enables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)#

Disables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)#

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)#

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)#

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)#

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)#

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)#

Gets the eDMA channel error status flags.

Parameters:

base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)#

Gets the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)#

Clears the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)#

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.
base – eDMA peripheral base address.
channel – eDMA channel number.

Return values:

kStatus_Success –
kStatus_InvalidArgument –

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)#

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

handle – eDMA handle pointer.
tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.
tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)#

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

handle – eDMA handle pointer.
callback – eDMA callback function pointer.
userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)#

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)#

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)#

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)#

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

submit single transfer

edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit static link transfer,

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

submit dynamic link transfer

edma_tcd_t tcdpool[2];
EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit loop transfer

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)#

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

handle – eDMA handle pointer.
config – Pointer to eDMA transfer configuration structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)#

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

handle – eDMA handle pointer
transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail
transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

kStatus_Success – It means submit transfer request succeed
kStatus_EDMA_Busy – channel is in busy status
kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)#

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)#

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)#

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)#

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)#

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)#

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

handle – eDMA handle pointer.

void EDMA_TcdInit(EDMA_Type *base, edma_tcd_t *tcdRegs)#

Initialize all fields to 0 for the TCD structure.

This function initialize all fields for this TCD structure to 0.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

FSL_EDMA_DRIVER_VERSION#

eDMA driver version

Version 2.10.14.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull#: TCD queue is full.

enumerator kStatus_EDMA_Busy#: Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size#

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes#: Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes#: Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes#: Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes#: Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes#: Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes#: Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes#: Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes#: Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo#

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable#: Disable modulo

enumerator kEDMA_Modulo2bytes#: Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes#: Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes#: Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes#: Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes#: Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes#: Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes#: Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes#: Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes#: Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes#: Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes#: Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes#: Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes#: Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes#: Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes#: Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes#: Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes#: Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes#: Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes#: Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes#: Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes#: Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes#: Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes#: Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes#: Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes#: Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes#: Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes#: Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes#: Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes#: Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes#: Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes#: Circular buffer size is 2 G bytes.

enum _edma_bandwidth#

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone#: No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle#: eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle#: eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type#

Channel link type.

Values:

enumerator kEDMA_LinkNone#: No channel link

enumerator kEDMA_MinorLink#: Channel link after each minor loop

enumerator kEDMA_MajorLink#: Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag#: DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag#: eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag#: eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag#: Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag#: Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag#: Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag#: NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag#: Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag#: Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag#: Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag#: Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag#: Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag#: Transfer cancelled

enumerator kEDMA_ValidFlag#: No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable#: Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable#: Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable#: Enable interrupt while major count to half value.

enum _edma_transfer_type#

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory#: Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory#: Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral#: Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral#: Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute#

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer#: No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable#: No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer#: No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable#: No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer#: No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable#: No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer#: No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable#: No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer#: write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable#: write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer#: write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable#: write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer#: write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable#: write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer#: write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable#: write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size#

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled#: Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap#: Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap#: Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap#: Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap#: Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap#: Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap#: Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel#: Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId#: DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type#

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess#: Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess#: Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level#

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser#: user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged#: Privileged protection level eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t#: eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t#: eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t#: Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t#: Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t#: eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t#: eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t#: eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t#: eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t#: eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t#: eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t#: eDMA4 channel protection level

typedef struct _edma_channel_config edma_channel_config_t#: eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t#

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t#

eDMA channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the eDMA interfaces will generate assert error.

typedef struct _edma_config edma_config_t#: eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)#

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:: EDMA handle pointer, users shall not touch the values inside.
Param userData:: The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
Param transferDone:: If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
Param tcds:: How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t#: eDMA transfer handle structure

FSL_EDMA_DRIVER_UNIFIED#

eDMA driver name.

This is the unified eDMA driver serving the eDMA3, eDMA4 and eDMA5 IP versions. Its Kconfig component is driver.edma_unified; the historical driver.edma4 component and the FSL_EDMA_DRIVER_EDMA4 macro are retained as deprecated aliases for backward compatibility. The version-specific edma4_* / edma5_* identifiers inside this driver refer to the corresponding IP TCD layout, not to the component name.

FSL_EDMA_DRIVER_EDMA4#: Deprecated alias of FSL_EDMA_DRIVER_UNIFIED; use FSL_EDMA_DRIVER_UNIFIED.

EDMA_ALLOCATE_TCD(name, number)#: Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel)#: Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config#

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption#: If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility#: If true: a channel can suspend other channel with low priority

uint8_t channelPriority#: Channel priority

struct _edma_minor_offset_config#

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset#: Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset#: Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset#: Offset for a minor loop mapping.

struct _edma_channel_config#

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig#: channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute#: channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute#: channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize#: channel swap size configuration

edma_channel_access_type_t channelAccessType#: channel access type configuration

uint8_t channelDataSignExtensionBitPosition#: channel data sign extension bit psition configuration

uint32_t channelRequestSource#: hardware service request source for the channel

bool enableMasterIDReplication#: enable master ID replication

edma_channel_protection_level_t protectionLevel#: protection level

struct _edma_transfer_config#

#include <fsl_edma.h>

eDMA channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the eDMA interfaces will generate assert error.

Public Members

uint32_t srcAddr#: Source data address.

uint32_t destAddr#: Destination data address.

edma_transfer_size_t srcTransferSize#: Source data transfer size.

edma_transfer_size_t destTransferSize#: Destination data transfer size.

int16_t srcOffset#: Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset#: Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes#: bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts#: minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask#: channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo#: source circular data queue range

int32_t srcMajorLoopOffset#: source major loop offset

edma_modulo_t dstAddrModulo#: destination circular data queue range

int32_t dstMajorLoopOffset#: destination major loop offset

bool enableSrcMinorLoopOffset#: enable source minor loop offset

bool enableDstMinorLoopOffset#: enable dest minor loop offset

int32_t minorLoopOffset#: burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink#: channel link when major loop complete

uint32_t majorLoopLinkChannel#: major loop link channel number

bool enableChannelMinorLoopLink#: channel link when minor loop complete

uint32_t minorLoopLinkChannel#: minor loop link channel number

edma_tcd_t *linkTCD#: pointer to the link transfer control descriptor

struct _edma_config#

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableMasterIdReplication#: Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink#: Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError#: Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode#: Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration#: Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]#: channel preemption configuration

struct _edma_handle#

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback#: Callback function for major count exhausted.

void *userData#: Callback function parameter.

EDMA_ChannelType *channelBase#: eDMA peripheral channel base address.

EDMA_Type *base#: eDMA peripheral base address

EDMA_TCDType *tcdBase#: eDMA peripheral tcd base address.

edma_tcd_t *tcdPool#: Pointer to memory stored TCDs.

uint32_t channel#: eDMA channel number.

volatile int8_t header#: The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail#: The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed#: The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize#: The total number of TCD slots in the queue.

eDMA core Driver#

enum _edma_tcd_type#

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag#: Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag#: Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t#: edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t#: edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t#: eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t#: edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t#: edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t#: edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType#: EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType#

typedef void EDMA_Type#

DMA_CORE_MP_CSR_EDBG_MASK#

DMA_CORE_MP_CSR_ERCA_MASK#

DMA_CORE_MP_CSR_HAE_MASK#

DMA_CORE_MP_CSR_HALT_MASK#

DMA_CORE_MP_CSR_GCLC_MASK#

DMA_CORE_MP_CSR_GMRC_MASK#

DMA_CORE_MP_CSR_EDBG(x)#

DMA_CORE_MP_CSR_ERCA(x)#

DMA_CORE_MP_CSR_HAE(x)#

DMA_CORE_MP_CSR_HALT(x)#

DMA_CORE_MP_CSR_GCLC(x)#

DMA_CORE_MP_CSR_GMRC(x)#

DMA_CSR_INTMAJOR_MASK#

DMA_CSR_INTHALF_MASK#

DMA_CSR_DREQ_MASK#

DMA_CSR_ESG_MASK#

DMA_CSR_BWC_MASK#

DMA_CSR_BWC(x)#

DMA_CSR_START_MASK#

DMA_CITER_ELINKNO_CITER_MASK#

DMA_BITER_ELINKNO_BITER_MASK#

DMA_CITER_ELINKNO_CITER_SHIFT#

DMA_CITER_ELINKYES_CITER_MASK#

DMA_CITER_ELINKYES_CITER_SHIFT#

DMA_ATTR_SMOD_MASK#

DMA_ATTR_DMOD_MASK#

DMA_ATTR_SSIZE_MASK#

DMA_ATTR_SSIZE_SHIFT#

DMA_ATTR_DSIZE_MASK#

DMA_ATTR_DSIZE_SHIFT#

DMA_CITER_ELINKNO_ELINK_MASK#

DMA_CSR_MAJORELINK_MASK#

DMA_BITER_ELINKYES_ELINK_MASK#

DMA_CITER_ELINKYES_ELINK_MASK#

DMA_CSR_MAJORLINKCH_MASK#

DMA_BITER_ELINKYES_LINKCH_MASK#

DMA_CITER_ELINKYES_LINKCH_MASK#

DMA_NBYTES_MLOFFYES_MLOFF_MASK#

DMA_NBYTES_MLOFFYES_DMLOE_MASK#

DMA_NBYTES_MLOFFYES_SMLOE_MASK#

DMA_NBYTES_MLOFFNO_NBYTES_MASK#

DMA_ATTR_DMOD(x)#

DMA_ATTR_SMOD(x)#

DMA_BITER_ELINKYES_LINKCH(x)#

DMA_CITER_ELINKYES_LINKCH(x)#

DMA_NBYTES_MLOFFYES_MLOFF(x)#

DMA_NBYTES_MLOFFYES_DMLOE(x)#

DMA_NBYTES_MLOFFYES_SMLOE(x)#

DMA_NBYTES_MLOFFNO_NBYTES(x)#

DMA_NBYTES_MLOFFYES_NBYTES(x)#

DMA_ATTR_DSIZE(x)#

DMA_ATTR_SSIZE(x)#

DMA_CSR_DREQ(x)#

DMA_CSR_MAJORLINKCH(x)#

DMA_CH_MATTR_WCACHE(x)#

DMA_CH_MATTR_RCACHE(x)#

DMA_CH_CSR_SIGNEXT_MASK#

DMA_CH_CSR_SIGNEXT_SHIFT#

DMA_CH_CSR_SWAP_MASK#

DMA_CH_CSR_SWAP_SHIFT#

DMA_CH_SBR_INSTR_MASK#

DMA_CH_SBR_INSTR_SHIFT#

DMA_CH_SBR_EMI_MASK#

DMA_CH_SBR_EMI_SHIFT#

DMA_CH_MUX_SOURCE(x)#

DMA_ERR_DBE_FLAG#: DMA error flag.

DMA_ERR_SBE_FLAG#

DMA_ERR_SGE_FLAG#

DMA_ERR_NCE_FLAG#

DMA_ERR_DOE_FLAG#

DMA_ERR_DAE_FLAG#

DMA_ERR_SOE_FLAG#

DMA_ERR_SAE_FLAG#

DMA_ERR_ERRCHAN_FLAG#

DMA_ERR_ECX_FLAG#

DMA_ERR_FLAG#

DMA_CLEAR_DONE_STATUS(base, channel)#: get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)#

DMA_ENABLE_ERROR_INT(base, channel)#: enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)#

DMA_CLEAR_ERROR_STATUS(base, channel)#: get/clear error status

DMA_GET_ERROR_STATUS(base, channel)#

DMA_CLEAR_INT_STATUS(base, channel)#: get/clear INT status

DMA_GET_INT_STATUS(base, channel)#

DMA_ENABLE_MAJOR_INT(base, channel)#: enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)#

DMA_DISABLE_MAJOR_INT(base, channel)#

DMA_DISABLE_HALF_INT(base, channel)#

EDMA_TCD_ALIGN_SIZE#: EDMA tcd align size.

EDMA_CORE_BASE(base)#: EDMA base address convert macro.

EDMA_MP_BASE(base)#

EDMA_CHANNEL_BASE(base, channel)#

EDMA_TCD_BASE(base, channel)#

EDMA_TCD_TYPE(x)#: EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag)#: EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)#

EDMA_TCD_ATTR(tcd, flag)#

EDMA_TCD_NBYTES(tcd, flag)#

EDMA_TCD_SLAST(tcd, flag)#

EDMA_TCD_DADDR(tcd, flag)#

EDMA_TCD_DOFF(tcd, flag)#

EDMA_TCD_CITER(tcd, flag)#

EDMA_TCD_DLAST_SGA(tcd, flag)#

EDMA_TCD_CSR(tcd, flag)#

EDMA_TCD_BITER(tcd, flag)#

struct _edma_core_mp#

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel#

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT: Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR: Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI: Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd#

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint32_t SADDR_HIGH: SADDR HIGH register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t SLAST_SDA_HIGH: SLAST SDA HIGH register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint32_t DADDR_HIGH: DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH: DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

uint8_t RESERVED[16]#: Aligned 64 bytes

struct _edma4_core_tcd#

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

struct _edma_core_tcd#: #include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS#

Public Members

struct _edma_core_mp EDMA5_REG#

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW: Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH: Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW: Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH: Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH: Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW: Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH: Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]: Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]: Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]: Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS#

Public Members

struct _edma_core_channel EDMA5_REG#

struct _edma_core_channel EDMA4_REG#

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX: Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS#

Public Members

edma4_core_tcd_t edma4_tcd#

eDMA soc Driver#

EIM: error injection module#

FSL_EIM_DRIVER_VERSION#: Driver version.

void EIM_Init(EIM_Type *base)#

EIM module initialization function.

Parameters:

base – EIM base address.

void EIM_Deinit(EIM_Type *base)#: De-initializes the EIM.

ERM: error recording module#

void ERM_Init(ERM_Type *base)#

ERM module initialization function.

Parameters:

base – ERM base address.

void ERM_Deinit(ERM_Type *base)#: De-initializes the ERM.

static inline void ERM_EnableInterrupts(ERM_Type *base, uint32_t channel, uint32_t mask)#

ERM enable interrupts.

Parameters:

base – ERM peripheral base address.
channel – memory channel.
mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline void ERM_DisableInterrupts(ERM_Type *base, uint32_t channel, uint32_t mask)#

ERM module disable interrupts.

Parameters:

base – ERM base address.
channel – memory channel.
mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, uint32_t channel)#

Gets ERM interrupt flags.

Parameters:

base – ERM peripheral base address.

Returns:

ERM event flags.

static inline void ERM_ClearInterruptStatus(ERM_Type *base, uint32_t channel, uint32_t mask)#

ERM module clear interrupt status flag.

Parameters:

base – ERM base address.
mask – event flag to clear. Refer to “_erm_interrupt_flag” enumeration.

uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, uint32_t channel)#

ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n.

Parameters:

base – ERM base address.
channel – memory channel.

Return values:

memory – error absolute address.

FSL_ERM_DRIVER_VERSION#: Driver version.

ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.

This structure contains the settings for all of the ERM interrupt configurations.

Values:

enumerator kERM_SingleCorrectionIntEnable#: Single Correction Interrupt Notification enable.

enumerator kERM_NonCorrectableIntEnable#: Non-Correction Interrupt Notification enable.

enumerator kERM_AllInterruptsEnable#: All Interrupts enable

ERM interrupt status, _erm_interrupt_flag.

This provides constants for the ERM event status for use in the ERM functions.

Values:

enumerator kERM_SingleBitCorrectionIntFlag#: Single-Bit Correction Event.

enumerator kERM_NonCorrectableErrorIntFlag#: Non-Correctable Error Event.

enumerator kERM_AllIntsFlag#: All Events.

FGPIO Driver#

C40ESP3 Flash Driver#

enum _flash_driver_api_keys#

Enumeration for Flash driver API keys.

Note

The resulting value is built with a byte order such that the string being readable in expected order when viewed in a hex editor, if the value is treated as a 32-bit little endian value.

Values:

enumerator kFLASH_ApiEraseKey#: Key value used to validate all flash erase APIs.

status_t FLASH_Init(flash_config_t *config)#

Initializes the global flash properties structure members.

This function checks and initializes the Flash module for the other Flash APIs. When async mode is enabled, this also initializes the async context including the operation queue and buffer pool.

Parameters:

config – Pointer to the storage for the driver runtime state.

Return values:

kStatus_FLASH_Success – API was executed successfully.
kStatus_FLASH_InvalidArgument – An invalid argument is provided.
kStatus_FLASH_CommandFailure – Run-time error during the command execution.
kStatus_FLASH_CommandNotSupported – Flash API is not supported.

status_t FLASH_Erase(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes, uint32_t key)#

Erases the flash sectors encompassed by parameters passed into function.

In synchronous mode, this function blocks until the erase completes. In asynchronous mode, this function queues the erase operation and returns immediately. The operation will be executed later by FLASH_Process() when sufficient idle time is available.

Parameters:

config – Pointer to the flash driver configuration.
base – FMU peripheral base address.
start – Start address of the region to erase.
lengthInBytes – Size of the region to erase in bytes.
key – Erase API key (kFLASH_ApiEraseKey).

Return values:

kStatus_FLASH_Success – Operation completed or queued successfully.
kStatus_FLASH_InvalidArgument – Invalid parameters.
#kStatus_FLASH_Busy – Queue or resources unavailable (async mode).

status_t FLASH_EraseAll(FMU_Type *base, uint32_t key)#

Erases entire flash and ifr.

Note

This function always executes synchronously regardless of async mode setting.

Parameters:

base – FMU peripheral base address.
key – Erase API key.

Return values:

kStatus_FLASH_Success – Operation completed successfully.

status_t FLASH_Program(flash_config_t *config, FMU_Type *base, uint32_t start, uint8_t *src, uint32_t lengthInBytes)#

Programs flash phrases with data at locations passed in through parameters.

In synchronous mode, this function blocks until programming completes. In asynchronous mode, this function copies the source data to an internal buffer, queues the operation, and returns immediately. The operation will be executed later by FLASH_Process() when sufficient idle time is available.

Parameters:

config – Pointer to the flash driver configuration.
base – FMU peripheral base address.
start – Target flash address for programming.
src – Pointer to source data buffer.
lengthInBytes – Number of bytes to program.

Return values:

kStatus_FLASH_Success – Operation completed or queued successfully.
kStatus_FLASH_InvalidArgument – Invalid parameters.
#kStatus_FLASH_Busy – Queue or buffer pool exhausted (async mode).

status_t FLASH_ProgramPage(flash_config_t *config, FMU_Type *base, uint32_t start, uint8_t *src, uint32_t lengthInBytes)#

Programs flash pages with data at locations passed in through parameters.

Note

In async mode, this function behaves the same as FLASH_Program().

Parameters:

config – Pointer to the flash driver configuration.
base – FMU peripheral base address.
start – Target flash address for programming.
src – Pointer to source data buffer.
lengthInBytes – Number of bytes to program.

Return values:

kStatus_FLASH_Success – Operation completed or queued successfully.

status_t FLASH_Read(uint8_t *dst, uint32_t start, uint32_t lengthInBytes)#

Reads data from flash memory.

This function always executes synchronously. In async mode, it checks the pending operation queue and applies any queued writes or erases to the returned data to ensure consistency.

Parameters:

config – Pointer to the flash driver configuration.
start – Source flash address to read from.
dst – Pointer to destination buffer.
lengthInBytes – Number of bytes to read.

Return values:

kStatus_FLASH_Success – Read completed successfully.
kStatus_FLASH_InvalidArgument – Invalid parameters.

status_t FLASH_VerifyErasePhrase(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes)#: Verify that the flash phrases are erased.

status_t FLASH_VerifyErasePage(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes)#: Verify that the flash pages are erased.

status_t FLASH_VerifyEraseSector(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes)#: Verify that the flash sectors are erased.

status_t FLASH_VerifyEraseAll(FMU_Type *base)#: Verify that all flash and IFR space is erased.

status_t FLASH_VerifyEraseBlock(flash_config_t *config, FMU_Type *base, uint32_t blockaddr)#: Verify that a flash block is erased.

status_t FLASH_VerifyEraseIFRPhrase(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes)#: Verify that the ifr phrases are erased.

status_t FLASH_VerifyEraseIFRPage(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes)#: Verify that the ifr pages are erased.

status_t FLASH_VerifyEraseIFRSector(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t lengthInBytes)#: Verify that the ifr sectors are erased.

status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)#: Returns the desired flash property.

status_t Read_Into_MISR(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t ending, uint32_t *seed, uint32_t *signature)#

Read into MISR.

The Read into MISR operation generates a signature based on the contents of the selected flash memory using an embedded MISR.

status_t Read_IFR_Into_MISR(flash_config_t *config, FMU_Type *base, uint32_t start, uint32_t ending, uint32_t *seed, uint32_t *signature)#

Read IFR into MISR.

The Read IFR into MISR operation generates a signature based on the contents of the selected IFR space using an embedded MISR.

FSL_FLASH_DRIVER_VERSION#

Flash driver version for SDK.

Version 2.4.2.

enum _flash_driver_version_constants#

Flash driver version for ROM.

Values:

enumerator kFLASH_DriverVersionName#: Flash driver version name.

enumerator kFLASH_DriverVersionMajor#: Major flash driver version.

enumerator kFLASH_DriverVersionMinor#: Minor flash driver version.

enumerator kFLASH_DriverVersionBugfix#: Bugfix for flash driver version.

enum _flash_property_tag#

Enumeration for various flash properties.

Values:

enumerator kFLASH_PropertyPflash0SectorSize#: Pflash sector size property.

enumerator kFLASH_PropertyPflash0TotalSize#: Pflash total size property.

enumerator kFLASH_PropertyPflash0BlockSize#: Pflash block size property.

enumerator kFLASH_PropertyPflash0BlockCount#: Pflash block count property.

enumerator kFLASH_PropertyPflash0BlockBaseAddr#: Pflash block base address property.

enumerator kFLASH_PropertyPflash0FacSupport#: Pflash fac support property.

enumerator kFLASH_PropertyPflash0AccessSegmentSize#: Pflash access segment size property.

enumerator kFLASH_PropertyPflash0AccessSegmentCount#: Pflash access segment count property.

enumerator kFLASH_PropertyPflash1SectorSize#: Pflash sector size property.

enumerator kFLASH_PropertyPflash1TotalSize#: Pflash total size property.

enumerator kFLASH_PropertyPflash1BlockSize#: Pflash block size property.

enumerator kFLASH_PropertyPflash1BlockCount#: Pflash block count property.

enumerator kFLASH_PropertyPflash1BlockBaseAddr#: Pflash block base address property.

enumerator kFLASH_PropertyPflash1FacSupport#: Pflash fac support property.

enumerator kFLASH_PropertyPflash1AccessSegmentSize#: Pflash access segment size property.

enumerator kFLASH_PropertyPflash1AccessSegmentCount#: Pflash access segment count property.

enumerator kFLASH_PropertyFlexRamBlockBaseAddr#: FlexRam block base address property.

enumerator kFLASH_PropertyFlexRamTotalSize#: FlexRam total size property.

typedef enum _flash_property_tag flash_property_tag_t#: Enumeration for various flash properties.

typedef struct _flash_mem_descriptor flash_mem_desc_t#: Flash memory descriptor.

typedef struct _flash_ifr_desc flash_ifr_desc_t#

typedef struct _msf1_config msf1_config_t#

typedef struct _flash_config flash_config_t#

Flash driver state information.

An instance of this structure is allocated by the user of the flash driver and passed into each of the driver APIs.

FLASH_ADDR_MASK#

struct _flash_mem_descriptor#

#include <fsl_k4_flash.h>

Flash memory descriptor.

Public Members

uint32_t blockBase#: Base address of the flash block

uint32_t totalSize#: The size of the flash block.

uint32_t blockCount#: A number of flash blocks.

struct _flash_ifr_desc#

struct _msf1_config#

struct _flash_config#

#include <fsl_k4_flash.h>

Flash driver state information.

An instance of this structure is allocated by the user of the flash driver and passed into each of the driver APIs.

FlexPWM: Enhanced Flex Pulse Width Modulator#

void FLEXPWM_GetDefaultSubmoduleConfig(flexpwm_submodule_config_t *config)#

Get default configuration for FlexPWM submodule.

This function initializes the FlexPWM submodule configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigSubmodule().

Default values:

Clock source: IPBus clock (kFLEXPWM_ClockSource_IPBusClock)
Prescaler: Divide by 1 (no prescaling)
Counter initial value: 0
Counter modulo value: 0xFFFF (maximum range)
Initialization source: Local sync
Load mode: Opportunity (load at PWM reload opportunity)
Load frequency: 0 (every PWM cycle)
Half-cycle reload: Disabled
Full-cycle reload: Enabled
Reload source: Local reload
Half-cycle value: 0
Debug mode: Disabled (PWM stops in Debug mode)
Wait mode: Disabled (PWM stops in Wait mode)

Parameters:

config – Pointer to the submodule configuration structure.

void FLEXPWM_ConfigSubmodule(PWM_Type *base, uint8_t submodule, const flexpwm_submodule_config_t *config)#

Configure a FlexPWM submodule.

This function configures the basic parameters of a FlexPWM submodule, including:

Clock source and prescaler (CTRL2[CLK_SEL], CTRL[PRSC])
Counter initialization and modulo values (INIT, VAL1)
Counter initialization source (CTRL2[INIT_SEL])
Register reload mode, frequency, and timing (CTRL[LDMOD, LDFQ, HALF, FULL], CTRL2[RELOAD_SEL])
Half-cycle reload point (VAL0)
Debug and Wait mode behavior (CTRL2[DBGEN, WAITEN])

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration write behavior:

This function writes configuration values to buffered registers.
The configuration does NOT take effect immediately.
After calling this function, you must set MCTRL[LDOK] bit using a separate function to transfer buffered register values to active registers.
The actual transfer timing depends on the configured reload mode and reload opportunities.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Start the PWM counter (use a separate start API)
Configure PWM waveform parameters (VAL2-VAL5, deadtime, polarity, etc.)
Configure fault protection or capture functionality
Configure FORCE_OUT behavior (use FLEXPWM_ConfigForceOut)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the submodule configuration structure.

void FLEXPWM_ConfigPWM(PWM_Type *base, uint8_t submodule, const flexpwm_pwm_config_t *config)#

Configure PWM output for a FlexPWM submodule.

This function configures the PWM output parameters for a FlexPWM submodule, including:

Compare values (VAL2, VAL3, VAL4, VAL5)
Output polarity (POLA, POLB)
Initial values (PWM23_INIT, PWM45_INIT)
Operating mode: independent or complementary (INDEP)
Complementary mode source selection (MCTRL[IPOL]) - only in complementary mode

Note

For complementary mode (complementary = true):

Only the selected channel compare values (pwma if ipolSource=kFLEXPWM_IPOL_PWM23, or pwmb if ipolSource=kFLEXPWM_IPOL_PWM45) needs to be configured.
But polarity still needs to be set for the complementary output to work correctly.
The unselected channel will be ignored by the hardware.
MCTRL[IPOL] will be set according to ipolSource parameter.

Note

For independent mode (complementary = false):

Both pwma and pwmb must be fully configured.
INDEP bit will be set to 1 in SMxCTRL2.
MCTRL[IPOL] is ignored by the hardware in this mode.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Trigger FORCE_OUT events (in complementary mode, MCTRL[IPOL] requires FORCE_OUT to take effect)
Enable PWM_A Output or PWM_B Output (use a separate API to enable outputs)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the PWM configuration structure.

void FLEXPWM_ConfigPWMChannelX(PWM_Type *base, uint8_t submodule, const flexpwm_pwm_channel_config_t *pwmx)#

Configure PWM_X output for a FlexPWM submodule.

This function configures the PWM_X output parameters for a FlexPWM submodule, including:

Compare values (VAL0, VAL1)
Output polarity (POLX)
Initial values (PWMX_INIT)

Note

When submodule works in local sync mode, PWM_X polarity is inverted, because VAL1 determines both counter modulo and PWM_X turn-off edge. VAL0 determines PWM_X turn-on edge. Recommend setting submodule counter works in master sync mode if you want to use the PWM_X output, then both VAL0 and VAL1 can be used to control PWM_X waveform shape and polarity is normal.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Enable PWM_X Output (use a separate API to enable outputs)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
pwmx – Pointer to the PWM_X configuration structure.

void FLEXPWM_GetDefaultForceOutConfig(flexpwm_force_out_config_t *config)#

Get default configuration for force output.

This function initializes the force output configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigForceOut().

Default values:

FORCE_OUT trigger source: Local software force (kFLEXPWM_ForceOutputSource_LocalForce)
Counter initialization on FORCE_OUT: Disabled (false)
PWM_A source: Generated PWM signal (kFLEXPWM_ForcePwmSource_Generated)
PWM_A software value: Logic 0 (false)
PWM_B source: Generated PWM signal (kFLEXPWM_ForcePwmSource_Generated)
PWM_B software value: Logic 0 (false)

Parameters:

config – Pointer to the force output configuration structure.

void FLEXPWM_ConfigForceOut(PWM_Type *base, uint8_t submodule, const flexpwm_force_out_config_t *config)#

Configure FORCE_OUT for a FlexPWM submodule.

This function configures the FORCE_OUT event parameters for a FlexPWM submodule, including:

FORCE_OUT trigger source (CTRL2[FORCE_SEL]): software, master, external, sync signals, etc.
Counter initialization triggered by FORCE_OUT (CTRL2[FRCEN])
PWM source selection for deadtime logic (DTSRCSEL[SMxSEL23/45]): generated, inverted, software-controlled, or external signals
Software-controlled output values (SWCOUT[SMxOUT23/45]) when source is software-controlled

Note

Configuration write behavior:

This function performs read-modify-write operations on global registers (DTSRCSEL, SWCOUT) to protect other submodules’ configurations.
Register writes are immediate and take effect when the corresponding FORCE_OUT event occurs.
SWCOUT and DTSRCSEL are NOT affected by MCTRL[LDOK]; they are independent double-buffered registers that update on FORCE_OUT events.

Note

FORCE_OUT event effects: When a FORCE_OUT event occurs, the following updated values take effect simultaneously:

PWM source routing from DTSRCSEL
Software-controlled output values from SWCOUT
Counter may be reinitialized if FRCEN is enabled

Note

This function does NOT:

Trigger FORCE_OUT events (DTSRCSEL and SWCOUT settings require FORCE_OUT event to take effect)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the force output configuration structure.

void FLEXPWM_GetDefaultFaultConfig(flexpwm_fault_config_t *config)#

Get default configuration for fault protection.

This function initializes the fault protection configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigFaultProtection().

Default values:

Fault Input Active Level (faultInputActiveLevel): Active high (true)
Fault Clearing Mode (faultClearingMode): Automatic fault clearing
Safety Mode (enableSafetyMode): Enabled (safe mode)
Full Cycle Recovery (enableFullCycleRecovery): Enabled
Half Cycle Recovery (enableHalfCycleRecovery): Disabled
Combinational Path (enableCombinatorialPath): Enabled (allow combinational path for fastest response)

Parameters:

config – Pointer to the fault protection configuration structure.

void FLEXPWM_GetDefaultFaultSubmoduleConfig(flexpwm_fault_submodule_config_t *config)#

Get default configuration for fault submodule protection.

This function initializes the fault submodule configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigFaultSubmodule().

Default values:

Disable Mask: All faults (0x0F) affect each output
Output Behavior: High-Z (high impedance) for all outputs

For single-channel platforms: disableMask_ch0 = 0x0F For dual-channel platforms: disableMask_ch0 = 0x0F, disableMask_ch1 = 0x0F

Parameters:

config – Pointer to the fault submodule configuration structure.

void FLEXPWM_GetDefaultFaultFilterConfig(flexpwm_fault_filter_config_t *config)#

Get default configuration for fault filter.

This function initializes the fault filter configuration structure with safe default values. The default configuration provides moderate debouncing suitable for typical applications.

Default values:

Filter Period (FILT_PER): 0x08 (8 IPBus clock cycles)
Filter Count (FILT_CNT): 0x04 (7 consecutive samples = 4+3)
Glitch Stretching (GSTR): Enabled

Effective debounce window: ~56 IPBus clock cycles

Parameters:

config – Pointer to the fault filter configuration structure.

void FLEXPWM_ConfigFaultProtection(PWM_Type *base, uint8_t faultChannel, const flexpwm_fault_config_t *config, uint16_t faultMask)#

Configure fault protection for a FlexPWM fault channel.

This function configures global fault protection parameters for one fault channel, including fault input active level, clearing mode, safety mode, and fault recovery timing.

Configuration details:

Fault input active level (faultInputActiveLevel): Selects whether fault is triggered by high or low
Fault clearing mode (faultClearingMode): Controls how and when PWM outputs are re-enabled
Safety mode (enableSafetyMode): Adds extra requirement that fault input be de-asserted before re-enable
Fault recovery timing (enableFullCycleRecovery, enableHalfCycleRecovery): Specifies during which PWM cycle phase outputs re-enable
Combinational path (enableCombinatorialPath): Trades off response speed vs. latency

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration applies to the entire fault channel (all submodules that reference it). For platforms with dual fault channels, call this function separately for each channel.

Note

For platforms with dual fault channels:

faultChannel 0: Configures FAULT0-3 (FCTRL/FSTS/FFILT at offset 0x18C)
faultChannel 1: Configures FAULT4-7 (FCTRL/FSTS/FFILT at offset 0x198)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number (0 or 1 for dual-channel platforms).
config – Pointer to the fault protection configuration structure.
faultMask – Fault input selection mask for the channel. Each bit corresponds to one fault input:
- bit[0] = FAULT0 (or FAULT4 for channel 1)
- bit[1] = FAULT1 (or FAULT5 for channel 1)
- bit[2] = FAULT2 (or FAULT6 for channel 1)
- bit[3] = FAULT3 (or FAULT7 for channel 1) Example: 0x05 = configure FAULT0 and FAULT2 with the same settings. Can use flexpwm_fault_mask_t enum values (kFLEXPWM_FaultMask_0/1/2/3) and OR them together for multiple faults: (kFLEXPWM_FaultMask_0 | kFLEXPWM_FaultMask_2) = 0x05.

void FLEXPWM_ConfigFaultSubmodule(PWM_Type *base, uint8_t submodule, const flexpwm_fault_submodule_config_t *config)#

Configure fault submodule protection for a FlexPWM submodule.

This function configures fault-to-PWM-output mapping and output behavior for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a single submodule. Each output can independently select which faults affect it and how it responds during a fault.

Configuration per output:

Disable Mask: Selects which fault inputs can disable this output
- disableMask_ch0: Bits [0-3] for FAULT0-3
- disableMask_ch1: Bits [0-3] for FAULT4-7 (dual-channel platforms only)
Output Behavior: Specifies pin state during fault (Force 0, Force 1, or High-Z)

Note

Configuration applies to SMxDISMAP and SMxOCTRL registers. These registers are not affected by LDOK or FORCE_OUT; configuration takes effect immediately upon register write.

Note

For dual-channel platforms, specify disableMask_ch0 and disableMask_ch1 to control which faults (from either channel) can disable each output.

Note

For single-channel platforms, only disableMask_ch0 is used; disableMask_ch1 is conditionally compiled out.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the fault submodule configuration structure.

void FLEXPWM_ConfigFaultFilter(PWM_Type *base, uint8_t faultChannel, const flexpwm_fault_filter_config_t *config)#

Configure fault filter for a FlexPWM fault channel.

This function configures the input filter for fault protection pins, including sampling period, sample count requirement, and glitch stretching logic.

The filter helps reject electrical noise and false fault triggers by requiring the FAULTx signal to be stable for N consecutive samples before a fault is reported. With GSTR enabled, narrow fault glitches (< 2 IPBus cycles) are automatically stretched.

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration applies to the entire fault channel (FFILT register). For platforms with dual fault channels, call this function separately for each channel.

Note

Filter delay calculation:

Without GSTR: delay = FILT_PER * (FILT_CNT + 3) IPBus cycles
With GSTR: may be reduced due to glitch stretching logic

Note

To disable filtering:

Set filterPeriod = 0 (sampling disabled, filter bypassed)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number (0 or 1 for dual-channel platforms).
config – Pointer to the fault filter configuration structure.

void FLEXPWM_GetDefaultOutputTriggerConfig(flexpwm_output_trigger_config_t *config)#

Get default configuration for output trigger.

This function initializes the output trigger configuration structure with safe default values:

outTriggerEnable: 0 (all triggers disabled)
triggerFrequency: kFLEXPWM_TriggerFrequency_EveryCycle (trigger every PWM cycle)
muxTrig0Source: kFLEXPWM_TriggerMuxSource_GeneratedTrigger (use PWM_OUT_TRIG0)
muxTrig1Source: kFLEXPWM_TriggerMuxSource_GeneratedTrigger (use PWM_OUT_TRIG1)
stretchPrescaler: kFLEXPWM_StretchPrescaler_None (no prescaling, if supported)

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigOutputTrigger().

void FLEXPWM_ConfigOutputTrigger(PWM_Type *base, uint8_t submodule, const flexpwm_output_trigger_config_t *config)#

Configure output trigger for a FlexPWM submodule.

This function configures the output trigger parameters for a FlexPWM submodule, including:

Trigger source mapping from VAL0-5 register matches (SMxTCTRL[OUT_TRIG_EN])
Trigger output frequency control (SMxTCTRL[TRGFRQ])
PWM_MUX_TRIG0 port source selection (SMxTCTRL[PWAOT0])
PWM_MUX_TRIG1 port source selection (SMxTCTRL[PWBOT1])

The output trigger mechanism allows PWM events (counter matches with VAL registers) to trigger external modules such as ADC, DMA, or other peripherals for synchronized operation.

Note

Trigger source mapping:

VAL0, VAL2, VAL4 matches generate PWM_OUT_TRIG0
VAL1, VAL3, VAL5 matches generate PWM_OUT_TRIG1 Multiple sources can be enabled simultaneously (OR logic).

Note

Trigger frequency control (TRGFRQ): This setting only takes effect when CTRL[LDFQ] is non-zero (reload frequency divider active).

false: Trigger outputs every PWM cycle regardless of reload occurrence
true: Trigger outputs only on the last PWM cycle before a reload opportunity

Note

Port routing: PWM_MUX_TRIG0/1 ports can be routed to either:

Generated trigger signals (PWM_OUT_TRIG0/1) from VAL register matches
Direct PWM outputs (PWM_A/PWM_B) for waveform monitoring Both ports are independently configurable.

Note

Configuration takes effect immediately upon register write. This function does NOT require setting MCTRL[LDOK].

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the output trigger configuration structure.

void FLEXPWM_GetDefaultInputCaptureConfig(flexpwm_input_capture_config_t *config)#

Get default configuration for input capture.

This function initializes the input capture configuration structure with safe default values. The default values are:

All channels (A/B/X):
- edge0 = kFLEXPWM_CaptureEdge_Disabled
- edge1 = kFLEXPWM_CaptureEdge_Disabled
- oneshot = false (free running mode)
- inputSelect = kFLEXPWM_CaptureInput_RawSignal
- edgeCompareValue = 0
- fifoWatermark = kFLEXPWM_CaptureFifoWatermark_1

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigInputCapture().

Parameters:

config – Pointer to the input capture configuration structure.

void FLEXPWM_GetDefaultCaptureFilterConfig(flexpwm_capture_filter_config_t *config)#

Get default configuration for capture filter.

This function initializes the capture filter configuration structure with safe default values. The default values are:

All channels (A/B/X):
- filterPeriod = 0 (filter bypassed, sampling disabled)
- filterCount = 0 (requires 3 consecutive samples)

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigInputCaptureFilter().

Parameters:

config – Pointer to the capture filter configuration structure.

void FLEXPWM_ConfigInputCapture(PWM_Type *base, uint8_t submodule, const flexpwm_input_capture_config_t *config)#

Configure input capture for a FlexPWM submodule.

This function configures the input capture parameters for up to three capture channels (Capture_A, Capture_B, Capture_X) of a FlexPWM submodule, including:

Edge detection configuration for two edge detectors per channel (SMxCAPTCTRLA/B/X[EDGx0/1])
One-shot or free-running mode (SMxCAPTCTRLA/B/X[ONESHOTx])
Input source selection: raw signal or edge counter output (SMxCAPTCTRLA/B/X[INP_SELx])
Edge counter compare value (SMxCAPTCOMPA/B/X[EDGCMPx])
FIFO watermark level (SMxCAPTCTRLA/B/X[CFxWM])

Note

Edge counter behavior:

When inputSelect = kFLEXPWM_CaptureInput_EdgeCounter, the edge counter is automatically enabled (EDGCNTx_EN = 1) by this function.
When inputSelect = kFLEXPWM_CaptureInput_RawSignal, the edge counter remains disabled.

Note

Capture enable control:

This function does NOT control the capture enable bits (ARMA/ARMB/ARMX).
After calling this function, use a separate enable API to start capture operation.

Note

CVAL register mapping (NON-INTUITIVE):

Capture_X: Edge0 -> CVAL0, Edge1 -> CVAL1
Capture_A: Edge0 -> CVAL2, Edge1 -> CVAL3
Capture_B: Edge0 -> CVAL4, Edge1 -> CVAL5

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the input capture configuration structure.

void FLEXPWM_ConfigInputCaptureFilter(PWM_Type *base, uint8_t submodule, const flexpwm_capture_filter_config_t *config)#

Configure input capture filter for a FlexPWM submodule.

This function configures the digital filter parameters for the three capture channels (Capture_A, Capture_B, Capture_X) of a FlexPWM submodule. The filter settings include:

Filter sampling period (SMxCAPTFILTA/B/X[CAPTx_FILT_PER])
Number of consecutive samples required (SMxCAPTFILTA/B/X[CAPTx_FILT_CNT])

The digital filter can eliminate glitches and noise on the capture input signals.

Note

Filter bypassing:

Set filterPeriod = 0 to bypass the filter (no sampling, filter disabled).

Note

Filter delay calculation:

Delay = filterPeriod * (filterCount + 3) IPBus clock cycles
Example: filterPeriod=5, filterCount=2 -> delay = 5*(2+3) = 25 cycles

Note

Hardware behavior:

This function always writes 0 to the filter register first, then writes the configuration value. This ensures correct behavior per hardware requirements.

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the capture filter configuration structure.

uint16_t FLEXPWM_GetInputCaptureValue(PWM_Type *base, uint8_t submodule, flexpwm_capture_index_t captureIndex)#

Read captured value from a FlexPWM capture channel.

This function reads the captured counter value from one of the six capture value registers (CVAL0-5) for the specified capture channel and edge detector.

Note

CVAL register mapping (NON-INTUITIVE):

kFLEXPWM_Capture_X_Edge0 -> CVAL0
kFLEXPWM_Capture_X_Edge1 -> CVAL1
kFLEXPWM_Capture_A_Edge0 -> CVAL2
kFLEXPWM_Capture_A_Edge1 -> CVAL3
kFLEXPWM_Capture_B_Edge0 -> CVAL4
kFLEXPWM_Capture_B_Edge1 -> CVAL5

Warning

Destructive read:

Reading a CVAL register decrements the FIFO count by 1.
If the FIFO is empty, the read value is undefined.
Check the FIFO empty flag (CFx) before reading to avoid invalid data.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
captureIndex – Capture channel and edge detector index (use flexpwm_capture_index_t enum).

Returns:

The captured counter value (16-bit).

uint16_t FLEXPWM_GetInputCaptureCycle(PWM_Type *base, uint8_t submodule, flexpwm_capture_index_t captureIndex)#

Read captured cycle counter value from a FlexPWM capture channel.

This function reads the captured cycle counter value from one of the six capture cycle registers (CCYC0-5) for the specified capture channel and edge detector. The cycle counter value represents the upper part of the extended timestamp when a capture event occurs.

Note

CCYC register mapping (matches CVAL mapping):

kFLEXPWM_Capture_X_Edge0 -> CCYC0
kFLEXPWM_Capture_X_Edge1 -> CCYC1
kFLEXPWM_Capture_A_Edge0 -> CCYC2
kFLEXPWM_Capture_A_Edge1 -> CCYC3
kFLEXPWM_Capture_B_Edge0 -> CCYC4
kFLEXPWM_Capture_B_Edge1 -> CCYC5

Note

Combined timestamp:

The full timestamp is {CCYC, CVAL} (cycle counter as upper 16 bits, capture value as lower 16 bits), forming a 32-bit extended timestamp.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
captureIndex – Capture channel and edge detector index (use flexpwm_capture_index_t enum).

Returns:

The captured cycle counter value (16-bit).

void FLEXPWM_EnableInputCapture(PWM_Type *base, uint8_t submodule, flexpwm_capture_channel_t channel)#

Enable input capture for a FlexPWM capture channel.

This function enables input capture operation for the specified capture channel by setting the corresponding ARM bit (ARMA/ARMB/ARMX) in the capture control register.

Note

ARM bit behavior in one-shot mode: When the capture channel is configured for one-shot mode (ONESHOT = 1), the ARM bit automatically clears after two capture events complete.

Note

Prerequisites: Before enabling capture, ensure:

Capture channel is configured (FLEXPWM_ConfigInputCapture)
Edge detectors are configured (EDGA0/EDGA1, EDGB0/EDGB1, or EDGX0/EDGX1)
Counter is running (FLEXPWM_EnableSubmoduleCounter)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
channel – Capture channel selection (use flexpwm_capture_channel_t enum).

void FLEXPWM_DisableInputCapture(PWM_Type *base, uint8_t submodule, flexpwm_capture_channel_t channel)#

Disable input capture for a FlexPWM capture channel.

This function disables input capture operation for the specified capture channel by clearing the corresponding ARM bit (ARMA/ARMB/ARMX) in the capture control register.

Note

FIFO handling: Disabling capture does not flush the FIFO. Any previously captured values remain readable. Clear the capture flags (CFx0/CFx1) separately if needed.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
channel – Capture channel selection (use flexpwm_capture_channel_t enum).

static inline void FLEXPWM_SetINIT(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the INIT register value for a FlexPWM submodule.

This function directly writes a value to the INIT register (initial count register). The INIT register defines the starting value of the counter when it is initialized.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM parameters. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for:

Ensuring LDOK is clear before calling this function
Setting LDOK after updating registers to trigger reload
Managing reload timing and synchronization

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the INIT register (16-bit).

static inline void FLEXPWM_SetVAL0(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL0 register value for a FlexPWM submodule.

This function directly writes a value to the VAL0 register. VAL0 defines the half-cycle reload point for the PWM counter.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL0 register (16-bit).

static inline void FLEXPWM_SetVAL1(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL1 register value for a FlexPWM submodule.

This function directly writes a value to the VAL1 register. VAL1 defines the modulo (period) value for the PWM counter.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM period. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL1 register (16-bit).

static inline void FLEXPWM_SetVAL2(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL2 register value for a FlexPWM submodule.

This function directly writes a value to the VAL2 register. VAL2 defines the count value at which PWM23 (PWM_A) is set high, controlling the turn-on edge of PWM_A output.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM_A duty cycle. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL2 register (16-bit).

static inline void FLEXPWM_SetVAL3(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL3 register value for a FlexPWM submodule.

This function directly writes a value to the VAL3 register. VAL3 defines the count value at which PWM23 (PWM_A) is set low, controlling the turn-off edge of PWM_A output.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL3 register (16-bit).

static inline void FLEXPWM_SetVAL4(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL4 register value for a FlexPWM submodule.

This function directly writes a value to the VAL4 register. VAL4 defines the count value at which PWM45 (PWM_B) is set high, controlling the turn-on edge of PWM_B output.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM_B duty cycle. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL4 register (16-bit).

static inline void FLEXPWM_SetVAL5(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL5 register value for a FlexPWM submodule.

This function directly writes a value to the VAL5 register. VAL5 defines the count value at which PWM45 (PWM_B) is set low, controlling the turn-off edge of PWM_B output.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL5 register (16-bit).

static inline void FLEXPWM_SetDTCNT0(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the DTCNT0 register value for a FlexPWM submodule.

This function directly writes a value to the DTCNT0 register (deadtime count register 0). DTCNT0 specifies the number of IPBus clock cycles for deadtime delay insertion, independent of the PWM clock prescaler settings (CTRL[PRSC] and CTRL2[CLK_SEL]). DTCNT0 inserts software-selectable activation delays at PWM_A turn-on edge.

Note

DTCNT0 is an 11-bit register with valid range 0-0x7FF. Values exceeding this range will be masked to 11 bits.

Note

This function applies only to complementary PWM mode.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the DTCNT0 register (11-bit, range: 0-0x7FF).

static inline void FLEXPWM_SetDTCNT1(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the DTCNT1 register value for a FlexPWM submodule.

This function directly writes a value to the DTCNT1 register (deadtime count register 1). DTCNT1 specifies the number of IPBus clock cycles for deadtime delay insertion, independent of the PWM clock prescaler settings (CTRL[PRSC] and CTRL2[CLK_SEL]). DTCNT1 inserts software-selectable activation delays at PWM_B turn-on edge.

Note

DTCNT1 is an 11-bit register with valid range 0-0x7FF. Values exceeding this range will be masked to 11 bits.

Note

This function applies only to complementary PWM mode.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the DTCNT1 register (11-bit, range: 0-0x7FF).

static inline void FLEXPWM_SetPhaseDelay(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the Phase Delay register value for a FlexPWM submodule.

This function directly writes a value to the PHASEDLY register (phase delay register). PHASEDLY defines the time delay from the master sync signal (from submodule 0) to when this submodule recognizes the master sync, specified in PWM clock cycles.

Setting this register to a non-zero value and using the master sync signal as the initialization source allows this submodule’s output to be delayed by a fixed number of cycles relative to submodule 0, enabling phase-shifted PWM outputs.

Note

PHASEDLY is only valid for submodules 1-3. Submodule 0 is the master sync source and cannot have a phase delay relative to itself.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust phase delay. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (1-3, must NOT be 0).
value – The value to write to the PHASEDLY register (16-bit).

static inline void FLEXPWM_SetCompareMode(PWM_Type *base, uint8_t submodule, flexpwm_compare_mode_t compareMode)#

Set Compare Mode for a FlexPWM submodule.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
compareMode – The compare mode to set for the submodule.

static inline void FLEXPWM_MaskPWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Mask PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function sets the MASK register bits to mask (disable) PWM outputs by forcing them to logic 0 before output polarity is applied. The mask takes effect when a FORCE_OUT event occurs on the corresponding submodule, unless immediate update is enabled.

Note

MASK register characteristics:

Double-buffered register: writes take effect on next FORCE_OUT event
Use FLEXPWM_EnableUpdateMaskImmediately() to bypass FORCE_OUT requirement
Masking forces output to logic 0 before polarity inversion

Note

This function performs read-modify-write to preserve:

Mask settings for other submodules not specified in parameters
UPDATE_MASK bits (on platforms with FSL_FEATURE_PWM_MASK_HAS_UPDATE_MASK_BITFIELD)

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_UnMaskPWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Unmask PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function clears the MASK register bits to unmask (enable) PWM outputs. The unmask takes effect when a FORCE_OUT event occurs on the corresponding submodule, unless immediate update is enabled.

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_EnableUpdateMaskImmediately(PWM_Type *base, uint16_t submoduleMask)#

Enable immediate MASK register update for specified submodules.

This function configures the specified submodules to update their MASK register values immediately, bypassing the FORCE_OUT event requirement. This is useful for emergency stop or fault protection scenarios where immediate output masking is required.

Note

MASK[UPDATE_MASK] register characteristics:

Setting a bit to 1 enables immediate MASK update for that submodule
Once enabled, MASK updates take effect immediately without waiting for FORCE_OUT

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetPWMSource23(PWM_Type *base, uint8_t submodule, uint16_t source)#

Set PWM source for PWM23 (PWM_A) of a submodule.

This function selects the signal source that feeds into the deadtime insertion logic for PWM23 (PWM_A) output by configuring the DTSRCSEL register. The setting takes effect when a FORCE_OUT event occurs on the submodule.

Available sources:

Generated PWM: Normal PWM signal from PWM generator
Inverted PWM: Inverted version of generated PWM
Software: Software-controlled value from SWCOUT register
External: External input signal

Note

DTSRCSEL register characteristics:

Double-buffered: Changes take effect on next FORCE_OUT event
NOT affected by MCTRL[LDOK]: Independent of reload mechanism
Global register: This function performs read-modify-write to protect other submodules

Note

When source is set to kFLEXPWM_ForcePwmSource_Software, use FLEXPWM_SetSoftwareControlOutput23() to set the output value.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
source – PWM source selection (use flexpwm_force_pwm_source_t enum).

static inline void FLEXPWM_SetPWMSource45(PWM_Type *base, uint8_t submodule, uint16_t source)#

Set PWM source for PWM45 (PWM_B) of a submodule.

This function selects the signal source that feeds into the deadtime insertion logic for PWM45 (PWM_B) output by configuring the DTSRCSEL register. The setting takes effect when a FORCE_OUT event occurs on the submodule.

Note

See FLEXPWM_SetPWMSource23() documentation for detailed information about source selection, register characteristics, and usage notes.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
source – PWM source selection (use flexpwm_force_pwm_source_t enum).

static inline void FLEXPWM_SetSoftwareControlOutput23(PWM_Type *base, uint8_t submodule, uint16_t softwareValue)#

Set software-controlled output value for PWM23 (PWM_A) of a submodule.

This function sets the software-controlled PWM output value in the SWCOUT register. This value is used as the PWM source when DTSRCSEL is configured to select software control (kFLEXPWM_ForcePwmSource_Software). The setting takes effect when a FORCE_OUT event occurs on the submodule.

Note

SWCOUT register characteristics:

Double-buffered: Changes take effect on next FORCE_OUT event
NOT affected by MCTRL[LDOK]: Independent of reload mechanism
Global register: This function performs read-modify-write to protect other submodules

Note

Typical usage sequence:

Call FLEXPWM_SetPWMSource23(base, kFLEXPWM_ForcePwmSource_Software, submodule)
Call FLEXPWM_SetSoftwareControlOutput23(base, value, submodule)
Trigger FORCE_OUT event to make both settings take effect

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
softwareValue – Software control output value (0 or 1).
- 0: Logic 0 provided to deadtime logic instead of PWM23
- 1: Logic 1 provided to deadtime logic instead of PWM23

static inline void FLEXPWM_SetSoftwareControlOutput45(PWM_Type *base, uint8_t submodule, uint16_t softwareValue)#

Set software-controlled output value for PWM45 (PWM_B) of a submodule.

Note

See FLEXPWM_SetSoftwareControlOutput23() documentation for detailed information about register characteristics, usage sequence, and notes.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
softwareValue – Software control output value (0 or 1).
- 0: Logic 0 provided to deadtime logic instead of PWM45
- 1: Logic 1 provided to deadtime logic instead of PWM45

static inline void FLEXPWM_SetComplementaryPWMSource23(PWM_Type *base, uint16_t submoduleMask)#

Select PWM23 (PWM_A) as complementary PWM source for specified submodules.

This function configures the MCTRL[IPOL] register to select PWM23 (PWM_A) as the source for generating complementary PWM pair outputs in complementary mode. The setting takes effect when a FORCE_OUT event occurs on the submodule.

In complementary mode:

PWM_A output: PWM23 signal (non-inverted)
PWM_B output: ~PWM23 signal (inverted complement)

Note

MCTRL[IPOL] register characteristics:

Takes effect on FORCE_OUT event (double-buffered behavior)
Only applies when submodule is in complementary mode (INDEP = 0)
Ignored in independent mode (INDEP = 1)

Note

This function clears IPOL bits for specified submodules (IPOL = 0 selects PWM23).

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetComplementaryPWMSource45(PWM_Type *base, uint16_t submoduleMask)#

Select PWM45 (PWM_B) as complementary PWM source for specified submodules.

This function configures the MCTRL[IPOL] register to select PWM45 (PWM_B) as the source for generating complementary PWM pair outputs in complementary mode. The setting takes effect when a FORCE_OUT event occurs on the submodule.

In complementary mode:

PWM_A output: ~PWM45 signal (inverted complement)
PWM_B output: PWM45 signal (non-inverted)

Note

See FLEXPWM_SetComplementaryPWMSource23() documentation for detailed information about MCTRL[IPOL] characteristics and complementary mode operation.

Note

This function sets IPOL bits for specified submodules (IPOL = 1 selects PWM45).

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetLoadOkay(PWM_Type *base, uint16_t submoduleMask)#

Set Load Okay (LDOK) for specified submodules.

This function sets the MCTRL[LDOK] bits to enable register reload for the specified submodules. When LDOK is set, buffered register values will be transferred to active registers according to the reload mode and timing configured in CTRL[LDMOD, LDFQ, HALF, FULL].

Note

LDOK behavior:

Can only be set when the corresponding LDOK bit is currently 0
Automatically cleared by hardware after reload completes
Can be manually cleared using FLEXPWM_ClearLoadOkay()
While LDOK=1, writes to buffered registers are blocked

Note

Typical usage flow:

Modify buffered registers (VAL0-5, INIT, etc.) using FLEXPWM_SetVALx() or similar
Call FLEXPWM_SetLoadOkay() to trigger reload
Hardware transfers buffered values at the configured reload opportunity
LDOK automatically clears after reload completes

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_ClearLoadOkay(PWM_Type *base, uint16_t submoduleMask)#

Clear Load Okay (LDOK) for specified submodules.

This function clears the MCTRL[LDOK] bits by writing to MCTRL[CLDOK] bits. This cancels a pending reload operation for the specified submodules.

Note

MCTRL[CLDOK] (Clear LDOK) mechanism:

Writing 1 to CLDOK[x] clears the corresponding LDOK[x] bit
CLDOK is write-only; reading always returns 0
Use this when you need to cancel a pending reload

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline uint16_t FLEXPWM_GetLoadOkay(PWM_Type *base)#

Get Load Okay (LDOK) status.

This function reads the MCTRL[LDOK] bits to check which submodules have pending reload operations.

Note

Return value format:

Bit[0]: Submodule 0 LDOK status
Bit[1]: Submodule 1 LDOK status
Bit[2]: Submodule 2 LDOK status
Bit[3]: Submodule 3 LDOK status

Note

Usage example:

uint16_t ldokStatus = FLEXPWM_GetLoadOkay(PWM0);
if (ldokStatus & kFLEXPWM_SubmoduleMask_0) {
}

Parameters:

base – FlexPWM peripheral base address.

Returns:

LDOK status bits (bit[3:0] correspond to submodules 3-0). Use flexpwm_submodule_mask_t enum values to check specific submodules.

static inline void FLEXPWM_SetLocalForceOut(PWM_Type *base, uint8_t submodule)#

Set local FORCE_OUT event for a submodule.

This function sets the SMxCTRL2[FORCE] bit to trigger a local FORCE_OUT event. When a FORCE_OUT event occurs, several double-buffered registers immediately update:

DTSRCSEL (PWM source selection)
SWCOUT (software-controlled output values)
MASK (output masking)
MCTRL[IPOL] (complementary PWM source selection)

Additionally, if CTRL2[FRCEN] is enabled and the counter is running, the counter will be initialized to the INIT register value.

Note

FORCE_OUT trigger source: This function triggers a local FORCE_OUT event by setting CTRL2[FORCE]. The FORCE_OUT event only occurs if CTRL2[FORCE_SEL] = 0 (local force selected). If FORCE_SEL selects a different source, setting FORCE has no effect.

Note

Counter initialization: The counter is reinitialized only if:

CTRL2[FRCEN] = 1 (force initialization enabled), AND
MCTRL[RUN] = 1 (counter running) OR CTRL2[CLK_SEL] = 2 (submodule 0 aux clock)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).

static inline void FLEXPWM_SetCounterForceInitialization(PWM_Type *base, uint8_t submodule, bool enable)#

Enable or disable counter initialization on FORCE_OUT event.

This function controls whether FORCE_OUT events can trigger counter initialization by configuring the CTRL2[FRCEN] bit. When enabled, the counter will be reset to the INIT register value when local software forced event occurs.

Note

Counter initialization conditions: The counter is reinitialized only when ALL of the following conditions are met:

CTRL2[FRCEN] = 1 (enabled via this function), AND
A local FORCE_OUT event occurs (CTRL2[FORCE_SEL] = 0, CTRL2[FORCE] = 1)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
enable – Enable or disable counter force initialization:
- true: FORCE_OUT events can trigger counter initialization (FRCEN = 1)
- false: FORCE_OUT events do not affect counter initialization (FRCEN = 0)

static inline void FLEXPWM_EnableSubmoduleCounter(PWM_Type *base, uint16_t submoduleMask)#

Enable PWM counter for specified submodules.

This function enables the PWM counters for the specified submodules by setting MCTRL[RUN] bits. When enabled, the counters start running and generating PWM waveforms.

Note

Effects of enabling counter (RUN=1):

Counter begins incrementing/decrementing according to configuration
PWM generation starts (if outputs are also enabled)
Reload events can occur at configured opportunities
FORCE_OUT can trigger counter initialization (if FRCEN enabled)

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_DisableSubmoduleCounter(PWM_Type *base, uint16_t submoduleMask)#

Disable PWM counter for specified submodules.

This function disables the PWM counters for the specified submodules by clearing MCTRL[RUN] bits. When disabled, the counters stop running but retain their configuration.

Note

Effects of disabling counter (RUN=0):

Counter stops incrementing/decrementing
PWM generation ceases (outputs hold last state or go to fault state)
Configuration registers remain intact
Fault clearing behavior changes (see fault protection documentation)

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_EnablePWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Enable PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function enables PWM outputs by setting the corresponding bits in the OUTEN register. Each output (PWM_A, PWM_B, PWM_X) can be independently enabled for each submodule.

Note

OUTEN register layout (same as MASK register):

bit[11:8]: PWMA_EN - PWM_A output enable for submodules 3-0
bit[7:4]: PWMB_EN - PWM_B output enable for submodules 3-0
bit[3:0]: PWMX_EN - PWM_X output enable for submodules 3-0

Note

Prerequisites: Before enabling outputs, ensure:

PWM waveform is configured (FLEXPWM_ConfigPWM)
Counter is running (FLEXPWM_EnableSubmoduleCounter)
Outputs are not masked (check MASK register)

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_DisablePWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Disable PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function disables PWM outputs by clearing the corresponding bits in the OUTEN register. When an output is disabled, the pin is released from FlexPWM control and may be controlled by other peripherals or GPIO.

Note

Output disable effects:

Pin is tri-stated or controlled by GPIO/other peripherals
PWM waveform generation continues internally
Re-enabling the output will resume PWM operation seamlessly

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetWriteProtection(PWM_Type *base, flexpwm_write_protect_t config)#

Set FlexPWM write protection mode.

This function configures the write protection for FlexPWM registers by setting MCTRL2[WRPROT]. Write protection prevents accidental modification of critical PWM configuration registers.

Note

Write protection modes:

kFLEXPWM_WriteProtect_Off: Write protection is disabled (default after reset)
kFLEXPWM_WriteProtect_On: Write protection is enabled but can be disabled
kFLEXPWM_WriteProtect_OffLocked: Write protection is disabled and locked until chip reset
kFLEXPWM_WriteProtect_OnLocked: Write protection is enabled and locked until chip reset

Note

Once a locked mode is set (OffLocked or OnLocked), the write protection state cannot be changed until the next chip reset. Use locked modes for safety-critical applications.

Parameters:

base – FlexPWM peripheral base address.
config – Write protection mode selection.

static inline void FLEXPWM_EnableSubmoduleInterrupts(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Enable FlexPWM submodule interrupts.

This function enables the specified interrupt sources for a FlexPWM submodule by setting the corresponding bits in the SMxINTEN register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Interrupt enable mask (OR’ed combination of _flexpwm_submodule_interrupt_enable flags).

static inline void FLEXPWM_DisableSubmoduleInterrupts(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Disable FlexPWM submodule interrupts.

This function disables the specified interrupt sources for a FlexPWM submodule by clearing the corresponding bits in the SMxINTEN register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Interrupt disable mask (OR’ed combination of _flexpwm_submodule_interrupt_enable flags).

static inline uint16_t FLEXPWM_GetSubmoduleStatusFlags(PWM_Type *base, uint8_t submodule)#

Get FlexPWM submodule status flags.

This function returns the current status flags from the SMxSTS register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).

Returns:

Current status flags (combination of _flexpwm_submodule_status_flag values).

static inline void FLEXPWM_ClearSubmoduleStatusFlags(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Clear FlexPWM submodule status flags.

This function clears the specified status flags in the SMxSTS register using the write-1-to-clear (W1C) mechanism.

Note

Do not attempt to clear kFLEXPWM_RegisterUpdatedFlag (RUF) as it is read-only.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Status flag clear mask (OR’ed combination of _flexpwm_submodule_status_flag values). To clear a flag, set the corresponding bit to 1 in the mask.

static inline void FLEXPWM_EnableFaultInterrupts(PWM_Type *base, uint8_t faultChannel, uint16_t mask)#

Enable FlexPWM fault interrupts.

This function enables the specified fault interrupt sources by setting the corresponding bits in the FCTRL[FIE] field.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1): The same mask bit values are used for both fault channels. The faultChannel parameter determines which set of fault inputs is controlled:

faultChannel = 0: Controls FAULT0-3 interrupts
faultChannel = 1: Controls FAULT4-7 interrupts

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault interrupt enable mask (OR’ed combination of _flexpwm_fault_interrupt_enable flags).

static inline void FLEXPWM_DisableFaultInterrupts(PWM_Type *base, uint8_t faultChannel, uint16_t mask)#

Disable FlexPWM fault interrupts.

This function disables the specified fault interrupt sources by clearing the corresponding bits in the FCTRL[FIE] field.

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault interrupt disable mask (OR’ed combination of _flexpwm_fault_interrupt_enable flags).

static inline uint16_t FLEXPWM_GetFaultStatusFlags(PWM_Type *base, uint8_t faultChannel)#

Get FlexPWM fault status flags.

This function returns the current fault status flags (FFLAG bits) from the FSTS register. These are latched flags that indicate a fault event has occurred.

Note

To check real-time hardware pin status (rather than latched flags), use FLEXPWM_GetFaultFilteredPinStatusFlags() instead.

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)

Returns:

Current fault flags (combination of _flexpwm_fault_status_flag values).

static inline void FLEXPWM_ClearFaultStatusFlags(PWM_Type *base, uint8_t faultChannel, uint16_t mask)#

Clear FlexPWM fault status flags.

This function clears the specified fault status flags (FFLAG bits) in the FSTS register using the write-1-to-clear (W1C) mechanism.

Note

Clearing FFLAG does not automatically re-enable PWM outputs. The re-enable timing depends on fault clearing mode (FAUTO), safety mode (FSAFE), recovery timing (FHALF/FFULL), and the state of FFPIN (filtered pin status).

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault flag clear mask (OR’ed combination of _flexpwm_fault_status_flag values). To clear a flag, set the corresponding bit to 1 in the mask.

static inline uint16_t FLEXPWM_GetFaultFilteredPinStatusFlags(PWM_Type *base, uint8_t faultChannel)#

Get FlexPWM filtered fault pin status.

This function returns the real-time status of fault pins after filtering (FFPIN bits) from the FSTS register. These are read-only hardware status bits that reflect the current state of external fault signals.

Note

Key differences:

FFLAG: Software-clearable latched flag (historical event - “a fault occurred”)
FFPIN: Read-only real-time status (current state - “fault is active now”)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3 pins)
- 1: Fault channel 1 (FAULT4-7 pins, if supported)

Returns:

Current filtered fault pin status (combination of _flexpwm_fault_pin_status values).

void FLEXPWM_ConfigDMA(PWM_Type *base, uint8_t submodule, const flexpwm_dma_config_t *config)#

Configures the DMA control strategy for a FlexPWM submodule.

This function configures the DMA trigger source and FIFO watermark logic. These settings define the DMA request generation strategy and should typically be configured once during initialization.

Note

This function only configures CAPTDE[7:6] and FAND bits in SMxDMAEN register. To enable/disable individual DMA channels at runtime, use FLEXPWM_EnableDMA() and FLEXPWM_DisableDMA().

Note

Prerequisites: Before calling this function, ensure:

FIFO watermark levels are configured in FLEXPWM_ConfigInputCapture()
Capture channels are properly configured if using capture DMA

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
config – Pointer to DMA configuration structure

static inline void FLEXPWM_EnableDMA(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Enable FlexPWM submodule DMA requests.

This function enables DMA request generation for the specified channels. It controls the VALDE bit (VALx/FRACVALx write) and capture channel enables (CX0DE, CX1DE, CB0DE, CB1DE, CA0DE, CA1DE).

Note

Before calling this function, ensure FLEXPWM_ConfigDMA() has been called to set up the DMA trigger strategy.

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
mask – Bit mask of DMA enable flags (OR’ed combination of _flexpwm_dma_enable)

static inline void FLEXPWM_DisableDMA(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Disable FlexPWM submodule DMA requests.

This function disables DMA request generation for the specified channels.

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
mask – Bit mask of DMA enable flags (OR’ed combination of _flexpwm_dma_enable)

FSL_FLEXPWM_DRIVER_VERSION#: Version 2.0.0

enum _flexpwm_clock_source#

FlexPWM clock source selection.

Values:

enumerator kFLEXPWM_ClockSource_IPBusClock#: IPBus clock

enumerator kFLEXPWM_ClockSource_ExtClock#: External clock (EXT_CLK)

enumerator kFLEXPWM_ClockSource_Submodule0Clock#: Submodule 0 auxiliary clock

enum _flexpwm_prescaler#

FlexPWM clock prescaler selection.

Values:

enumerator kFLEXPWM_Prescale_Divide_1#: Divide by 1

enumerator kFLEXPWM_Prescale_Divide_2#: Divide by 2

enumerator kFLEXPWM_Prescale_Divide_4#: Divide by 4

enumerator kFLEXPWM_Prescale_Divide_8#: Divide by 8

enumerator kFLEXPWM_Prescale_Divide_16#: Divide by 16

enumerator kFLEXPWM_Prescale_Divide_32#: Divide by 32

enumerator kFLEXPWM_Prescale_Divide_64#: Divide by 64

enumerator kFLEXPWM_Prescale_Divide_128#: Divide by 128

enum _flexpwm_load_mode#

FlexPWM load mode selection.

Values:

enumerator kFLEXPWM_LoadMode_Opportunity#: Load at PWM reload opportunity

enumerator kFLEXPWM_LoadMode_Immediate#: Load immediately after LDOK is set

enum _flexpwm_reload_source#

FlexPWM reload source selection.

Values:

enumerator kFLEXPWM_ReloadSource_LocalReload#: Local reload signal

enumerator kFLEXPWM_ReloadSource_MasterReload#: Master reload signal from submodule 0

enum _flexpwm_init_source#

FlexPWM counter initialization source selection.

Values:

enumerator kFLEXPWM_InitSource_LocalSync#: Local sync signal

enumerator kFLEXPWM_InitSource_MasterReload#: Master reload signal from submodule 0

enumerator kFLEXPWM_InitSource_MasterSync#: Master sync signal from submodule 0

enumerator kFLEXPWM_InitSource_ExtSync#: External sync signal (EXT_SYNC)

enum _flexpwm_compare_mode#

FlexPWM PWM compare mode selection.

Values:

enumerator kFLEXPWM_CompareMode_Equal#: Compare when counter equals compare value

enumerator kFLEXPWM_CompareMode_EqualGreater#: Compare when counter is equal or greater than compare value

enum _flexpwm_submodule_mask#

FlexPWM submodule mask for multi-submodule operations.

These flags can be OR’ed together to specify multiple submodules simultaneously. Used with functions that operate on multiple submodules at once.

Values:

enumerator kFLEXPWM_SubmoduleMask_0#: Submodule 0

enumerator kFLEXPWM_SubmoduleMask_1#: Submodule 1

enumerator kFLEXPWM_SubmoduleMask_2#: Submodule 2

enum _flexpwm_pwm_polarity#

FlexPWM PWM output polarity selection.

Values:

enumerator kFLEXPWM_Polarity_ActiveHigh#: PWM signal is normal (active high)

enumerator kFLEXPWM_Polarity_ActiveLow#: PWM signal is inverted (active low)

enum _flexpwm_ipol_source#

FlexPWM PWM output source selection for complementary mode.

Values:

enumerator kFLEXPWM_IPOL_PWM23#: Use PWM23 (PWM_A) as complementary PWM source

enumerator kFLEXPWM_IPOL_PWM45#: Use PWM45 (PWM_B) as complementary PWM source

enum _flexpwm_force_output_source#

FlexPWM FORCE_OUT event source selection.

Values:

enumerator kFLEXPWM_ForceOutputSource_LocalForce#: Local software forced event

enumerator kFLEXPWM_ForceOutputSource_MasterForce#: Master force signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_LocalReload#: Local reload signal

enumerator kFLEXPWM_ForceOutputSource_MasterReload#: Master reload signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_LocalSync#: Local sync signal

enumerator kFLEXPWM_ForceOutputSource_MasterSync#: Master sync signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_ExtForce#: External force signal (EXT_FORCE)

enumerator kFLEXPWM_ForceOutputSource_ExtSync#: External sync signal (EXT_SYNC)

enum _flexpwm_force_pwm_source#

FlexPWM PWM source selection for deadtime logic (DTSRCSEL)

Values:

enumerator kFLEXPWM_ForcePwmSource_Generated#: Generated PWM signal

enumerator kFLEXPWM_ForcePwmSource_Inverted#: Inverted PWM signal

enumerator kFLEXPWM_ForcePwmSource_Software#: Software controlled output (SWCOUT)

enumerator kFLEXPWM_ForcePwmSource_External#: External signal

enum _flexpwm_fault_output_behavior#

FlexPWM fault output behavior during fault condition.

Defines how PWM outputs respond when a fault is detected. Values map directly to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS] bitfields.

Values:

enumerator kFLEXPWM_FaultOutput_Force0#: 0b00 - Force output to logic 0

enumerator kFLEXPWM_FaultOutput_Force1#: 0b01 - Force output to logic 1

enumerator kFLEXPWM_FaultOutput_HighZ#: 0b10/0b11 - High impedance (3-state) output

enum _flexpwm_fault_mask#

FlexPWM fault input mask for fault protection configuration.

These flags can be OR’ed together to configure multiple fault inputs simultaneously with the same protection parameters. Used with FLEXPWM_ConfigFaultProtection() function.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1):

When faultChannel = 0: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT0-3
When faultChannel = 1: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT4-7 The enum values are the same, but the channel parameter determines which physical fault inputs are configured.

Values:

enumerator kFLEXPWM_FaultMask_0#: FAULT0 (ch0) or FAULT4 (ch1)

enumerator kFLEXPWM_FaultMask_1#: FAULT1 (ch0) or FAULT5 (ch1)

enumerator kFLEXPWM_FaultMask_2#: FAULT2 (ch0) or FAULT6 (ch1)

enumerator kFLEXPWM_FaultMask_3#: FAULT3 (ch0) or FAULT7 (ch1)

enum _flexpwm_fault_clearing_mode#

FlexPWM fault clearing mode selection.

Defines how fault conditions are cleared after a fault event.

Values:

enumerator kFLEXPWM_FaultClearingMode_Manual#: Manual clearing - software must clear FSTS[FFLAGx]

enumerator kFLEXPWM_FaultClearingMode_Automatic#: Automatic clearing when FAULTx de-asserts

enum _flexpwm_write_protect#

FlexPWM write protection mode selection.

Values:

enumerator kFLEXPWM_WriteProtect_Off#: Write protection off (default)

enumerator kFLEXPWM_WriteProtect_On#: Write protection on

enumerator kFLEXPWM_WriteProtect_OffLocked#: Write protection off and locked until chip reset

enumerator kFLEXPWM_WriteProtect_OnLocked#: Write protection on and locked until chip reset

enum _flexpwm_stretch_prescaler#

FlexPWM trigger signal stretch prescaler selection.

Stretch IPBus clock count prescaler for trigger signals including: mux0_trig, mux1_trig, out0_trig, out1_trig, pwma_trig, pwmb_trig

Values:

enumerator kFLEXPWM_StretchPrescaler_None#: No stretch

enumerator kFLEXPWM_StretchPrescaler_2Clocks#: Stretch for 2 IPBus clock periods

enumerator kFLEXPWM_StretchPrescaler_4Clocks#: Stretch for 4 IPBus clock periods

enumerator kFLEXPWM_StretchPrescaler_8Clocks#: Stretch for 8 IPBus clock periods

enum _flexpwm_trigger_mux_source#

FlexPWM output trigger source selection for PWM_MUX_TRIG0/1 ports.

Selects which signal is routed to the PWM_MUX_TRIG0/1 output ports.

Values:

enumerator kFLEXPWM_TriggerMuxSource_GeneratedTrigger#: Use PWM_OUT_TRIG0/1 (generated trigger signal)

enumerator kFLEXPWM_TriggerMuxSource_PWMOutput#: Use PWM_A/PWM_B output directly

enum _flexpwm_trigger_frequency#

FlexPWM output trigger frequency selection.

Controls the trigger output frequency when CTRL[LDFQ] is non-zero. Only takes effect when reload frequency divider is active (LDFQ > 0).

Values:

enumerator kFLEXPWM_TriggerFrequency_EveryCycle#: Trigger every PWM cycle even if reload doesn’t occur

enumerator kFLEXPWM_TriggerFrequency_OnReload#: Trigger only on last cycle before reload opportunity

enum _flexpwm_output_trigger_mask#

FlexPWM output trigger enable mask.

These flags can be OR’ed together to enable multiple trigger sources simultaneously. Used with outTriggerEnable field in flexpwm_output_trigger_config_t structure.

Values:

enumerator kFLEXPWM_OutputTriggerMask_VAL0#: VAL0 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL1#: VAL1 match triggers PWM_OUT_TRIG1

enumerator kFLEXPWM_OutputTriggerMask_VAL2#: VAL2 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL3#: VAL3 match triggers PWM_OUT_TRIG1

enumerator kFLEXPWM_OutputTriggerMask_VAL4#: VAL4 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL5#: VAL5 match triggers PWM_OUT_TRIG1

enum _flexpwm_capture_edge#

FlexPWM input capture edge selection.

This enumeration defines the edge detection modes for input capture. The enum values directly map to hardware register bit values.

Values:

enumerator kFLEXPWM_CaptureEdge_Disabled#: Disable capture (register bit value: 00b)

enumerator kFLEXPWM_CaptureEdge_Falling#: Capture on falling edge (register bit value: 01b)

enumerator kFLEXPWM_CaptureEdge_Rising#: Capture on rising edge (register bit value: 10b)

enumerator kFLEXPWM_CaptureEdge_Both#: Capture on any edge (register bit value: 11b)

enum _flexpwm_capture_fifo_watermark#

FlexPWM capture FIFO watermark selection.

This enumeration defines the FIFO watermark levels that determine when a watermark interrupt is triggered based on the number of valid samples in the FIFO.

Values:

enumerator kFLEXPWM_CaptureFifoWatermark_1#: Trigger when FIFO has 1 or more samples (00b)

enumerator kFLEXPWM_CaptureFifoWatermark_2#: Trigger when FIFO has 2 or more samples (01b)

enumerator kFLEXPWM_CaptureFifoWatermark_3#: Trigger when FIFO has 3 or more samples (10b)

enumerator kFLEXPWM_CaptureFifoWatermark_4#: Trigger when FIFO is full with 4 samples (11b)

enum _flexpwm_capture_input_select#

FlexPWM capture input source selection.

This enumeration selects the source signal for input capture.

Values:

enumerator kFLEXPWM_CaptureInput_RawSignal#: Use raw PWM input signal (register bit value: 0)

enumerator kFLEXPWM_CaptureInput_EdgeCounter#: Use edge counter output (register bit value: 1). Used to reduce capture frequency by counting N edges

enum _flexpwm_capture_index#

FlexPWM capture value index.

This enumeration defines the index for accessing capture value registers (CVAL0-5).

Note

Capture channel to CVAL register mapping (non-intuitive hardware mapping):

Capture_X Edge0/Edge1 -> CVAL0/CVAL1 (and CVAL0CYC/CVAL1CYC)
Capture_A Edge0/Edge1 -> CVAL2/CVAL3 (and CVAL2CYC/CVAL3CYC)
Capture_B Edge0/Edge1 -> CVAL4/CVAL5 (and CVAL4CYC/CVAL5CYC)

Values:

enumerator kFLEXPWM_Capture_X_Edge0#: CVAL0 - Capture_X Edge0

enumerator kFLEXPWM_Capture_X_Edge1#: CVAL1 - Capture_X Edge1

enumerator kFLEXPWM_Capture_A_Edge0#: CVAL2 - Capture_A Edge0

enumerator kFLEXPWM_Capture_A_Edge1#: CVAL3 - Capture_A Edge1

enumerator kFLEXPWM_Capture_B_Edge0#: CVAL4 - Capture_B Edge0

enumerator kFLEXPWM_Capture_B_Edge1#: CVAL5 - Capture_B Edge1

enum _flexpwm_capture_channel#

FlexPWM capture channel selection.

This enumeration defines the capture channel for enable/disable operations.

Values:

enumerator kFLEXPWM_Capture_A#: Capture channel A (PWM_A)

enumerator kFLEXPWM_Capture_B#: Capture channel B (PWM_B)

enumerator kFLEXPWM_Capture_X#: Capture channel X (PWM_X)

enum _flexpwm_submodule_interrupt_enable#

FlexPWM submodule interrupt enable flags.

These flags can be OR’ed together to enable multiple interrupt sources simultaneously. Use with FLEXPWM_EnableSubmoduleInterrupts() and FLEXPWM_DisableSubmoduleInterrupts().

Values:

enumerator kFLEXPWM_Compare0InterruptEnable#: VAL0 compare interrupt

enumerator kFLEXPWM_Compare1InterruptEnable#: VAL1 compare interrupt

enumerator kFLEXPWM_Compare2InterruptEnable#: VAL2 compare interrupt

enumerator kFLEXPWM_Compare3InterruptEnable#: VAL3 compare interrupt

enumerator kFLEXPWM_Compare4InterruptEnable#: VAL4 compare interrupt

enumerator kFLEXPWM_Compare5InterruptEnable#: VAL5 compare interrupt

enumerator kFLEXPWM_CaptureX0InterruptEnable#: Capture X0 interrupt

enumerator kFLEXPWM_CaptureX1InterruptEnable#: Capture X1 interrupt

enumerator kFLEXPWM_CaptureB0InterruptEnable#: Capture B0 interrupt

enumerator kFLEXPWM_CaptureB1InterruptEnable#: Capture B1 interrupt

enumerator kFLEXPWM_CaptureA0InterruptEnable#: Capture A0 interrupt

enumerator kFLEXPWM_CaptureA1InterruptEnable#: Capture A1 interrupt

enumerator kFLEXPWM_ReloadInterruptEnable#: Reload interrupt

enumerator kFLEXPWM_ReloadErrorInterruptEnable#: Reload error interrupt

enum _flexpwm_submodule_status_flag#

FlexPWM submodule status flags.

These flags represent the status of various events in a FlexPWM submodule. Use with FLEXPWM_GetSubmoduleStatusFlags() and FLEXPWM_ClearSubmoduleStatusFlags().

Note

kFLEXPWM_RegisterUpdatedFlag is read-only and cannot be cleared by software.

Values:

enumerator kFLEXPWM_Compare0Flag#: VAL0 compare flag

enumerator kFLEXPWM_Compare1Flag#: VAL1 compare flag

enumerator kFLEXPWM_Compare2Flag#: VAL2 compare flag

enumerator kFLEXPWM_Compare3Flag#: VAL3 compare flag

enumerator kFLEXPWM_Compare4Flag#: VAL4 compare flag

enumerator kFLEXPWM_Compare5Flag#: VAL5 compare flag

enumerator kFLEXPWM_CaptureX0Flag#: Capture X0 flag

enumerator kFLEXPWM_CaptureX1Flag#: Capture X1 flag

enumerator kFLEXPWM_CaptureB0Flag#: Capture B0 flag

enumerator kFLEXPWM_CaptureB1Flag#: Capture B1 flag

enumerator kFLEXPWM_CaptureA0Flag#: Capture A0 flag

enumerator kFLEXPWM_CaptureA1Flag#: Capture A1 flag

enumerator kFLEXPWM_ReloadFlag#: Reload flag

enumerator kFLEXPWM_ReloadErrorFlag#: Reload error flag

enumerator kFLEXPWM_RegisterUpdatedFlag#: Register updated flag (read-only)

enum _flexpwm_fault_interrupt_enable#

FlexPWM fault interrupt enable flags.

These flags can be OR’ed together to enable multiple fault interrupt sources. Use with FLEXPWM_EnableFaultInterrupts() and FLEXPWM_DisableFaultInterrupts().

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1): The same bit mask values are used for both fault channels:

faultChannel = 0: Controls FAULT0-3
faultChannel = 1: Controls FAULT4-7 The bit positions are the same, but the function parameter determines which fault channel is configured.

Values:

enumerator kFLEXPWM_Fault0InterruptEnable#: FAULT0 (ch0) or FAULT4 (ch1) interrupt

enumerator kFLEXPWM_Fault1InterruptEnable#: FAULT1 (ch0) or FAULT5 (ch1) interrupt

enumerator kFLEXPWM_Fault2InterruptEnable#: FAULT2 (ch0) or FAULT6 (ch1) interrupt

enumerator kFLEXPWM_Fault3InterruptEnable#: FAULT3 (ch0) or FAULT7 (ch1) interrupt

enum _flexpwm_fault_status_flag#

FlexPWM fault status flags (FFLAG)

These flags represent the latched fault status (FFLAG bits in FSTS register). Use with FLEXPWM_GetFaultStatusFlags() and FLEXPWM_ClearFaultStatusFlags().

Note

FFLAG characteristics:

Write-1-to-clear: Software must write 1 to clear each flag
Latched event: Set within 2 CPU cycles after FAULTx pin transitions to active state
Historical record: Indicates a fault event has occurred (not current pin state)
Interrupt capable: Can generate CPU interrupt requests when enabled
Manual clearing: Does not auto-clear; requires explicit software action

Note

To check the real-time, filtered hardware pin status (not the latched event), use FLEXPWM_GetFaultFilteredPinStatusFlags() to read FFPIN instead.

Note

For dual-channel platforms: The same bit mask values apply to both channels.

faultChannel = 0: FAULT0-3 flags
faultChannel = 1: FAULT4-7 flags

Values:

enumerator kFLEXPWM_Fault0Flag#: FAULT0 (ch0) or FAULT4 (ch1) flag

enumerator kFLEXPWM_Fault1Flag#: FAULT1 (ch0) or FAULT5 (ch1) flag

enumerator kFLEXPWM_Fault2Flag#: FAULT2 (ch0) or FAULT6 (ch1) flag

enumerator kFLEXPWM_Fault3Flag#: FAULT3 (ch0) or FAULT7 (ch1) flag

enum _flexpwm_fault_pin_status#

FlexPWM filtered fault pin status (FFPIN - read-only)

These flags represent the real-time status of fault pins after filtering (FFPIN bits in FSTS register). Use with FLEXPWM_GetFaultFilteredPinStatusFlags() to check if external fault signals are currently active.

Note

FFPIN characteristics:

Read-only: Cannot be written or cleared by software
Real-time status: Reflects current state of filtered FAULTx pin (not historical)
Polarity converted: Always shows active-high logic (1 = fault present)
Filter output: Shows fault filter output, not raw pin state
No interrupt: Does not directly generate interrupts (use FFLAG for interrupts)
Filter delay: May remain high briefly after raw pin clears due to filter latency

Note

Key differences from FFLAG:

FFLAG: Software-clearable latched flag (historical event - “a fault occurred”)
FFPIN: Read-only real-time status (current state - “fault is active now”)

Note

For dual-channel platforms: The same bit positions apply to both channels.

faultChannel = 0: FAULT0-3 pin status
faultChannel = 1: FAULT4-7 pin status

Values:

enumerator kFLEXPWM_Fault0PinActive#: FAULT0/4 pin active (filtered)

enumerator kFLEXPWM_Fault1PinActive#: FAULT1/5 pin active (filtered)

enumerator kFLEXPWM_Fault2PinActive#: FAULT2/6 pin active (filtered)

enumerator kFLEXPWM_Fault3PinActive#: FAULT3/7 pin active (filtered)

enum _flexpwm_dma_capture_source#

FlexPWM DMA capture source selection.

This enumeration defines the trigger source for DMA read requests from capture FIFOs.

Values:

enumerator kFLEXPWM_DMADisable#: Read DMA requests disabled

enumerator kFLEXPWM_DMAFIFOWatermark#: Exceeding FIFO watermark sets read DMA request

enumerator kFLEXPWM_DMALocalSync#: Local sync sets read DMA request

enumerator kFLEXPWM_DMALocalReload#: Local reload sets read DMA request

enum _flexpwm_dma_enable#

FlexPWM DMA enable flags.

These flags are used with FLEXPWM_EnableDMA() and FLEXPWM_DisableDMA() to control individual DMA channel enables. Multiple flags can be ORed together.

Values:

enumerator kFLEXPWM_DMA_CaptureX0Enable#: Capture X0 FIFO DMA enable (CX0DE)

enumerator kFLEXPWM_DMA_CaptureX1Enable#: Capture X1 FIFO DMA enable (CX1DE)

enumerator kFLEXPWM_DMA_CaptureB0Enable#: Capture B0 FIFO DMA enable (CB0DE)

enumerator kFLEXPWM_DMA_CaptureB1Enable#: Capture B1 FIFO DMA enable (CB1DE)

enumerator kFLEXPWM_DMA_CaptureA0Enable#: Capture A0 FIFO DMA enable (CA0DE)

enumerator kFLEXPWM_DMA_CaptureA1Enable#: Capture A1 FIFO DMA enable (CA1DE)

enumerator kFLEXPWM_DMA_ValueWriteEnable#: Value registers DMA write enable (VALDE)

typedef enum _flexpwm_clock_source flexpwm_clock_source_t#: FlexPWM clock source selection.

typedef enum _flexpwm_prescaler flexpwm_prescaler_t#: FlexPWM clock prescaler selection.

typedef enum _flexpwm_load_mode flexpwm_load_mode_t#: FlexPWM load mode selection.

typedef enum _flexpwm_reload_source flexpwm_reload_source_t#: FlexPWM reload source selection.

typedef enum _flexpwm_init_source flexpwm_init_source_t#: FlexPWM counter initialization source selection.

typedef enum _flexpwm_compare_mode flexpwm_compare_mode_t#: FlexPWM PWM compare mode selection.

typedef enum _flexpwm_submodule_mask flexpwm_submodule_mask_t#

FlexPWM submodule mask for multi-submodule operations.

These flags can be OR’ed together to specify multiple submodules simultaneously. Used with functions that operate on multiple submodules at once.

typedef struct _flexpwm_counter_config flexpwm_counter_config_t#: FlexPWM counter configuration structure.

typedef struct _flexpwm_reload_config flexpwm_reload_config_t#: FlexPWM reload configuration structure.

typedef struct _flexpwm_submodule_config flexpwm_submodule_config_t#

FlexPWM submodule configuration structure.

This structure defines the basic configuration parameters for a FlexPWM submodule, including clock source, prescaler, counter behavior, reload mechanism, and operating modes.

Note

This configuration writes to buffered registers. After calling FLEXPWM_ConfigSubmodule(), you must set MCTRL[LDOK] using a separate function to transfer the configuration to active registers.

Note

This function does not start the PWM counter. Use a separate API to enable the counter.

typedef enum _flexpwm_pwm_polarity flexpwm_pwm_polarity_t#: FlexPWM PWM output polarity selection.

typedef enum _flexpwm_ipol_source flexpwm_ipol_source_t#: FlexPWM PWM output source selection for complementary mode.

typedef struct _flexpwm_pwm_channel_config flexpwm_pwm_channel_config_t#

FlexPWM PWM channel configuration structure.

This structure defines the configuration for a PWM channel pair (PWM_A or PWM_B), including compare values, output polarity, and initial value.

typedef struct _flexpwm_pwm_config flexpwm_pwm_config_t#

FlexPWM PWM configuration structure.

This structure defines the PWM output configuration for a FlexPWM submodule, including compare values, polarity, and operating mode (independent or complementary).

Note

For complementary mode: Only the selected channel (specified by ipolSource) needs to be configured. The other channel will be ignored by the hardware. For example, if ipolSource = kFLEXPWM_IPOL_PWM23, only pwma will be used.

Note

For independent mode: Both pwma and pwmb must be configured separately. The ipolSource field is ignored when complementary = false.

typedef enum _flexpwm_force_output_source flexpwm_force_output_source_t#: FlexPWM FORCE_OUT event source selection.

typedef enum _flexpwm_force_pwm_source flexpwm_force_pwm_source_t#: FlexPWM PWM source selection for deadtime logic (DTSRCSEL)

typedef struct _flexpwm_force_out_channel_config flexpwm_force_out_channel_config_t#

FlexPWM PWM channel force output configuration structure.

This structure defines the force output configuration for a PWM channel (PWM_A or PWM_B), including the source selection and software-controlled output value.

typedef struct _flexpwm_force_out_config flexpwm_force_out_config_t#

FlexPWM force output configuration structure.

This structure defines the force output (FORCE_OUT event) configuration for a FlexPWM submodule, including the trigger source, PWM logical initial value, and PWM source selection.

typedef enum _flexpwm_fault_output_behavior flexpwm_fault_output_behavior_t#

FlexPWM fault output behavior during fault condition.

Defines how PWM outputs respond when a fault is detected. Values map directly to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS] bitfields.

typedef enum _flexpwm_fault_mask flexpwm_fault_mask_t#

FlexPWM fault input mask for fault protection configuration.

These flags can be OR’ed together to configure multiple fault inputs simultaneously with the same protection parameters. Used with FLEXPWM_ConfigFaultProtection() function.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1):

When faultChannel = 0: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT0-3
When faultChannel = 1: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT4-7 The enum values are the same, but the channel parameter determines which physical fault inputs are configured.

typedef struct _flexpwm_fault_output_config flexpwm_fault_output_config_t#

FlexPWM fault output configuration structure.

Configures fault protection for a single PWM output (PWM_A, PWM_B, or PWM_X). Supports both single-channel (FAULT0-3 only) and dual-channel (FAULT0-3 and FAULT4-7) platforms via conditional compilation. Can use flexpwm_fault_mask_t enum values (kFLEXPWM_FaultMask_0/1/2/3) and OR them together for multiple faults.

typedef struct _flexpwm_fault_submodule_config flexpwm_fault_submodule_config_t#

FlexPWM fault submodule configuration structure.

Configures fault protection for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a FlexPWM submodule. Includes fault disable mapping and output behavior for each output.

typedef enum _flexpwm_fault_clearing_mode flexpwm_fault_clearing_mode_t#

FlexPWM fault clearing mode selection.

Defines how fault conditions are cleared after a fault event.

typedef struct _flexpwm_fault_config flexpwm_fault_config_t#

FlexPWM fault protection configuration structure.

Configures global fault protection parameters for one fault channel. These settings apply to all submodules and their outputs that reference this channel. For platforms with dual fault channels (FAULT0-3 and FAULT4-7), configure each channel separately using FLEXPWM_ConfigFaultProtection().

typedef struct _flexpwm_fault_filter_config flexpwm_fault_filter_config_t#

FlexPWM fault filter configuration structure.

Configures input filter for fault protection pins to debounce electrical noise. The filter requires the input signal to be stable for N consecutive samples (where each sample is taken every T IPBus clock cycles) before reporting a fault. Helps avoid false fault triggers from noise on FAULTx pins.

typedef enum _flexpwm_write_protect flexpwm_write_protect_t#: FlexPWM write protection mode selection.

typedef enum _flexpwm_stretch_prescaler flexpwm_stretch_prescaler_t#

FlexPWM trigger signal stretch prescaler selection.

Stretch IPBus clock count prescaler for trigger signals including: mux0_trig, mux1_trig, out0_trig, out1_trig, pwma_trig, pwmb_trig

typedef enum _flexpwm_trigger_mux_source flexpwm_trigger_mux_source_t#

FlexPWM output trigger source selection for PWM_MUX_TRIG0/1 ports.

Selects which signal is routed to the PWM_MUX_TRIG0/1 output ports.

typedef enum _flexpwm_trigger_frequency flexpwm_trigger_frequency_t#

FlexPWM output trigger frequency selection.

Controls the trigger output frequency when CTRL[LDFQ] is non-zero. Only takes effect when reload frequency divider is active (LDFQ > 0).

typedef enum _flexpwm_output_trigger_mask flexpwm_output_trigger_mask_t#

FlexPWM output trigger enable mask.

These flags can be OR’ed together to enable multiple trigger sources simultaneously. Used with outTriggerEnable field in flexpwm_output_trigger_config_t structure.

typedef struct _flexpwm_output_trigger_config flexpwm_output_trigger_config_t#

FlexPWM output trigger configuration structure.

This structure defines the output trigger configuration for a FlexPWM submodule, including trigger source mapping from VAL registers, trigger frequency control, and output port routing.

Note

outTriggerEnable is a 6-bit mask corresponding to OUT_TRIG_EN[5:0], where each bit enables a trigger source from VAL0-5 register matches:

bit[0]: VAL0 match triggers PWM_OUT_TRIG0
bit[1]: VAL1 match triggers PWM_OUT_TRIG1
bit[2]: VAL2 match triggers PWM_OUT_TRIG0
bit[3]: VAL3 match triggers PWM_OUT_TRIG1
bit[4]: VAL4 match triggers PWM_OUT_TRIG0
bit[5]: VAL5 match triggers PWM_OUT_TRIG1 Multiple bits can be set to combine trigger sources (OR logic).

Note

triggerFrequency only takes effect when CTRL[LDFQ] is non-zero.

false: Triggers output every PWM cycle even if reload doesn’t occur
true: Triggers output only on the last PWM cycle before a reload opportunity

typedef enum _flexpwm_capture_edge flexpwm_capture_edge_t#

FlexPWM input capture edge selection.

This enumeration defines the edge detection modes for input capture. The enum values directly map to hardware register bit values.

typedef enum _flexpwm_capture_fifo_watermark flexpwm_capture_fifo_watermark_t#

FlexPWM capture FIFO watermark selection.

This enumeration defines the FIFO watermark levels that determine when a watermark interrupt is triggered based on the number of valid samples in the FIFO.

typedef enum _flexpwm_capture_input_select flexpwm_capture_input_select_t#

FlexPWM capture input source selection.

This enumeration selects the source signal for input capture.

typedef enum _flexpwm_capture_index flexpwm_capture_index_t#

FlexPWM capture value index.

This enumeration defines the index for accessing capture value registers (CVAL0-5).

Note

Capture channel to CVAL register mapping (non-intuitive hardware mapping):

Capture_X Edge0/Edge1 -> CVAL0/CVAL1 (and CVAL0CYC/CVAL1CYC)
Capture_A Edge0/Edge1 -> CVAL2/CVAL3 (and CVAL2CYC/CVAL3CYC)
Capture_B Edge0/Edge1 -> CVAL4/CVAL5 (and CVAL4CYC/CVAL5CYC)

typedef enum _flexpwm_capture_channel flexpwm_capture_channel_t#

FlexPWM capture channel selection.

This enumeration defines the capture channel for enable/disable operations.

typedef struct _flexpwm_capture_channel_config flexpwm_capture_channel_config_t#

FlexPWM single capture channel configuration structure.

This structure defines the configuration parameters for a single input capture channel.

typedef struct _flexpwm_input_capture_config flexpwm_input_capture_config_t#

FlexPWM input capture configuration structure.

This structure contains the configuration for three independent input capture channels. Users can configure only the channels they need; unused channels should be left at default values.

Note

Capture channel to CVAL/CVALxCYC register mapping (important for reading capture values):

captureA -> CVAL2/CVAL3 (CVAL2CYC/CVAL3CYC)
captureB -> CVAL4/CVAL5 (CVAL4CYC/CVAL5CYC)
captureX -> CVAL0/CVAL1 (CVAL0CYC/CVAL1CYC)

typedef struct _flexpwm_capture_filter_channel_config flexpwm_capture_filter_channel_config_t#

FlexPWM capture filter channel configuration structure.

This structure defines the digital filter parameters for a single capture input pin.

typedef struct _flexpwm_capture_filter_config flexpwm_capture_filter_config_t#

FlexPWM input capture filter configuration structure.

This structure contains the filter configuration for three independent capture input pins.

Note

Capture filter to register mapping:

captureA -> SMxCAPTFILTA register
captureB -> SMxCAPTFILTB register
captureX -> SMxCAPTFILTX register

typedef enum _flexpwm_dma_capture_source flexpwm_dma_capture_source_t#

FlexPWM DMA capture source selection.

This enumeration defines the trigger source for DMA read requests from capture FIFOs.

typedef struct _flexpwm_dma_config flexpwm_dma_config_t#

FlexPWM DMA configuration structure.

This structure holds the DMA control strategy configuration. These settings should be configured during initialization and typically do not need to be modified at runtime.

uint32_t FLEXPWM_GetInstance(PWM_Type *base)#

Get the instance for FlexPWM module.

Parameters:

base – FlexPWM base address

Returns:

Instance number if valid base address is provided, otherwise returns ARRAY_SIZE(s_flexpwmBases)

status_t FLEXPWM_Init(PWM_Type *base)#

Initialize the FlexPWM module.

This function initializes the FlexPWM peripheral by:

Enabling clocks for all submodules (SM0-SM3)
Releasing peripheral reset (if supported by platform)

After calling this function, the FlexPWM module is ready for configuration. Additional configuration functions (FLEXPWM_ConfigSubmodule, FLEXPWM_ConfigPWM, etc.) should be called to set up the desired PWM behavior.

Note

This function does not configure any PWM parameters. It only enables the peripheral.

Note

This function does not start PWM generation. Use FLEXPWM_EnableSubmoduleCounter() and FLEXPWM_EnablePWMOutput() to start PWM output.

Parameters:

base – FlexPWM peripheral base address.

Returns:

kStatus_Success if initialization is successful. kStatus_InvalidArgument if the base address is invalid.

status_t FLEXPWM_DeInit(PWM_Type *base)#

Deinitialize the FlexPWM module.

This function deinitializes the FlexPWM peripheral by:

Disabling clocks for all submodules (SM0-SM3)
Asserting peripheral reset (if supported by platform)

After calling this function, all FlexPWM registers are reset.

Note

To re-enable PWM operation, call FLEXPWM_Init() again.

Parameters:

base – FlexPWM peripheral base address.

Returns:

kStatus_Success if deinitialization is successful. kStatus_InvalidArgument if the base address is invalid.

FLEXPWM_GET_FCTRL_REG(base, ch)#

FLEXPWM_GET_FSTS_REG(base, ch)#

FLEXPWM_GET_FFILT_REG(base, ch)#

FLEXPWM_GET_FCTRL2_REG(base, ch)#

struct _flexpwm_counter_config#

#include <fsl_flexpwm.h>

FlexPWM counter configuration structure.

Public Members

uint16_t initValue#: Counter initial value (INIT register).

uint16_t modValue#: Counter modulo value (VAL1 register). Defines the PWM period upper limit.

flexpwm_init_source_t initSource#: Counter initialization source selection. Determines when the counter resets to initValue.

struct _flexpwm_reload_config#

#include <fsl_flexpwm.h>

FlexPWM reload configuration structure.

Public Members

flexpwm_load_mode_t loadMode#

kFLEXPWM_LoadMode_Opportunity: Load at next reload opportunity (PWM cycle)
kFLEXPWM_LoadMode_Immediate: Load immediately after LDOK is set

uint8_t loadFrequency#

Load frequency divider (LDFQ field, 0-15). Buffered registers reload every (loadFrequency + 1) PWM cycles.

0: Every PWM cycle
1: Every 2 PWM cycles
15: Every 16 PWM cycles

bool enableHalfCycleReload#

Enable reload at half-cycle point (VAL0 match).

true: Reload can occur at VAL0 match
false: No reload at half-cycle

bool enableFullCycleReload#

Enable reload at full-cycle point (VAL1 match).

true: Reload can occur at VAL1 match
false: No reload at full-cycle

flexpwm_reload_source_t reloadSource#

Reload signal source selection.

kFLEXPWM_ReloadSource_LocalReload: Use local reload signal
kFLEXPWM_ReloadSource_MasterReload: Use master reload from submodule 0

uint16_t halfCycleValue#: Half-cycle reload point (VAL0 register). This value determines when half-cycle reload occurs. Note: Does not need to be exactly half the PWM period.

struct _flexpwm_submodule_config#

#include <fsl_flexpwm.h>

FlexPWM submodule configuration structure.

This structure defines the basic configuration parameters for a FlexPWM submodule, including clock source, prescaler, counter behavior, reload mechanism, and operating modes.

Note

This configuration writes to buffered registers. After calling FLEXPWM_ConfigSubmodule(), you must set MCTRL[LDOK] using a separate function to transfer the configuration to active registers.

Note

This function does not start the PWM counter. Use a separate API to enable the counter.

Public Members

flexpwm_clock_source_t clockSource#: Clock source for the submodule PWM counter.

flexpwm_prescaler_t prescaler#: Clock prescaler divider.

flexpwm_counter_config_t counterConfig#: Counter initialization and behavior configuration.

flexpwm_reload_config_t reloadConfig#: Register reload mechanism configuration.

bool enableDebugMode#

PWM behavior in Debug mode.

true: PWM continues running when MCU enters Debug mode
false: PWM stops when MCU enters Debug mode

struct _flexpwm_pwm_channel_config#

#include <fsl_flexpwm.h>

FlexPWM PWM channel configuration structure.

This structure defines the configuration for a PWM channel pair (PWM_A or PWM_B), including compare values, output polarity, and initial value.

Public Members

uint16_t compareValue_ON#

Compare value that defines the PWM turn-on edge (in normal polarity). Mapping per channel:

PWM_A: written to VAL2
PWM_B: written to VAL4
PWM_X: written to VAL0

uint16_t compareValue_OFF#

Compare value that defines the PWM turn-off edge (in normal polarity). Mapping per channel:

PWM_A: written to VAL3
PWM_B: written to VAL5
PWM_X: written to VAL1

flexpwm_pwm_polarity_t polarity#

Output polarity.

kFLEXPWM_Polarity_ActiveLow: PWM signal is inverted (active low)
kFLEXPWM_Polarity_ActiveHigh: PWM signal is normal (active high)

struct _flexpwm_pwm_config#

#include <fsl_flexpwm.h>

FlexPWM PWM configuration structure.

This structure defines the PWM output configuration for a FlexPWM submodule, including compare values, polarity, and operating mode (independent or complementary).

Note

For independent mode: Both pwma and pwmb must be configured separately. The ipolSource field is ignored when complementary = false.

Public Members

flexpwm_pwm_channel_config_t pwma#: PWM_A (PWM23) channel configuration

flexpwm_pwm_channel_config_t pwmb#: PWM_B (PWM45) channel configuration

bool complementary#

Operating mode.

true: Complementary mode (PWM_A and PWM_B form a complementary pair)
false: Independent mode (PWM_A and PWM_B are independent channels)

flexpwm_ipol_source_t ipolSource#

MCTRL[IPOL] - Select which channel pair as complementary source. Only used when complementary = true.

kFLEXPWM_IPOL_PWM23: Use PWM23 as source
kFLEXPWM_IPOL_PWM45: Use PWM45 as source

struct _flexpwm_force_out_channel_config#

#include <fsl_flexpwm.h>

FlexPWM PWM channel force output configuration structure.

This structure defines the force output configuration for a PWM channel (PWM_A or PWM_B), including the source selection and software-controlled output value.

Public Members

flexpwm_force_pwm_source_t source#: PWM source selection for this channel (DTSRCSEL).

bool softwareValue#: When source=kFLEXPWM_ForcePwmSource_Software, this value (0 or 1) is output to deadtime logic (SWCOUT).

struct _flexpwm_force_out_config#

#include <fsl_flexpwm.h>

FlexPWM force output configuration structure.

This structure defines the force output (FORCE_OUT event) configuration for a FlexPWM submodule, including the trigger source, PWM logical initial value, and PWM source selection.

Public Members

flexpwm_force_output_source_t forceSource#: FORCE_OUT trigger source (CTRL2[FORCE_SEL]).

flexpwm_force_out_channel_config_t pwma#: PWM_A (PWM23) force output configuration.

flexpwm_force_out_channel_config_t pwmb#: PWM_B (PWM45) force output configuration.

bool pwma_initialValue#

PWM_A (PWM23) logical initial value in normal polarity.

true: PWM_A output starts at logic 1
false: PWM_A output starts at logic 0

bool pwmb_initialValue#

PWM_B (PWM45) logical initial value in normal polarity.

true: PWM_B output starts at logic 1
false: PWM_B output starts at logic 0

bool pwmx_initialValue#

PWM_X logical initial value in normal polarity.

true: PWM_X output starts at logic 1
false: PWM_X output starts at logic 0

struct _flexpwm_fault_output_config#

#include <fsl_flexpwm.h>

FlexPWM fault output configuration structure.

Public Members

uint16_t disableMask_ch0#

Fault disable mask for channel 0 (FAULT0-3). Each bit selects one fault input:

bit[0] = FAULT0
bit[1] = FAULT1
bit[2] = FAULT2
bit[3] = FAULT3 Maps to SMxDISMAP[0] register.

flexpwm_fault_output_behavior_t outputBehavior#: Output behavior when fault is detected Maps to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS].

struct _flexpwm_fault_submodule_config#

#include <fsl_flexpwm.h>

FlexPWM fault submodule configuration structure.

Configures fault protection for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a FlexPWM submodule. Includes fault disable mapping and output behavior for each output.

Public Members

flexpwm_fault_output_config_t pwma#: PWM_A (PWM23) fault configuration. Controls which faults disable PWM_A output and how PWM_A behaves during fault.

flexpwm_fault_output_config_t pwmb#: PWM_B (PWM45) fault configuration. Controls which faults disable PWM_B output and how PWM_B behaves during fault.

flexpwm_fault_output_config_t pwmx#: PWM_X fault configuration. Controls which faults disable PWM_X output and how PWM_X behaves during fault.

struct _flexpwm_fault_config#

#include <fsl_flexpwm.h>

FlexPWM fault protection configuration structure.

Public Members

bool faultInputActiveLevel#

FAULTx input active level (FCTRL[FLVL])

false: Logic 0 on FAULTx indicates fault (active low)
true: Logic 1 on FAULTx indicates fault (active high)

flexpwm_fault_clearing_mode_t faultClearingMode#: Fault clearing mode (FCTRL[FAUTO])

bool enableSafetyMode#

Safety Mode (FCTRL[FSAFE]) Only useful for Manual fault clearing mode

false: Normal mode (PWM outputs enabled when FFLAG clears)
true: Safe mode (PWM outputs enabled only when both FFLAG and FFPIN are clear)

bool enableFullCycleRecovery#

Full Cycle Recovery (FSTS[FFULL])

true: PWM outputs can be re-enabled at PWM full cycle start
false: No re-enable at full cycle

bool enableHalfCycleRecovery#

Half Cycle Recovery (FSTS[FHALF])

true: PWM outputs can be re-enabled at PWM half cycle start
false: No re-enable at half cycle

bool enableCombinatorialPath#

Combinational Path Control (FCTRL2[NOCOMB])

true: Combinational path active - fault input directly disables PWM outputs (fastest response)
false: Combinational path disabled - only latched fault signal disables PWM outputs (adds latency)

struct _flexpwm_fault_filter_config#

#include <fsl_flexpwm.h>

FlexPWM fault filter configuration structure.

Public Members

uint8_t filterPeriod#

Fault Filter Period (FFILT[FILT_PER]) Sampling period in IPBus clock cycles. Range: 0-255

0: Input filter bypassed
N: FAULTx sampled every N IPBus cycles

uint8_t filterCount#

Fault Filter Count (FFILT[FILT_CNT]) Number of consecutive stable samples required to accept input transition. Range: 0-7 (actual samples = value + 3)

0: 3 samples
1: 4 samples
7: 10 samples

bool enableGlitchStretch#

Fault Glitch Stretching (FFILT[GSTR])

false: Glitch stretching disabled
true: Input fault signals stretched to min 2 IPBus cycles Prevents false triggers from narrow glitches

struct _flexpwm_output_trigger_config#

#include <fsl_flexpwm.h>

FlexPWM output trigger configuration structure.

This structure defines the output trigger configuration for a FlexPWM submodule, including trigger source mapping from VAL registers, trigger frequency control, and output port routing.

Note

outTriggerEnable is a 6-bit mask corresponding to OUT_TRIG_EN[5:0], where each bit enables a trigger source from VAL0-5 register matches:

bit[0]: VAL0 match triggers PWM_OUT_TRIG0
bit[1]: VAL1 match triggers PWM_OUT_TRIG1
bit[2]: VAL2 match triggers PWM_OUT_TRIG0
bit[3]: VAL3 match triggers PWM_OUT_TRIG1
bit[4]: VAL4 match triggers PWM_OUT_TRIG0
bit[5]: VAL5 match triggers PWM_OUT_TRIG1 Multiple bits can be set to combine trigger sources (OR logic).

Note

triggerFrequency only takes effect when CTRL[LDFQ] is non-zero.

false: Triggers output every PWM cycle even if reload doesn’t occur
true: Triggers output only on the last PWM cycle before a reload opportunity

Public Members

uint16_t outTriggerEnable#: Output trigger enable mask (OUT_TRIG_EN[5:0]). Bit mask for VAL0-5 trigger sources. OR’ed combination of flexpwm_output_trigger_mask_t Example: 0x05 enables VAL0 and VAL2 for TRIG0.

flexpwm_trigger_mux_source_t muxTrig0Source#

PWM_MUX_TRIG0 port source selection (PWAOT0).

kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Route PWM_OUT_TRIG0 signal
kFLEXPWM_TriggerMuxSource_PWMOutput: Route PWM_A output directly

flexpwm_trigger_mux_source_t muxTrig1Source#

PWM_MUX_TRIG1 port source selection (PWBOT1).

kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Route PWM_OUT_TRIG1 signal
kFLEXPWM_TriggerMuxSource_PWMOutput: Route PWM_B output directly

flexpwm_trigger_frequency_t triggerFrequency#

Trigger frequency control (TRGFRQ). Controls trigger output frequency when CTRL[LDFQ] > 0.

kFLEXPWM_TriggerFrequency_EveryCycle: Trigger every PWM cycle
kFLEXPWM_TriggerFrequency_OnReload: Trigger only on last cycle before reload

flexpwm_stretch_prescaler_t stretchPrescaler#: Trigger signal stretch prescaler (MCTRL2[STRETCH_CNT_PRSC]). Stretches trigger signal pulse width by specified IPBus clock cycles.

struct _flexpwm_capture_channel_config#

#include <fsl_flexpwm.h>

FlexPWM single capture channel configuration structure.

This structure defines the configuration parameters for a single input capture channel.

Public Members

flexpwm_capture_edge_t edge0#: Edge0 capture edge selection

flexpwm_capture_edge_t edge1#: Edge1 capture edge selection

bool oneshot#

Capture mode.

true: One-shot mode
false: Free-running mode

flexpwm_capture_input_select_t inputSelect#

Input signal source selection.

kFLEXPWM_CaptureInput_RawSignal: Raw PWM input
kFLEXPWM_CaptureInput_EdgeCounter: Edge counter output

bool enableEdgeCounter#

Edge counter enable control.

true: Enable edge counter (EDGCNT_EN = 1)
false: Disable edge counter (EDGCNT_EN = 0)

uint8_t edgeCompareValue#: Edge counter compare value (0-255). Capture occurs when edge count reaches this value. Only valid when enableEdgeCounter = true

flexpwm_capture_fifo_watermark_t fifoWatermark#: FIFO watermark level

struct _flexpwm_input_capture_config#

#include <fsl_flexpwm.h>

FlexPWM input capture configuration structure.

This structure contains the configuration for three independent input capture channels. Users can configure only the channels they need; unused channels should be left at default values.

Note

Capture channel to CVAL/CVALxCYC register mapping (important for reading capture values):

captureA -> CVAL2/CVAL3 (CVAL2CYC/CVAL3CYC)
captureB -> CVAL4/CVAL5 (CVAL4CYC/CVAL5CYC)
captureX -> CVAL0/CVAL1 (CVAL0CYC/CVAL1CYC)

Public Members

flexpwm_capture_channel_config_t captureA#: Capture_A (PWM_A) channel configuration

flexpwm_capture_channel_config_t captureB#: Capture_B (PWM_B) channel configuration

flexpwm_capture_channel_config_t captureX#: Capture_X (PWM_X) channel configuration

struct _flexpwm_capture_filter_channel_config#

#include <fsl_flexpwm.h>

FlexPWM capture filter channel configuration structure.

This structure defines the digital filter parameters for a single capture input pin.

Public Members

uint8_t filterPeriod#

Filter sampling period in IPBus clock cycles (0-255).

0: Bypass filter (default)
Non-zero: Enable filter with specified sampling period

uint8_t filterCount#: Number of consecutive consistent samples required (0-7). Actual sample count = filterCount + 3 (i.e., 3-10 samples)

struct _flexpwm_capture_filter_config#

#include <fsl_flexpwm.h>

FlexPWM input capture filter configuration structure.

This structure contains the filter configuration for three independent capture input pins.

Note

Capture filter to register mapping:

captureA -> SMxCAPTFILTA register
captureB -> SMxCAPTFILTB register
captureX -> SMxCAPTFILTX register

Public Members

flexpwm_capture_filter_channel_config_t captureA#: Capture_A filter configuration

flexpwm_capture_filter_channel_config_t captureB#: Capture_B filter configuration

flexpwm_capture_filter_channel_config_t captureX#: Capture_X filter configuration

struct _flexpwm_dma_config#

#include <fsl_flexpwm.h>

FlexPWM DMA configuration structure.

This structure holds the DMA control strategy configuration. These settings should be configured during initialization and typically do not need to be modified at runtime.

Public Members

flexpwm_dma_capture_source_t captureSource#: Capture DMA enable source selection (CAPTDE[7:6])

bool fifoWatermarkAND#

FIFO watermark AND/OR control (FAND).

true: Selected FIFO watermarks are ANDed
false: Selected FIFO watermarks are ORed

FREQME: Frequency Measurement#

FTM: FlexTimer Driver#

status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)#

Ungates the FTM clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application which is using the FTM driver. If the FTM instance has only TPM features, please use the TPM driver.

Parameters:

base – FTM peripheral base address
config – Pointer to the user configuration structure.

Returns:

kStatus_Success indicates success; Else indicates failure.

void FTM_Deinit(FTM_Type *base)#

Gates the FTM clock.

Parameters:

base – FTM peripheral base address

void FTM_GetDefaultConfig(ftm_config_t *config)#

Fills in the FTM configuration structure with the default settings.

The default values are:

config->prescale = kFTM_Prescale_Divide_1;
config->bdmMode = kFTM_BdmMode_0;
config->pwmSyncMode = kFTM_SoftwareTrigger;
config->reloadPoints = 0;
config->faultMode = kFTM_Fault_Disable;
config->faultFilterValue = 0;
config->deadTimePrescale = kFTM_Deadtime_Prescale_1;
config->deadTimeValue =  0;
config->extTriggers = 0;
config->chnlInitState = 0;
config->chnlPolarity = 0;
config->useGlobalTimeBase = false;
config->hwTriggerResetCount = false;
config->swTriggerResetCount = true;

Parameters:

config – Pointer to the user configuration structure.

static inline ftm_clock_prescale_t FTM_CalculateCounterClkDiv(FTM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz)#

brief Calculates the counter clock prescaler.

This function calculates the values for SC[PS] bit.

param base FTM peripheral base address param counterPeriod_Hz The desired frequency in Hz which corresponding to the time when the counter reaches the mod value param srcClock_Hz FTM counter clock in Hz

return Calculated clock prescaler value, see ftm_clock_prescale_t.

status_t FTM_SetupPwm(FTM_Type *base, const ftm_chnl_pwm_signal_param_t *chnlParams, uint8_t numOfChnls, ftm_pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)#

Configures the PWM signal parameters.

Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this function to configure all FTM channels that are used to output a PWM signal.

Parameters:

base – FTM peripheral base address
chnlParams – Array of PWM channel parameters to configure the channel(s)
numOfChnls – Number of channels to configure; This should be the size of the array passed in
mode – PWM operation mode, options available in enumeration ftm_pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – FTM counter clock in Hz

Returns:

kStatus_Success if the PWM setup was successful kStatus_Error on failure

status_t FTM_UpdatePwmDutycycle(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_pwm_mode_t currentPwmMode, uint8_t dutyCyclePercent)#

Updates the duty cycle of an active PWM signal.

Note

This function only writes the new duty cycle value to the CnV buffer register. FTM_Init() unconditionally enables enhanced PWM synchronization mode by setting SYNCONF.SYNCMODE = 1 and COMBINE.SYNCENn = 1 in FTM_SetPwmSync(), regardless of the configuration passed by the user. Therefore, the buffered CnV value does NOT take effect immediately. The caller must trigger a register reload after this function returns, using one of the following methods:

Software trigger: call FTM_SetSoftwareTrigger(base, true) (if pwmSyncMode includes kFTM_SoftwareTrigger). Note that if swTriggerResetCount was set to true during initialization, this trigger will also force the FTM counter to the CNTIN value (SYNCONF.SWRSTCNT = 1).
Hardware trigger: no software call is needed. If pwmSyncMode includes kFTM_HardwareTrigger_0/1/2, the reload happens automatically when the corresponding hardware trigger fires (SYNCONF.HWWRBUF is set by FTM_Init()).
LDOK: call FTM_SetLdok(base, true). The new value becomes active at the next reload point: by default at counter overflow (MOD to CNTIN), or at earlier events if additional reload points are configured via FTM_SetReloadPoints().

Parameters:

base – FTM peripheral base address
chnlNumber – The channel/channel pair number. In combined mode, this represents the channel pair number
currentPwmMode – The current PWM mode set during PWM setup
dutyCyclePercent – New PWM pulse width; The value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)

Returns:

kStatus_Success if the PWM update was successful kStatus_Error on failure

void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level)#

Updates the edge level selection for a channel.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel number
level – The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. See the Kinetis SoC reference manual for details about this field.

status_t FTM_SetupPwmMode(FTM_Type *base, const ftm_chnl_pwm_config_param_t *chnlParams, uint8_t numOfChnls, ftm_pwm_mode_t mode)#

Configures the PWM mode parameters.

Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this function to configure all FTM channels that are used to output a PWM signal. Please note that: This API is similar with FTM_SetupPwm() API, but will not set the timer period, and this API will set channel match value in timer ticks, not period percent.

Parameters:

base – FTM peripheral base address
chnlParams – Array of PWM channel parameters to configure the channel(s)
numOfChnls – Number of channels to configure; This should be the size of the array passed in
mode – PWM operation mode, options available in enumeration ftm_pwm_mode_t

Returns:

kStatus_Success if the PWM setup was successful kStatus_Error on failure

void FTM_ConfigSinglePWM(FTM_Type *base, const ftm_chnl_param_t *chnlParams, ftm_chnl_t chnlNumber)#

Configure FTM edge aligned PWM or center aligned PWM by each channel.

This function configure PWM signal by setting channel n value register. Need to invoke FTM_SetInitialModuloValue to configure FTM period.

Parameters:

base – FTM peripheral base address
chnlParams – PWM configuration structure pointer.
chnlPairNumber – Channel number.

void FTM_ConfigCombinePWM(FTM_Type *base, const ftm_chnl_param_t *chnlParams, ftm_chnl_t chnlPairNumber)#

Configure FTM Combine PWM, Modified Combine PWM or Asymmetrical PWM by each channel pair.

This function configure PWM signal by setting channel n value register. Need to invoke FTM_SetInitialModuloValue to configure FTM period.

Parameters:

base – FTM peripheral base address
chnlParams – PWM configuration structure pointer.
chnlPairNumber – Channel pair number, options are 0, 1, 2, 3.

void FTM_SetupInputCapture(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_input_capture_edge_t captureMode, uint32_t filterValue)#

Enables capturing an input signal on the channel using the function parameters.

When the edge specified in the captureMode argument occurs on the channel, the FTM counter is captured into the CnV register. The user has to read the CnV register separately to get this value. The filter function is disabled if the filterVal argument passed in is 0. The filter function is available only for channels 0, 1, 2, 3.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel number
captureMode – Specifies which edge to capture
filterValue – Filter value, specify 0 to disable filter. Available only for channels 0-3.

void FTM_SetupOutputCompare(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_output_compare_mode_t compareMode, uint32_t compareValue)#

Configures the FTM to generate timed pulses.

When the FTM counter matches the value of compareVal argument (this is written into CnV reg), the channel output is changed based on what is specified in the compareMode argument.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel number
compareMode – Action to take on the channel output when the compare condition is met
compareValue – Value to be programmed in the CnV register.

void FTM_SetupDualEdgeCapture(FTM_Type *base, ftm_chnl_t chnlPairNumber, const ftm_dual_edge_capture_param_t *edgeParam, uint32_t filterValue)#

Configures the dual edge capture mode of the FTM.

This function sets up the dual edge capture mode on a channel pair. The capture edge for the channel pair and the capture mode (one-shot or continuous) is specified in the parameter argument. The filter function is disabled if the filterVal argument passed is zero. The filter function is available only on channels 0 and 2. The user has to read the channel CnV registers separately to get the capture values.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
edgeParam – Sets up the dual edge capture function
filterValue – Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1.

void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask)#

Enables the selected FTM interrupts.

Parameters:

base – FTM peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ftm_interrupt_enable_t

void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask)#

Disables the selected FTM interrupts.

Parameters:

base – FTM peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ftm_interrupt_enable_t

uint32_t FTM_GetEnabledInterrupts(FTM_Type *base)#

Gets the enabled FTM interrupts.

Parameters:

base – FTM peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration ftm_interrupt_enable_t

uint32_t FTM_GetInstance(FTM_Type *base)#

Gets the instance from the base address.

Parameters:

base – FTM peripheral base address

Returns:

The FTM instance

uint32_t FTM_GetStatusFlags(FTM_Type *base)#

Gets the FTM status flags.

Parameters:

base – FTM peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration ftm_status_flags_t

void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask)#

Clears the FTM status flags.

Parameters:

base – FTM peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration ftm_status_flags_t

static inline void FTM_SetTimerPeriod(FTM_Type *base, uint32_t ticks)#

Sets the timer period in units of ticks.

Timers counts from 0 until it equals the count value set here. The count value is written to the MOD register.

Note

This API allows the user to use the FTM module as a timer. Do not mix usage of this API with FTM’s PWM setup API’s.
Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.

Parameters:

base – FTM peripheral base address
ticks – A timer period in units of ticks, which should be equal or greater than 1.

static inline void FTM_SetInitialModuloValue(FTM_Type *base, uint16_t initialValue, uint16_t moduloValue)#

Set initial value and modulo value for FTM.

Parameters:

base – FTM peripheral base address
initialValue – FTM counter initial value.
moduloValue – FTM counter modulo value.

static inline uint32_t FTM_GetCurrentTimerCount(FTM_Type *base)#

Reads the current timer counting value.

This function returns the real-time timer counting value in a range from 0 to a timer period.

Note

Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.

Parameters:

base – FTM peripheral base address

Returns:

The current counter value in ticks

static inline void FTM_SetChannelMatchValue(FTM_Type *base, ftm_chnl_t chnlNumber, uint16_t value)#

Set channel match value for output.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to set.
value – Channel match value for output.

static inline uint32_t FTM_GetInputCaptureValue(FTM_Type *base, ftm_chnl_t chnlNumber)#

Reads the captured value.

This function returns the captured value of a FTM channel configured in input capture or dual edge capture mode.

Note

Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be read

Returns:

The captured FTM counter value of the input modes.

static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource)#

Starts the FTM counter.

Parameters:

base – FTM peripheral base address
clockSource – FTM clock source; After the clock source is set, the counter starts running.

static inline void FTM_StopTimer(FTM_Type *base)#

Stops the FTM counter.

Parameters:

base – FTM peripheral base address

static inline uint32_t FTM_GetSoftwareOutputValue(FTM_Type *base)#

Get channel software output status.

Parameters:

base – FTM peripheral base address

Returns:

Status of channel software output, logical OR value of ftm_channel_index_t.

static inline uint32_t FTM_GetSoftwareOutputEnable(FTM_Type *base)#

Get channel software enable status.

Parameters:

base – FTM peripheral base address

Returns:

Status of channel software enable, logical OR value of ftm_channel_index_t.

static inline void FTM_SetSoftwareOutputCtrl(FTM_Type *base, uint32_t chnlEnable, uint32_t chnlValue)#

Enables or disables the channel software output control and set channel software output value.

Parameters:

base – FTM peripheral base address
chnlEnable – Channels to enable or disable software output control, logical OR of enumeration ftm_channel_index_t members.
chnlValue – Channels output value, logical OR of enumeration ftm_channel_index_t members

static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)#

Enables or disables the channel software output control.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be enabled or disabled
value – true: channel output is affected by software output control false: channel output is unaffected by software output control

static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)#

Sets the channel software output control value.

Parameters:

base – FTM peripheral base address.
chnlNumber – Channel to be configured
value – true to set 1, false to set 0

static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)#

This function enables/disables the fault control in a channel pair.

This function enables/disables the dead time insertion in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: Enable fault control for this channel pair; false: No fault control
base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: Insert dead time in this channel pair; false: No dead time inserted

static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)#

This function enables/disables complementary mode in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: enable complementary mode; false: disable complementary mode

static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)#

This function enables/disables inverting control in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: enable inverting; false: disable inverting

void FTM_SetupQuadDecode(FTM_Type *base, const ftm_phase_params_t *phaseAParams, const ftm_phase_params_t *phaseBParams, ftm_quad_decode_mode_t quadMode)#

Configures the parameters and activates the quadrature decoder mode.

Parameters:

base – FTM peripheral base address
phaseAParams – Phase A configuration parameters
phaseBParams – Phase B configuration parameters
quadMode – Selects encoding mode used in quadrature decoder mode

static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue)#

Sets the modulo values for Quad Decoder.

The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes over, the counter value goes to the other side and decrease/increase again.

Parameters:

base – FTM peripheral base address.
startValue – The low limit value for Quad Decoder counter.
overValue – The high limit value for Quad Decoder counter.

static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base)#

Gets the current Quad Decoder counter value.

Parameters:

base – FTM peripheral base address.

Returns:

Current quad Decoder counter value.

static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base)#

Clears the current Quad Decoder counter value.

The counter is set as the initial value.

Parameters:

base – FTM peripheral base address.

FSL_FTM_DRIVER_VERSION#: FTM driver version 2.7.6.

enum _ftm_chnl#

List of FTM channels.

Note

Actual number of available channels is SoC dependent

Values:

enumerator kFTM_Chnl_0#: FTM channel number 0

enumerator kFTM_Chnl_1#: FTM channel number 1

enumerator kFTM_Chnl_2#: FTM channel number 2

enumerator kFTM_Chnl_3#: FTM channel number 3

enumerator kFTM_Chnl_4#: FTM channel number 4

enumerator kFTM_Chnl_5#: FTM channel number 5

enumerator kFTM_Chnl_6#: FTM channel number 6

enumerator kFTM_Chnl_7#: FTM channel number 7

enum _ftm_pwm_mode#

FTM PWM operation modes.

Values:

enumerator kFTM_EdgeAlignedPwm#: Edge-aligned PWM

enumerator kFTM_CenterAlignedPwm#: Center-aligned PWM

enumerator kFTM_EdgeAlignedCombinedPwm#: Edge-aligned combined PWM

enumerator kFTM_CenterAlignedCombinedPwm#: Center-aligned combined PWM

enumerator kFTM_ModifiedCombinedPwm#: Modified combined PWM

enumerator kFTM_AsymmetricalCombinedPwm#: Asymmetrical combined PWM

enum _ftm_pwm_level_select#

FTM PWM output pulse mode: high-true, low-true or no output.

Note

kFTM_NoPwmSignal: ELSnB:ELSnA = 0:0 kFTM_LowTrue: ELSnB:ELSnA = 0:1 EPWM: Channel n output is forced low at counter overflow, forced high at channel n match. CPWM: Channel n output is forced low at channel n match when counting down, and forced high at channel n match when counting up. Combined PWM: Channel n output is forced high at beginning of period and at channel n+1 match. It is forced low at the channel n match. kFTM_HighTrue: ELSnB:ELSnA = 1:0 EPWM: Channel n output is forced high at counter overflow, forced low at channel n match. CPWM: Channel n output is forced high at channel n match when counting down, and forced low at channel n match when counting up. Combined PWM: Channel n output is forced low at beginning of period and at channel n+1 match. It is forced high at the channel n match.

Values:

enumerator kFTM_NoPwmSignal#: No PWM output on pin

enumerator kFTM_LowTrue#: Low true pulses

enumerator kFTM_HighTrue#: High true pulses

enum _ftm_output_compare_mode#

FlexTimer output compare mode.

Values:

enumerator kFTM_NoOutputSignal#: No channel output when counter reaches CnV

enumerator kFTM_ToggleOnMatch#: Toggle output

enumerator kFTM_ClearOnMatch#: Clear output

enumerator kFTM_SetOnMatch#: Set output

enum _ftm_input_capture_edge#

FlexTimer input capture edge.

Values:

enumerator kFTM_RisingEdge#: Capture on rising edge only

enumerator kFTM_FallingEdge#: Capture on falling edge only

enumerator kFTM_RiseAndFallEdge#: Capture on rising or falling edge

enum _ftm_dual_edge_capture_mode#

FlexTimer dual edge capture modes.

Values:

enumerator kFTM_OneShot#: One-shot capture mode

enumerator kFTM_Continuous#: Continuous capture mode

enum _ftm_quad_decode_mode#

FlexTimer quadrature decode modes.

Values:

enumerator kFTM_QuadPhaseEncode#: Phase A and Phase B encoding mode

enumerator kFTM_QuadCountAndDir#: Count and direction encoding mode

enum _ftm_phase_polarity#

FlexTimer quadrature phase polarities.

Values:

enumerator kFTM_QuadPhaseNormal#: Phase input signal is not inverted

enumerator kFTM_QuadPhaseInvert#: Phase input signal is inverted

enum _ftm_fault_output_state#

FlexTimer pre-scaler factor for the dead time insertion.

Values:

enumerator kFTM_FaultOutput_PreDefined#: FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).

enumerator kFTM_FaultOutput_TriStated#: FTM outputs will be tri-stated when fault event is ongoing.

enum _ftm_deadtime_prescale#

FlexTimer pre-scaler factor for the dead time insertion.

Values:

enumerator kFTM_Deadtime_Prescale_1#: Divide by 1

enumerator kFTM_Deadtime_Prescale_4#: Divide by 4

enumerator kFTM_Deadtime_Prescale_16#: Divide by 16

enum _ftm_clock_source#

FlexTimer clock source selection.

Values:

enumerator kFTM_SystemClock#: System clock selected

enumerator kFTM_FixedClock#: Fixed frequency clock

enumerator kFTM_ExternalClock#: External clock

enum _ftm_clock_prescale#

FlexTimer pre-scaler factor selection for the clock source.

Values:

enumerator kFTM_Prescale_Divide_1#: Divide by 1

enumerator kFTM_Prescale_Divide_2#: Divide by 2

enumerator kFTM_Prescale_Divide_4#: Divide by 4

enumerator kFTM_Prescale_Divide_8#: Divide by 8

enumerator kFTM_Prescale_Divide_16#: Divide by 16

enumerator kFTM_Prescale_Divide_32#: Divide by 32

enumerator kFTM_Prescale_Divide_64#: Divide by 64

enumerator kFTM_Prescale_Divide_128#: Divide by 128

enum _ftm_filter_prescale#

FlexTimer filter clock prescaler selection.

Values:

enumerator kFTM_Filter_Prescale_Divide_1#: Divide by 1

enumerator kFTM_Filter_Prescale_Divide_2#: Divide by 2

enumerator kFTM_Filter_Prescale_Divide_3#: Divide by 3

enumerator kFTM_Filter_Prescale_Divide_4#: Divide by 4

enumerator kFTM_Filter_Prescale_Divide_5#: Divide by 5

enumerator kFTM_Filter_Prescale_Divide_6#: Divide by 6

enumerator kFTM_Filter_Prescale_Divide_7#: Divide by 7

enumerator kFTM_Filter_Prescale_Divide_8#: Divide by 8

enumerator kFTM_Filter_Prescale_Divide_9#: Divide by 9

enumerator kFTM_Filter_Prescale_Divide_10#: Divide by 10

enumerator kFTM_Filter_Prescale_Divide_11#: Divide by 11

enumerator kFTM_Filter_Prescale_Divide_12#: Divide by 12

enumerator kFTM_Filter_Prescale_Divide_13#: Divide by 13

enumerator kFTM_Filter_Prescale_Divide_14#: Divide by 14

enumerator kFTM_Filter_Prescale_Divide_15#: Divide by 15

enumerator kFTM_Filter_Prescale_Divide_16#: Divide by 16

enum _ftm_bdm_mode#

Options for the FlexTimer behaviour in BDM Mode.

Values:

enumerator kFTM_BdmMode_0#: FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers

enumerator kFTM_BdmMode_1#: FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to MOD,CNTIN and C(n)V registers bypass the register buffers

enumerator kFTM_BdmMode_2#: FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers

enumerator kFTM_BdmMode_3#: FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers is in fully functional mode

enum _ftm_external_trigger#

FTM external trigger options.

Note

Actual available external trigger sources are SoC-specific

Values:

enumerator kFTM_Chnl0Trigger#: Generate trigger when counter equals chnl 0 CnV reg

enumerator kFTM_Chnl1Trigger#: Generate trigger when counter equals chnl 1 CnV reg

enumerator kFTM_Chnl2Trigger#: Generate trigger when counter equals chnl 2 CnV reg

enumerator kFTM_Chnl3Trigger#: Generate trigger when counter equals chnl 3 CnV reg

enumerator kFTM_Chnl4Trigger#: Generate trigger when counter equals chnl 4 CnV reg

enumerator kFTM_Chnl5Trigger#: Generate trigger when counter equals chnl 5 CnV reg

enumerator kFTM_Chnl6Trigger#: Available on certain SoC’s, generate trigger when counter equals chnl 6 CnV reg

enumerator kFTM_Chnl7Trigger#: Available on certain SoC’s, generate trigger when counter equals chnl 7 CnV reg

enumerator kFTM_InitTrigger#: Generate Trigger when counter is updated with CNTIN

enumerator kFTM_ReloadInitTrigger#: Available on certain SoC’s, trigger on reload point

enum _ftm_pwm_sync_method#

FlexTimer PWM sync options to update registers with buffer.

Values:

enumerator kFTM_SoftwareTrigger#: Software triggers PWM sync

enumerator kFTM_HardwareTrigger_0#: Hardware trigger 0 causes PWM sync

enumerator kFTM_HardwareTrigger_1#: Hardware trigger 1 causes PWM sync

enumerator kFTM_HardwareTrigger_2#: Hardware trigger 2 causes PWM sync

enum _ftm_reload_point#

FTM options available as loading point for register reload.

Note

Actual available reload points are SoC-specific

Values:

enumerator kFTM_Chnl0Match#: Channel 0 match included as a reload point

enumerator kFTM_Chnl1Match#: Channel 1 match included as a reload point

enumerator kFTM_Chnl2Match#: Channel 2 match included as a reload point

enumerator kFTM_Chnl3Match#: Channel 3 match included as a reload point

enumerator kFTM_Chnl4Match#: Channel 4 match included as a reload point

enumerator kFTM_Chnl5Match#: Channel 5 match included as a reload point

enumerator kFTM_Chnl6Match#: Channel 6 match included as a reload point

enumerator kFTM_Chnl7Match#: Channel 7 match included as a reload point

enumerator kFTM_CntMax#: Use in up-down count mode only, reload when counter reaches the maximum value

enumerator kFTM_CntMin#: Use in up-down count mode only, reload when counter reaches the minimum value

enumerator kFTM_HalfCycMatch#: Available on certain SoC’s, half cycle match reload point

enum _ftm_interrupt_enable#

List of FTM interrupts.

Note

Actual available interrupts are SoC-specific

Values:

enumerator kFTM_Chnl0InterruptEnable#: Channel 0 interrupt

enumerator kFTM_Chnl1InterruptEnable#: Channel 1 interrupt

enumerator kFTM_Chnl2InterruptEnable#: Channel 2 interrupt

enumerator kFTM_Chnl3InterruptEnable#: Channel 3 interrupt

enumerator kFTM_Chnl4InterruptEnable#: Channel 4 interrupt

enumerator kFTM_Chnl5InterruptEnable#: Channel 5 interrupt

enumerator kFTM_Chnl6InterruptEnable#: Channel 6 interrupt

enumerator kFTM_Chnl7InterruptEnable#: Channel 7 interrupt

enumerator kFTM_TimeOverflowInterruptEnable#: Time overflow interrupt

enumerator kFTM_ReloadInterruptEnable#: Reload interrupt; Available only on certain SoC’s

enum _ftm_status_flags#

List of FTM flags.

Note

Actual available flags are SoC-specific

Values:

enumerator kFTM_Chnl0Flag#: Channel 0 Flag

enumerator kFTM_Chnl1Flag#: Channel 1 Flag

enumerator kFTM_Chnl2Flag#: Channel 2 Flag

enumerator kFTM_Chnl3Flag#: Channel 3 Flag

enumerator kFTM_Chnl4Flag#: Channel 4 Flag

enumerator kFTM_Chnl5Flag#: Channel 5 Flag

enumerator kFTM_Chnl6Flag#: Channel 6 Flag

enumerator kFTM_Chnl7Flag#: Channel 7 Flag

enumerator kFTM_TimeOverflowFlag#: Time overflow Flag

enumerator kFTM_ChnlTriggerFlag#: Channel trigger Flag

enumerator kFTM_ReloadFlag#: Reload Flag; Available only on certain SoC’s

enum _ftm_channel_index#

List of FTM channel index used in logic OR.

Values:

enumerator kFTM_Chnl0_Mask#: Channel 0 Mask

enumerator kFTM_Chnl1_Mask#: Channel 1 Mask

enumerator kFTM_Chnl2_Mask#: Channel 2 Mask

enumerator kFTM_Chnl3_Mask#: Channel 3 Mask

enumerator kFTM_Chnl4_Mask#: Channel 4 Mask

enumerator kFTM_Chnl5_Mask#: Channel 5 Mask

enumerator kFTM_Chnl6_Mask#: Channel 6 Mask

enumerator kFTM_Chnl7_Mask#: Channel 7 Mask

typedef enum _ftm_chnl ftm_chnl_t#: List of FTM channels.

Note

Actual number of available channels is SoC dependent

typedef enum _ftm_pwm_mode ftm_pwm_mode_t#: FTM PWM operation modes.

typedef enum _ftm_pwm_level_select ftm_pwm_level_select_t#: FTM PWM output pulse mode: high-true, low-true or no output.

Note

kFTM_NoPwmSignal: ELSnB:ELSnA = 0:0 kFTM_LowTrue: ELSnB:ELSnA = 0:1 EPWM: Channel n output is forced low at counter overflow, forced high at channel n match. CPWM: Channel n output is forced low at channel n match when counting down, and forced high at channel n match when counting up. Combined PWM: Channel n output is forced high at beginning of period and at channel n+1 match. It is forced low at the channel n match. kFTM_HighTrue: ELSnB:ELSnA = 1:0 EPWM: Channel n output is forced high at counter overflow, forced low at channel n match. CPWM: Channel n output is forced high at channel n match when counting down, and forced low at channel n match when counting up. Combined PWM: Channel n output is forced low at beginning of period and at channel n+1 match. It is forced high at the channel n match.

typedef struct _ftm_chnl_pwm_signal_param ftm_chnl_pwm_signal_param_t#: Options to configure a FTM channel’s PWM signal.

typedef struct _ftm_chnl_pwm_config_param ftm_chnl_pwm_config_param_t#: Options to configure a FTM channel using precise setting.

typedef struct _ftm_chnl_param ftm_chnl_param_t#: General options to configure a FTM channel using precise setting.

typedef enum _ftm_output_compare_mode ftm_output_compare_mode_t#: FlexTimer output compare mode.

typedef enum _ftm_input_capture_edge ftm_input_capture_edge_t#: FlexTimer input capture edge.

typedef enum _ftm_dual_edge_capture_mode ftm_dual_edge_capture_mode_t#: FlexTimer dual edge capture modes.

typedef struct _ftm_dual_edge_capture_param ftm_dual_edge_capture_param_t#: FlexTimer dual edge capture parameters.

typedef enum _ftm_quad_decode_mode ftm_quad_decode_mode_t#: FlexTimer quadrature decode modes.

typedef enum _ftm_phase_polarity ftm_phase_polarity_t#: FlexTimer quadrature phase polarities.

typedef struct _ftm_phase_param ftm_phase_params_t#: FlexTimer quadrature decode phase parameters.

typedef enum _ftm_fault_output_state ftm_fault_output_state_t#: FlexTimer pre-scaler factor for the dead time insertion.

typedef enum _ftm_deadtime_prescale ftm_deadtime_prescale_t#: FlexTimer pre-scaler factor for the dead time insertion.

typedef struct _ftm_deadtime_param ftm_deadtime_param_t#: Options to configure FTM combined channel pair deadtime.

typedef enum _ftm_clock_source ftm_clock_source_t#: FlexTimer clock source selection.

typedef enum _ftm_clock_prescale ftm_clock_prescale_t#: FlexTimer pre-scaler factor selection for the clock source.

typedef enum _ftm_filter_prescale ftm_filter_prescale_t#: FlexTimer filter clock prescaler selection.

typedef enum _ftm_bdm_mode ftm_bdm_mode_t#: Options for the FlexTimer behaviour in BDM Mode.

typedef enum _ftm_external_trigger ftm_external_trigger_t#: FTM external trigger options.

Note

Actual available external trigger sources are SoC-specific

typedef enum _ftm_pwm_sync_method ftm_pwm_sync_method_t#: FlexTimer PWM sync options to update registers with buffer.

typedef enum _ftm_reload_point ftm_reload_point_t#: FTM options available as loading point for register reload.

Note

Actual available reload points are SoC-specific

typedef enum _ftm_interrupt_enable ftm_interrupt_enable_t#: List of FTM interrupts.

Note

Actual available interrupts are SoC-specific

typedef enum _ftm_status_flags ftm_status_flags_t#: List of FTM flags.

Note

Actual available flags are SoC-specific

typedef enum _ftm_channel_index ftm_channel_index_t#: List of FTM channel index used in logic OR.

typedef struct _ftm_config ftm_config_t#

FTM configuration structure.

This structure holds the configuration settings for the FTM peripheral. To initialize this structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

void FTM_ERRATA_010856(FTM_Type *base, uint8_t *faultFlag, uint32_t channel, uint32_t channelValue)#

Sets up the working of the FTM fault inputs protection.

FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and input filter.

Workaround for ERR010856.

This API should be invoked in TOF interrupt handler when a fault is detected to ensure that the outputs return to the value configured by SWOCTRL, then FTM should be configured as follows:

MODE[FAULTM] configured for manual fault clearing. (MODE[FAULTM] = 0b10)
For devices that include the CONF[NUMTOF] field, it must be cleared to 0b00000.
SYNC[SYNCHOM] and SYNCONF[SWOC] configured for update OUTMASK and SWOCTRL register at each rising edge of system clock. (SYNC[SYNCHOM] = 0, SYNCONF[SWOC] = 0)

Parameters:

base – FTM peripheral base address
faultNumber – FTM fault to configure.
faultParams – Parameters passed in to set up the fault
base – FTM peripheral base address
faultFlag – Pointer to variable to indicate that a fault was detected
channel – Channels controlled by Software output, logical OR of enumeration ftm_channel_index_t
channelValue – Channels value controlled by Software output, logical OR of enumeration ftm_channel_index_t

static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable)#

Enables or disables the FTM global time base signal generation to other FTMs.

Parameters:

base – FTM peripheral base address
enable – true to enable, false to disable

static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask)#

Sets the FTM peripheral timer channel output mask.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be configured
mask – true: masked, channel is forced to its inactive state; false: unmasked

static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)#

Allows users to enable an output on an FTM channel.

To enable the PWM channel output call this function with val=true. For input mode, call this function with val=false.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be configured
value – true: enable output; false: output is disabled, used in input mode

static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable)#

Enables or disables the FTM software trigger for PWM synchronization.

Parameters:

base – FTM peripheral base address
enable – true: software trigger is selected, false: software trigger is not selected

static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable)#

Enables or disables the FTM write protection.

Parameters:

base – FTM peripheral base address
enable – true: Write-protection is enabled, false: Write-protection is disabled

static inline void FTM_EnableDmaTransfer(FTM_Type *base, ftm_chnl_t chnlNumber, bool enable)#

Enable DMA transfer or not.

Note: CHnIE bit needs to be set when calling this API. The channel DMA transfer request is generated and the channel interrupt is not generated if (CHnF = 1) when DMA and CHnIE bits are set.

Parameters:

base – FTM peripheral base address.
chnlNumber – Channel to be configured
enable – true to enable, false to disable

static inline void FTM_SetLdok(FTM_Type *base, bool value)#

Enable the LDOK bit.

This function enables loading updated values.

Parameters:

base – FTM peripheral base address
value – true: loading updated values is enabled; false: loading updated values is disabled.

static inline void FTM_SetHalfCycReloadMatchValue(FTM_Type *base, uint32_t ticks)#

Sets the half cycle relade period in units of ticks.

This function can be callled to set the half-cycle reload value when half-cycle matching is enabled as a reload point. Note: Need enable kFTM_HalfCycMatch as reload point, and when this API call after FTM_StartTimer(), the new HCR value will not be active until next reload point (need call FTM_SetLdok to set LDOK) or register synchronization.

Parameters:

base – FTM peripheral base address
ticks – A timer period in units of ticks, which should be equal or greater than 1.

static inline void FTM_SetLoadFreq(FTM_Type *base, uint32_t loadfreq)#

Set load frequency value.

Parameters:

base – FTM peripheral base address.
loadfreq – PWM reload frequency, range: 0 ~ 31.

static inline void FTM_SetPairDeadTime(FTM_Type *base, const ftm_deadtime_param_t *config, ftm_chnl_t chnlPairNumber)#

brief Configure deadtime for specific combined channel pair.

param base FTM peripheral base address param config Pointer to the user configuration structure. param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3

static inline void FTM_SetPeriodDithering(FTM_Type *base, uint16_t moduloValue, uint8_t fractionalValue)#

Set PWM Period Dithering. For the PWM period dithering, the register MOD_MIRROR should be used instead of the register MOD.

Parameters:

base – FTM peripheral base address.
moduloValue – FTM counter modulo value.
fractionalValue – The modulo fractional value used in the PWM period dithering.

static inline void FTM_SetEdgeDithering(FTM_Type *base, ftm_chnl_t chnlNumber, uint16_t matchValue, uint8_t fractionalValue)#

Set PWM Edge Dithering. For the PWM edge dithering, the register CnV_MIRROR should be used instead of the register CnV.

Parameters:

base – FTM peripheral base address.
chnlNumber – The channel number.
matchValue – FTM channel n match value.
fractionalValue – The channel n match fractional value used in the PWM edge dithering.

static inline uint32_t FTM_GetChannelInputState(FTM_Type *base, ftm_chnl_t chnlNumber)#

Get value of channel n input after the double-sampling or the filtering.

Parameters:

base – FTM peripheral base address.
chnlNumber – The channel number.

Returns:

Channel n input state, 0 or 1.

static inline uint32_t FTM_GetChannelOutputState(FTM_Type *base, ftm_chnl_t chnlNumber)#

Get final value of the channel n output.

Parameters:

base – FTM peripheral base address.
chnlNumber – The channel number.

Returns:

Channel n output value, 0 or 1.

struct _ftm_chnl_pwm_signal_param#

#include <fsl_ftm.h>

Options to configure a FTM channel’s PWM signal.

Public Members

ftm_chnl_t chnlNumber#: The channel/channel pair number. In combined mode, this represents the channel pair number.

ftm_pwm_level_select_t level#: PWM output active level select.

uint8_t dutyCyclePercent#: PWM pulse width, value should be between 0 to 100 0 = inactive signal(0% duty cycle)… 100 = always active signal (100% duty cycle).

uint8_t firstEdgeDelayPercent#: Used only in kFTM_AsymmetricalCombinedPwm mode to generate an asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure leave as 0; Should be specified as a percentage of the PWM period

bool enableComplementary#: Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals;

bool enableDeadtime#: Used only in combined PWM mode with enable complementary. true: The deadtime insertion in this pair of channels is enabled; false: The deadtime insertion in this pair of channels is disabled.

struct _ftm_chnl_pwm_config_param#

#include <fsl_ftm.h>

Options to configure a FTM channel using precise setting.

Public Members

ftm_chnl_t chnlNumber#: The channel/channel pair number. In combined mode, this represents the channel pair number.

ftm_pwm_level_select_t level#: PWM output active level select.

uint16_t dutyValue#: PWM pulse width, the uint of this value is timer ticks.

uint16_t firstEdgeValue#: Used only in kFTM_AsymmetricalCombinedPwm mode to generate an asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure leave as 0, uint of this value is timer ticks.

bool enableComplementary#: Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals;

bool enableDeadtime#: Used only in combined PWM mode with enable complementary. true: The deadtime insertion in this pair of channels is enabled; false: The deadtime insertion in this pair of channels is disabled.

struct _ftm_chnl_param#

#include <fsl_ftm.h>

General options to configure a FTM channel using precise setting.

Public Members

ftm_pwm_mode_t mode#: PWM output mode.

ftm_pwm_level_select_t level#: PWM output active level select.

uint16_t initialValue#: FTM counter initial value.

uint16_t moduloValue#: FTM counter modulo value.

uint16_t chnlValue#: FTM channel n match value.

uint16_t combinedChnlValue#: FTM combined channel n+1 match value, used only in (modified) combined PWM mode.

bool enableComplementary#: Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals;

bool enableDeadtime#: Used only in combined PWM mode with enable complementary. true: The deadtime insertion in this pair of channels is enabled; false: The deadtime insertion in this pair of channels is disabled.

bool enablePulseOutput#: Used only in Edge-aligned PWM and Center-aligned PWM. true: If a match in channel occurs, a trigger pulse with one FTM input clock width is generated in the channel n; false: Channel outputs will generate normal PWM outputs without generating a pulse.

bool enableDithering#: Enable fractional delay to achieve fine resolution on generated PWM signals. true: Enable dithering; false: Disable dithering.

uint8_t moduloFracValue#: Modulo fractional value, used in Period Dithering.

uint8_t chnlFracValue#: Channel n match fractional value, used in Edge Dithering.

uint8_t combinedChnlFracValue#: Combined channel n+1 match fractional value, used in Edge Dithering. It is recommended to use only one PWM Edge Dithering (channel n PWM Edge Dithering or channel n+1 PWM Edge Dithering) at a time.

struct _ftm_dual_edge_capture_param#

#include <fsl_ftm.h>

FlexTimer dual edge capture parameters.

Public Members

ftm_dual_edge_capture_mode_t mode#: Dual Edge Capture mode

ftm_input_capture_edge_t currChanEdgeMode#: Input capture edge select for channel n

ftm_input_capture_edge_t nextChanEdgeMode#: Input capture edge select for channel n+1

struct _ftm_phase_param#

#include <fsl_ftm.h>

FlexTimer quadrature decode phase parameters.

Public Members

bool enablePhaseFilter#: True: enable phase filter; false: disable filter

uint32_t phaseFilterVal#: Filter value, used only if phase filter is enabled

ftm_phase_polarity_t phasePolarity#: Phase polarity

struct _ftm_deadtime_param#

#include <fsl_ftm.h>

Options to configure FTM combined channel pair deadtime.

Public Members

ftm_deadtime_prescale_t deadTimePrescale#: The dead time prescalar value

uint32_t deadTimeValue#: The dead time value deadTimeValue’s available range is 0-1023 when register has DTVALEX, otherwise its available range is 0-63.

struct _ftm_config#

#include <fsl_ftm.h>

FTM configuration structure.

The configuration structure can be made constant so as to reside in flash.

Public Members

ftm_clock_prescale_t prescale#: FTM clock prescale value

ftm_filter_prescale_t filterPrescale#: Clock prescaler used in FTM filters

ftm_bdm_mode_t bdmMode#: FTM behavior in BDM mode

uint32_t pwmSyncMode#: Synchronization methods to use to update buffered registers; Multiple update modes can be used by providing an OR’ed list of options available in enumeration ftm_pwm_sync_method_t.

uint32_t reloadPoints#: FTM reload points; When using this, the PWM synchronization is not required. Multiple reload points can be used by providing an OR’ed list of options available in enumeration ftm_reload_point_t.

ftm_fault_output_state_t faultOutputState#: Fault output state

ftm_deadtime_prescale_t deadTimePrescale#: The dead time prescalar value

uint32_t deadTimeValue#: The dead time value deadTimeValue’s available range is 0-1023 when register has DTVALEX, otherwise its available range is 0-63.

uint32_t extTriggers#: External triggers to enable. Multiple trigger sources can be enabled by providing an OR’ed list of options available in enumeration ftm_external_trigger_t.

uint8_t chnlInitState#: Defines the initialization value of the channels in OUTINT register

uint8_t chnlPolarity#: Defines the output polarity of the channels in POL register

bool useGlobalTimeBase#: True: Use of an external global time base is enabled; False: disabled

bool swTriggerResetCount#: FTM counter synchronization activated by software trigger, avtive when (syncMethod & FTM_SYNC_SWSYNC_MASK) != 0U

bool hwTriggerResetCount#: FTM counter synchronization activated by hardware trigger, avtive when (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) != 0U

GPIO: General-Purpose Input/Output Driver#

FSL_GPIO_DRIVER_VERSION#: GPIO driver version.

enum _gpio_pin_direction#

GPIO direction definition.

Values:

enumerator kGPIO_DigitalInput#: Set current pin as digital input

enumerator kGPIO_DigitalOutput#: Set current pin as digital output

enum _gpio_checker_attribute#

GPIO checker attribute.

Values:

enumerator kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW#: User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW#: User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW#: User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW#: User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW#: User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW#: User nonsecure:None; User Secure:None; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR#: User nonsecure:None; User Secure:None; Privileged Secure:Read

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN#: User nonsecure:None; User Secure:None; Privileged Secure:None

enumerator kGPIO_IgnoreAttributeCheck#: Ignores the attribute check

enum _gpio_interrupt_config#

Configures the interrupt generation condition.

Values:

enumerator kGPIO_InterruptStatusFlagDisabled#: Interrupt status flag is disabled.

enumerator kGPIO_DMARisingEdge#: ISF flag and DMA request on rising edge.

enumerator kGPIO_DMAFallingEdge#: ISF flag and DMA request on falling edge.

enumerator kGPIO_DMAEitherEdge#: ISF flag and DMA request on either edge.

enumerator kGPIO_FlagRisingEdge#: Flag sets on rising edge.

enumerator kGPIO_FlagFallingEdge#: Flag sets on falling edge.

enumerator kGPIO_FlagEitherEdge#: Flag sets on either edge.

enumerator kGPIO_InterruptLogicZero#: Interrupt when logic zero.

enumerator kGPIO_InterruptRisingEdge#: Interrupt on rising edge.

enumerator kGPIO_InterruptFallingEdge#: Interrupt on falling edge.

enumerator kGPIO_InterruptEitherEdge#: Interrupt on either edge.

enumerator kGPIO_InterruptLogicOne#: Interrupt when logic one.

enumerator kGPIO_ActiveHighTriggerOutputEnable#: Enable active high-trigger output.

enumerator kGPIO_ActiveLowTriggerOutputEnable#: Enable active low-trigger output.

enum _gpio_interrupt_selection#

Configures the selection of interrupt/DMA request/trigger output.

Values:

enumerator kGPIO_InterruptOutput0#: Interrupt/DMA request/trigger output 0.

enumerator kGPIO_InterruptOutput1#: Interrupt/DMA request/trigger output 1.

enum gpio_pin_interrupt_control_t#

GPIO pin and interrupt control.

Values:

enumerator kGPIO_PinControlNonSecure#: Pin Control Non-Secure.

enumerator kGPIO_InterruptControlNonSecure#: Interrupt Control Non-Secure.

enumerator kGPIO_PinControlNonPrivilege#: Pin Control Non-Privilege.

enumerator kGPIO_InterruptControlNonPrivilege#: Interrupt Control Non-Privilege.

typedef enum _gpio_pin_direction gpio_pin_direction_t#: GPIO direction definition.

typedef enum _gpio_checker_attribute gpio_checker_attribute_t#: GPIO checker attribute.

typedef struct _gpio_pin_config gpio_pin_config_t#

The GPIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().

typedef enum _gpio_interrupt_config gpio_interrupt_config_t#: Configures the interrupt generation condition.

typedef enum _gpio_interrupt_selection gpio_interrupt_selection_t#: Configures the selection of interrupt/DMA request/trigger output.

typedef struct _gpio_version_info gpio_version_info_t#: GPIO version information.

GPIO_FIT_REG(value)#

struct _gpio_pin_config#

#include <fsl_gpio.h>

The GPIO pin configuration structure.

Public Members

gpio_pin_direction_t pinDirection#: GPIO direction, input or output

uint8_t outputLogic#: Set a default output logic, which has no use in input

struct _gpio_version_info#

#include <fsl_gpio.h>

GPIO version information.

Public Members

uint16_t feature#: Feature Specification Number.

uint8_t minor#: Minor Version Number.

uint8_t major#: Major Version Number.

GPIO Driver#

void GPIO_PortInit(GPIO_Type *base)#

Initializes the GPIO peripheral.

This function ungates the GPIO clock.

Parameters:

base – GPIO peripheral base pointer.

void GPIO_PortDenit(GPIO_Type *base)#

Denitializes the GPIO peripheral.

Parameters:

base – GPIO peripheral base pointer.

void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)#

Initializes a GPIO pin used by the board.

To initialize the GPIO, define a pin configuration, as either input or output, in the user file. Then, call the GPIO_PinInit() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalInput,
  0,
}
Define a digital output pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalOutput,
  0,
}

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO port pin number
config – GPIO pin configuration pointer

void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *verInfo)#

Get GPIO version information.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
verInfo – GPIO version information

static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)#

lock or unlock secure privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – pin or interrupt macro

static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)#

Enable Pin Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)#

Disable Pin Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Enable Pin Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Disable Pin Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)#

Enable Interrupt Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)#

Disable Interrupt Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Enable Interrupt Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Disable Interrupt Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)#

Enable port input.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)#

Disable port input.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)#

Sets the output level of the multiple GPIO pins to the logic 1 or 0.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO pin number
output – GPIO pin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)#

Sets the output level of the multiple GPIO pins to the logic 1.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)#

Sets the output level of the multiple GPIO pins to the logic 0.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)#

Reverses the current output logic of the multiple GPIO pins.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)#

Reads the current input value of the GPIO port.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO pin number

Return values:

GPIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.

static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)#

Configures the gpio pin interrupt/DMA request.

Parameters:

base – GPIO peripheral base pointer.
pin – GPIO pin number.
config – GPIO pin interrupt configuration.
- kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
- kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- kGPIO_InterruptLogicZero : Interrupt when logic zero.
- kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- kGPIO_InterruptEitherEdge : Interrupt on either edge.
- kGPIO_InterruptLogicOne : Interrupt when logic one.
- kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).

static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)#

Configures the gpio pin interrupt/DMA request/trigger output channel selection.

Parameters:

base – GPIO peripheral base pointer.
pin – GPIO pin number.
selection – GPIO pin interrupt output selection.
- kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
- kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.

uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)#

Read the GPIO interrupt status flags.

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)

Returns:

The current GPIO’s interrupt status flag. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)#

Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

Returns:

The current GPIO’s interrupt status flag based on the selected interrupt channel. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)#

Read individual pin’s interrupt status flag.

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
pin – GPIO specific pin number.

Returns:

The current selected pin’s interrupt status flag.

void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)#

Clears GPIO pin interrupt status flags.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)#

Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro
channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)#

Clear GPIO individual pin’s interrupt status flag.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
pin – GPIO specific pin number.

static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)#

Sets the GPIO interrupt configuration in PCR register for multiple pins.

Parameters:

base – GPIO peripheral base pointer.
mask – GPIO pin number macro.
config – GPIO pin interrupt configuration.
- kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
- kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- kGPIO_InterruptLogicZero : Interrupt when logic zero.
- kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- kGPIO_InterruptEitherEdge : Interrupt on either edge.
- kGPIO_InterruptLogicOne : Interrupt when logic one.
- kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..

void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)#

brief The GPIO module supports a device-specific number of data ports, organized as 32-bit words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the GPIO programming model. If the GPIO module’s GACR register organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
attribute – GPIO checker attribute

GPIO_PortGetInterruptFlags(base)#

GPIO_PortClearInterruptFlags(base, mask)#

HSCMP: High Speed Analog Comparator Driver#

uint32_t HSCMP_GetInstance(HSCMP_Type *base)#

Get instance number for HSCMP module.

Parameters:

base – HSCMP peripheral base address

Returns:

Instance number if valid base address is provided, otherwise returns 0xFFFFFFFF

void HSCMP_Init(HSCMP_Type *base, const hscmp_config_t *config)#

Initialize the HSCMP.

This function initializes the HSCMP module. The operations included are:

Enabling the clock for HSCMP module.
Configuring the comparator.
Enabling the HSCMP module optionally.

Note

For some devices, multiple HSCMP instance share the same clock gate. In this case, to enable the clock for any instance enables all the HSCMPs. Check the chip reference manual for the clock assignment of the HSCMP.

Parameters:

base – HSCMP peripheral base address.
config – Pointer to “hscmp_config_t” structure.

void HSCMP_Deinit(HSCMP_Type *base)#

De-initializes the HSCMP module.

This function de-initializes the HSCMP module. The operations included are:

Disabling the HSCMP module.
Disabling the clock for HSCMP module.

This function disables the clock for the HSCMP.

Note

For some devices, multiple HSCMP instance shares the same clock gate. In this case, before disabling the clock for the HSCMP, ensure that all the HSCMP instances are not used.

Parameters:

base – HSCMP peripheral base address.

void HSCMP_GetDefaultConfig(hscmp_config_t *config)#

Gets an available pre-defined settings for the comparator’s configuration.

This function initializes the comparator configuration structure to these default values:

config->enableComparator    = true;
config->enableStopMode      = false;
config->enableOutputPin     = false;
config->useUnfilteredOutput = false;
config->enableInvertOutput  = false;
config->hysteresisMode      = kHSCMP_HysteresisLevel0;
config->powerMode           = kHSCMP_LowSpeedPowerMode;

Parameters:

config – Pointer to “hscmp_config_t” structure.

static inline void HSCMP_Enable(HSCMP_Type *base, bool enable)#

Enable/Disable HSCMP module.

Parameters:

base – HSCMP peripheral base address.
enable – “true” means enable the module, and “false” means disable the module.

void HSCMP_SetInputChannels(HSCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel)#

Select the input channels for HSCMP. This function determines which input is selected for the negative and positive Analog Mux.

Parameters:

base – HSCMP peripheral base address.
positiveChannel – Positive side Analog Mux input channel number. Available range is 0-7.
negativeChannel – Negative side Analog Mux input channel number. Available range is 0-7.

void HSCMP_SetInputMux(HSCMP_Type *base, hscmp_input_t plus, hscmp_input_t minus)#

Select the high-level input source for the Plus and Minus comparator ports.

Configures CCR2.INPSEL and CCR2.INMSEL to choose between the internal DAC output (IN0) and the analog 8-to-1 mux path (IN1, whose channel is selected by PSEL/MSEL). Call HSCMP_SetInputChannels to set the PSEL/MSEL channel when using kHSCMP_InputFromAnalogMux.

Parameters:

base – HSCMP peripheral base address.
plus – Plus input of the comparator. See hscmp_input_t.
minus – Minus input of the comparator. See hscmp_input_t.

static inline void HSCMP_EnableDMA(HSCMP_Type *base, bool enable)#

Enables/disables the DMA request for rising/falling events. Normally, the HSCMP generates a CPU interrupt if there is a rising/falling event. When DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling event forces a DMA transfer request rather than a CPU interrupt instead.

Parameters:

base – HSCMP peripheral base address.
enable – “true” means enable DMA support, and “false” means disable DMA support.

static inline void HSCMP_EnableWindowMode(HSCMP_Type *base, bool enable)#

Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. The optionally inverted comparator output COUT_RAW is sampled on every bus clock when WINDOW=1 to generate COUTA.

Parameters:

base – HSCMP peripheral base address.
enable – “true” means enable window mode, and “false” means disable window mode.

void HSCMP_SetWindowConfig(HSCMP_Type *base, const hscmp_window_config_t *config)#

Configure the window mode with full control over all window-related options.

This function configures CCR1 window-related bits: WINDOW_EN, WINDOW_INV, WINDOW_CLS, EVT_SEL, COUTA_OWEN, and COUTA_OW.

Parameters:

base – HSCMP peripheral base address.
config – Pointer to hscmp_window_config_t structure.

void HSCMP_SetFilterConfig(HSCMP_Type *base, const hscmp_filter_config_t *config)#

Configures the filter.

Parameters:

base – HSCMP peripheral base address.
config – Pointer to “hscmp_filter_config_t” structure.

void HSCMP_SetDACConfig(HSCMP_Type *base, const hscmp_dac_config_t *config)#

Configure the internal DAC module.

Parameters:

base – HSCMP peripheral base address.
config – Pointer to “hscmp_dac_config_t” structure. If config is “NULL”, disable internal DAC.

static inline void HSCMP_SetDACValue(HSCMP_Type *base, uint8_t value)#

Dynamically update the DAC output voltage.

Parameters:

base – HSCMP peripheral base address.
value – New DAC output voltage code.

void HSCMP_SetRoundRobinConfig(HSCMP_Type *base, const hscmp_roundrobin_config_t *config)#

Configure the round-robin comparison mode.

This function configures RRCR0, RRCR1, and RRCR2 registers.

Parameters:

base – HSCMP peripheral base address.
config – Pointer to hscmp_roundrobin_config_t structure.

static inline uint32_t HSCMP_GetRoundRobinLastResult(HSCMP_Type *base)#

Get the round-robin last comparison results for each channel.

Returns the RRCSR register. Each bit[n] reflects the latest comparison output for channel n after the round-robin sweep. Use _hscmp_roundrobin_channel_mask to decode the result.

Parameters:

base – HSCMP peripheral base address.

Returns:

Bitmask of last comparison results. See _hscmp_roundrobin_channel_mask.

static inline void HSCMP_SetRoundRobinPresetState(HSCMP_Type *base, uint32_t mask)#

Set the round-robin preset comparison state for each channel.

Writes the RRCSR register to set the reference comparison results. The hardware compares each new sweep result against this preset; if a channel result differs, the corresponding flag in RRSR is set. Call this before enabling round-robin to establish the initial reference state. Use _hscmp_roundrobin_channel_mask values.

Parameters:

base – HSCMP peripheral base address.
mask – Bitmask of channels whose preset comparison output is high (1). See _hscmp_roundrobin_channel_mask.

static inline uint32_t HSCMP_GetRoundRobinChannelFlags(HSCMP_Type *base)#

Get the round-robin channel changed flags.

Returns the RRSR register. A flag bit is set when the comparison result for that channel differs from the previous round. Use _hscmp_roundrobin_channel_mask to decode.

Parameters:

base – HSCMP peripheral base address.

Returns:

Bitmask of channel-changed flags. See _hscmp_roundrobin_channel_mask.

static inline void HSCMP_ClearRoundRobinChannelFlags(HSCMP_Type *base, uint32_t mask)#

Clear the round-robin channel changed flags.

Parameters:

base – HSCMP peripheral base address.
mask – Bitmask of flags to clear. See _hscmp_roundrobin_channel_mask.

FSL_HSCMP_DRIVER_VERSION#: HSCMP driver version 2.1.0.

enum _hscmp_status_flags#

HSCMP status falgs mask.

Values:

enumerator kHSCMP_OutputRisingEventFlag#: Rising-edge on the comparison output has occurred.

enumerator kHSCMP_OutputFallingEventFlag#: Falling-edge on the comparison output has occurred.

enumerator kHSCMP_RoundRobinEventFlag#: Round-Robin comparison result changed for a channel.

enumerator kHSCMP_OutputAssertEventFlag#: Return the current value of the analog comparator output. The flag does not support W1C.

enum _hscmp_interrupt_enable#

HSCMP interrupt enable/disable mask.

Values:

enumerator kHSCMP_OutputRisingInterruptEnable#: Comparator interrupt enable rising.

enumerator kHSCMP_OutputFallingInterruptEnable#: Comparator interrupt enable falling.

enumerator kHSCMP_RoundRobinInterruptEnable#: Round-Robin interrupt enable: assert when comparison result changes for a channel.

enum _hscmp_hysteresis_mode#

HSCMP hysteresis mode. See chip data sheet to get the actual hystersis value with each level.

Values:

enumerator kHSCMP_HysteresisLevel0#: The hard block output has level 0 hysteresis internally.

enumerator kHSCMP_HysteresisLevel1#: The hard block output has level 1 hysteresis internally.

enumerator kHSCMP_HysteresisLevel2#: The hard block output has level 2 hysteresis internally.

enumerator kHSCMP_HysteresisLevel3#: The hard block output has level 3 hysteresis internally.

enum _hscmp_power_mode#

HSCMP power mode.

Values:

enumerator kHSCMP_LowSpeedPowerMode#: Low speed comparison mode is selected.

enumerator kHSCMP_HighSpeedPowerMode#: High speed comparison mode is selected.

enumerator kHSCMP_NanoPowerMode#: Nano power comparator is enabled.

enum _hscmp_func_clock#

Functional clock source selection for HSCMP.

Values:

enumerator kHSCMP_FuncClockSource0#: Select functional clock source 0.

enumerator kHSCMP_FuncClockSource1#: Select functional clock source 1.

enumerator kHSCMP_FuncClockSource2#: Select functional clock source 2.

enumerator kHSCMP_FuncClockSource3#: Select functional clock source 3.

enum _hscmp_dac_reference_voltage_source#

Internal DAC reference voltage source.

Values:

enumerator kHSCMP_VrefSourceVin1#: vrefh_int is selected as resistor ladder network supply reference Vin.

enumerator kHSCMP_VrefSourceVin2#: vrefh_ext is selected as resistor ladder network supply reference Vin.

enum _hscmp_input#

Input Plus/Minus port source selection (CCR2.INPSEL / CCR2.INMSEL).

Selects the signal source fed into the comparator’s Plus or Minus port before the 8-to-1 analog mux stage (PSEL/MSEL).

Values:

enumerator kHSCMP_InputFromDAC#: IN0: input driven from the internal 8-bit DAC output.

enumerator kHSCMP_InputFromAnalogMux#: IN1: input driven from the analog 8-to-1 mux (selected by PSEL/MSEL).

enum _hscmp_window_event_select#

HSCMP window COUT event select for closing the window.

Values:

enumerator kHSCMP_WindowEventRisingEdge#: Rising edge of COUT can close the window.

enumerator kHSCMP_WindowEventFallingEdge#: Falling edge of COUT can close the window.

enumerator kHSCMP_WindowEventBothEdges#: Both edges of COUT can close the window.

enum _hscmp_roundrobin_fixed_port#

Round-Robin fixed port selection (RRCR1.FIXP).

Values:

enumerator kHSCMP_RoundRobinFixedPlusPort#: Fix the Plus port; sweep only the Minus port inputs.

enumerator kHSCMP_RoundRobinFixedMinusPort#: Fix the Minus port; sweep only the Plus port inputs.

enum _hscmp_roundrobin_channel_mask#

Round-Robin channel bitmask.

Use OR combinations of these values for:

hscmp_roundrobin_config_t::channelEnableMask (RRCR1 channel enables)
HSCMP_SetRoundRobinPresetState (RRCSR preset comparison results)
HSCMP_GetRoundRobinLastResult (RRCSR last comparison results)
HSCMP_GetRoundRobinChannelFlags (RRSR channel-changed flags)
HSCMP_ClearRoundRobinChannelFlags (RRSR clear flags)

Values:

enumerator kHSCMP_RoundRobinChannel0Mask#: Channel 0 mask.

enumerator kHSCMP_RoundRobinChannel1Mask#: Channel 1 mask.

enumerator kHSCMP_RoundRobinChannel2Mask#: Channel 2 mask.

enumerator kHSCMP_RoundRobinChannel3Mask#: Channel 3 mask.

enumerator kHSCMP_RoundRobinChannel4Mask#: Channel 4 mask.

enumerator kHSCMP_RoundRobinChannel5Mask#: Channel 5 mask.

enumerator kHSCMP_RoundRobinChannel6Mask#: Channel 6 mask.

enumerator kHSCMP_RoundRobinChannel7Mask#: Channel 7 mask.

enum _hscmp_roundrobin_trig_sel#

Round-Robin trigger source selection.

Values:

enumerator kHSCMP_RoundRobinExternalTrigger#: External trigger drives round-robin scanning.

enumerator kHSCMP_RoundRobinInternalTrigger#: Internal trigger drives round-robin scanning.

enum _hscmp_roundrobin_clk_sel#

Round-Robin sampling clock source selection.

Values:

enumerator kHSCMP_RoundRobinClockSource0#: Round-Robin clock source 0.

enumerator kHSCMP_RoundRobinClockSource1#: Round-Robin clock source 1.

enumerator kHSCMP_RoundRobinClockSource2#: Round-Robin clock source 2.

enumerator kHSCMP_RoundRobinClockSource3#: Round-Robin clock source 3.

typedef enum _hscmp_hysteresis_mode hscmp_hysteresis_mode_t#: HSCMP hysteresis mode. See chip data sheet to get the actual hystersis value with each level.

typedef enum _hscmp_power_mode hscmp_power_mode_t#: HSCMP power mode.

typedef enum _hscmp_func_clock hscmp_func_clock_t#: Functional clock source selection for HSCMP.

typedef enum _hscmp_dac_reference_voltage_source hscmp_dac_reference_voltage_source_t#: Internal DAC reference voltage source.

typedef enum _hscmp_input hscmp_input_t#

Input Plus/Minus port source selection (CCR2.INPSEL / CCR2.INMSEL).

Selects the signal source fed into the comparator’s Plus or Minus port before the 8-to-1 analog mux stage (PSEL/MSEL).

typedef enum _hscmp_window_event_select hscmp_window_event_select_t#: HSCMP window COUT event select for closing the window.

typedef struct _hscmp_window_config hscmp_window_config_t#: Configures HSCMP window mode.

typedef struct _hscmp_filter_config hscmp_filter_config_t#: Configure the filter.

typedef struct _hscmp_dac_config hscmp_dac_config_t#: configure the internal DAC.

typedef struct _hscmp_config hscmp_config_t#: Configures the comparator.

typedef enum _hscmp_roundrobin_fixed_port hscmp_roundrobin_fixed_port_t#: Round-Robin fixed port selection (RRCR1.FIXP).

typedef enum _hscmp_roundrobin_trig_sel hscmp_roundrobin_trig_sel_t#: Round-Robin trigger source selection.

typedef enum _hscmp_roundrobin_clk_sel hscmp_roundrobin_clk_sel_t#: Round-Robin sampling clock source selection.

typedef struct _hscmp_roundrobin_config hscmp_roundrobin_config_t#: Configures the round-robin comparison mode.

static inline void HSCMP_EnableInterrupts(HSCMP_Type *base, uint32_t mask)#

Enable the interrupts.

Parameters:

base – HSCMP peripheral base address.
mask – Mask value for interrupts. See “_hscmp_interrupt_enable”.

static inline void HSCMP_DisableInterrupts(HSCMP_Type *base, uint32_t mask)#

Disable the interrupts.

Parameters:

base – HSCMP peripheral base address.
mask – Mask value for interrupts. See “_hscmp_interrupt_enable”.

static inline uint32_t HSCMP_GetStatusFlags(HSCMP_Type *base)#

Get the HSCMP status flags.

Parameters:

base – HSCMP peripheral base address.

Returns:

Mask value for the asserted flags. See “_hscmp_status_flags”.

static inline void HSCMP_ClearStatusFlags(HSCMP_Type *base, uint32_t mask)#

Clear the HSCMP status flags.

Parameters:

base – HSCMP peripheral base address.
mask – Mask value for the flags. See “_hscmp_status_flags”.

HSCMP_RRCR1_RR_CHEN_MASK#

HSCMP_RRCR1_RR_CHEN_SHIFT#

struct _hscmp_window_config#

#include <fsl_hscmp.h>

Configures HSCMP window mode.

Public Members

bool enableWindowMode#: Enable window mode. When true, COUTA is clocked by bus clock whenever WINDOW=1.

bool enableWindowInvert#: Invert the WINDOW/SAMPLE input signal.

bool enableWindowCloseByEvent#: Allow a COUT edge event (selected by windowEventSelect) to close the window.

hscmp_window_event_select_t windowEventSelect#: COUT edge event that can close the window. Only effective when enableWindowCloseByEvent is true.

bool enableCoutaOwenMode#: Enable COUTA output-override mode: COUTA is defined by coutaOwLevel when window is closed instead of holding the last sampled value.

bool coutaOwLevel#: COUTA output level while window is closed (when enableCoutaOwenMode is true). false=0, true=1.

struct _hscmp_filter_config#

#include <fsl_hscmp.h>

Configure the filter.

Public Members

bool enableSample#: Decide whether to use the external SAMPLE as a sampling clock input.

uint8_t filterSampleCount#: Filter Sample Count. Available range is 1-7; 0 disables the filter.

uint8_t filterSamplePeriod#: Filter Sample Period. The divider to the bus clock. Available range is 0-255. The sampling clock must be at least 4 times slower than the system clock to the comparator. So if enableSample is “false”, filterSamplePeriod should be set greater than 4.

struct _hscmp_dac_config#

#include <fsl_hscmp.h>

configure the internal DAC.

Public Members

bool enableLowPowerMode#: Decide whether to enable DAC low power mode.

hscmp_dac_reference_voltage_source_t referenceVoltageSource#: Internal DAC supply voltage reference source.

uint8_t DACValue#: Value for the DAC Output Voltage. Available range is 0-63.

bool enableDacOutput#: Enables the DAC output to be available for other on-chip peripherals.

bool enableDacStopMode#: Allow DAC_EN to enable the DAC in stop mode.

struct _hscmp_config#

#include <fsl_hscmp.h>

Configures the comparator.

Public Members

bool enableComparator#: Decide whether to enable the comparator.

bool enableStopMode#: Decide whether to enable the comparator when in STOP modes.

bool enableOutputPin#: Decide whether to enable the comparator is available in selected pin.

bool useUnfilteredOutput#: Decide whether to use unfiltered output.

bool enableInvertOutput#: Decide whether to inverts the comparator output.

hscmp_hysteresis_mode_t hysteresisMode#: HSCMP hysteresis mode.

hscmp_power_mode_t powerMode#: HSCMP power mode.

bool enableDacLink#: CMP-to-DAC link enable: when true the DAC is enabled/disabled by CMP_EN instead of DCR[DAC_EN].

bool enableOffset#: Comparator offset control: when true, hysteresis is asymmetric — does not apply when INP crosses INM rising or INM crosses INP falling.

hscmp_func_clock_t funcClockSel#: Functional clock source for the comparator core.

struct _hscmp_roundrobin_config#

#include <fsl_hscmp.h>

Configures the round-robin comparison mode.

Public Members

bool enableRoundRobin#: Enable round-robin mode.

uint8_t sampleClockCount#: Number of sample clocks after mux switch before sampling (0-3).

uint8_t initDelayModulus#: Initialization delay modulus in bus clock cycles (1-63; 0 means 63).

hscmp_roundrobin_fixed_port_t fixedPort#: Fixed port select: sweeps Minus inputs or Plus inputs.

uint8_t fixedChannel#: Fixed channel select (0-7).

uint32_t channelEnableMask#: Bitmask of channels enabled for round-robin scanning. Use OR combinations of _hscmp_roundrobin_channel_mask values.

bool enableRRTimer#: Enable the round-robin internal timer to auto-trigger scanning (RRCR2).

uint32_t timerReloadValue#: Timer reload value in bus clock cycles (28-bit, valid range 0-0x0FFFFFFFU).

hscmp_roundrobin_trig_sel_t triggerSelect#: Round-Robin trigger source select.

hscmp_roundrobin_clk_sel_t rrClockSel#: Round-Robin sampling clock source select.

uint8_t sampleCount#: Number of samples for one channel.

uint8_t sampleThreshold#: For one channel, when (RR_SAMPLE_THRESHOLD+1) sample results are “1”, the final result is “1”; otherwise the final result is “0”. This value must not be larger than sampleCount.

Common Driver#

FSL_COMMON_DRIVER_VERSION#: common driver version.

DEBUG_CONSOLE_DEVICE_TYPE_NONE#: No debug console.

DEBUG_CONSOLE_DEVICE_TYPE_UART#: Debug console based on UART.

DEBUG_CONSOLE_DEVICE_TYPE_LPUART#: Debug console based on LPUART.

DEBUG_CONSOLE_DEVICE_TYPE_LPSCI#: Debug console based on LPSCI.

DEBUG_CONSOLE_DEVICE_TYPE_USBCDC#: Debug console based on USBCDC.

DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM#: Debug console based on FLEXCOMM.

DEBUG_CONSOLE_DEVICE_TYPE_IUART#: Debug console based on i.MX UART.

DEBUG_CONSOLE_DEVICE_TYPE_VUSART#: Debug console based on LPC_VUSART.

DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART#: Debug console based on LPC_USART.

DEBUG_CONSOLE_DEVICE_TYPE_SWO#: Debug console based on SWO.

DEBUG_CONSOLE_DEVICE_TYPE_QSCI#: Debug console based on QSCI.

MIN(a, b)#: Computes the minimum of a and b.

MAX(a, b)#: Computes the maximum of a and b.

UINT16_MAX#: Max value of uint16_t type.

UINT32_MAX#: Max value of uint32_t type.

UINTPTR_SIZE#

UINT64_H(X)#: Macro to get upper 32 bits of a 64-bit value

UINT64_L(X)#: Macro to get lower 32 bits of a 64-bit value

MCUX_MASK_INVERT_8(mask)#: 8-bit mask inversion.

MCUX_MASK_INVERT_16(mask)#: 16-bit mask inversion.

MCUX_MASK_INVERT_32(mask)#: 32-bit mask inversion for completeness.

MCUX_REG_WRITE8(reg, value)#: 8-bit register write macro

MCUX_REG_WRITE16(reg, value)#: 16-bit register write macro

MCUX_REG_WRITE32(reg, value)#: 32-bit register write macro

MCUX_REG_READ8(reg)#: 8-bit register read macro

MCUX_REG_READ16(reg)#: 16-bit register read macro

MCUX_REG_READ32(reg)#: 32-bit register read macro

MCUX_REG_BIT_SET8(reg, mask)#: 8-bit register bit set macro

MCUX_REG_BIT_SET16(reg, mask)#: 16-bit register bit set macro

MCUX_REG_BIT_SET32(reg, mask)#: 32-bit register bit set macro

MCUX_REG_BIT_CLEAR8(reg, mask)#: 8-bit register bit clear macro

MCUX_REG_BIT_CLEAR16(reg, mask)#: 16-bit register bit clear macro

MCUX_REG_BIT_CLEAR32(reg, mask)#: 32-bit register bit clear macro

MCUX_REG_BIT_GET8(reg, mask)#: 8-bit register bit get macro

MCUX_REG_BIT_GET16(reg, mask)#: 16-bit register bit get macro

MCUX_REG_BIT_GET32(reg, mask)#: 32-bit register bit get macro

MCUX_REG_MODIFY8(reg, mask, value)#: 32-bit register read-modify-write macro

MCUX_REG_MODIFY16(reg, mask, value)#: 16-bit register read-modify-write macro

MCUX_REG_MODIFY32(reg, mask, value)#: 32-bit register read-modify-write macro

SDK_ATOMIC_LOCAL_ADD(addr, val)#: Add value val from the variable at address address.

SDK_ATOMIC_LOCAL_SUB(addr, val)#: Subtract value val to the variable at address address.

SDK_ATOMIC_LOCAL_SET(addr, bits)#: Set the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR(addr, bits)#: Clear the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)#: Toggle the bits specifiled by bits to the variable at address address.

SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)#: For the variable at address address, clear the bits specifiled by clearBits and set the bits specifiled by setBits.

SDK_ATOMIC_LOCAL_COMPARE_AND_SET(addr, expected, newValue)#: For the variable at address address, check whether the value equal to expected. If value same as expected then update newValue to address and return true , else return false .

SDK_ATOMIC_LOCAL_TEST_AND_SET(addr, newValue)#: For the variable at address address, set as newValue value and return old value.

USEC_TO_COUNT(us, clockFreqInHz)#: Macro to convert a microsecond period to raw count value

COUNT_TO_USEC(count, clockFreqInHz)#: Macro to convert a raw count value to microsecond

MSEC_TO_COUNT(ms, clockFreqInHz)#: Macro to convert a millisecond period to raw count value

COUNT_TO_MSEC(count, clockFreqInHz)#: Macro to convert a raw count value to millisecond

SDK_ISR_EXIT_BARRIER#

SDK_ALIGN(var, alignbytes)#: Macro to define a variable with alignbytes alignment

SDK_SIZEALIGN(var, alignbytes)#

Macro to define a variable with L1 d-cache line size alignment

Macro to define a variable with L2 cache line size alignment

Macro to change a value to a given size aligned value (rounded up)

SDK_SIZEALIGN_UP(var, alignbytes)#: Macro to change a value to a given size aligned value (rounded up), the wrapper of SDK_SIZEALIGN

SDK_SIZEALIGN_DOWN(var, alignbytes)#: Macro to change a value to a given size aligned value (rounded down)

SDK_IS_ALIGNED(var, alignbytes)#: Macro to check if a value is aligned to a given size

AT_NONCACHEABLE_SECTION(var)#: Define a variable var, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)#: Define a variable var, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_NONCACHEABLE_SECTION_INIT(var)#: Define a variable var with initial value, and place it in non-cacheable section.

AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)#: Define a variable var with initial value, and place it in non-cacheable section, the start address of the variable is aligned to alignbytes.

AT_CACHE_LINE_SECTION(var)#: Define a variable var, which is cache line size aligned and be placed in CacheLineData section.

AT_CACHE_LINE_SECTION_INIT(var)#: Define a variable var with initial value, which is cache line size aligned and be placed in CacheLineData.init section.

AT_QUICKACCESS_SECTION_CODE(func)#: Place function in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA(var)#: Place data in a section which can be accessed quickly by core.

AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)#: Place data in a section which can be accessed quickly by core, and the variable address is set to align with alignbytes.

MCUX_RAMFUNC#

Function attribute to place function in RAM. For example, to place function my_func in ram, use like:

MCUX_RAMFUNC my_func

RAMFUNCTION_SECTION_CODE(func)#: Place function in ram.

MCUX_DEPRECATED#: Deprecated APIs.

MCUX_DEPRECATED_MACRO#: Deprecated macros.

MCUX_EXPERIMENTAL#: Experimental APIs.

MCUX_EXPERIMENTAL_MACRO#: Experimental macros.

enum _status_groups#

Status group numbers.

Values:

enumerator kStatusGroup_Generic#: Group number for generic status codes.

enumerator kStatusGroup_FLASH#: Group number for FLASH status codes.

enumerator kStatusGroup_LPSPI#: Group number for LPSPI status codes.

enumerator kStatusGroup_FLEXIO_SPI#: Group number for FLEXIO SPI status codes.

enumerator kStatusGroup_DSPI#: Group number for DSPI status codes.

enumerator kStatusGroup_FLEXIO_UART#: Group number for FLEXIO UART status codes.

enumerator kStatusGroup_FLEXIO_I2C#: Group number for FLEXIO I2C status codes.

enumerator kStatusGroup_LPI2C#: Group number for LPI2C status codes.

enumerator kStatusGroup_UART#: Group number for UART status codes.

enumerator kStatusGroup_I2C#: Group number for UART status codes.

enumerator kStatusGroup_LPSCI#: Group number for LPSCI status codes.

enumerator kStatusGroup_LPUART#: Group number for LPUART status codes.

enumerator kStatusGroup_SPI#: Group number for SPI status code.

enumerator kStatusGroup_XRDC#: Group number for XRDC status code.

enumerator kStatusGroup_SEMA42#: Group number for SEMA42 status code.

enumerator kStatusGroup_SDHC#: Group number for SDHC status code

enumerator kStatusGroup_SDMMC#: Group number for SDMMC status code

enumerator kStatusGroup_SAI#: Group number for SAI status code

enumerator kStatusGroup_MCG#: Group number for MCG status codes.

enumerator kStatusGroup_SCG#: Group number for SCG status codes.

enumerator kStatusGroup_SDSPI#: Group number for SDSPI status codes.

enumerator kStatusGroup_FLEXIO_I2S#: Group number for FLEXIO I2S status codes

enumerator kStatusGroup_FLEXIO_MCULCD#: Group number for FLEXIO LCD status codes

enumerator kStatusGroup_FLASHIAP#: Group number for FLASHIAP status codes

enumerator kStatusGroup_FLEXCOMM_I2C#: Group number for FLEXCOMM I2C status codes

enumerator kStatusGroup_I2S#: Group number for I2S status codes

enumerator kStatusGroup_IUART#: Group number for IUART status codes

enumerator kStatusGroup_CSI#: Group number for CSI status codes

enumerator kStatusGroup_MIPI_DSI#: Group number for MIPI DSI status codes

enumerator kStatusGroup_SDRAMC#: Group number for SDRAMC status codes.

enumerator kStatusGroup_POWER#: Group number for POWER status codes.

enumerator kStatusGroup_ENET#: Group number for ENET status codes.

enumerator kStatusGroup_PHY#: Group number for PHY status codes.

enumerator kStatusGroup_TRGMUX#: Group number for TRGMUX status codes.

enumerator kStatusGroup_SMARTCARD#: Group number for SMARTCARD status codes.

enumerator kStatusGroup_LMEM#: Group number for LMEM status codes.

enumerator kStatusGroup_QSPI#: Group number for QSPI status codes.

enumerator kStatusGroup_DMA#: Group number for DMA status codes.

enumerator kStatusGroup_EDMA#: Group number for EDMA status codes.

enumerator kStatusGroup_DMAMGR#: Group number for DMAMGR status codes.

enumerator kStatusGroup_FLEXCAN#: Group number for FlexCAN status codes.

enumerator kStatusGroup_LTC#: Group number for LTC status codes.

enumerator kStatusGroup_FLEXIO_CAMERA#: Group number for FLEXIO CAMERA status codes.

enumerator kStatusGroup_LPC_SPI#: Group number for LPC_SPI status codes.

enumerator kStatusGroup_LPC_USART#: Group number for LPC_USART status codes.

enumerator kStatusGroup_DMIC#: Group number for DMIC status codes.

enumerator kStatusGroup_SDIF#: Group number for SDIF status codes.

enumerator kStatusGroup_SPIFI#: Group number for SPIFI status codes.

enumerator kStatusGroup_OTP#: Group number for OTP status codes.

enumerator kStatusGroup_MCAN#: Group number for MCAN status codes.

enumerator kStatusGroup_CAAM#: Group number for CAAM status codes.

enumerator kStatusGroup_ECSPI#: Group number for ECSPI status codes.

enumerator kStatusGroup_USDHC#: Group number for USDHC status codes.

enumerator kStatusGroup_LPC_I2C#: Group number for LPC_I2C status codes.

enumerator kStatusGroup_DCP#: Group number for DCP status codes.

enumerator kStatusGroup_MSCAN#: Group number for MSCAN status codes.

enumerator kStatusGroup_ESAI#: Group number for ESAI status codes.

enumerator kStatusGroup_FLEXSPI#: Group number for FLEXSPI status codes.

enumerator kStatusGroup_MMDC#: Group number for MMDC status codes.

enumerator kStatusGroup_PDM#: Group number for MIC status codes.

enumerator kStatusGroup_SDMA#: Group number for SDMA status codes.

enumerator kStatusGroup_ICS#: Group number for ICS status codes.

enumerator kStatusGroup_SPDIF#: Group number for SPDIF status codes.

enumerator kStatusGroup_LPC_MINISPI#: Group number for LPC_MINISPI status codes.

enumerator kStatusGroup_HASHCRYPT#: Group number for Hashcrypt status codes

enumerator kStatusGroup_LPC_SPI_SSP#: Group number for LPC_SPI_SSP status codes.

enumerator kStatusGroup_I3C#: Group number for I3C status codes

enumerator kStatusGroup_LPC_I2C_1#: Group number for LPC_I2C_1 status codes.

enumerator kStatusGroup_NOTIFIER#: Group number for NOTIFIER status codes.

enumerator kStatusGroup_DebugConsole#: Group number for debug console status codes.

enumerator kStatusGroup_SEMC#: Group number for SEMC status codes.

enumerator kStatusGroup_ApplicationRangeStart#: Starting number for application groups.

enumerator kStatusGroup_IAP#: Group number for IAP status codes

enumerator kStatusGroup_SFA#: Group number for SFA status codes

enumerator kStatusGroup_SPC#: Group number for SPC status codes.

enumerator kStatusGroup_PUF#: Group number for PUF status codes.

enumerator kStatusGroup_TOUCH_PANEL#: Group number for touch panel status codes

enumerator kStatusGroup_VBAT#: Group number for VBAT status codes

enumerator kStatusGroup_XSPI#: Group number for XSPI status codes

enumerator kStatusGroup_PNGDEC#: Group number for PNGDEC status codes

enumerator kStatusGroup_JPEGDEC#: Group number for JPEGDEC status codes

enumerator kStatusGroup_AUDMIX#: Group number for AUDMIX status codes

enumerator kStatusGroup_HAL_GPIO#: Group number for HAL GPIO status codes.

enumerator kStatusGroup_HAL_UART#: Group number for HAL UART status codes.

enumerator kStatusGroup_HAL_TIMER#: Group number for HAL TIMER status codes.

enumerator kStatusGroup_HAL_SPI#: Group number for HAL SPI status codes.

enumerator kStatusGroup_HAL_I2C#: Group number for HAL I2C status codes.

enumerator kStatusGroup_HAL_FLASH#: Group number for HAL FLASH status codes.

enumerator kStatusGroup_HAL_PWM#: Group number for HAL PWM status codes.

enumerator kStatusGroup_HAL_RNG#: Group number for HAL RNG status codes.

enumerator kStatusGroup_HAL_I2S#: Group number for HAL I2S status codes.

enumerator kStatusGroup_HAL_ADC_SENSOR#: Group number for HAL ADC SENSOR status codes.

enumerator kStatusGroup_TIMERMANAGER#: Group number for TiMER MANAGER status codes.

enumerator kStatusGroup_SERIALMANAGER#: Group number for SERIAL MANAGER status codes.

enumerator kStatusGroup_LED#: Group number for LED status codes.

enumerator kStatusGroup_BUTTON#: Group number for BUTTON status codes.

enumerator kStatusGroup_EXTERN_EEPROM#: Group number for EXTERN EEPROM status codes.

enumerator kStatusGroup_SHELL#: Group number for SHELL status codes.

enumerator kStatusGroup_MEM_MANAGER#: Group number for MEM MANAGER status codes.

enumerator kStatusGroup_LIST#: Group number for List status codes.

enumerator kStatusGroup_OSA#: Group number for OSA status codes.

enumerator kStatusGroup_COMMON_TASK#: Group number for Common task status codes.

enumerator kStatusGroup_MSG#: Group number for messaging status codes.

enumerator kStatusGroup_SDK_OCOTP#: Group number for OCOTP status codes.

enumerator kStatusGroup_SDK_FLEXSPINOR#: Group number for FLEXSPINOR status codes.

enumerator kStatusGroup_CODEC#: Group number for codec status codes.

enumerator kStatusGroup_ASRC#: Group number for codec status ASRC.

enumerator kStatusGroup_OTFAD#: Group number for codec status codes.

enumerator kStatusGroup_SDIOSLV#: Group number for SDIOSLV status codes.

enumerator kStatusGroup_MECC#: Group number for MECC status codes.

enumerator kStatusGroup_ENET_QOS#: Group number for ENET_QOS status codes.

enumerator kStatusGroup_LOG#: Group number for LOG status codes.

enumerator kStatusGroup_I3CBUS#: Group number for I3CBUS status codes.

enumerator kStatusGroup_QSCI#: Group number for QSCI status codes.

enumerator kStatusGroup_ELEMU#: Group number for ELEMU status codes.

enumerator kStatusGroup_QUEUEDSPI#: Group number for QSPI status codes.

enumerator kStatusGroup_POWER_MANAGER#: Group number for POWER_MANAGER status codes.

enumerator kStatusGroup_IPED#: Group number for IPED status codes.

enumerator kStatusGroup_ELS_PKC#: Group number for ELS PKC status codes.

enumerator kStatusGroup_CSS_PKC#: Group number for CSS PKC status codes.

enumerator kStatusGroup_HOSTIF#: Group number for HOSTIF status codes.

enumerator kStatusGroup_CLIF#: Group number for CLIF status codes.

enumerator kStatusGroup_BMA#: Group number for BMA status codes.

enumerator kStatusGroup_NETC#: Group number for NETC status codes.

enumerator kStatusGroup_ELE#: Group number for ELE status codes.

enumerator kStatusGroup_GLIKEY#: Group number for GLIKEY status codes.

enumerator kStatusGroup_AON_POWER#: Group number for AON_POWER status codes.

enumerator kStatusGroup_AON_COMMON#: Group number for AON_COMMON status codes.

enumerator kStatusGroup_ENDAT3#: Group number for ENDAT3 status codes.

enumerator kStatusGroup_HIPERFACE#: Group number for HIPERFACE status codes.

enumerator kStatusGroup_NPX#: Group number for NPX status codes.

enumerator kStatusGroup_ELA_CSEC#: Group number for ELA_CSEC status codes.

enumerator kStatusGroup_FLEXIO_T_FORMAT#: Group number for T-format status codes.

enumerator kStatusGroup_FLEXIO_A_FORMAT#: Group number for A-format status codes.

enumerator kStatusGroup_LPC_QSPI#: Group number for LPC QSPI status codes.

enumerator kStatusGroup_EVENT_CTRL#: Group number for Event controller status codes.

Generic status return codes.

Values:

enumerator kStatus_Success#: Generic status for Success.

enumerator kStatus_Fail#: Generic status for Fail.

enumerator kStatus_ReadOnly#: Generic status for read only failure.

enumerator kStatus_OutOfRange#: Generic status for out of range access.

enumerator kStatus_InvalidArgument#: Generic status for invalid argument check.

enumerator kStatus_Timeout#: Generic status for timeout.

enumerator kStatus_NoTransferInProgress#: Generic status for no transfer in progress.

enumerator kStatus_Busy#: Generic status for module is busy.

enumerator kStatus_NoData#: Generic status for no data is found for the operation.

typedef int32_t status_t#: Type used for all status and error return values.

void *SDK_Malloc(size_t size, size_t alignbytes)#

Allocate memory with given alignment and aligned size.

This is provided to support the dynamically allocated memory used in cache-able region.

Parameters:

size – The length required to malloc.
alignbytes – The alignment size.

Return values:

The – allocated memory.

void SDK_Free(void *ptr)#

Free memory.

Parameters:

ptr – The memory to be release.

void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)#

Delay at least for some time. Please note that, this API uses while loop for delay, different run-time environments make the time not precise, if precise delay count was needed, please implement a new delay function with hardware timer.

Parameters:

delayTime_us – Delay time in unit of microsecond.
coreClock_Hz – Core clock frequency with Hz.

static inline status_t EnableIRQ(IRQn_Type interrupt)#

Enable specific interrupt.

Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number.

Return values:

kStatus_Success – Interrupt enabled successfully
kStatus_Fail – Failed to enable the interrupt

static inline status_t DisableIRQ(IRQn_Type interrupt)#

Disable specific interrupt.

Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ number.

Return values:

kStatus_Success – Interrupt disabled successfully
kStatus_Fail – Failed to disable the interrupt

static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum)#

Enable the IRQ, and also set the interrupt priority.

Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt levels. For example, there are NVIC and intmux. Here the interrupts connected to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. The interrupts connected to intmux are the LEVEL2 interrupts, they are routed to NVIC first then routed to core.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to Enable.
priNum – Priority number set to interrupt controller register.

Return values:

kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum)#

Set the IRQ priority.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The IRQ to set.
priNum – Priority number set to interrupt controller register.

Return values:

kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.

static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt)#

Clear the pending IRQ flag.

This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.

Parameters:

interrupt – The flag which IRQ to clear.

Return values:

kStatus_Success – Interrupt priority set successfully
kStatus_Fail – Failed to set the interrupt priority.

static inline uint32_t DisableGlobalIRQ(void)#

Disable the global IRQ.

Disable the global interrupt and return the current primask register. User is required to provided the primask register for the EnableGlobalIRQ().

Returns:: Current primask value.

static inline void EnableGlobalIRQ(uint32_t primask)#

Enable the global IRQ.

Set the primask register with the provided primask value but not just enable the primask. The idea is for the convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.

Parameters:

primask – value of primask register to be restored. The primask value is supposed to be provided by the DisableGlobalIRQ().

static inline bool _SDK_AtomicLocalCompareAndSet(uint32_t *addr, uint32_t expected, uint32_t newValue)#

static inline uint32_t _SDK_AtomicTestAndSet(uint32_t *addr, uint32_t newValue)#

FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ#: Macro to use the default weak IRQ handler in drivers.

MAKE_STATUS(group, code)#: Construct a status code value from a group and code number.

MAKE_VERSION(major, minor, bugfix)#

Construct the version number for drivers.

The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) and 16-bit platforms(such as DSC).

| Unused    || Major Version || Minor Version ||  Bug Fix    |
31        25  24           17  16            9  8            0

ARRAY_SIZE(x)#: Computes the number of elements in an array.

SUPPRESS_FALL_THROUGH_WARNING()#: For switch case code block, if case section ends without “break;” statement, there wil be fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. To suppress this warning, “SUPPRESS_FALL_THROUGH_WARNING();” need to be added at the end of each case section which misses “break;”statement.

MSDK_REG_SECURE_ADDR(x)#: Convert the register address to the one used in secure mode.

MSDK_REG_NONSECURE_ADDR(x)#: Convert the register address to the one used in non-secure mode.

MSDK_HAS_DWT_CYCCNT#: The chip supports DWT CYCCNT or not.

MSDK_INVALID_IRQ_HANDLER#: Invalid IRQ handler address.

Lpc_freqme#

void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config)#

Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle.

Parameters:

base – FREQME peripheral base address.
config – The pointer to module basic configuration, please refer to freq_measure_config_t.

void FREQME_GetDefaultConfig(freq_measure_config_t *config)#

Get default configuration.

config->operateMode = kFREQME_FreqMeasurementMode;
config->operateModeAttribute.refClkScaleFactor = 0U;
config->enableContinuousMode                   = false;
config->startMeasurement                       = false;

Parameters:

config – The pointer to module basic configuration, please refer to freq_measure_config_t.

static inline void FREQME_StartMeasurementCycle(FREQME_Type *base)#

Start frequency or pulse width measurement process.

Parameters:

base – FREQME peripheral base address.

static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base)#

Force the termination of any measurement cycle currently in progress and resets RESULT or just reset RESULT if the module in idle state.

Parameters:

base – FREQME peripheral base address.

static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable)#

Enable/disable Continuous mode.

Parameters:

base – FREQME peripheral base address.
enable – Used to enable/disable continuous mode,
- true Enable Continuous mode.
- false Disable Continuous mode.

static inline bool FREQME_CheckContinuousMode(FREQME_Type *base)#

Check whether continuous mode is enabled.

Parameters:

base – FREQME peripheral base address.

Return values:

True – Continuous mode is enabled, the measurement is performed continuously.
False – Continuous mode is disabled.

static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode)#

Set operate mode of freqme module.

Parameters:

base – FREQME peripheral base address.
operateMode – The operate mode to be set, please refer to freqme_operate_mode_t.

static inline bool FREQME_CheckOperateMode(FREQME_Type *base)#

Check module’s operate mode.

Parameters:

base – FREQME peripheral base address.

Return values:

True – Pulse width measurement mode.
False – Frequency measurement mode.

static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue)#

Set the minimum expected value for the measurement result.

Parameters:

base – FREQME peripheral base address.
minValue – The minimum value to set, please note that this value is 31 bits width.

static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue)#

Set the maximum expected value for the measurement result.

Parameters:

base – FREQME peripheral base address.
maxValue – The maximum value to set, please note that this value is 31 bits width.

static inline void FREQME_SetReferenceClk(FREQME_Type *base, uint32_t referenceClk)#

Set the reference clock source.

Parameters:

base – FREQME peripheral base address.
referenceClk – The reference clock source, see freqme_reference_clock_t in <device>_COMMON.h.

static inline void FREQME_SetTargetClk(FREQME_Type *base, uint32_t targetClk)#

Set the target clock source.

Parameters:

base – FREQME peripheral base address.
targetClk – The target clock source, see freqme_target_clock_t in <device>_COMMON.h.

uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency)#

Calculate the frequency of selected target clock.

Note

The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE or Ftarget = (RESULT + 1) * Freference / 2 ^ REF_SCALE

Note

This function only useful when the operate mode is selected as frequency measurement mode.

Parameters:

base – FREQME peripheral base address.
refClkFrequency – The frequency of reference clock.

Returns:

The frequency of target clock, if the output result is 0, please check the module’s operate mode.

static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base)#

Get reference clock scaling factor.

Parameters:

base – FREQME peripheral base address.

Returns:

Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale.

static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity)#

Set pulse polarity when operate mode is selected as Pulse Width Measurement mode.

Parameters:

base – FREQME peripheral base address.
pulsePolarity – The pulse polarity to be set, please refer to freqme_pulse_polarity_t.

static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base)#

Check pulse polarity when the operate mode is selected as pulse width measurement mode.

Parameters:

base – FREQME peripheral base address.

Return values:

True – Low period.
False – High period.

static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base)#

Get measurement result.

Parameters:

base – FREQME peripheral base address.

Returns:

Measurement result.

static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base)#

Get interrupt status flags, such as overflow interrupt status flag, underflow interrupt status flag, and so on.

Parameters:

base – FREQME peripheral base address.

Returns:

Current interrupt status flags, should be the OR’ed value of _freqme_interrupt_status_flags.

static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags)#

Clear interrupt status flags.

Parameters:

base – FREQME peripheral base address.
statusFlags – The combination of interrupt status flags to clear, should be the OR’ed value of _freqme_interrupt_status_flags.

static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks)#

Enable interrupts, such as result ready interrupt, overflow interrupt and so on.

Parameters:

base – FREQME peripheral base address.
masks – The mask of interrupts to enable, should be the OR’ed value of _freqme_interrupt_enable.

static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)#

Disable interrupts, such as result ready interrupt, overflow interrupt and so on.

Parameters:

base – FREQME peripheral base address.
masks – The mask of interrupts to disable, should be the OR’ed value of _freqme_interrupt_enable.

FSL_FREQME_DRIVER_VERSION#: FREQME driver version 2.2.0.

enum _freqme_interrupt_status_flags#

The enumeration of interrupt status flags. .

Values:

enumerator kFREQME_UnderflowInterruptStatusFlag#: Indicate the measurement is just done and the result is less than minimum value.

enumerator kFREQME_OverflowInterruptStatusFlag#: Indicate the measurement is just done and the result is greater than maximum value.

enumerator kFREQME_ReadyInterruptStatusFlag#: Indicate the measurement is just done and the result is ready to read.

enumerator kFREQME_AllInterruptStatusFlags#: All interrupt status flags.

enum _freqme_interrupt_enable#

The enumeration of interrupts, including underflow interrupt, overflow interrupt, and result ready interrupt. .

Values:

enumerator kFREQME_UnderflowInterruptEnable#: Enable interrupt when the result is less than minimum value.

enumerator kFREQME_OverflowInterruptEnable#: Enable interrupt when the result is greater than maximum value.

enumerator kFREQME_ReadyInterruptEnable#: Enable interrupt when a measurement completes and the result is ready.

enum _freqme_operate_mode#

FREQME module operate mode enumeration, including frequency measurement mode and pulse width measurement mode.

Values:

enumerator kFREQME_FreqMeasurementMode#: The module works in the frequency measurement mode.

enumerator kFREOME_PulseWidthMeasurementMode#: The module works in the pulse width measurement mode.

enum _freqme_pulse_polarity#

The enumeration of pulse polarity.

Values:

enumerator kFREQME_PulseHighPeriod#: Select high period of the reference clock.

enumerator kFREQME_PulseLowPeriod#: Select low period of the reference clock.

typedef enum _freqme_operate_mode freqme_operate_mode_t#: FREQME module operate mode enumeration, including frequency measurement mode and pulse width measurement mode.

typedef enum _freqme_pulse_polarity freqme_pulse_polarity_t#: The enumeration of pulse polarity.

typedef union _freqme_mode_attribute freqme_mode_attribute_t#: The union of operate mode attribute.

Note

If the operate mode is selected as frequency measurement mode the member refClkScaleFactor should be used, if the operate mode is selected as pulse width measurement mode the member pulsePolarity should be used.

typedef struct _freq_measure_config freq_measure_config_t#: The structure of freqme module basic configuration, including operate mode, operate mode attribute and so on.

union _freqme_mode_attribute#

#include <fsl_freqme.h>

The union of operate mode attribute.

Note

If the operate mode is selected as frequency measurement mode the member refClkScaleFactor should be used, if the operate mode is selected as pulse width measurement mode the member pulsePolarity should be used.

Public Members

uint8_t refClkScaleFactor#: Only useful in frequency measurement operate mode, used to set the reference clock counter scaling factor.

freqme_pulse_polarity_t pulsePolarity#: Only Useful in pulse width measurement operate mode, used to set period polarity.

struct _freq_measure_config#

#include <fsl_freqme.h>

The structure of freqme module basic configuration, including operate mode, operate mode attribute and so on.

Public Members

freqme_operate_mode_t operateMode#: Select operate mode, please refer to freqme_operate_mode_t.

freqme_mode_attribute_t operateModeAttribute#: Used to set the attribute of the selected operate mode, if the operate mode is selected as kFREQME_FreqMeasurementMode set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is selected as kFREOME_PulseWidthMeasurementMode, please set freqme_mode_attribute_t::pulsePolarity.

bool enableContinuousMode#: Enable/disable continuous mode, if continuous mode is enable, the measurement is performed continuously and the result for the last completed measurement is available in the result register.

LPI2C: Low Power Inter-Integrated Circuit Driver#

void LPI2C_DriverIRQHandler(uint32_t instance)#

LPI2C driver IRQ handler common entry.

This function provides the common IRQ request entry for LPI2C.

Parameters:

instance – LPI2C instance.

FSL_LPI2C_DRIVER_VERSION#: LPI2C driver version.

LPI2C status return codes.

Values:

enumerator kStatus_LPI2C_Busy#: The master is already performing a transfer.

enumerator kStatus_LPI2C_Idle#: The slave driver is idle.

enumerator kStatus_LPI2C_Nak#: The slave device sent a NAK in response to a byte.

enumerator kStatus_LPI2C_FifoError#: FIFO under run or overrun.

enumerator kStatus_LPI2C_BitError#: Transferred bit was not seen on the bus.

enumerator kStatus_LPI2C_ArbitrationLost#: Arbitration lost error.

enumerator kStatus_LPI2C_PinLowTimeout#: SCL or SDA were held low longer than the timeout.

enumerator kStatus_LPI2C_NoTransferInProgress#: Attempt to abort a transfer when one is not in progress.

enumerator kStatus_LPI2C_DmaRequestFail#: DMA request failed.

enumerator kStatus_LPI2C_Timeout#: Timeout polling status flags.

IRQn_Type const kLpi2cMasterIrqs[]#: Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional APIs.

IRQn_Type const kLpi2cSlaveIrqs[]#

lpi2c_master_isr_t s_lpi2cMasterIsr#: Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

void *s_lpi2cMasterHandle[]#: Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional APIs.

uint32_t LPI2C_GetInstance(LPI2C_Type *base)#

Returns an instance number given a base address.

If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

base – The LPI2C peripheral base address.

Returns:

LPI2C instance number starting from 0.

I2C_RETRY_TIMES#: Retry times for waiting flag.

LPI2C Master Driver#

void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)#

Provides a default configuration for the LPI2C master peripheral.

This function provides the following default configuration for the LPI2C master peripheral:

masterConfig->enableMaster            = true;
masterConfig->debugEnable             = false;
masterConfig->ignoreAck               = false;
masterConfig->pinConfig               = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busIdleTimeout_ns       = 0;
masterConfig->pinLowTimeout_ns        = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable      = false;
masterConfig->hostRequest.source      = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity    = kLPI2C_HostRequestPinActiveHigh;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with LPI2C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to lpi2c_master_config_t.

void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)#

Initializes the LPI2C master peripheral.

This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The LPI2C peripheral base address.
masterConfig – User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of defaults that you can override.
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

void LPI2C_MasterDeinit(LPI2C_Type *base)#

Deinitializes the LPI2C master peripheral.

This function disables the LPI2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address.

void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig)#

Configures LPI2C master data match feature.

Parameters:

base – The LPI2C peripheral base address.
matchConfig – Settings for the data match feature.

status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)#

Convert provided flags to status code, and clear any errors if present.

Parameters:

base – The LPI2C peripheral base address.
status – Current status flags value that will be checked.

Return values:

kStatus_Success –
kStatus_LPI2C_PinLowTimeout –
kStatus_LPI2C_ArbitrationLost –
kStatus_LPI2C_Nak –
kStatus_LPI2C_FifoError –

status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)#

Make sure the bus isn’t already busy.

A busy bus is allowed if we are the one driving it.

Parameters:

base – The LPI2C peripheral base address.

Return values:

kStatus_Success –
kStatus_LPI2C_Busy –

static inline void LPI2C_MasterReset(LPI2C_Type *base)#

Performs a software reset.

Restores the LPI2C master peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address.

static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)#

Enables or disables the LPI2C module as master.

Parameters:

base – The LPI2C peripheral base address.
enable – Pass true to enable or false to disable the specified LPI2C as master.

static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base)#

Gets the LPI2C master status flags.

A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_master_flags

Parameters:

base – The LPI2C peripheral base address.

Returns:

State of the status flags:

1: related status flag is set.
0: related status flag is not set.

static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)#

Clears the LPI2C master status flag state.

The following status register flags can be cleared:

kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_master_flags.

Parameters:

base – The LPI2C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_master_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_MasterGetStatusFlags().

static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)#

Enables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)#

Disables the LPI2C master interrupt requests.

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _lpi2c_master_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)#

Returns the set of currently enabled LPI2C master interrupt requests.

Parameters:

base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_master_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx)#

Enables or disables LPI2C master DMA requests.

Parameters:

base – The LPI2C peripheral base address.
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable.
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable.

static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base)#

Gets LPI2C master transmit data register address for DMA transfer.

Parameters:

base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Transmit Data Register address.

static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)#

Gets LPI2C master receive data register address for DMA transfer.

Parameters:

base – The LPI2C peripheral base address.

Returns:

The LPI2C Master Receive Data Register address.

static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords)#

Sets the watermarks for LPI2C master FIFOs.

Parameters:

base – The LPI2C peripheral base address.
txWords – Transmit FIFO watermark value in words. The kLPI2C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO is equal or less than txWords. Writing a value equal or greater than the FIFO size is truncated.
rxWords – Receive FIFO watermark value in words. The kLPI2C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO is greater than rxWords. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount)#

Gets the current number of words in the LPI2C master FIFOs.

Parameters:

base – The LPI2C peripheral base address.
txCount – [out] Pointer through which the current number of words in the transmit FIFO is returned. Pass NULL if this value is not required.
rxCount – [out] Pointer through which the current number of words in the receive FIFO is returned. Pass NULL if this value is not required.

void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)#

Sets the I2C bus frequency for master transactions.

The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note

Please note that the second parameter is the clock frequency of LPI2C module, the third parameter means user configured bus baudrate, this implementation is different from other I2C drivers which use baudrate configuration as second parameter and source clock frequency as third parameter.

Parameters:

base – The LPI2C peripheral base address.
sourceClock_Hz – LPI2C functional clock frequency in Hertz.
baudRate_Hz – Requested bus frequency in Hertz.

static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base)#

Returns whether the bus is idle.

Requires the master mode to be enabled.

Parameters:

base – The LPI2C peripheral base address.

Return values:

true – Bus is busy.
false – Bus is idle.

status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)#

Sends a START signal and slave address on the I2C bus.

This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The LPI2C peripheral base address.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)#

Sends a repeated START signal and slave address on the I2C bus.

This function is used to send a Repeated START signal when a transfer is already in progress. Like LPI2C_MasterStart(), it also sends the specified 7-bit address.

Note

This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, as well as to better document the intent of code that uses these APIs.

Parameters:

base – The LPI2C peripheral base address.
address – 7-bit slave device address, in bits [6:0].
dir – Master transfer direction, either kLPI2C_Read or kLPI2C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address.

Return values:

kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.

status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)#

Performs a polling send transfer on the I2C bus.

Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_LPI2C_Nak.

Parameters:

base – The LPI2C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.

Return values:

kStatus_Success – Data was sent successfully.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or over run.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)#

Performs a polling receive transfer on the I2C bus.

Parameters:

base – The LPI2C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.

Return values:

kStatus_Success – Data was received successfully.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or overrun.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterStop(LPI2C_Type *base)#

Sends a STOP signal on the I2C bus.

This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

base – The LPI2C peripheral base address.

Return values:

kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or overrun.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)#

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to error happens during transfer.

Parameters:

base – The LPI2C peripheral base address.
transfer – Pointer to the transfer structure.

Return values:

kStatus_Success – Data was received successfully.
kStatus_LPI2C_Busy – Another master is currently utilizing the bus.
kStatus_LPI2C_Nak – The slave device sent a NAK in response to a byte.
kStatus_LPI2C_FifoError – FIFO under run or overrun.
kStatus_LPI2C_ArbitrationLost – Arbitration lost error.
kStatus_LPI2C_PinLowTimeout – SCL or SDA were held low longer than the timeout.

void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_callback_t callback, void *userData)#

Creates a new handle for the LPI2C master non-blocking APIs.

The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.

Note

The function also enables the NVIC IRQ for the input LPI2C. Need to notice that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.

Parameters:

base – The LPI2C peripheral base address.
handle – [out] Pointer to the LPI2C master driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, lpi2c_master_handle_t *handle, lpi2c_master_transfer_t *transfer)#

Performs a non-blocking transaction on the I2C bus.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
transfer – The pointer to the transfer descriptor.

Return values:

kStatus_Success – The transaction was started successfully.
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress.

status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)#

Returns number of bytes transferred so far.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_Success –
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)#

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the LPI2C peripheral’s IRQ priority.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.

void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle)#

Reusable routine to handle master interrupts.

Note

This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality.

Parameters:

base – The LPI2C peripheral base address.
lpi2cMasterHandle – Pointer to the LPI2C master driver handle.

enum _lpi2c_master_flags#

LPI2C master peripheral flags.

The following status register flags can be cleared:

kLPI2C_MasterEndOfPacketFlag
kLPI2C_MasterStopDetectFlag
kLPI2C_MasterNackDetectFlag
kLPI2C_MasterArbitrationLostFlag
kLPI2C_MasterFifoErrFlag
kLPI2C_MasterPinLowTimeoutFlag
kLPI2C_MasterDataMatchFlag

All flags except kLPI2C_MasterBusyFlag and kLPI2C_MasterBusBusyFlag can be enabled as interrupts.

Note

These enums are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_MasterTxReadyFlag#: Transmit data flag

enumerator kLPI2C_MasterRxReadyFlag#: Receive data flag

enumerator kLPI2C_MasterEndOfPacketFlag#: End Packet flag

enumerator kLPI2C_MasterStopDetectFlag#: Stop detect flag

enumerator kLPI2C_MasterNackDetectFlag#: NACK detect flag

enumerator kLPI2C_MasterArbitrationLostFlag#: Arbitration lost flag

enumerator kLPI2C_MasterFifoErrFlag#: FIFO error flag

enumerator kLPI2C_MasterPinLowTimeoutFlag#: Pin low timeout flag

enumerator kLPI2C_MasterDataMatchFlag#: Data match flag

enumerator kLPI2C_MasterBusyFlag#: Master busy flag

enumerator kLPI2C_MasterBusBusyFlag#: Bus busy flag

enumerator kLPI2C_MasterClearFlags#: All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_MasterIrqFlags#: IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_MasterErrorFlags#: Errors to check for.

enum _lpi2c_direction#

Direction of master and slave transfers.

Values:

enumerator kLPI2C_Write#: Master transmit.

enumerator kLPI2C_Read#: Master receive.

enum _lpi2c_master_pin_config#

LPI2C pin configuration.

Values:

enumerator kLPI2C_2PinOpenDrain#: LPI2C Configured for 2-pin open drain mode

enumerator kLPI2C_2PinOutputOnly#: LPI2C Configured for 2-pin output only mode (ultra-fast mode)

enumerator kLPI2C_2PinPushPull#: LPI2C Configured for 2-pin push-pull mode

enumerator kLPI2C_4PinPushPull#: LPI2C Configured for 4-pin push-pull mode

enumerator kLPI2C_2PinOpenDrainWithSeparateSlave#: LPI2C Configured for 2-pin open drain mode with separate LPI2C slave

enumerator kLPI2C_2PinOutputOnlyWithSeparateSlave#: LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave

enumerator kLPI2C_2PinPushPullWithSeparateSlave#: LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave

enumerator kLPI2C_4PinPushPullWithInvertedOutput#: LPI2C Configured for 4-pin push-pull mode(inverted outputs)

enum _lpi2c_host_request_source#

LPI2C master host request selection.

Values:

enumerator kLPI2C_HostRequestExternalPin#: Select the LPI2C_HREQ pin as the host request input

enumerator kLPI2C_HostRequestInputTrigger#: Select the input trigger as the host request input

enum _lpi2c_host_request_polarity#

LPI2C master host request pin polarity configuration.

Values:

enumerator kLPI2C_HostRequestPinActiveLow#: Configure the LPI2C_HREQ pin active low

enumerator kLPI2C_HostRequestPinActiveHigh#: Configure the LPI2C_HREQ pin active high

enum _lpi2c_data_match_config_mode#

LPI2C master data match configuration modes.

Values:

enumerator kLPI2C_MatchDisabled#: LPI2C Match Disabled

enumerator kLPI2C_1stWordEqualsM0OrM1#: LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1

enumerator kLPI2C_AnyWordEqualsM0OrM1#: LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1

enumerator kLPI2C_1stWordEqualsM0And2ndWordEqualsM1#: LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1

enumerator kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1#: LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1

enumerator kLPI2C_1stWordAndM1EqualsM0AndM1#: LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1

enumerator kLPI2C_AnyWordAndM1EqualsM0AndM1#: LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1

enum _lpi2c_master_transfer_flags#

Transfer option flags.

Note

These enumerations are intended to be OR’d together to form a bit mask of options for the _lpi2c_master_transfer::flags field.

Values:

enumerator kLPI2C_TransferDefaultFlag#: Transfer starts with a start signal, stops with a stop signal.

enumerator kLPI2C_TransferNoStartFlag#: Don’t send a start condition, address, and sub address

enumerator kLPI2C_TransferNoStopFlag#: Don’t send a stop condition.

typedef enum _lpi2c_direction lpi2c_direction_t#: Direction of master and slave transfers.

typedef enum _lpi2c_master_pin_config lpi2c_master_pin_config_t#: LPI2C pin configuration.

typedef enum _lpi2c_host_request_source lpi2c_host_request_source_t#: LPI2C master host request selection.

typedef enum _lpi2c_host_request_polarity lpi2c_host_request_polarity_t#: LPI2C master host request pin polarity configuration.

typedef struct _lpi2c_master_config lpi2c_master_config_t#

Structure with settings to initialize the LPI2C master module.

This structure holds configuration settings for the LPI2C peripheral. To initialize this structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_data_match_config_mode lpi2c_data_match_config_mode_t#: LPI2C master data match configuration modes.

typedef struct _lpi2c_match_config lpi2c_data_match_config_t#: LPI2C master data match configuration structure.

typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t#: LPI2C master descriptor of the transfer.

typedef struct _lpi2c_master_handle lpi2c_master_handle_t#: LPI2C master handle of the transfer.

typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle, status_t completionStatus, void *userData)#

Master completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterTransferCreateHandle().

Param base:: The LPI2C peripheral base address.
Param handle:: Pointer to the LPI2C master driver handle.
Param completionStatus:: Either kStatus_Success or an error code describing how the transfer completed.
Param userData:: Arbitrary pointer-sized value passed from the application.

typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle)#: Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs.

struct _lpi2c_master_config#

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C master module.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableMaster#: Whether to enable master mode.

bool enableDoze#: Whether master is enabled in doze mode.

bool debugEnable#: Enable transfers to continue when halted in debug mode.

bool ignoreAck#: Whether to ignore ACK/NACK.

lpi2c_master_pin_config_t pinConfig#: The pin configuration option.

uint32_t baudRate_Hz#: Desired baud rate in Hertz.

uint32_t busIdleTimeout_ns#: Bus idle timeout in nanoseconds. Set to 0 to disable.

uint32_t pinLowTimeout_ns#: Pin low timeout in nanoseconds. Set to 0 to disable.

uint8_t sdaGlitchFilterWidth_ns#: Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable.

uint8_t sclGlitchFilterWidth_ns#: Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable.

struct _lpi2c_master_config hostRequest#: Host request options.

struct _lpi2c_match_config#

#include <fsl_lpi2c.h>

LPI2C master data match configuration structure.

Public Members

lpi2c_data_match_config_mode_t matchMode#: Data match configuration setting.

bool rxDataMatchOnly#: When set to true, received data is ignored until a successful match.

uint32_t match0#: Match value 0.

uint32_t match1#: Match value 1.

struct _lpi2c_master_transfer#

#include <fsl_lpi2c.h>

Non-blocking transfer descriptor structure.

This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API.

Public Members

uint32_t flags#: Bit mask of options for the transfer. See enumeration _lpi2c_master_transfer_flags for available options. Set to 0 or kLPI2C_TransferDefaultFlag for normal transfers.

uint16_t slaveAddress#: The 7-bit slave address.

lpi2c_direction_t direction#: Either kLPI2C_Read or kLPI2C_Write.

uint32_t subaddress#: Sub address. Transferred MSB first.

size_t subaddressSize#: Length of sub address to send in bytes. Maximum size is 4 bytes.

void *data#: Pointer to data to transfer.

size_t dataSize#: Number of bytes to transfer.

struct _lpi2c_master_handle#

#include <fsl_lpi2c.h>

Driver handle for master non-blocking APIs.

Note

The contents of this structure are private and subject to change.

Public Members

uint8_t state#: Transfer state machine current state.

uint16_t remainingBytes#: Remaining byte count in current state.

uint8_t *buf#: Buffer pointer for current state.

uint16_t commandBuffer[6]#: LPI2C command sequence. When all 6 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word]

lpi2c_master_transfer_t transfer#: Copy of the current transfer info.

lpi2c_master_transfer_callback_t completionCallback#: Callback function pointer.

void *userData#: Application data passed to callback.

uint16_t chunkSize#: Remaining byte count in current chunk.

struct hostRequest

Public Members

bool enable#: Enable host request.

lpi2c_host_request_source_t source#: Host request source.

lpi2c_host_request_polarity_t polarity#: Host request pin polarity.

LPI2C Master DMA Driver#

void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle, lpi2c_master_edma_transfer_callback_t callback, void *userData)#

Create a new handle for the LPI2C master DMA APIs.

The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called.

For devices where the LPI2C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The LPI2C peripheral base address.
handle – [out] Pointer to the LPI2C master driver handle.
rxDmaHandle – Handle for the eDMA receive channel. Created by the user prior to calling this function.
txDmaHandle – Handle for the eDMA transmit channel. Created by the user prior to calling this function.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.

status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, lpi2c_master_transfer_t *transfer)#

Performs a non-blocking DMA-based transaction on the I2C bus.

The callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
transfer – The pointer to the transfer descriptor.

Return values:

kStatus_Success – The transaction was started successfully.
kStatus_LPI2C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress.

status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count)#

Returns number of bytes transferred so far.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.
count – [out] Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_Success –
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress.

status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle)#

Terminates a non-blocking LPI2C master transmission early.

Note

It is not safe to call this function from an IRQ handler that has a higher priority than the eDMA peripheral’s IRQ priority.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to the LPI2C master driver handle.

Return values:

kStatus_Success – A transaction was successfully aborted.
kStatus_LPI2C_Idle – There is not a DMA transaction currently in progress.

typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t#: LPI2C master EDMA handle of the transfer.

typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, status_t completionStatus, void *userData)#

Master DMA completion callback function pointer type.

This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use in the call to LPI2C_MasterCreateEDMAHandle().

Param base:: The LPI2C peripheral base address.
Param handle:: Handle associated with the completed transfer.
Param completionStatus:: Either kStatus_Success or an error code describing how the transfer completed.
Param userData:: Arbitrary pointer-sized value passed from the application.

struct _lpi2c_master_edma_handle#

#include <fsl_lpi2c_edma.h>

Driver handle for master DMA APIs.

Note

The contents of this structure are private and subject to change.

Public Members

LPI2C_Type *base#: LPI2C base pointer.

bool isBusy#: Transfer state machine current state.

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

uint16_t commandBuffer[20U]#: LPI2C command sequence. When all 10 command words are used: Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words]

lpi2c_master_transfer_t transfer#: Copy of the current transfer info.

lpi2c_master_edma_transfer_callback_t completionCallback#: Callback function pointer.

void *userData#: Application data passed to callback.

edma_handle_t *rx#: Handle for receive DMA channel.

edma_handle_t *tx#: Handle for transmit DMA channel.

edma_tcd_t tcds[3]#: Software TCD. Three are allocated to provide enough room to align to 32-bytes.

LPI2C Slave Driver#

void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)#

Provides a default configuration for the LPI2C slave peripheral.

This function provides the following default configuration for the LPI2C slave peripheral:

slaveConfig->enableSlave               = true;
slaveConfig->address0                  = 0U;
slaveConfig->address1                  = 0U;
slaveConfig->addressMatchMode          = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable          = true;
slaveConfig->filterEnable              = true;
slaveConfig->enableGeneralCall         = false;
slaveConfig->sclStall.enableAck        = false;
slaveConfig->sclStall.enableTx         = true;
slaveConfig->sclStall.enableRx         = true;
slaveConfig->sclStall.enableAddress    = true;
slaveConfig->ignoreAck                 = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns   = 0;
slaveConfig->sclGlitchFilterWidth_ns   = 0;
slaveConfig->dataValidDelay_ns         = 0;
slaveConfig->clockHoldTime_ns          = 0;

After calling this function, override any settings to customize the configuration, prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the address0 member of the configuration structure with the desired slave address.

Parameters:

slaveConfig – [out] User provided configuration structure that is set to default values. Refer to lpi2c_slave_config_t.

void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)#

Initializes the LPI2C slave peripheral.

This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user provided configuration.

Parameters:

base – The LPI2C peripheral base address.
slaveConfig – User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults that you can override.
sourceClock_Hz – Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, data valid delay, and clock hold time.

void LPI2C_SlaveDeinit(LPI2C_Type *base)#

Deinitializes the LPI2C slave peripheral.

This function disables the LPI2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveReset(LPI2C_Type *base)#

Performs a software reset of the LPI2C slave peripheral.

Parameters:

base – The LPI2C peripheral base address.

static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)#

Enables or disables the LPI2C module as slave.

Parameters:

base – The LPI2C peripheral base address.
enable – Pass true to enable or false to disable the specified LPI2C as slave.

static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base)#

Gets the LPI2C slave status flags.

A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also

_lpi2c_slave_flags

Parameters:

base – The LPI2C peripheral base address.

Returns:

State of the status flags:

1: related status flag is set.
0: related status flag is not set.

static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask)#

Clears the LPI2C status flag state.

The following status register flags can be cleared:

kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag

Attempts to clear other flags has no effect.

See also

_lpi2c_slave_flags.

Parameters:

base – The LPI2C peripheral base address.
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _lpi2c_slave_flags enumerators OR’d together. You may pass the result of a previous call to LPI2C_SlaveGetStatusFlags().

static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask)#

Enables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to enable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask)#

Disables the LPI2C slave interrupt requests.

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Parameters:

base – The LPI2C peripheral base address.
interruptMask – Bit mask of interrupts to disable. See _lpi2c_slave_flags for the set of constants that should be OR’d together to form the bit mask.

static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)#

Returns the set of currently enabled LPI2C slave interrupt requests.

Parameters:

base – The LPI2C peripheral base address.

Returns:

A bitmask composed of _lpi2c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts.

static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx)#

Enables or disables the LPI2C slave peripheral DMA requests.

Parameters:

base – The LPI2C peripheral base address.
enableAddressValid – Enable flag for the address valid DMA request. Pass true for enable, false for disable. The address valid DMA request is shared with the receive data DMA request.
enableRx – Enable flag for the receive data DMA request. Pass true for enable, false for disable.
enableTx – Enable flag for the transmit data DMA request. Pass true for enable, false for disable.

static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base)#

Returns whether the bus is idle.

Requires the slave mode to be enabled.

Parameters:

base – The LPI2C peripheral base address.

Return values:

true – Bus is busy.
false – Bus is idle.

static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack)#

Transmits either an ACK or NAK on the I2C bus in response to a byte from the master.

Use this function to send an ACK or NAK when the kLPI2C_SlaveTransmitAckFlag is asserted. This only happens if you enable the sclStall.enableAck field of the lpi2c_slave_config_t configuration structure used to initialize the slave peripheral.

Parameters:

base – The LPI2C peripheral base address.
ackOrNack – Pass true for an ACK or false for a NAK.

static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable)#

Enables or disables ACKSTALL.

When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to a byte from the master.

Parameters:

base – The LPI2C peripheral base address.
enable – True will enable ACKSTALL,false will disable ACKSTALL.

static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base)#

Returns the slave address sent by the I2C master.

This function should only be called if the kLPI2C_SlaveAddressValidFlag is asserted.

Parameters:

base – The LPI2C peripheral base address.

Returns:

The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and the 7-bit slave address is in the upper 7 bits.

status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)#

Performs a polling send transfer on the I2C bus.

Parameters:

base – The LPI2C peripheral base address.
txBuff – The pointer to the data to be transferred.
txSize – The length in bytes of the data to be transferred.
actualTxSize – [out]

Returns:

Error or success status returned by API.

status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)#

Performs a polling receive transfer on the I2C bus.

Parameters:

base – The LPI2C peripheral base address.
rxBuff – The pointer to the data to be transferred.
rxSize – The length in bytes of the data to be transferred.
actualRxSize – [out]

Returns:

Error or success status returned by API.

void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, lpi2c_slave_handle_t *handle, lpi2c_slave_transfer_callback_t callback, void *userData)#

Creates a new handle for the LPI2C slave non-blocking APIs.

Note

Parameters:

base – The LPI2C peripheral base address.
handle – [out] Pointer to the LPI2C slave driver handle.
callback – User provided pointer to the asynchronous callback function.
userData – User provided pointer to the application callback data.

status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)#

Starts accepting slave transfers.

Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.

The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. The kLPI2C_SlaveTransmitEvent and kLPI2C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kLPI2C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
eventMask – Bit mask formed by OR’ing together lpi2c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kLPI2C_SlaveAllEvents to enable all events.

Return values:

kStatus_Success – Slave transfers were successfully started.
kStatus_LPI2C_Busy – Slave transfers have already been started on this handle.

status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)#

Gets the slave transfer status during a non-blocking transfer.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to i2c_slave_handle_t structure.
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required.

Return values:

kStatus_Success –
kStatus_NoTransferInProgress –

void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)#

Aborts the slave non-blocking transfers.

Note

This API could be called at any time to stop slave for handling the bus events.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)#

Reusable routine to handle slave interrupts.

Note

This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality.

Parameters:

base – The LPI2C peripheral base address.
handle – Pointer to lpi2c_slave_handle_t structure which stores the transfer state.

enum _lpi2c_slave_flags#

LPI2C slave peripheral flags.

The following status register flags can be cleared:

kLPI2C_SlaveRepeatedStartDetectFlag
kLPI2C_SlaveStopDetectFlag
kLPI2C_SlaveBitErrFlag
kLPI2C_SlaveFifoErrFlag

All flags except kLPI2C_SlaveBusyFlag and kLPI2C_SlaveBusBusyFlag can be enabled as interrupts.

Note

These enumerations are meant to be OR’d together to form a bit mask.

Values:

enumerator kLPI2C_SlaveTxReadyFlag#: Transmit data flag

enumerator kLPI2C_SlaveRxReadyFlag#: Receive data flag

enumerator kLPI2C_SlaveAddressValidFlag#: Address valid flag

enumerator kLPI2C_SlaveTransmitAckFlag#: Transmit ACK flag

enumerator kLPI2C_SlaveRepeatedStartDetectFlag#: Repeated start detect flag

enumerator kLPI2C_SlaveStopDetectFlag#: Stop detect flag

enumerator kLPI2C_SlaveBitErrFlag#: Bit error flag

enumerator kLPI2C_SlaveFifoErrFlag#: FIFO error flag

enumerator kLPI2C_SlaveAddressMatch0Flag#: Address match 0 flag

enumerator kLPI2C_SlaveAddressMatch1Flag#: Address match 1 flag

enumerator kLPI2C_SlaveGeneralCallFlag#: General call flag

enumerator kLPI2C_SlaveBusyFlag#: Master busy flag

enumerator kLPI2C_SlaveBusBusyFlag#: Bus busy flag

enumerator kLPI2C_SlaveClearFlags#: All flags which are cleared by the driver upon starting a transfer.

enumerator kLPI2C_SlaveIrqFlags#: IRQ sources enabled by the non-blocking transactional API.

enumerator kLPI2C_SlaveErrorFlags#: Errors to check for.

enum _lpi2c_slave_address_match#

LPI2C slave address match options.

Values:

enumerator kLPI2C_MatchAddress0#: Match only address 0.

enumerator kLPI2C_MatchAddress0OrAddress1#: Match either address 0 or address 1.

enumerator kLPI2C_MatchAddress0ThroughAddress1#: Match a range of slave addresses from address 0 through address 1.

enum _lpi2c_slave_transfer_event#

Set of events sent to the callback for non blocking slave transfers.

These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

Values:

enumerator kLPI2C_SlaveAddressMatchEvent#: Received the slave address after a start or repeated start.

enumerator kLPI2C_SlaveTransmitEvent#: Callback is requested to provide data to transmit (slave-transmitter role).

enumerator kLPI2C_SlaveReceiveEvent#: Callback is requested to provide a buffer in which to place received data (slave-receiver role).

enumerator kLPI2C_SlaveTransmitAckEvent#: Callback needs to either transmit an ACK or NACK.

enumerator kLPI2C_SlaveRepeatedStartEvent#: A repeated start was detected.

enumerator kLPI2C_SlaveCompletionEvent#: A stop was detected, completing the transfer.

enumerator kLPI2C_SlaveAllEvents#: Bit mask of all available events.

typedef enum _lpi2c_slave_address_match lpi2c_slave_address_match_t#: LPI2C slave address match options.

typedef struct _lpi2c_slave_config lpi2c_slave_config_t#

Structure with settings to initialize the LPI2C slave module.

This structure holds configuration settings for the LPI2C slave peripheral. To initialize this structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

typedef enum _lpi2c_slave_transfer_event lpi2c_slave_transfer_event_t#

Set of events sent to the callback for non blocking slave transfers.

Note

These enumerations are meant to be OR’d together to form a bit mask of events.

typedef struct _lpi2c_slave_transfer lpi2c_slave_transfer_t#: LPI2C slave transfer structure.

typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t#: LPI2C slave handle structure.

typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData)#

Slave event callback function pointer type.

This callback is used only for the slave non-blocking transfer API. To install a callback, use the LPI2C_SlaveSetCallback() function after you have created a handle.

Param base:: Base address for the LPI2C instance on which the event occurred.
Param transfer:: Pointer to transfer descriptor containing values passed to and/or from the callback.
Param userData:: Arbitrary pointer-sized value passed from the application.

struct _lpi2c_slave_config#

#include <fsl_lpi2c.h>

Structure with settings to initialize the LPI2C slave module.

The configuration structure can be made constant so it resides in flash.

Public Members

bool enableSlave#: Enable slave mode.

uint8_t address0#: Slave’s 7-bit address.

uint8_t address1#: Alternate slave 7-bit address.

lpi2c_slave_address_match_t addressMatchMode#: Address matching options.

bool filterDozeEnable#: Enable digital glitch filter in doze mode.

bool filterEnable#: Enable digital glitch filter.

bool enableGeneralCall#: Enable general call address matching.

struct _lpi2c_slave_config sclStall#: SCL stall enable options.

bool ignoreAck#: Continue transfers after a NACK is detected.

bool enableReceivedAddressRead#: Enable reading the address received address as the first byte of data.

uint32_t sdaGlitchFilterWidth_ns#: Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to disable.

uint32_t sclGlitchFilterWidth_ns#: Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to disable.

uint32_t dataValidDelay_ns#: Width in nanoseconds of the data valid delay.

uint32_t clockHoldTime_ns#: Width in nanoseconds of the clock hold time.

struct _lpi2c_slave_transfer#

#include <fsl_lpi2c.h>

LPI2C slave transfer structure.

Public Members

lpi2c_slave_transfer_event_t event#: Reason the callback is being invoked.

uint8_t receivedAddress#: Matching address send by master.

uint8_t *data#: Transfer buffer

size_t dataSize#: Transfer size

status_t completionStatus#: Success or error code describing how the transfer completed. Only applies for kLPI2C_SlaveCompletionEvent.

size_t transferredCount#: Number of bytes actually transferred since start or last repeated start.

struct _lpi2c_slave_handle#

#include <fsl_lpi2c.h>

LPI2C slave handle structure.

Note

The contents of this structure are private and subject to change.

Public Members

lpi2c_slave_transfer_t transfer#: LPI2C slave transfer copy.

bool isBusy#: Whether transfer is busy.

bool wasTransmit#: Whether the last transfer was a transmit.

uint32_t eventMask#: Mask of enabled events.

uint32_t transferredCount#: Count of bytes transferred.

lpi2c_slave_transfer_callback_t callback#: Callback function called at transfer event.

void *userData#: Callback parameter passed to callback.

struct sclStall

Public Members

bool enableAck#: Enables SCL clock stretching during slave-transmit address byte(s) and slave-receiver address and data byte(s) to allow software to write the Transmit ACK Register before the ACK or NACK is transmitted. Clock stretching occurs when transmitting the 9th bit. When enableAckSCLStall is enabled, there is no need to set either enableRxDataSCLStall or enableAddressSCLStall.

bool enableTx#: Enables SCL clock stretching when the transmit data flag is set during a slave-transmit transfer.

bool enableRx#: Enables SCL clock stretching when receive data flag is set during a slave-receive transfer.

bool enableAddress#: Enables SCL clock stretching when the address valid flag is asserted.

LPSPI: Low Power Serial Peripheral Interface#

LPSPI Peripheral driver#

void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)#

Initializes the LPSPI master.

Parameters:

base – LPSPI peripheral address.
masterConfig – Pointer to structure lpspi_master_config_t.
srcClock_Hz – Module source input clock in Hertz

void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)#

Sets the lpspi_master_config_t structure to default values.

This API initializes the configuration structure for LPSPI_MasterInit(). The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified before calling the LPSPI_MasterInit(). Example:

lpspi_master_config_t  masterConfig;
LPSPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

masterConfig – pointer to lpspi_master_config_t structure

void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)#

LPSPI slave configuration.

Parameters:

base – LPSPI peripheral address.
slaveConfig – Pointer to a structure lpspi_slave_config_t.

void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig)#

Sets the lpspi_slave_config_t structure to default values.

This API initializes the configuration structure for LPSPI_SlaveInit(). The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified before calling the LPSPI_SlaveInit(). Example:

lpspi_slave_config_t  slaveConfig;
LPSPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

slaveConfig – pointer to lpspi_slave_config_t structure.

void LPSPI_Deinit(LPSPI_Type *base)#

De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.

Parameters:

base – LPSPI peripheral address.

void LPSPI_Reset(LPSPI_Type *base)#

Restores the LPSPI peripheral to reset state. Note that this function sets all registers to reset state. As a result, the LPSPI module can’t work after calling this API.

Parameters:

base – LPSPI peripheral address.

uint32_t LPSPI_GetInstance(LPSPI_Type *base)#

Get the LPSPI instance from peripheral base address.

Parameters:

base – LPSPI peripheral base address.

Returns:

LPSPI instance.

static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)#

Enables the LPSPI peripheral and sets the MCR MDIS to 0.

Parameters:

base – LPSPI peripheral address.
enable – Pass true to enable module, false to disable module.

static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)#

Gets the LPSPI status flag state.

Parameters:

base – LPSPI peripheral address.

Returns:

The LPSPI status(in SR register).

static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)#

Gets the LPSPI Tx FIFO size.

Parameters:

base – LPSPI peripheral address.

Returns:

The LPSPI Tx FIFO size.

static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)#

Gets the LPSPI Rx FIFO size.

Parameters:

base – LPSPI peripheral address.

Returns:

The LPSPI Rx FIFO size.

static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)#

Gets the LPSPI Tx FIFO count.

Parameters:

base – LPSPI peripheral address.

Returns:

The number of words in the transmit FIFO.

static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)#

Gets the LPSPI Rx FIFO count.

Parameters:

base – LPSPI peripheral address.

Returns:

The number of words in the receive FIFO.

static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)#

Clears the LPSPI status flag.

This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. Example usage:

LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);

Parameters:

base – LPSPI peripheral address.
statusFlags – The status flag used from type _lpspi_flags.

static inline uint32_t LPSPI_GetTcr(LPSPI_Type *base)#

static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)#

Enables the LPSPI interrupts.

This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.

LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)#

Disables the LPSPI interrupts.

LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );

Parameters:

base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_interrupt_enable.

static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)#

Enables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)#

Disables the LPSPI DMA request.

This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.

SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);

Parameters:

base – LPSPI peripheral address.
mask – The interrupt mask; Use the enum _lpspi_dma_enable.

static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)#

Gets the LPSPI Transmit Data Register address for a DMA operation.

This function gets the LPSPI Transmit Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address.

Returns:

The LPSPI Transmit Data Register address.

static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)#

Gets the LPSPI Receive Data Register address for a DMA operation.

This function gets the LPSPI Receive Data Register address because this value is needed for the DMA operation. This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address.

Returns:

The LPSPI Receive Data Register address.

bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma)#

Check the argument for transfer .

Parameters:

base – LPSPI peripheral address.
transfer – the transfer struct to be used.
isEdma – True to check for EDMA transfer, false to check interrupt non-blocking transfer

Returns:

Return true for right and false for wrong.

static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)#

Configures the LPSPI for either master or slave.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

Parameters:

base – LPSPI peripheral address.
mode – Mode setting (master or slave) of type lpspi_master_slave_mode_t.

static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)#

Configures the peripheral chip select used for the transfer.

Parameters:

base – LPSPI peripheral address.
select – LPSPI Peripheral Chip Select (PCS) configuration.

static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)#

Set the PCS signal to continuous or uncontinuous mode.

Note

In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after that the LPSPI will transmit received data back (assuming a 32-bit shift register).

Parameters:

base – LPSPI peripheral address.
IsContinous – True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.

static inline bool LPSPI_IsMaster(LPSPI_Type *base)#

Returns whether the LPSPI module is in master mode.

Parameters:

base – LPSPI peripheral address.

Returns:

Returns true if the module is in master mode or false if the module is in slave mode.

static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)#

Flushes the LPSPI FIFOs.

Parameters:

base – LPSPI peripheral address.
flushTxFifo – Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
flushRxFifo – Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.

static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)#

Sets the transmit and receive FIFO watermark values.

This function allows the user to set the receive and transmit FIFO watermarks. The function does not compare the watermark settings to the FIFO size. The FIFO watermark should not be equal to or greater than the FIFO size. It is up to the higher level driver to make this check.

Parameters:

base – LPSPI peripheral address.
txWater – The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
rxWater – The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.

static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)#

Configures all LPSPI peripheral chip select polarities simultaneously.

Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).

This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of PCS is device-specific.

LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);

Parameters:

base – LPSPI peripheral address.
mask – The PCS polarity mask; Use the enum _lpspi_pcs_polarity.

static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)#

Configures the frame size.

The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.

Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command register should only be changed if the LPSPI is idle.

Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That means the TCR register should be written to when the Tx FIFO is not full.

Parameters:

base – LPSPI peripheral address.
frameSize – The frame size in number of bits.

uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue)#

Sets the LPSPI baud rate in bits per second.

This function takes in the desired bitsPerSec (baud rate) and calculates the nearest possible baud rate without exceeding the desired baud rate and returns the calculated baud rate in bits-per-second. It requires the caller to provide the frequency of the module source clock (in Hertz). Note that the baud rate does not go into effect until the Transmit Control Register (TCR) is programmed with the prescale value. Hence, this function returns the prescale tcrPrescaleValue parameter for later programming in the TCR. The higher level peripheral driver should alert the user of an out of range baud rate input.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address.
baudRate_Bps – The desired baud rate in bits per second.
srcClock_Hz – Module source input clock in Hertz.
tcrPrescaleValue – The TCR prescale value needed to program the TCR.

Returns:

The actual calculated baud rate. This function may also return a “0” if the LPSPI is not configured for master mode or if the LPSPI module is not disabled.

void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay)#

Manually configures a specific LPSPI delay parameter (module must be disabled to change the delay values).

This function configures the following: SCK to PCS delay, or PCS to SCK delay, or The configurations must occur between the transfer delay.

The delay names are available in type lpspi_delay_type_t.

The user passes the desired delay along with the delay value. This allows the user to directly set the delay values if they have pre-calculated them or if they simply wish to manually increment the value.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address.
scaler – The 8-bit delay value 0x00 to 0xFF (255).
whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.

uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, uint32_t delayTimeInNanoSec, lpspi_delay_type_t whichDelay, uint32_t srcClock_Hz)#

Calculates the delay based on the desired delay input in nanoseconds (module must be disabled to change the delay values).

This function configures the SCK to PCS delay, PCS to SCK delay, or the delay between transfers. The delay names are available in type lpspi_delay_type_t.

The function calculates the value needed for the desired delay parameter and returns the actual calculated delay. An exact delay match may not be possible, in which case the closest match is calculated without going below the desired delay value. If the input exceeds the maximum capability, the maximum supported delay is returned.

Note that the LPSPI module must first be disabled before configuring this. Note that the LPSPI module must be configured for master mode before configuring this.

Parameters:

base – LPSPI peripheral address.
delayTimeInNanoSec – The desired delay value in nanoseconds.
whichDelay – The desired delay to configure, must be of type lpspi_delay_type_t.
srcClock_Hz – Module source input clock in Hertz.

Returns:

Actual calculated delay value in nanoseconds.

static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)#

Writes data into the transmit data buffer.

This function writes data passed in by the user to the Transmit Data Register (TDR). The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, the user has to manage sending the data one 32-bit word at a time. Any writes to the TDR result in an immediate push to the transmit FIFO. This function can be used for either master or slave modes.

Parameters:

base – LPSPI peripheral address.
data – The data word to be sent.

static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)#

Reads data from the data buffer.

This function reads the data from the Receive Data Register (RDR). This function can be used for either master or slave mode.

Parameters:

base – LPSPI peripheral address.

Returns:

The data read from the data buffer.

void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)#

Set up the dummy data.

Parameters:

base – LPSPI peripheral address.
dummyData – Data to be transferred when tx buffer is NULL. Note: This API has no effect when LPSPI in slave interrupt mode, because driver will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit FIFO and output pin is tristated.

void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_master_transfer_callback_t callback, void *userData)#

Initializes the LPSPI master handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

base – LPSPI peripheral address.
handle – LPSPI handle pointer to lpspi_master_handle_t.
callback – DSPI callback.
userData – callback function parameter.

status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer)#

LPSPI master transfer data using a polling method.

This function transfers data using a polling method. This is a blocking function, which does not return until all transfers have been completed.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address.
transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer)#

LPSPI master transfer data using an interrupt method.

This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count)#

Gets the master transfer remaining bytes.

This function gets the master transfer remaining bytes.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle)#

LPSPI master abort transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle)#

LPSPI Master IRQ handler function.

This function processes the LPSPI transmit and receive IRQ.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_master_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_slave_transfer_callback_t callback, void *userData)#

Initializes the LPSPI slave handle.

This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Parameters:

base – LPSPI peripheral address.
handle – LPSPI handle pointer to lpspi_slave_handle_t.
callback – DSPI callback.
userData – callback function parameter.

status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer)#

LPSPI slave transfer data using an interrupt method.

This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count)#

Gets the slave transfer remaining bytes.

This function gets the slave transfer remaining bytes.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)#

LPSPI slave aborts a transfer which uses an interrupt method.

This function aborts a transfer which uses an interrupt method.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle)#

LPSPI Slave IRQ handler function.

This function processes the LPSPI transmit and receives an IRQ.

Parameters:

base – LPSPI peripheral address.
handle – pointer to lpspi_slave_handle_t structure which stores the transfer state.

bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base)#

Wait for tx FIFO to be empty.

This function wait the tx fifo empty

Parameters:

base – LPSPI peripheral address.

Returns:

true for the tx FIFO is ready, false is not.

void LPSPI_DriverIRQHandler(uint32_t instance)#

LPSPI driver IRQ handler common entry.

This function provides the common IRQ request entry for LPSPI.

Parameters:

instance – LPSPI instance.

FSL_LPSPI_DRIVER_VERSION#: LPSPI driver version.

Status for the LPSPI driver.

Values:

enumerator kStatus_LPSPI_Busy#: LPSPI transfer is busy.

enumerator kStatus_LPSPI_Error#: LPSPI driver error.

enumerator kStatus_LPSPI_Idle#: LPSPI is idle.

enumerator kStatus_LPSPI_OutOfRange#: LPSPI transfer out Of range.

enumerator kStatus_LPSPI_Timeout#: LPSPI timeout polling status flags.

enum _lpspi_flags#

LPSPI status flags in SPIx_SR register.

Values:

enumerator kLPSPI_TxDataRequestFlag#: Transmit data flag

enumerator kLPSPI_RxDataReadyFlag#: Receive data flag

enumerator kLPSPI_WordCompleteFlag#: Word Complete flag

enumerator kLPSPI_FrameCompleteFlag#: Frame Complete flag

enumerator kLPSPI_TransferCompleteFlag#: Transfer Complete flag

enumerator kLPSPI_TransmitErrorFlag#: Transmit Error flag (FIFO underrun)

enumerator kLPSPI_ReceiveErrorFlag#: Receive Error flag (FIFO overrun)

enumerator kLPSPI_DataMatchFlag#: Data Match flag

enumerator kLPSPI_ModuleBusyFlag#: Module Busy flag

enumerator kLPSPI_AllStatusFlag#: Used for clearing all w1c status flags

enum _lpspi_interrupt_enable#

LPSPI interrupt source.

Values:

enumerator kLPSPI_TxInterruptEnable#: Transmit data interrupt enable

enumerator kLPSPI_RxInterruptEnable#: Receive data interrupt enable

enumerator kLPSPI_WordCompleteInterruptEnable#: Word complete interrupt enable

enumerator kLPSPI_FrameCompleteInterruptEnable#: Frame complete interrupt enable

enumerator kLPSPI_TransferCompleteInterruptEnable#: Transfer complete interrupt enable

enumerator kLPSPI_TransmitErrorInterruptEnable#: Transmit error interrupt enable(FIFO underrun)

enumerator kLPSPI_ReceiveErrorInterruptEnable#: Receive Error interrupt enable (FIFO overrun)

enumerator kLPSPI_DataMatchInterruptEnable#: Data Match interrupt enable

enumerator kLPSPI_AllInterruptEnable#: All above interrupts enable.

enum _lpspi_dma_enable#

LPSPI DMA source.

Values:

enumerator kLPSPI_TxDmaEnable#: Transmit data DMA enable

enumerator kLPSPI_RxDmaEnable#: Receive data DMA enable

enum _lpspi_master_slave_mode#

LPSPI master or slave mode configuration.

Values:

enumerator kLPSPI_Master#: LPSPI peripheral operates in master mode.

enumerator kLPSPI_Slave#: LPSPI peripheral operates in slave mode.

enum _lpspi_which_pcs_config#

LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

Values:

enumerator kLPSPI_Pcs0#: PCS[0]

enumerator kLPSPI_Pcs1#: PCS[1]

enumerator kLPSPI_Pcs2#: PCS[2]

enumerator kLPSPI_Pcs3#: PCS[3]

enum _lpspi_pcs_polarity_config#

LPSPI Peripheral Chip Select (PCS) Polarity configuration.

Values:

enumerator kLPSPI_PcsActiveHigh#: PCS Active High (idles low)

enumerator kLPSPI_PcsActiveLow#: PCS Active Low (idles high)

enum _lpspi_pcs_polarity#

LPSPI Peripheral Chip Select (PCS) Polarity.

Values:

enumerator kLPSPI_Pcs0ActiveLow#: Pcs0 Active Low (idles high).

enumerator kLPSPI_Pcs1ActiveLow#: Pcs1 Active Low (idles high).

enumerator kLPSPI_Pcs2ActiveLow#: Pcs2 Active Low (idles high).

enumerator kLPSPI_Pcs3ActiveLow#: Pcs3 Active Low (idles high).

enumerator kLPSPI_PcsAllActiveLow#: Pcs0 to Pcs5 Active Low (idles high).

enum _lpspi_clock_polarity#

LPSPI clock polarity configuration.

Values:

enumerator kLPSPI_ClockPolarityActiveHigh#: CPOL=0. Active-high LPSPI clock (idles low)

enumerator kLPSPI_ClockPolarityActiveLow#: CPOL=1. Active-low LPSPI clock (idles high)

enum _lpspi_clock_phase#

LPSPI clock phase configuration.

Values:

enumerator kLPSPI_ClockPhaseFirstEdge#: CPHA=0. Data is captured on the leading edge of the SCK and changed on the following edge.

enumerator kLPSPI_ClockPhaseSecondEdge#: CPHA=1. Data is changed on the leading edge of the SCK and captured on the following edge.

enum _lpspi_shift_direction#

LPSPI data shifter direction options.

Values:

enumerator kLPSPI_MsbFirst#: Data transfers start with most significant bit.

enumerator kLPSPI_LsbFirst#: Data transfers start with least significant bit.

enum _lpspi_host_request_select#

LPSPI Host Request select configuration.

Values:

enumerator kLPSPI_HostReqExtPin#: Host Request is an ext pin.

enumerator kLPSPI_HostReqInternalTrigger#: Host Request is an internal trigger.

enum _lpspi_match_config#

LPSPI Match configuration options.

Values:

enumerator kLPSI_MatchDisabled#: LPSPI Match Disabled.

enumerator kLPSI_1stWordEqualsM0orM1#: LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0orM1#: LPSPI Match Enabled.

enumerator kLPSI_1stWordEqualsM0and2ndWordEqualsM1#: LPSPI Match Enabled.

enumerator kLPSI_AnyWordEqualsM0andNxtWordEqualsM1#: LPSPI Match Enabled.

enumerator kLPSI_1stWordAndM1EqualsM0andM1#: LPSPI Match Enabled.

enumerator kLPSI_AnyWordAndM1EqualsM0andM1#: LPSPI Match Enabled.

enum _lpspi_pin_config#

LPSPI pin (SDO and SDI) configuration.

Values:

enumerator kLPSPI_SdiInSdoOut#: LPSPI SDI input, SDO output.

enumerator kLPSPI_SdiInSdiOut#: LPSPI SDI input, SDI output.

enumerator kLPSPI_SdoInSdoOut#: LPSPI SDO input, SDO output.

enumerator kLPSPI_SdoInSdiOut#: LPSPI SDO input, SDI output.

enum _lpspi_data_out_config#

LPSPI data output configuration.

Values:

enumerator kLpspiDataOutRetained#: Data out retains last value when chip select is de-asserted

enumerator kLpspiDataOutTristate#: Data out is tristated when chip select is de-asserted

enum _lpspi_transfer_width#

LPSPI transfer width configuration.

Values:

enumerator kLPSPI_SingleBitXfer#: 1-bit shift at a time, data out on SDO, in on SDI (normal mode)

enumerator kLPSPI_TwoBitXfer#: 2-bits shift out on SDO/SDI and in on SDO/SDI

enumerator kLPSPI_FourBitXfer#: 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2]

enum _lpspi_delay_type#

LPSPI delay type selection.

Values:

enumerator kLPSPI_PcsToSck#: PCS-to-SCK delay.

enumerator kLPSPI_LastSckToPcs#: Last SCK edge to PCS delay.

enumerator kLPSPI_BetweenTransfer#: Delay between transfers.

enum _lpspi_transfer_config_flag_for_master#

Use this enumeration for LPSPI master transfer configFlags.

Values:

enumerator kLPSPI_MasterPcs0#: LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS0 signal

enumerator kLPSPI_MasterPcs1#: LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS1 signal

enumerator kLPSPI_MasterPcs2#: LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS2 signal

enumerator kLPSPI_MasterPcs3#: LPSPI master PCS shift macro , internal used. LPSPI master transfer use PCS3 signal

enumerator kLPSPI_MasterPcsContinuous#: Is PCS signal continuous

enumerator kLPSPI_MasterByteSwap#

Is master swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.

enum _lpspi_transfer_config_flag_for_slave#

Use this enumeration for LPSPI slave transfer configFlags.

Values:

enumerator kLPSPI_SlavePcs0#: LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS0 signal

enumerator kLPSPI_SlavePcs1#: LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS1 signal

enumerator kLPSPI_SlavePcs2#: LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS2 signal

enumerator kLPSPI_SlavePcs3#: LPSPI slave PCS shift macro , internal used. LPSPI slave transfer use PCS3 signal

enumerator kLPSPI_SlaveByteSwap#

Is slave swap the byte. For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set lpspi_shift_direction_t to MSB).

If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used or not, the waveform is 1 2 3 4 5 6 7 8.
If you set bitPerFrame = 16 : (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
If you set bitPerFrame = 32 : (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.

enum _lpspi_transfer_state#

LPSPI transfer state, which is used for LPSPI transactional API state machine.

Values:

enumerator kLPSPI_Idle#: Nothing in the transmitter/receiver.

enumerator kLPSPI_Busy#: Transfer queue is not finished.

enumerator kLPSPI_Error#: Transfer error.

typedef enum _lpspi_master_slave_mode lpspi_master_slave_mode_t#: LPSPI master or slave mode configuration.

typedef enum _lpspi_which_pcs_config lpspi_which_pcs_t#: LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).

typedef enum _lpspi_pcs_polarity_config lpspi_pcs_polarity_config_t#: LPSPI Peripheral Chip Select (PCS) Polarity configuration.

typedef enum _lpspi_clock_polarity lpspi_clock_polarity_t#: LPSPI clock polarity configuration.

typedef enum _lpspi_clock_phase lpspi_clock_phase_t#: LPSPI clock phase configuration.

typedef enum _lpspi_shift_direction lpspi_shift_direction_t#: LPSPI data shifter direction options.

typedef enum _lpspi_host_request_select lpspi_host_request_select_t#: LPSPI Host Request select configuration.

typedef enum _lpspi_match_config lpspi_match_config_t#: LPSPI Match configuration options.

typedef enum _lpspi_pin_config lpspi_pin_config_t#: LPSPI pin (SDO and SDI) configuration.

typedef enum _lpspi_data_out_config lpspi_data_out_config_t#: LPSPI data output configuration.

typedef enum _lpspi_transfer_width lpspi_transfer_width_t#: LPSPI transfer width configuration.

typedef enum _lpspi_delay_type lpspi_delay_type_t#: LPSPI delay type selection.

typedef struct _lpspi_master_config lpspi_master_config_t#: LPSPI master configuration structure.

typedef struct _lpspi_slave_config lpspi_slave_config_t#: LPSPI slave configuration structure.

typedef struct _lpspi_master_handle lpspi_master_handle_t#: Forward declaration of the _lpspi_master_handle typedefs.

typedef struct _lpspi_slave_handle lpspi_slave_handle_t#: Forward declaration of the _lpspi_slave_handle typedefs.

typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)#

Master completion callback function pointer type.

Param base:: LPSPI peripheral address.
Param handle:: Pointer to the handle for the LPSPI master.
Param status:: Success or error code describing whether the transfer is completed.
Param userData:: Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle, status_t status, void *userData)#

Slave completion callback function pointer type.

Param base:: LPSPI peripheral address.
Param handle:: Pointer to the handle for the LPSPI slave.
Param status:: Success or error code describing whether the transfer is completed.
Param userData:: Arbitrary pointer-dataSized value passed from the application.

typedef struct _lpspi_transfer lpspi_transfer_t#: LPSPI master/slave transfer structure.

volatile uint8_t g_lpspiDummyData[]#: Global variable for dummy data value setting.

LPSPI_DUMMY_DATA#

LPSPI dummy data if no Tx data.

Dummy data used for tx if there is not txData.

SPI_RETRY_TIMES#: Retry times for waiting flag.

LPSPI_MASTER_PCS_SHIFT#: LPSPI master PCS shift macro , internal used.

LPSPI_MASTER_PCS_MASK#: LPSPI master PCS shift macro , internal used.

LPSPI_SLAVE_PCS_SHIFT#: LPSPI slave PCS shift macro , internal used.

LPSPI_SLAVE_PCS_MASK#: LPSPI slave PCS shift macro , internal used.

struct _lpspi_master_config#

#include <fsl_lpspi.h>

LPSPI master configuration structure.

Public Members

uint32_t baudRate#: Baud Rate for LPSPI.

uint32_t bitsPerFrame#: Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol#: Clock polarity.

lpspi_clock_phase_t cpha#: Clock phase.

lpspi_shift_direction_t direction#: MSB or LSB data shift direction.

uint32_t pcsToSckDelayInNanoSec#: PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t lastSckToPcsDelayInNanoSec#: Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

uint32_t betweenTransferDelayInNanoSec#: After the SCK delay time with nanoseconds, setting to 0 sets the minimum delay. It sets the boundary value if out of range.

lpspi_which_pcs_t whichPcs#: Desired Peripheral Chip Select (PCS).

lpspi_pcs_polarity_config_t pcsActiveHighOrLow#: Desired PCS active high or low

lpspi_pin_config_t pinCfg#: Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig#: Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

bool enableInputDelay#: Enable master to sample the input data on a delayed SCK. This can help improve slave setup time. Refer to device data sheet for specific time length.

struct _lpspi_slave_config#

#include <fsl_lpspi.h>

LPSPI slave configuration structure.

Public Members

uint32_t bitsPerFrame#: Bits per frame, minimum 8, maximum 4096.

lpspi_clock_polarity_t cpol#: Clock polarity.

lpspi_clock_phase_t cpha#: Clock phase.

lpspi_shift_direction_t direction#: MSB or LSB data shift direction.

lpspi_which_pcs_t whichPcs#: Desired Peripheral Chip Select (pcs)

lpspi_pcs_polarity_config_t pcsActiveHighOrLow#: Desired PCS active high or low

lpspi_pin_config_t pinCfg#: Configures which pins are used for input and output data during single bit transfers.

lpspi_data_out_config_t dataOutConfig#: Configures if the output data is tristated between accesses (LPSPI_PCS is negated).

struct _lpspi_transfer#

#include <fsl_lpspi.h>

LPSPI master/slave transfer structure.

Public Members

const uint8_t *txData#: Send buffer.

uint8_t *rxData#: Receive buffer.

volatile size_t dataSize#: Transfer bytes.

uint32_t configFlags#: Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave.

struct _lpspi_master_handle#

#include <fsl_lpspi.h>

LPSPI master transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous#: Is PCS continuous in transfer.

volatile bool writeTcrInIsr#: A flag that whether should write TCR in ISR.

volatile bool isByteSwap#: A flag that whether should byte swap.

volatile bool isTxMask#: A flag that whether TCR[TXMSK] is set.

volatile uint16_t bytesPerFrame#: Number of bytes in each frame

volatile uint16_t frameSize#: Backup of TCR[FRAMESZ]

volatile uint8_t fifoSize#: FIFO dataSize.

volatile uint8_t rxWatermark#: Rx watermark.

volatile uint8_t bytesEachWrite#: Bytes for each write TDR.

volatile uint8_t bytesEachRead#: Bytes for each read RDR.

const uint8_t *volatile txData#: Send buffer.

uint8_t *volatile rxData#: Receive buffer.

volatile size_t txRemainingByteCount#: Number of bytes remaining to send.

volatile size_t rxRemainingByteCount#: Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes#: Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes#: Read RDR register remaining times.

uint32_t totalByteCount#: Number of transfer bytes

uint32_t txBuffIfNull#: Used if the txData is NULL.

volatile uint8_t state#: LPSPI transfer state , _lpspi_transfer_state.

lpspi_master_transfer_callback_t callback#: Completion callback.

void *userData#: Callback user data.

struct _lpspi_slave_handle#

#include <fsl_lpspi.h>

LPSPI slave transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap#: A flag that whether should byte swap.

volatile uint8_t fifoSize#: FIFO dataSize.

volatile uint8_t rxWatermark#: Rx watermark.

volatile uint8_t bytesEachWrite#: Bytes for each write TDR.

volatile uint8_t bytesEachRead#: Bytes for each read RDR.

const uint8_t *volatile txData#: Send buffer.

uint8_t *volatile rxData#: Receive buffer.

volatile size_t txRemainingByteCount#: Number of bytes remaining to send.

volatile size_t rxRemainingByteCount#: Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes#: Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes#: Read RDR register remaining times.

uint32_t totalByteCount#: Number of transfer bytes

volatile uint8_t state#: LPSPI transfer state , _lpspi_transfer_state.

volatile uint32_t errorCount#: Error count for slave transfer.

lpspi_slave_transfer_callback_t callback#: Completion callback.

void *userData#: Callback user data.

LPSPI eDMA Driver#

FSL_LPSPI_EDMA_DRIVER_VERSION#: LPSPI EDMA driver version.

DMA_MAX_TRANSFER_COUNT#: DMA max transfer size.

typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t#: Forward declaration of the _lpspi_master_edma_handle typedefs.

typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t#: Forward declaration of the _lpspi_slave_edma_handle typedefs.

typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)#

Completion callback function pointer type.

Param base:: LPSPI peripheral base address.
Param handle:: Pointer to the handle for the LPSPI master.
Param status:: Success or error code describing whether the transfer completed.
Param userData:: Arbitrary pointer-dataSized value passed from the application.

typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, status_t status, void *userData)#

Completion callback function pointer type.

Param base:: LPSPI peripheral base address.
Param handle:: Pointer to the handle for the LPSPI slave.
Param status:: Success or error code describing whether the transfer completed.
Param userData:: Arbitrary pointer-dataSized value passed from the application.

void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)#

Initializes the LPSPI master eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA request source. (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.

Parameters:

base – LPSPI peripheral base address.
handle – LPSPI handle pointer to lpspi_master_edma_handle_t.
callback – LPSPI callback.
userData – callback function parameter.
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)#

LPSPI master transfer data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)#

LPSPI master config transfer parameter while using eDMA.

This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
configFlags – transfer configuration flags. _lpspi_transfer_config_flag_for_master.

Return values:

kStatus_Success – Execution successfully.
kStatus_LPSPI_Busy – The LPSPI device is busy.

Returns:

Indicates whether LPSPI master transfer was successful or not.

status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)#

LPSPI master transfer data using eDMA without configs.

This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data is transferred, the callback function is called.

Note: This API is only for transfer through DMA without configuration. Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. For bytesPerFrame greater than 4: The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure, config field is not uesed.

Return values:

kStatus_Success – Execution successfully.
kStatus_LPSPI_Busy – The LPSPI device is busy.
kStatus_InvalidArgument – The transfer structure is invalid.

Returns:

Indicates whether LPSPI master transfer was successful or not.

void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle)#

LPSPI master aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.

status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count)#

Gets the master eDMA transfer remaining bytes.

This function gets the master eDMA transfer remaining bytes.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the EDMA transaction.

Returns:

status of status_t.

void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *edmaRxRegToRxDataHandle, edma_handle_t *edmaTxDataToTxRegHandle)#

Initializes the LPSPI slave eDMA handle.

This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a specified LPSPI instance, call this API once to get the initialized handle.

Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request source.

(1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and Tx DMAMUX source for edmaTxDataToTxRegHandle. (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle .

Parameters:

base – LPSPI peripheral base address.
handle – LPSPI handle pointer to lpspi_slave_edma_handle_t.
callback – LPSPI callback.
userData – callback function parameter.
edmaRxRegToRxDataHandle – edmaRxRegToRxDataHandle pointer to edma_handle_t.
edmaTxDataToTxRegHandle – edmaTxDataToTxRegHandle pointer to edma_handle_t.

status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer)#

LPSPI slave transfers data using eDMA.

This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data is transferred, the callback function is called.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
transfer – pointer to lpspi_transfer_t structure.

Returns:

status of status_t.

void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle)#

LPSPI slave aborts a transfer which is using eDMA.

This function aborts a transfer which is using eDMA.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.

status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count)#

Gets the slave eDMA transfer remaining bytes.

This function gets the slave eDMA transfer remaining bytes.

Parameters:

base – LPSPI peripheral base address.
handle – pointer to lpspi_slave_edma_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the eDMA transaction.

Returns:

status of status_t.

struct _lpspi_master_edma_handle#

#include <fsl_lpspi_edma.h>

LPSPI master eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isPcsContinuous#: Is PCS continuous in transfer.

volatile bool isByteSwap#: A flag that whether should byte swap.

volatile uint8_t fifoSize#: FIFO dataSize.

volatile uint8_t rxWatermark#: Rx watermark.

volatile uint8_t bytesEachWrite#: Bytes for each write TDR.

volatile uint8_t bytesEachRead#: Bytes for each read RDR.

volatile uint8_t bytesLastRead#: Bytes for last read RDR.

volatile bool isThereExtraRxBytes#: Is there extra RX byte.

const uint8_t *volatile txData#: Send buffer.

uint8_t *volatile rxData#: Receive buffer.

volatile size_t txRemainingByteCount#: Number of bytes remaining to send.

volatile size_t rxRemainingByteCount#: Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes#: Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes#: Read RDR register remaining times.

uint32_t totalByteCount#: Number of transfer bytes

edma_tcd_t *lastTimeTCD#: Pointer to the lastTime TCD

bool isMultiDMATransmit#: Is there multi DMA transmit

volatile uint8_t dmaTransmitTime#: DMA Transfer times.

uint32_t lastTimeDataBytes#: DMA transmit last Time data Bytes

uint32_t dataBytesEveryTime#: Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT

edma_transfer_config_t transferConfigRx#: Config of DMA rx channel.

edma_transfer_config_t transferConfigTx#: Config of DMA tx channel.

uint32_t txBuffIfNull#: Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull#: Used if there is not rxData for DMA purpose.

uint32_t transmitCommand#: Used to write TCR for DMA purpose.

volatile uint8_t state#: LPSPI transfer state , _lpspi_transfer_state.

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

lpspi_master_edma_transfer_callback_t callback#: Completion callback.

void *userData#: Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle#: edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle#: edma_handle_t handle point used for TxData to TxReg buff

edma_tcd_t lpspiSoftwareTCD[3]#: SoftwareTCD, internal used

struct _lpspi_slave_edma_handle#

#include <fsl_lpspi_edma.h>

LPSPI slave eDMA transfer handle structure used for transactional API.

Public Members

volatile bool isByteSwap#: A flag that whether should byte swap.

volatile uint8_t fifoSize#: FIFO dataSize.

volatile uint8_t rxWatermark#: Rx watermark.

volatile uint8_t bytesEachWrite#: Bytes for each write TDR.

volatile uint8_t bytesEachRead#: Bytes for each read RDR.

volatile uint8_t bytesLastRead#: Bytes for last read RDR.

volatile bool isThereExtraRxBytes#: Is there extra RX byte.

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

const uint8_t *volatile txData#: Send buffer.

uint8_t *volatile rxData#: Receive buffer.

volatile size_t txRemainingByteCount#: Number of bytes remaining to send.

volatile size_t rxRemainingByteCount#: Number of bytes remaining to receive.

volatile uint32_t writeRegRemainingTimes#: Write TDR register remaining times.

volatile uint32_t readRegRemainingTimes#: Read RDR register remaining times.

uint32_t totalByteCount#: Number of transfer bytes

uint32_t txBuffIfNull#: Used if there is not txData for DMA purpose.

uint32_t rxBuffIfNull#: Used if there is not rxData for DMA purpose.

volatile uint8_t state#: LPSPI transfer state.

uint32_t errorCount#: Error count for slave transfer.

lpspi_slave_edma_transfer_callback_t callback#: Completion callback.

void *userData#: Callback user data.

edma_handle_t *edmaRxRegToRxDataHandle#: edma_handle_t handle point used for RxReg to RxData buff

edma_handle_t *edmaTxDataToTxRegHandle#: edma_handle_t handle point used for TxData to TxReg

edma_tcd_t lpspiSoftwareTCD[2]#: SoftwareTCD, internal used

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver#

LPUART Driver#

static inline void LPUART_SoftwareReset(LPUART_Type *base)#

Resets the LPUART using software.

This function resets all internal logic and registers except the Global Register. Remains set until cleared by software.

Parameters:

base – LPUART peripheral base address.

status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)#

Initializes an LPUART instance with the user configuration structure and the peripheral clock.

This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function to configure the configuration structure and get the default configuration. The example below shows how to use this API to configure the LPUART.

lpuart_config_t lpuartConfig;
lpuartConfig.baudRate_Bps = 115200U;
lpuartConfig.parityMode = kLPUART_ParityDisabled;
lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
lpuartConfig.isMsb = false;
lpuartConfig.stopBitCount = kLPUART_OneStopBit;
lpuartConfig.txFifoWatermark = 0;
lpuartConfig.rxFifoWatermark = 1;
LPUART_Init(LPUART1, &lpuartConfig, 20000000U);

Parameters:

base – LPUART peripheral base address.
config – Pointer to a user-defined configuration structure.
srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

kStatus_LPUART_BaudrateNotSupport – Baudrate is not support in current clock source.
kStatus_Success – LPUART initialize succeed

status_t LPUART_Deinit(LPUART_Type *base)#

Deinitializes a LPUART instance.

This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.

Parameters:

base – LPUART peripheral base address.

Return values:

kStatus_Success – Deinit is success.
kStatus_LPUART_Timeout – Timeout during deinit.

void LPUART_GetDefaultConfig(lpuart_config_t *config)#

Gets the default configuration structure.

This function initializes the LPUART configuration structure to a default value. The default values are: lpuartConfig->baudRate_Bps = 115200U; lpuartConfig->parityMode = kLPUART_ParityDisabled; lpuartConfig->dataBitsCount = kLPUART_EightDataBits; lpuartConfig->isMsb = false; lpuartConfig->stopBitCount = kLPUART_OneStopBit; lpuartConfig->txFifoWatermark = 0; lpuartConfig->rxFifoWatermark = 1; lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; lpuartConfig->enableTx = false; lpuartConfig->enableRx = false;

Parameters:

config – Pointer to a configuration structure.

status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)#

Sets the LPUART instance baudrate.

This function configures the LPUART module baudrate. This function is used to update the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.

LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);

Parameters:

base – LPUART peripheral base address.
baudRate_Bps – LPUART baudrate to be set.
srcClock_Hz – LPUART clock source frequency in HZ.

Return values:

kStatus_LPUART_BaudrateNotSupport – Baudrate is not supported in the current clock source.
kStatus_Success – Set baudrate succeeded.

void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)#

Enable 9-bit data mode for LPUART.

This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.

Parameters:

base – LPUART peripheral base address.
enable – true to enable, flase to disable.

static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2)#

Set the LPUART address.

This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address fields can be configured. When the address field’s match enable bit is set, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one of slave’s own addresses, this slave is addressed. This address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with unmatched address.

Note

Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.

Parameters:

base – LPUART peripheral base address.
address1 – LPUART slave address1.
address2 – LPUART slave address2.

static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2)#

Enable the LPUART match address feature.

Parameters:

base – LPUART peripheral base address.
match1 – true to enable match address1, false to disable.
match2 – true to enable match address2, false to disable.

static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water)#

Sets the rx FIFO watermark.

Parameters:

base – LPUART peripheral base address.
water – Rx FIFO watermark.

static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)#

Sets the tx FIFO watermark.

Parameters:

base – LPUART peripheral base address.
water – Tx FIFO watermark.

static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)#

Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.

This function Enable 16bit Data transmit in lpuart_handle_t.

Parameters:

handle – LPUART handle pointer.
enable – true to enable, false to disable.

uint32_t LPUART_GetStatusFlags(LPUART_Type *base)#

Gets LPUART status flags.

This function gets all LPUART status flags. The flags are returned as the logical OR value of the enumerators _lpuart_flags. To check for a specific status, compare the return value with enumerators in the _lpuart_flags. For example, to check whether the TX is empty:

if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
{
    ...
}

Parameters:

base – LPUART peripheral base address.

Returns:

LPUART status flags which are ORed by the enumerators in the _lpuart_flags.

status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)#

Clears status flags with a provided mask.

This function clears LPUART status flags with a provided mask. Automatically cleared flags can’t be cleared by this function. Flags that can only cleared or set by hardware are: kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.

Parameters:

base – LPUART peripheral base address.
mask – the status flags to be cleared. The user can use the enumerators in the _lpuart_status_flag_t to do the OR operation and get the mask.

Return values:

kStatus_LPUART_FlagCannotClearManually – The flag can’t be cleared by this function but it is cleared automatically by hardware.
kStatus_Success – Status in the mask are cleared.

Returns:

0 succeed, others failed.

void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)#

Enables LPUART interrupts according to a provided mask.

This function enables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See the _lpuart_interrupt_enable. This examples shows how to enable TX empty interrupt and RX full interrupt:

LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

base – LPUART peripheral base address.
mask – The interrupts to enable. Logical OR of _lpuart_interrupt_enable.

void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)#

Disables LPUART interrupts according to a provided mask.

This function disables the LPUART interrupts according to a provided mask. The mask is a logical OR of enumeration members. See _lpuart_interrupt_enable. This example shows how to disable the TX empty interrupt and RX full interrupt:

LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);

Parameters:

base – LPUART peripheral base address.
mask – The interrupts to disable. Logical OR of _lpuart_interrupt_enable.

uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)#

Gets enabled LPUART interrupts.

This function gets the enabled LPUART interrupts. The enabled interrupts are returned as the logical OR value of the enumerators _lpuart_interrupt_enable. To check a specific interrupt enable status, compare the return value with enumerators in _lpuart_interrupt_enable. For example, to check whether the TX empty interrupt is enabled:

uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);

if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
{
    ...
}

Parameters:

base – LPUART peripheral base address.

Returns:

LPUART interrupt flags which are logical OR of the enumerators in _lpuart_interrupt_enable.

static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base)#

Gets the LPUART data register address.

This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.

Parameters:

base – LPUART peripheral base address.

Returns:

LPUART data register addresses which are used both by the transmitter and receiver.

static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)#

Enables or disables the LPUART transmitter DMA request.

This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.

Parameters:

base – LPUART peripheral base address.
enable – True to enable, false to disable.

static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)#

Enables or disables the LPUART receiver DMA.

This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.

Parameters:

base – LPUART peripheral base address.
enable – True to enable, false to disable.

uint32_t LPUART_GetInstance(LPUART_Type *base)#

Get the LPUART instance from peripheral base address.

Parameters:

base – LPUART peripheral base address.

Returns:

LPUART instance.

static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)#

Enables or disables the LPUART transmitter.

This function enables or disables the LPUART transmitter.

Parameters:

base – LPUART peripheral base address.
enable – True to enable, false to disable.

static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)#

Enables or disables the LPUART receiver.

This function enables or disables the LPUART receiver.

Parameters:

base – LPUART peripheral base address.
enable – True to enable, false to disable.

static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)#

Writes to the transmitter register.

This function writes data to the transmitter register directly. The upper layer must ensure that the TX register is empty or that the TX FIFO has room before calling this function.

Parameters:

base – LPUART peripheral base address.
data – Data write to the TX register.

static inline uint8_t LPUART_ReadByte(LPUART_Type *base)#

Reads the receiver register.

This function reads data from the receiver register directly. The upper layer must ensure that the receiver register is full or that the RX FIFO has data before calling this function.

Parameters:

base – LPUART peripheral base address.

Returns:

Data read from data register.

static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base)#

Gets the rx FIFO data count.

Parameters:

base – LPUART peripheral base address.

Returns:

rx FIFO data count.

static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base)#

Gets the tx FIFO data count.

Parameters:

base – LPUART peripheral base address.

Returns:

tx FIFO data count.

void LPUART_SendAddress(LPUART_Type *base, uint8_t address)#

Transmit an address frame in 9-bit data mode.

Parameters:

base – LPUART peripheral base address.
address – LPUART slave address.

status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)#

Writes to the transmitter register using a blocking method.

This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus.

Parameters:

base – LPUART peripheral base address.
data – Start address of the data to write.
length – Size of the data to write.

Return values:

kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)#

Writes to the transmitter register using a blocking method in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer. Please make sure only 10bit of data is valid and other bits are 0.

Parameters:

base – LPUART peripheral base address.
data – Start address of the data to write.
length – Size of the data to write.

Return values:

kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)#

Reads the receiver data register using a blocking method.

This function polls the receiver register, waits for the receiver register full or receiver FIFO has data, and reads data from the TX register.

Parameters:

base – LPUART peripheral base address.
data – Start address of the buffer to store the received data.
length – Size of the buffer.

Return values:

kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.
kStatus_LPUART_NoiseError – Noise error happened while receiving data.
kStatus_LPUART_FramingError – Framing error happened while receiving data.
kStatus_LPUART_ParityError – Parity error happened while receiving data.
kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)#

Reads the receiver data register in 9bit or 10bit mode.

Note

This function only support 9bit or 10bit transfer.

Parameters:

base – LPUART peripheral base address.
data – Start address of the buffer to store the received data by 16bit, only 10bit is valid.
length – Size of the buffer.

Return values:

kStatus_LPUART_RxHardwareOverrun – Receiver overrun happened while receiving data.
kStatus_LPUART_NoiseError – Noise error happened while receiving data.
kStatus_LPUART_FramingError – Framing error happened while receiving data.
kStatus_LPUART_ParityError – Parity error happened while receiving data.
kStatus_LPUART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

void LPUART_TransferCreateHandle(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_callback_t callback, void *userData)#

Initializes the LPUART handle.

This function initializes the LPUART handle, which can be used for other LPUART transactional APIs. Usually, for a specified LPUART instance, call this API once to get the initialized handle.

The LPUART driver supports the “background” receiving, which means that user can set up an RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the LPUART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
callback – Callback function.
userData – User data.

status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)#

Transmits a buffer of data using the interrupt method.

This function send data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data written to the transmitter register. When all data is written to the TX register in the ISR, the LPUART driver calls the callback function and passes the kStatus_LPUART_TxIdle as status parameter.

Note

The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
xfer – LPUART transfer structure, see lpuart_transfer_t.

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_LPUART_TxBusy – Previous transmission still not finished, data not all written to the TX register.
kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferStartRingBuffer(LPUART_Type *base, lpuart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)#

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, the user can get the received data from the ring buffer directly.

Note

When using RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, then only 31 bytes are used for saving data.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – size of the ring buffer.

void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)#

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.

size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)#

Get the length of received data in RX ring buffer.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.

Returns:

Length of received data in RX ring buffer.

void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)#

Aborts the interrupt-driven data transmit.

This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out how many bytes are not sent out.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.

status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)#

Gets the number of bytes that have been sent out to bus.

This function gets the number of bytes that have been sent out to bus by an interrupt method.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Send bytes count.

Return values:

kStatus_NoTransferInProgress – No send in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer, size_t *receivedBytes)#

Receives a buffer of data using the interrupt method.

This function receives data using an interrupt method. This is a non-blocking function which returns without waiting to ensure that all data are received. If the RX ring buffer is used and not empty, the data in the ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in the ring buffer is not enough for read, the receive request is saved by the LPUART driver. When the new data arrives, the receive request is serviced first. When all data is received, the LPUART driver notifies the upper layer through a callback function and passes a status parameter kStatus_UART_RxIdle. For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. The 5 bytes are copied to xfer->data, which returns with the parameter receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
xfer – LPUART transfer structure, see uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_LPUART_RxBusy – Previous receive request is not finished.
kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)#

Aborts the interrupt-driven data receiving.

This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out how many bytes not received yet.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.

status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)#

Gets the number of bytes that have been received.

This function gets the number of bytes that have been received.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Receive bytes count.

Return values:

kStatus_NoTransferInProgress – No receive in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)#

LPUART IRQ handle function.

This function handles the LPUART transmit and receive IRQ request.

Parameters:

base – LPUART peripheral base address.
irqHandle – LPUART handle pointer.

void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)#

LPUART Error IRQ handle function.

This function handles the LPUART error IRQ request.

Parameters:

base – LPUART peripheral base address.
irqHandle – LPUART handle pointer.

void LPUART_DriverIRQHandler(uint32_t instance)#

LPUART driver IRQ handler common entry.

This function provides the common IRQ request entry for LPUART.

Parameters:

instance – LPUART instance.

FSL_LPUART_DRIVER_VERSION#: LPUART driver version.

Error codes for the LPUART driver.

Values:

enumerator kStatus_LPUART_TxBusy#: TX busy

enumerator kStatus_LPUART_RxBusy#: RX busy

enumerator kStatus_LPUART_TxIdle#: LPUART transmitter is idle.

enumerator kStatus_LPUART_RxIdle#: LPUART receiver is idle.

enumerator kStatus_LPUART_TxWatermarkTooLarge#: TX FIFO watermark too large

enumerator kStatus_LPUART_RxWatermarkTooLarge#: RX FIFO watermark too large

enumerator kStatus_LPUART_FlagCannotClearManually#: Some flag can’t manually clear

enumerator kStatus_LPUART_Error#: Error happens on LPUART.

enumerator kStatus_LPUART_RxRingBufferOverrun#: LPUART RX software ring buffer overrun.

enumerator kStatus_LPUART_RxHardwareOverrun#: LPUART RX receiver overrun.

enumerator kStatus_LPUART_NoiseError#: LPUART noise error.

enumerator kStatus_LPUART_FramingError#: LPUART framing error.

enumerator kStatus_LPUART_ParityError#: LPUART parity error.

enumerator kStatus_LPUART_BaudrateNotSupport#: Baudrate is not support in current clock source

enumerator kStatus_LPUART_IdleLineDetected#: IDLE flag.

enumerator kStatus_LPUART_Timeout#: LPUART times out.

enum _lpuart_parity_mode#

LPUART parity mode.

Values:

enumerator kLPUART_ParityDisabled#: Parity disabled

enumerator kLPUART_ParityEven#: Parity enabled, type even, bit setting: PE|PT = 10

enumerator kLPUART_ParityOdd#: Parity enabled, type odd, bit setting: PE|PT = 11

enum _lpuart_data_bits#

LPUART data bits count.

Values:

enumerator kLPUART_EightDataBits#: Eight data bit

enumerator kLPUART_SevenDataBits#: Seven data bit

enum _lpuart_stop_bit_count#

LPUART stop bit count.

Values:

enumerator kLPUART_OneStopBit#: One stop bit

enumerator kLPUART_TwoStopBit#: Two stop bits

enum _lpuart_transmit_cts_source#

LPUART transmit CTS source.

Values:

enumerator kLPUART_CtsSourcePin#: CTS resource is the LPUART_CTS pin.

enumerator kLPUART_CtsSourceMatchResult#: CTS resource is the match result.

enum _lpuart_transmit_cts_config#

LPUART transmit CTS configure.

Values:

enumerator kLPUART_CtsSampleAtStart#: CTS input is sampled at the start of each character.

enumerator kLPUART_CtsSampleAtIdle#: CTS input is sampled when the transmitter is idle

enum _lpuart_transmit_rts_polarity#

LPUART transmitter RTS polarity.

Values:

enumerator kLPUART_RtsPolarityLow#: Transmitter RTS is active low.

enumerator kLPUART_RtsPolarityHigh#: Transmitter RTS is active high.

enum _lpuart_idle_type_select#

LPUART idle flag type defines when the receiver starts counting.

Values:

enumerator kLPUART_IdleTypeStartBit#: Start counting after a valid start bit.

enumerator kLPUART_IdleTypeStopBit#: Start counting after a stop bit.

enum _lpuart_idle_config#

LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

Values:

enumerator kLPUART_IdleCharacter1#: the number of idle characters.

enumerator kLPUART_IdleCharacter2#: the number of idle characters.

enumerator kLPUART_IdleCharacter4#: the number of idle characters.

enumerator kLPUART_IdleCharacter8#: the number of idle characters.

enumerator kLPUART_IdleCharacter16#: the number of idle characters.

enumerator kLPUART_IdleCharacter32#: the number of idle characters.

enumerator kLPUART_IdleCharacter64#: the number of idle characters.

enumerator kLPUART_IdleCharacter128#: the number of idle characters.

enum _lpuart_interrupt_enable#

LPUART interrupt configuration structure, default settings all disabled.

This structure contains the settings for all LPUART interrupt configurations.

Values:

enumerator kLPUART_LinBreakInterruptEnable#: LIN break detect. bit 7

enumerator kLPUART_RxActiveEdgeInterruptEnable#: Receive Active Edge. bit 6

enumerator kLPUART_TxDataRegEmptyInterruptEnable#: Transmit data register empty. bit 23

enumerator kLPUART_TransmissionCompleteInterruptEnable#: Transmission complete. bit 22

enumerator kLPUART_RxDataRegFullInterruptEnable#: Receiver data register full. bit 21

enumerator kLPUART_IdleLineInterruptEnable#: Idle line. bit 20

enumerator kLPUART_RxOverrunInterruptEnable#: Receiver Overrun. bit 27

enumerator kLPUART_NoiseErrorInterruptEnable#: Noise error flag. bit 26

enumerator kLPUART_FramingErrorInterruptEnable#: Framing error flag. bit 25

enumerator kLPUART_ParityErrorInterruptEnable#: Parity error flag. bit 24

enumerator kLPUART_Match1InterruptEnable#: Parity error flag. bit 15

enumerator kLPUART_Match2InterruptEnable#: Parity error flag. bit 14

enumerator kLPUART_TxFifoOverflowInterruptEnable#: Transmit FIFO Overflow. bit 9

enumerator kLPUART_RxFifoUnderflowInterruptEnable#: Receive FIFO Underflow. bit 8

enumerator kLPUART_AllInterruptEnable#

enum _lpuart_flags#

LPUART status flags.

This provides constants for the LPUART status flags for use in the LPUART functions.

Values:

enumerator kLPUART_TxDataRegEmptyFlag#: Transmit data register empty flag, sets when transmit buffer is empty. bit 23

enumerator kLPUART_TransmissionCompleteFlag#: Transmission complete flag, sets when transmission activity complete. bit 22

enumerator kLPUART_RxDataRegFullFlag#: Receive data register full flag, sets when the receive data buffer is full. bit 21

enumerator kLPUART_IdleLineFlag#: Idle line detect flag, sets when idle line detected. bit 20

enumerator kLPUART_RxOverrunFlag#: Receive Overrun, sets when new data is received before data is read from receive register. bit 19

enumerator kLPUART_NoiseErrorFlag#: Receive takes 3 samples of each received bit. If any of these samples differ, noise flag sets. bit 18

enumerator kLPUART_FramingErrorFlag#: Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17

enumerator kLPUART_ParityErrorFlag#: If parity enabled, sets upon parity error detection. bit 16

enumerator kLPUART_LinBreakFlag#: LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled. bit 31

enumerator kLPUART_RxActiveEdgeFlag#: Receive pin active edge interrupt flag, sets when active edge detected. bit 30

enumerator kLPUART_RxActiveFlag#: Receiver Active Flag (RAF), sets at beginning of valid start. bit 24

enumerator kLPUART_DataMatch1Flag#: The next character to be read from LPUART_DATA matches MA1. bit 15

enumerator kLPUART_DataMatch2Flag#: The next character to be read from LPUART_DATA matches MA2. bit 14

enumerator kLPUART_TxFifoEmptyFlag#: TXEMPT bit, sets if transmit buffer is empty. bit 7

enumerator kLPUART_RxFifoEmptyFlag#: RXEMPT bit, sets if receive buffer is empty. bit 6

enumerator kLPUART_TxFifoOverflowFlag#: TXOF bit, sets if transmit buffer overflow occurred. bit 1

enumerator kLPUART_RxFifoUnderflowFlag#: RXUF bit, sets if receive buffer underflow occurred. bit 0

enumerator kLPUART_AllClearFlags#

enumerator kLPUART_AllFlags#

typedef enum _lpuart_parity_mode lpuart_parity_mode_t#: LPUART parity mode.

typedef enum _lpuart_data_bits lpuart_data_bits_t#: LPUART data bits count.

typedef enum _lpuart_stop_bit_count lpuart_stop_bit_count_t#: LPUART stop bit count.

typedef enum _lpuart_transmit_cts_source lpuart_transmit_cts_source_t#: LPUART transmit CTS source.

typedef enum _lpuart_transmit_cts_config lpuart_transmit_cts_config_t#: LPUART transmit CTS configure.

typedef enum _lpuart_transmit_rts_polarity lpuart_transmit_rts_polarity_t#: LPUART transmitter RTS polarity.

typedef enum _lpuart_idle_type_select lpuart_idle_type_select_t#: LPUART idle flag type defines when the receiver starts counting.

typedef enum _lpuart_idle_config lpuart_idle_config_t#: LPUART idle detected configuration. This structure defines the number of idle characters that must be received before the IDLE flag is set.

typedef struct _lpuart_config lpuart_config_t#: LPUART configuration structure.

typedef struct _lpuart_transfer lpuart_transfer_t#: LPUART transfer structure.

typedef struct _lpuart_handle lpuart_handle_t#

typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)#: LPUART transfer callback function.

typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle)#

void *s_lpuartHandle[]#

const IRQn_Type s_lpuartTxIRQ[]#

lpuart_isr_t s_lpuartIsr[]#

UART_RETRY_TIMES#: Retry times for waiting flag.

struct _lpuart_config#

#include <fsl_lpuart.h>

LPUART configuration structure.

Public Members

uint32_t baudRate_Bps#: LPUART baud rate

lpuart_parity_mode_t parityMode#: Parity mode, disabled (default), even, odd

lpuart_data_bits_t dataBitsCount#: Data bits count, eight (default), seven

bool isMsb#: Data bits order, LSB (default), MSB

lpuart_stop_bit_count_t stopBitCount#: Number of stop bits, 1 stop bit (default) or 2 stop bits

uint8_t txFifoWatermark#: TX FIFO watermark

uint8_t rxFifoWatermark#: RX FIFO watermark

bool enableRxRTS#: RX RTS enable

bool enableTxRTS#: TX RTS enable

bool enableTxCTS#: TX CTS enable

lpuart_transmit_cts_source_t txCtsSource#: TX CTS source

lpuart_transmit_cts_config_t txCtsConfig#: TX CTS configure

lpuart_transmit_rts_polarity_t txRtsPolarity#: TX RTS polarity

uint8_t rtsWatermark#: RTS watermark

lpuart_idle_type_select_t rxIdleType#: RX IDLE type.

lpuart_idle_config_t rxIdleConfig#: RX IDLE configuration.

bool enableTx#: Enable TX

bool enableRx#: Enable RX

bool swapTxdRxd#: Swap TXD and RXD pins

bool inverseTxd#: Transmit Data Inversion - Setting true reverses the polarity of the transmitted data output

struct _lpuart_transfer#

#include <fsl_lpuart.h>

LPUART transfer structure.

Public Members

size_t dataSize#: The byte count to be transfer.

struct _lpuart_handle#

#include <fsl_lpuart.h>

LPUART handle structure.

Public Members

volatile size_t txDataSize#: Size of the remaining data to send.

size_t txDataSizeAll#: Size of the data to send out.

volatile size_t rxDataSize#: Size of the remaining data to receive.

size_t rxDataSizeAll#: Size of the data to receive.

size_t rxRingBufferSize#: Size of the ring buffer.

volatile uint16_t rxRingBufferHead#: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail#: Index for the user to get data from the ring buffer.

lpuart_transfer_callback_t callback#: Callback function.

void *userData#: LPUART callback function parameter.

volatile uint8_t txState#: TX transfer state.

volatile uint8_t rxState#: RX transfer state.

bool isSevenDataBits#: Seven data bits flag.

bool is16bitData#: 16bit data bits flag, only used for 9bit or 10bit data

union __unnamed21__#

Public Members

uint8_t *data#: The buffer of data to be transfer.

uint8_t *rxData#: The buffer to receive data.

uint16_t *rxData16#: The buffer to receive data.

const uint8_t *txData#: The buffer of data to be sent.

const uint16_t *txData16#: The buffer of data to be sent.

union __unnamed23__#

Public Members

const uint8_t *volatile txData#: Address of remaining data to send.

const uint16_t *volatile txData16#: Address of remaining data to send.

union __unnamed25__#

Public Members

uint8_t *volatile rxData#: Address of remaining data to receive.

uint16_t *volatile rxData16#: Address of remaining data to receive.

union __unnamed27__#

Public Members

uint8_t *rxRingBuffer#: Start address of the receiver ring buffer.

uint16_t *rxRingBuffer16#: Start address of the receiver ring buffer.

LPUART eDMA Driver#

void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)#

Initializes the LPUART handle which is used in transactional functions.

Note

This function disables all LPUART interrupts.

Parameters:

base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.
callback – Callback function.
userData – User data.
txEdmaHandle – User requested DMA handle for TX DMA transfer.
rxEdmaHandle – User requested DMA handle for RX DMA transfer.

status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)#

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent, the send callback function is called.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
xfer – LPUART eDMA transfer structure. See lpuart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_LPUART_TxBusy – Previous transfer on going.
kStatus_InvalidArgument – Invalid argument.

status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)#

Receives data using eDMA.

This function receives data using eDMA. This is non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.
xfer – LPUART eDMA transfer structure, see lpuart_transfer_t.

Return values:

kStatus_Success – if succeed, others fail.
kStatus_LPUART_RxBusy – Previous transfer ongoing.
kStatus_InvalidArgument – Invalid argument.

void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)#

Aborts the sent data using eDMA.

This function aborts the sent data using eDMA.

Parameters:

base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.

void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)#

Aborts the received data using eDMA.

This function aborts the received data using eDMA.

Parameters:

base – LPUART peripheral base address.
handle – Pointer to lpuart_edma_handle_t structure.

status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)#

Gets the number of bytes written to the LPUART TX register.

This function gets the number of bytes written to the LPUART TX register by DMA.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Send bytes count.

Return values:

kStatus_NoTransferInProgress – No send in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter count;

status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)#

Gets the number of received bytes.

This function gets the number of received bytes.

Parameters:

base – LPUART peripheral base address.
handle – LPUART handle pointer.
count – Receive bytes count.

Return values:

kStatus_NoTransferInProgress – No receive in progress.
kStatus_InvalidArgument – Parameter is invalid.
kStatus_Success – Get successfully through the parameter count;

void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle)#

LPUART eDMA IRQ handle function.

This function handles the LPUART tx complete IRQ request and invoke user callback. It is not set to static so that it can be used in user application.

Note

This function is used as default IRQ handler by double weak mechanism. If user’s specific IRQ handler is implemented, make sure this function is invoked in the handler.

Parameters:

base – LPUART peripheral base address.
lpuartEdmaHandle – LPUART handle pointer.

FSL_LPUART_EDMA_DRIVER_VERSION#: LPUART EDMA driver version.

typedef struct _lpuart_edma_handle lpuart_edma_handle_t#

typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData)#: LPUART transfer callback function.

struct _lpuart_edma_handle#

#include <fsl_lpuart_edma.h>

LPUART eDMA handle.

Public Members

lpuart_edma_transfer_callback_t callback#: Callback function.

void *userData#: LPUART callback function parameter.

size_t rxDataSizeAll#: Size of the data to receive.

size_t txDataSizeAll#: Size of the data to send out.

edma_handle_t *txEdmaHandle#: The eDMA TX channel used.

edma_handle_t *rxEdmaHandle#: The eDMA RX channel used.

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

volatile uint8_t txState#: TX transfer state.

volatile uint8_t rxState#: RX transfer state

MAU: Math Accelerator Unit Driver#

typedef int16_t mau_q15_t#: MAU Q15 type.

typedef int32_t mau_q31_t#: MAU Q31 type.

mau_result_t res {return (base->RES_STATUS >> (8 << (uint8_t)(res))) & 0xFF

mau_result_t uint32_t mask {base->RES_STATUS &= ~((mask & 0xFF) << (8 << (uint8_t)(res)))

uint32_t input#

(*volatile uint32_t )(addr))) = input

(*volatile float )(addr))) = input

float float *pSin = (*((volatile float*)((uint32_t)(&MAU0->RES0) + (sin_res << 2))))#

float float float *pCos = (*((volatile float*)((uint32_t)(&MAU0->RES0) + (cos_res << 2))))#

float float float mau_result_t sin_res

float float float mau_result_t mau_result_t cos_res {uint32_t sin_addr = (( (uint32_t)base ) | (( kMAU_DT_FLOAT ) << 9U) | (( sin_res ) << 7U) | (( kMAU_MOPC_SIN ) << 2U))

uint32_t cos_addr = (((uint32_t)base) | ((kMAU_DT_FLOAT) << 9U) | ((cos_res) << 7U) | ((kMAU_MOPC_COS) << 2U))#

float input_value = input #

static inline static __attribute__ ((always_inline)) void MAU_GetDefaultConfig(mau_config_t *config)

Gets the default configuration structure.

Calculate the arctangent(X)/PI for Q15.

Calculate the sine(PI*X) and cosine(PI*X) for Q15.

Calculate the cosine(PI*X) for Q15.

Calculate the sine(PI*X) for Q15.

Calculate the reciprocal square root for Q15.

Calculate the square root for Q15.

Calculate the reciprocal for Q15.

Calculate the arctangent(X)/PI for Q31.

Calculate the sine(PI*X) and cosine(PI*X) for Q31.

Calculate the cosine(PI*X) for Q31.

Calculate the sine(PI*X) for Q31.

Calculate the reciprocal square root for Q31.

Calculate the square root for Q31.

Calculate the reciprocal for Q31.

Calculate the arctangent(X)/PI for float.

Calculate the sine(PI*X) and cosine(PI*X) for float.

Calculate the cosine(PI*X) for float.

Calculate the sine(PI*X) for float.

Calculate the reciprocal square root for float.

Calculate the square root for float.

Calculate the reciprocal for float.

Calculate the square root for uint32.

Clears the result register status flag.

Gets the result register status flag.

This function initializes the MAU configuration structure to a default value.

Parameters:

base – MAU peripheral base address.
res – MAU result register. see mau_result_t.
base – MAU peripheral base address.
res – MAU result register. see mau_result_t.
mask – MAU result register flag mask, see mau_flags_t.
base – MAU peripheral base address.
input – Input data.
res – MAU result register. see mau_result_t.
base – MAU peripheral base address.
input – Input data.
res – MAU result register. see mau_result_t.
base – MAU peripheral base address.
input – Input data.
pSin – Points to the block of sine output data
pCos – Points to the block of cosine output data
sin_res – MAU result register for sine. see mau_result_t.
cos_res – MAU result register for cosine. see mau_result_t.
base – MAU peripheral base address.
input – Input data.
res – MAU result register. see mau_result_t.
base – MAU peripheral base address.
input – Input data.
res – MAU result register. see mau_result_t.

Returns:

uint32_t MAU result register flags, see mau_flags_t.

Returns:

uint32_t

Returns:

float

Returns:

mau_q31_t

Returns:

mau_q15_t

void MAU_Init(MAU_Type *base, mau_config_t *config)#

Initializes MAU instance with the user configuration structure.

Parameters:

base – MAU peripheral base address.
config – Pointer to a user-defined configuration structure.

void MAU_Deinit(MAU_Type *base)#

Deinitializes MAU instance.

Parameters:

base – MAU peripheral base address.

FSL_MAU_DRIVER_VERSION#: MAU driver version.

enum _mau_data_type#

MAU data type.

Values:

enumerator kMAU_DT_UINT#

enumerator kMAU_DT_INT#

enumerator kMAU_DT_Q1X#

enumerator kMAU_DT_FLOAT#

enum _mau_result#

MAU result register.

Values:

enumerator kMAU_RES0#

enumerator kMAU_RES1#

enumerator kMAU_RES2#

enumerator kMAU_RES3#

enum _mau_mopc#

MAU calculation code.

Values:

enumerator kMAU_MOPC_BYPASS#

enumerator kMAU_MOPC_RECIP#

enumerator kMAU_MOPC_SQRT#

enumerator kMAU_MOPC_SQRT_RECIP#

enumerator kMAU_MOPC_COS#

enumerator kMAU_MOPC_SIN#

enumerator kMAU_MOPC_ATAN#

enum _mau_flags#

MAU result register status flag.

Values:

enumerator kMAU_FLAG_NX#

enumerator kMAU_FLAG_UF#

enumerator kMAU_FLAG_OF#

enumerator kMAU_FLAG_DZ#

enumerator kMAU_FLAG_NV#

enumerator kMAU_FLAG_ERR#

enumerator kMAU_FLAG_OVWR#

enumerator kMAU_FLAG_FULL#

typedef enum _mau_data_type mau_data_type_t#: MAU data type.

typedef enum _mau_result mau_result_t#: MAU result register.

typedef enum _mau_mopc mau_mopc_t#: MAU calculation code.

typedef enum _mau_flags mau_flags_t#: MAU result register status flag.

typedef struct _mau_config mau_config_t#: MAU configuration structure.

MAU_MATH_PI#

MAU_DT_SET(dt)#

MAU_RES_SET(res)#

MAU_MOPC_SET(mopc)#

MAU_INDIRECT_ADDR(base, dt, ds, mopc)#

MAU_REG_UINT32(addr)#

MAU_REG_Q15(addr)#

MAU_REG_Q31(addr)#

MAU_REG_FLOAT(addr)#

CONFIG_MAU_ENABLE_CMSIS_DSP_API#: Enable the MAU CMSIS DSP function.

CONFIG_MAU_ENABLE_CMSIS_DSP_ARM_SQRT_F32_API#: Enable the MAU arm_sqrt_f32 function.

struct _mau_config#

#include <fsl_mau.h>

MAU configuration structure.

Public Members

bool enableRes0Interrupt#: Enable RES0 interrupt.

bool enableRes1Interrupt#: Enable RES1 interrupt.

bool enableRes2Interrupt#: Enable RES2 interrupt.

bool enableRes3Interrupt#: Enable RES3 interrupt.

MCX_CMC: Core Mode Controller Driver#

enum _cmc_power_mode_protection#

CMC power mode Protection enumeration.

Values:

enumerator kCMC_AllowDeepSleepMode#: Allow Deep Sleep mode.

enumerator kCMC_AllowPowerDownMode#: Allow Power Down mode.

enumerator kCMC_AllowDeepPowerDownMode#: Allow Deep Power Down mode.

enumerator kCMC_AllowAllLowPowerModes#: Allow Deep Sleep, Power Down, Deep Power Down modes.

enum _cmc_wakeup_sources#

Wake up sources from the previous low power mode entry.

Note

kCMC_WakeupFromUsbFs, kCMC_WakeupFromITRC, kCMC_WakeupFromCpu1 are not supported in MCXA family.

Values:

enumerator kCMC_WakeupFromResetInterruptOrPowerDown#: Wakeup source is reset interrupt, or wake up from Deep Power Down.

enumerator kCMC_WakeupFromDebugReuqest#: Wakeup source is debug request.

enumerator kCMC_WakeupFromInterrupt#: Wakeup source is interrupt.

enumerator kCMC_WakeupFromDMAWakeup#: Wakeup source is DMA Wakeup.

enumerator kCMC_WakeupFromWUURequest#: Wakeup source is WUU request.

enumerator kCMC_WakeupFromUsbFs#: Wakeup source is USBFS(USB0).

enumerator kCMC_WakeupFromITRC#: Wakeup source is ITRC.

enumerator kCMC_WakeupFromCpu1#: Wakeup source is CPU1.

enum _cmc_system_reset_interrupt_enable#

System Reset Interrupt enable enumeration.

Values:

enumerator kCMC_PinResetInterruptEnable#: Pin Reset interrupt enable.

enumerator kCMC_DAPResetInterruptEnable#: DAP Reset interrupt enable.

enumerator kCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable#: Low Power Acknowledge Timeout Reset interrupt enable.

enumerator kCMC_SoftwareResetInterruptEnable#: Software Reset interrupt enable.

enumerator kCMC_LockupResetInterruptEnable#: Lockup Reset interrupt enable.

enum _cmc_system_reset_interrupt_flag#

CMC System Reset Interrupt Status flag.

Values:

enumerator kCMC_PinResetInterruptFlag#: Pin Reset interrupt flag.

enumerator kCMC_DAPResetInterruptFlag#: DAP Reset interrupt flag.

enumerator kCMC_LowPowerAcknowledgeTimeoutResetFlag#: Low Power Acknowledge Timeout Reset interrupt flag.

enumerator kCMC_SoftwareResetInterruptFlag#: Software Reset interrupt flag.

enumerator kCMC_LockupResetInterruptFlag#: Lock up Reset interrupt flag.

enum _cmc_system_sram_arrays#

CMC System SRAM arrays low power mode enable enumeration.

Values:

enumerator kCMC_RAMX0#: Used to control RAMX0.

enumerator kCMC_RAMX1#: Used to control RAMX1.

enumerator kCMC_RAMX2#: Used to control RAMX2.

enumerator kCMC_RAMB#: Used to control RAMB.

enumerator kCMC_RAMC0#: Used to control RAMC0.

enumerator kCMC_RAMC1#: Used to control RAMC1.

enumerator kCMC_RAMD0#: Used to control RAMD0.

enumerator kCMC_RAMD1#: Used to control RAMD1.

enumerator kCMC_RAME0#: Used to control RAME0.

enumerator kCMC_RAME1#: Used to control RAME1.

enumerator kCMC_RAMF0#: Used to control RAMF0.

enumerator kCMC_RAMF1#: Used to control RAMF1.

enumerator kCMC_RAMG0_RAMG1#: Used to control RAMG0 and RAMG1.

enumerator kCMC_RAMG2_RAMG3#: Used to control RAMG2 and RAMG3.

enumerator kCMC_RAMH0_RAMH1#: Used to control RAMH0 and RAMH1.

enumerator kCMC_LPCAC#: Used to control LPCAC.

enumerator kCMC_DMA0_DMA1_PKC#: Used to control DMA0, DMA1 and PKC.

enumerator kCMC_USB0#: Used to control USB0.

enumerator kCMC_PQ#: Used to control PQ.

enumerator kCMC_CAN0_CAN1_ENET_USB1#: Used to control CAN0, CAN1, ENET, USB1.

enumerator kCMC_FlexSPI#: Used to control FlexSPI.

enumerator kCMC_AllSramArrays#: Mask of all System SRAM arrays.

enum _cmc_system_reset_sources#

System reset sources enumeration.

Values:

enumerator kCMC_WakeUpReset#: The reset caused by a wakeup from Power Down or Deep Power Down mode.

enumerator kCMC_PORReset#: The reset caused by power on reset detection logic.

enumerator kCMC_WarmReset#: The last reset source is a warm reset source.

enumerator kCMC_FatalReset#: The last reset source is a fatal reset source.

enumerator kCMC_PinReset#: The reset caused by the RESET_b pin.

enumerator kCMC_DAPReset#: The reset caused by a reset request from the Debug Access port.

enumerator kCMC_ResetTimeout#: The reset caused by a timeout or other error condition in the system reset generation.

enumerator kCMC_LowPowerAcknowledgeTimeoutReset#: The reset caused by a timeout in low power mode entry logic.

enumerator kCMC_SCGReset#: The reset caused by a loss of clock or loss of lock event in the SCG.

enumerator kCMC_SoftwareReset#: The reset caused by a software reset request.

enumerator kCMC_LockUoReset#: The reset caused by the ARM core indication of a LOCKUP event.

enumerator kCMC_JTAGSystemReset#: The reset caused by a JTAG system reset request.

enum _cmc_core_clock_gate_status#

Indicate the core clock was gated.

Values:

enumerator kCMC_CoreClockNotGated#: Core clock not gated.

enumerator kCMC_CoreClockGated#: Core clock was gated due to low power mode entry.

enum _cmc_clock_mode#

CMC clock mode enumeration.

Values:

enumerator kCMC_GateNoneClock#: No clock gating.

enumerator kCMC_GateCoreClock#: Gate Core clock.

enumerator kCMC_GateCorePlatformClock#: Gate Core clock and platform clock.

enumerator kCMC_GateAllSystemClocks#: Gate all System clocks, without getting core entering into low power mode.

enumerator kCMC_GateAllSystemClocksEnterLowPowerMode#: Gate all System clocks, with core entering into low power mode.

enum _cmc_low_power_mode#

CMC power mode enumeration.

Values:

enumerator kCMC_ActiveOrSleepMode#: Select Active/Sleep mode.

enumerator kCMC_DeepSleepMode#: Select Deep Sleep mode when a core executes WFI or WFE instruction.

enumerator kCMC_PowerDownMode#: Select Power Down mode when a core executes WFI or WFE instruction.

enumerator kCMC_DeepPowerDown#: Select Deep Power Down mode when a core executes WFI or WFE instruction.

typedef enum _cmc_core_clock_gate_status cmc_core_clock_gate_status_t#: Indicate the core clock was gated.

typedef enum _cmc_clock_mode cmc_clock_mode_t#: CMC clock mode enumeration.

typedef enum _cmc_low_power_mode cmc_low_power_mode_t#: CMC power mode enumeration.

typedef struct _cmc_reset_pin_config cmc_reset_pin_config_t#: CMC reset pin configuration.

typedef struct _cmc_power_domain_config cmc_power_domain_config_t#: power mode configuration for each power domain.

FSL_CMC_DRIVER_VERSION#: CMC driver version 2.5.0.

CMC_BLR_LOCK_FIELD_WIDTH#

CMC_BLR_LOCK_IDX_MASK(index)#

CMC_BLR_LOCK_IDX_SHIFT(index)#

CMC_BLR_LOCK_IDX(index, value)#

void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode)#

Sets clock mode.

This function configs the amount of clock gating when the core asserts Sleeping due to WFI, WFE or SLEEPONEXIT.

Parameters:

base – CMC peripheral base address.
mode – System clock mode.

static inline void CMC_LockClockModeSetting(CMC_Type *base)#

Locks the clock mode setting.

After invoking this function, any clock mode setting will be blocked.

Parameters:

base – CMC peripheral base address.

static inline cmc_core_clock_gate_status_t CMC_GetCoreClockGatedStatus(CMC_Type *base)#

Gets the core clock gated status.

This function get the status to indicate whether the core clock is gated. The core clock gated status can be cleared by software.

Parameters:

base – CMC peripheral base address.

Returns:

The status to indicate whether the core clock is gated.

static inline void CMC_ClearCoreClockGatedStatus(CMC_Type *base)#

Clears the core clock gated status.

This function clear clock status flag by software.

Parameters:

base – CMC peripheral base address.

static inline uint8_t CMC_GetWakeupSource(CMC_Type *base)#

Gets the Wakeup Source.

This function gets the Wakeup sources from the previous low power mode entry.

Parameters:

base – CMC peripheral base address.

Returns:

The Wakeup sources from the previous low power mode entry. See _cmc_wakeup_sources for details.

static inline cmc_clock_mode_t CMC_GetClockMode(CMC_Type *base)#

Gets the Clock mode.

This function gets the clock mode of the previous low power mode entry.

Parameters:

base – CMC peripheral base address.

Returns:

The Low Power status.

static inline uint32_t CMC_GetSystemResetStatus(CMC_Type *base)#

Gets the System reset status.

This function returns the system reset status. Those status updates on every MAIN Warm Reset to indicate the type/source of the most recent reset.

Parameters:

base – CMC peripheral base address.

Returns:

The most recent system reset status. See _cmc_system_reset_sources for details.

static inline uint32_t CMC_GetStickySystemResetStatus(CMC_Type *base)#

Gets the sticky system reset status since the last WAKE Cold Reset.

This function gets all source of system reset that have generated a system reset since the last WAKE Cold Reset, and that have not been cleared by software.

Parameters:

base – CMC peripheral base address.

Returns:

System reset status that have not been cleared by software. See _cmc_system_reset_sources for details.

static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask)#

Clears the sticky system reset status flags.

Parameters:

base – CMC peripheral base address.
mask – Bitmap of the sticky system reset status to be cleared.

static inline uint8_t CMC_GetResetCount(CMC_Type *base)#

Gets the number of reset sequences completed since the last Cold Reset.

Parameters:

base – CMC peripheral base address.

Returns:

The number of reset sequences.

void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes)#

Configures all power mode protection settings.

This function configures the power mode protection settings for supported power modes. This should be done before set the lowPower mode for each power doamin.

The allowed lowpower modes are passed as bit map. For example, to allow Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes).

Parameters:

base – CMC peripheral base address.
allowedModes – Bitmaps of the allowed power modes. See _cmc_power_mode_protection for details.

static inline void CMC_LockPowerModeProtectionSetting(CMC_Type *base)#

Locks the power mode protection.

This function locks the power mode protection. After invoking this function, any power mode protection setting will be ignored.

Parameters:

base – CMC peripheral base address.

static inline void CMC_SetGlobalPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)#

Config the same lowPower mode for all power domain.

This function configures the same low power mode for MAIN power domian and WAKE power domain.

Parameters:

base – CMC peripheral base address.
lowPowerMode – The desired lowPower mode. See cmc_low_power_mode_t for details.

static inline void CMC_SetMAINPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)#

Configures entry into low power mode for the MAIN Power domain.

This function configures the low power mode for the MAIN power domian, when the core executes WFI/WFE instruction. The available lowPower modes are defined in the cmc_low_power_mode_t.

Parameters:

base – CMC peripheral base address.
lowPowerMode – The desired lowPower mode. See cmc_low_power_mode_t for details.

static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base)#

Gets the power mode of the MAIN Power domain.

Parameters:

base – CMC peripheral base address.

Returns:

The power mode of MAIN Power domain. See cmc_low_power_mode_t for details.

void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)#

Configure reset pin.

This function configures reset pin. When enabled, the low power filter is enabled in both Active and Low power modes, the reset filter is only enabled in Active mode. When both filers are enabled, they operate in series.

Parameters:

base – CMC peripheral base address.
config – Pointer to the reset pin config structure.

static inline void CMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask)#

Enable system reset interrupts.

This function enables the system reset interrupts. The assertion of non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock while an enabled interrupt is generated. Then Software can perform a graceful shutdown or abort the non-fatal warm reset provided the pending reset source is cleared by resetting the reset source and then clearing the pending flag.

Parameters:

base – CMC peripheral base address.
mask – System reset interrupts. See _cmc_system_reset_interrupt_enable for details.

static inline void CMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask)#

Disable system reset interrupts.

This function disables the system reset interrupts.

Parameters:

base – CMC peripheral base address.
mask – System reset interrupts. See _cmc_system_reset_interrupt_enable for details.

static inline uint32_t CMC_GetSystemResetInterruptFlags(CMC_Type *base)#

Gets System Reset interrupt flags.

This function returns the System reset interrupt flags.

Parameters:

base – CMC peripheral base address.

Returns:

System reset interrupt flags. See _cmc_system_reset_interrupt_flag for details.

static inline void CMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask)#

Clears System Reset interrupt flags.

This function clears system reset interrupt flags. The pending reset source can be cleared by resetting the source of the reset and then clearing the pending flags.

Parameters:

base – CMC peripheral base address.
mask – System Reset interrupt flags. See _cmc_system_reset_interrupt_flag for details.

static inline void CMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable)#

Enable/Disable Non maskable Pin interrupt.

Parameters:

base – CMC peripheral base address.
enable – Enable or disable Non maskable pin interrupt. true - enable Non-maskable pin interrupt. false - disable Non-maskable pin interupt.

static inline uint8_t CMC_GetISPMODEPinLogic(CMC_Type *base)#

Gets the logic state of the ISPMODE_n pin.

This function returns the logic state of the ISPMODE_n pin on the last negation of RESET_b pin.

Parameters:

base – CMC peripheral base address.

Returns:

The logic state of the ISPMODE_n pin on the last negation of RESET_b pin.

static inline void CMC_ClearISPMODEPinLogic(CMC_Type *base)#

Clears ISPMODE_n pin state.

Parameters:

base – CMC peripheral base address.

static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert)#

Set the logic state of the BOOT_CONFIGn pin.

This function force the logic state of the Boot_Confign pin to assert on next system reset.

Parameters:

base – CMC peripheral base address.
assert – Assert the corresponding pin or not. true - Assert corresponding pin on next system reset. false - No effect.

static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base)#

Gets the status information written by the BootROM.

Parameters:

base – CMC peripheral base address.

Returns:

The status information written by the BootROM.

static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue)#

Sets the bootROM status value.

Note

This function is useful when result of CMC_CheckBootRomRegisterWrittable() is true.

Parameters:

base – CMC peripheral base address.
stat – The state value to set.

static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base, uint8_t index)

Gets the information written by the BootROM.

Parameters:

base – CMC peripheral base address.
index – The index of BootROM status register, ranges from 0.

Returns:

The status information written by the BootROM.

static inline void CMC_WriteBootRomStatusReg(CMC_Type *base, uint8_t index, uint32_t value)#

Writes value to BootROM status register, in this way, BootROM status registers are used as general purpose register.

Note

Value in BootROM status registers are reset in cold reset.

Parameters:

base – CMC peripheral base address.
index – The index of BootROM status register, ranges from 0.
value – Value to write.

static inline void CMC_LockWriteOperationToBootRomStatusReg(CMC_Type *base, uint8_t index)#

Lock write operation to BootROM status register and BootROM Lock register.

Note

If locked, BootROM status register cannot be written.

Note

Once locked, only cold reset can reset related register.

Parameters:

base – CMC peripheral base address.
index – The index of BootROM status register, ranges from 0.

static inline bool CMC_CheckBootRomStatusRegWriteLocked(CMC_Type *base, uint8_t index)#

Check if BootROM status register can be written.

Parameters:

base – CMC peripheral base address.
index – The index of BootROM status register, ranges from 0.

Return values:

true – The selected BootRom status register is locked and cannot be written.
false – The selected BootRom Status register is unlocked and cannot be written.

void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)#

Power off the selected system SRAM always.

Note

This function power off the selected system SRAM always. The SRAM arrays should not be accessed while they are shut down. SRAM array contents are not retained if they are powered off.

Note

Once invoked, the previous settings will be overwritten.

Parameters:

base – CMC peripheral base address.
mask – Bitmap of the SRAM arrays to be powered off all modes. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

static inline void CMC_PowerOnSRAMAllMode(CMC_Type *base, uint32_t mask)#

Power on SRAM during all mode.

Note

Once invoked, the previous settings will be overwritten.

Parameters:

base – CMC peripheral base address.
mask – Bitmap of the SRAM arrays to be powered on all modes. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)#

Power off the selected system SRAM during low power modes only.

This function power off the selected system SRAM only during low power mode. SRAM array contents are not retained if they are power off.

Parameters:

base – CMC peripheral base address.
mask – Bitmap of the SRAM arrays to be power off during low power mode only. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)#

Power on the selected system SRAM during low power modes only.

This function power on the selected system SRAM. The SRAM arrray contents are retained in low power modes.

Parameters:

base – CMC peripheral base address.
mask – Bitmap of the SRAM arrays to be power on during low power mode only. See _cmc_system_sram_arrays for details. Check Reference Manual for the SRAM region and mask bit relationship.

void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)#

Configs the low power mode of the on-chip flash memory.

This function configs the low power mode of the on-chip flash memory.

Parameters:

base – CMC peripheral base address.
doze – true: Flash is disabled while core is sleeping false: No effect.
disable – true: Flash memory is placed in low power state. false: No effect.

static inline void CMC_EnableDebugOperation(CMC_Type *base, bool enable)#

Enables/Disables debug Operation when the core sleep.

This function configs what happens to debug when core sleeps.

Parameters:

base – CMC peripheral base address.
enable – Enable or disable Debug when Core is sleeping. true - Debug remains enabled when the core is sleeping. false - Debug is disabled when the core is sleeping.

void CMC_PreEnterLowPowerMode(void)#

Prepares to enter low power modes.

This function should be called before entering low power modes.

void CMC_PostExitLowPowerMode(void)#

Recovers after wake up from low power modes.

This function should be called after wake up from low power modes. This function should be used with CMC_PreEnterLowPowerMode()

void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)#

Configs the entry into the same low power mode for each power domains.

This function provides the feature to entry into the same low power mode for each power domains. Before invoking this function, please ensure the selected power mode have been allowed.

Parameters:

base – CMC peripheral base address.
lowPowerMode – The low power mode to be entered. See cmc_low_power_mode_t for the details.

void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)#

Configs the entry into different low power modes for each power domains.

This function provides the feature to entry into different low power modes for each power domains. Before invoking this function please ensure the selected modes are allowed.

Parameters:

base – CMC peripheral base address.
config – Pointer to the cmc_power_domain_config_t structure.

bool lowpowerFilterEnable#: Low Power Filter enable.

bool resetFilterEnable#: Reset Filter enable.

uint8_t resetFilterWidth#: Width of the Reset Filter.

cmc_clock_mode_t clock_mode#: Clock mode for each power domain.

cmc_low_power_mode_t main_domain#: The low power mode of the MAIN power domain.

struct _cmc_reset_pin_config#: #include <fsl_cmc.h>

CMC reset pin configuration.

struct _cmc_power_domain_config#: #include <fsl_cmc.h>

power mode configuration for each power domain.

MCX_SPC: System Power Control driver#

uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base)#

Gets Isolation status for each power domains.

This function gets the status which indicates whether certain peripheral and the IO pads are in a latched state as a result of having been in POWERDOWN mode.

Parameters:

base – SPC peripheral base address.

Returns:

Current isolation status for each power domains. See _spc_power_domains for details.

static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base)#

Clears peripherals and I/O pads isolation flags for each power domains.

This function clears peripherals and I/O pads isolation flags for each power domains. After recovering from the POWERDOWN mode, user must invoke this function to release the I/O pads and certain peripherals to their normal run mode state. Before invoking this function, user must restore chip configuration in particular pin configuration for enabled WUU wakeup pins.

Parameters:

base – SPC peripheral base address.

static inline bool SPC_GetBusyStatusFlag(SPC_Type *base)#

Gets SPC busy status flag.

This function gets SPC busy status flag. When SPC executing any type of power mode transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set and this function returns true. When changing CORE LDO voltage level and DCDC voltage level in ACTIVE mode, the SPC busy status flag is set and this function return true.

Parameters:

base – SPC peripheral base address.

Returns:

Ack busy flag. true - SPC is busy. false - SPC is not busy.

static inline bool SPC_CheckLowPowerReqest(SPC_Type *base)#

Checks system low power request.

Note

Only when all power domains request low power mode entry, the result of this function is true. That means when all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register.

Parameters:

base – SPC peripheral base address.

Returns:

The system low power request check result.

true All power domains have requested low power mode and SPC has entered a low power state and power mode configuration are based on the LP_CFG configuration register.
false SPC in active mode and ACTIVE_CFG register control system power supply.

static inline void SPC_ClearLowPowerRequest(SPC_Type *base)#

Clears system low power request, set SPC in active mode.

Parameters:

base – SPC peripheral base address.

static inline spc_power_domain_low_power_mode_t SPC_GetRequestedLowPowerMode(SPC_Type *base)#

Check the last low-power mode that the power domain requested.

Parameters:

base – SPC peripheral base address.

Returns:

The last low-power mode that the power domain requested.

static inline bool SPC_CheckSwitchState(SPC_Type *base)#

Checks whether the power switch is on.

Parameters:

base – SPC peripheral base address.

Return values:

true – The power switch is on.
false – The power switch is off.

spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId)#

Gets selected power domain’s requested low power mode.

Parameters:

base – SPC peripheral base address.
powerDomainId – Power Domain Id, please refer to spc_power_domain_id_t.

Returns:

The selected power domain’s requested low power mode, please refer to spc_power_domain_low_power_mode_t.

static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId)#

Checks power domain’s low power request.

Parameters:

base – SPC peripheral base address.
powerDomainId – Power Domain Id, please refer to spc_power_domain_id_t.

Returns:

The result of power domain’s low power request.

true The selected power domain requests low power mode entry.
false The selected power domain does not request low power mode entry.

static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId)#

Clears selected power domain’s low power request flag.

Parameters:

base – SPC peripheral base address.
powerDomainId – Power Domain Id, please refer to spc_power_domain_id_t.

static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue)#

Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V.

Parameters:

base – SPC peripheral base address.
trimValue – Reference voltage trim value.

static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable)#

Enables/disables SRAM retention LDO.

Parameters:

base – SPC peripheral base address.
enable – Used to enable/disable SRAM LDO :
- true Enable SRAM LDO;
- false Disable SRAM LDO.

static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask)#

Parameters:

base – SPC peripheral base address.
mask – The OR’ed value of SRAM Array.

static inline void SPC_UnRetainSRAMArray(SPC_Type *base, uint8_t mask)#

Unretain SRAM array.

Parameters:

base – SPC peripheral base address.
mask – The OR’ed value of SRAM Array.

void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config)#

Configs Low power request output pin.

This function config the low power request output pin

Parameters:

base – SPC peripheral base address.
config – Pointer the spc_lowpower_request_config_t structure.

static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable)#

Enables/disables the integrated power switch manually.

Parameters:

base – SPC peripheral base address.
enable – Used to enable/disable the integrated power switch:
- true Enable the integrated power switch;
- false Disable the integrated power switch.

static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate)#

Enables/disables the integrated power switch automatically.

To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low power modes:

SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true);

Parameters:

base – SPC peripheral base address.
sleepGate – Enable the integrated power switch when chip enter low power modes:
- true SPC asserts an output pin at low-power entry to power-gate the switch;
- false SPC does not assert an output pin at low-power entry to power-gate the switch.
wakeupUngate – Enables the switch after wake-up from low power modes:
- true SPC asserts an output pin at low-power exit to power-ungate the switch;
- false SPC does not assert an output pin at low-power exit to power-ungate the switch.

void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config)#

Set SRAM operate voltage.

Parameters:

base – SPC peripheral base address.
config – The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage.

static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base)#

Gets the Bandgap mode in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

Bandgap mode in the type of spc_bandgap_mode_t enumeration.

static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base)#

Gets all voltage detectors status in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

All voltage detectors status in Active mode.

status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode)#

Configs Bandgap mode in Active mode.

Note

To disable bandgap in Active mode:

Disable all LVD’s and HVD’s in active mode;
Disable Glitch detect;
Configrue LDO’s and DCDC to low drive strength in active mode;
Invoke this function to disable bandgap in active mode; otherwise the error status will be reported.

Note

Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please take care of other system resources.

Parameters:

base – SPC peripheral base address.
mode – The Bandgap mode be selected.

Return values:

kStatus_SPC_BandgapModeWrong – The Bandgap can not be disabled in active mode.
kStatus_Success – Config Bandgap mode in Active power mode successful.

static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable)#

Enables/Disable the CMP Bandgap Buffer in Active mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable CMP Bandgap buffer. true - Enable Buffer Stored Reference voltage to CMP. false - Disable Buffer Stored Reference voltage to CMP.

static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay)#

Sets the delay when the regulators change voltage level in Active mode.

Parameters:

base – SPC peripheral base address.
delay – The number of SPC timer clock cycles.

status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config)#

Configs all settings of regulators in Active mode at a time.

Note

This function is used to overwrite all settings of regulators(including bandgap mode, regulators’ drive strength and voltage level) in active mode at a time.

Note

Enable/disable LVDs/HVDs before invoking this function.

Note

This function will check input parameters based on hardware restrictions before setting registers, if input parameters do not satisfy hardware restrictions the specific error will be reported.

Note

Some hardware restrictions not covered, application should be aware of this and follow this hardware restrictions otherwise some unkown issue may occur:

If Core LDO’s drive strength are set to same value in both Active mode and low power mode, the voltage level should also set to same value.
When switching Core LDO’s drive strength from low to normal, ensure the LDO_CORE high voltage level is set to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are enabled, an unexpected LVD can occur.

Note

If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group.

Parameters:

base – SPC peripheral base address.
config – Pointer to spc_active_mode_regulators_config_t structure.

Return values:

kStatus_Success – Config regulators in Active power mode successful.
kStatus_SPC_BandgapModeWrong – Based on input setting, bandgap can not be disabled.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_CORELDOLowDriveStrengthIgnore – Any of LVDs/HVDs kept enabled before invoking this function.
kStatus_SPC_SYSLDOOverDriveVoltageFail – Fail to regulator to Over Drive Voltage due to System VDD HVD is not disabled.
kStatus_SPC_SYSLDOLowDriveStrengthIgnore – Any of LVDs/HVDs kept enabled before invoking this function.
kStatus_SPC_CORELDOVoltageWrong – Core LDO and System LDO do not have same voltage level.

static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue)#

Enables analog modules in active mode.

Parameters:

base – SPC peripheral base address.
maskValue – The mask of analog modules to enable in active mode, should be the OR’ed value of spc_analog_module_control.

static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue)#

Disables analog modules in active mode.

Parameters:

base – SPC peripheral base address.
maskValue – The mask of analog modules to disable in active mode, should be the OR’ed value of spc_analog_module_control.

static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base)#

Gets enabled analog modules that enabled in active mode.

Parameters:

base – SPC peripheral base address.

Returns:

The mask of enabled analog modules that enabled in active mode.

static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base)#

Gets the Bandgap mode in Low Power mode.

Parameters:

base – SPC peripheral base address.

Returns:

Bandgap mode in the type of spc_bandgap_mode_t enumeration.

static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base)#

Gets the status of all voltage detectors in Low Power mode.

Parameters:

base – SPC peripheral base address.

Returns:

The status of all voltage detectors in low power mode.

static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable)#

Enables/Disables Low Power IREF in low power modes.

This function enables/disables Low Power IREF. Low Power IREF can only get disabled in Deep power down mode. In other low power modes, the Low Power IREF is always enabled.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable Low Power IREF. true - Enable Low Power IREF for Low Power modes. false - Disable Low Power IREF for Deep Power Down mode.

status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode)#

Configs Bandgap mode in Low Power mode.

Note

To disable Bandgap in Low-power mode:

Disable all LVD’s ad HVD’s in low power mode;
Disable Glitch detect in low power mode;
Configure LDO’s and DCDC to low drive strength in low power mode;
Disable bandgap in low power mode; Otherwise, the error status will be reported.

Note

Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please take care of other system resources.

Parameters:

base – SPC peripheral base address.
mode – The Bandgap mode be selected.

Return values:

kStatus_SPC_BandgapModeWrong – The bandgap mode setting in Low Power mode is wrong.
kStatus_Success – Config Bandgap mode in Low Power power mode successful.

static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable)#

Enables/disables SRAM_LDO deep power low power IREF.

Parameters:

base – SPC peripheral base address.
enable – Used to enable/disable low power IREF :
- true: Low Power IREF is enabled ;
- false: Low Power IREF is disabled for power saving.

static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable)#

Enables/Disables CMP Bandgap Buffer.

This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off in Deep Power Down mode.

Deprecated:: No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable CMP Bandgap buffer. true - Enable Buffer Stored Reference Voltage to CMP. false - Disable Buffer Stored Reference Voltage to CMP.

static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable)#

Enables/Disables CMP Bandgap Buffer.

This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off in Deep Power Down mode.

Deprecated:: No longer used.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable CMP Bandgap buffer. true - Enable Buffer Stored Reference Voltage to CMP. false - Disable Buffer Stored Reference Voltage to CMP.

static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable)#

Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes.

This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the external input CORE VDD to a lower voltage level to reduce internal leakage. IVS is invalid in Sleep or Deep power down mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable IVS. true - enable CORE VDD IVS in Power Down mode. false - disable CORE VDD IVS in Power Down mode.

static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay)#

Sets the delay when exit the low power modes.

Parameters:

base – SPC peripheral base address.
delay – The number of SPC timer clock cycles that the SPC waits on exit from low power modes.

status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config)#

Configs all settings of regulators in Low power mode at a time.

Note

This function is used to overwrite all settings of regulators(including bandgap mode, regulators’ drive strength and voltage level) in low power mode at a time.

Note

Enable/disable LVDs/HVDs before invoking this function.

Note

This function will check input parameters based on hardware restrictions before setting registers, if input parameters do not satisfy hardware restrictions the specific error will be reported.

Note

Some hardware restrictions not covered, application should be aware of this and follow this hardware restrictions otherwise some unkown issue may occur:

If Core LDO’s drive strength are set to same value in both Active mode and low power mode, the voltage level should also set to same value.
When switching Core LDO’s drive strength from low to normal, ensure the LDO_CORE high voltage level is set to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are enabled, an unexpected LVD can occur.

Note

If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group.

Parameters:

base – SPC peripheral base address.
config – Pointer to spc_lowpower_mode_regulators_config_t structure.

Return values:

kStatus_Success – Config regulators in Low power mode successful.
kStatus_SPC_BandgapModeWrong – The bandgap should not be disabled based on input settings.
kStatus_SPC_CORELDOLowDriveStrengthIgnore – Set driver strength to low will be ignored.
kStatus_SPC_SYSLDOLowDriveStrengthIgnore – Set driver strength to low will be ignored.
kStatus_SPC_CORELDOVoltageWrong – Core LDO and System LDO do not have same voltage level.

static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue)#

Enables analog modules in low power modes.

Parameters:

base – SPC peripheral base address.
maskValue – The mask of analog modules to enable in low power modes, should be OR’ed value of spc_analog_module_control.

static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue)#

Disables analog modules in low power modes.

Parameters:

base – SPC peripheral base address.
maskValue – The mask of analog modules to disable in low power modes, should be OR’ed value of spc_analog_module_control.

static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base)#

Gets enabled analog modules that enabled in low power modes.

Parameters:

base – SPC peripheral base address.

Returns:

The mask of enabled analog modules that enabled in low power modes.

static inline uint32_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base)#

Get Voltage Detect Status Flags.

Parameters:

base – SPC peripheral base address.

Returns:

Voltage Detect Status Flags. See _spc_voltage_detect_flags for details.

static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask)#

Clear Voltage Detect Status Flags.

Parameters:

base – SPC peripheral base address.
mask – The mask of the voltage detect status flags. See _spc_voltage_detect_flags for details.

void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config)#

Configs CORE voltage detect options.

Note

: Setting both the voltage detect interrupt and reset enable will cause interrupt to be generated on exit from reset. If those conditioned is not desired, interrupt/reset so only one is enabled.

Parameters:

base – SPC peripheral base address.
config – Pointer to spc_core_voltage_detect_config_t structure.

static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base)#

Locks Core voltage detect reset setting.

This function locks core voltage detect reset setting. After invoking this function any configuration of Core voltage detect reset will be ignored.

Parameters:

base – SPC peripheral base address.

static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base)#

Unlocks Core voltage detect reset setting.

This function unlocks core voltage detect reset setting. If locks the Core voltage detect reset setting, invoking this function to unlock.

Parameters:

base – SPC peripheral base address.

status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the Core Low Voltage Detector in Active mode.

Note

If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable Core LVD. true - Enable Core Low voltage detector in active mode. false - Disable Core Low voltage detector in active mode.

Return values:

kStatus_Success – Enable/Disable Core Low Voltage Detect successfully.

status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the Core Low Voltage Detector in Low Power mode.

This function enables/disables the Core Low Voltage Detector. If enabled the Core Low Voltage detector. The Bandgap mode in low power mode must be programmed so that Bandgap is enabled.

Note

If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Low Power mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable Core HVD. true - Enable Core Low voltage detector in low power mode. false - Disable Core Low voltage detector in low power mode.

Return values:

kStatus_Success – Enable/Disable Core Low Voltage Detect in low power mode successfully.

status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the Core High Voltage Detector in Active mode.

Note

If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable Core HVD. true - Enable Core High voltage detector in active mode. false - Disable Core High voltage detector in active mode.

Return values:

kStatus_Success – Enable/Disable Core High Voltage Detect successfully.

status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the Core High Voltage Detector in Low Power mode.

This function enables/disables the Core High Voltage Detector. If enabled the Core High Voltage detector. The Bandgap mode in low power mode must be programmed so that Bandgap is enabled.

Note

If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in low power mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable Core HVD. true - Enable Core High voltage detector in low power mode. false - Disable Core High voltage detector in low power mode.

Return values:

kStatus_Success – Enable/Disable Core High Voltage Detect in low power mode successfully.

void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level)#

Set system VDD Low-voltage level selection.

This function selects the system VDD low-voltage level. Changing system VDD low-voltage level must be done after disabling the System VDD low voltage reset and interrupt.

Deprecated:: In latest RM, reserved for all devices, will removed in next release.

Parameters:

base – SPC peripheral base address.
level – System VDD Low-Voltage level selection.

void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config)#

Configs SYS voltage detect options.

This function config SYS voltage detect options.

Note

: Setting both the voltage detect interrupt and reset enable will cause interrupt to be generated on exit from reset. If those conditioned is not desired, interrupt/reset so only one is enabled.

Parameters:

base – SPC peripheral base address.
config – Pointer to spc_system_voltage_detect_config_t structure.

static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base)#

Lock System voltage detect reset setting.

This function locks system voltage detect reset setting. After invoking this function any configuration of System Voltage detect reset will be ignored.

Parameters:

base – SPC peripheral base address.

static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base)#

Unlock System voltage detect reset setting.

This function unlocks system voltage detect reset setting. If locks the System voltage detect reset setting, invoking this function to unlock.

Parameters:

base – SPC peripheral base address.

status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the System High Voltage Detector in Active mode.

Note

If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Active mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable System HVD. true - Enable System High voltage detector in active mode. false - Disable System High voltage detector in active mode.

Return values:

kStatus_Success – Enable/Disable System High Voltage Detect successfully.

status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disable the System Low Voltage Detector in Active mode.

Note

If the System_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Active mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable System LVD. true - Enable System Low voltage detector in active mode. false - Disable System Low voltage detector in active mode.

Return values:

kStatus_Success – Enable/Disable the System Low Voltage Detect successfully.

status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the System High Voltage Detector in Low Power mode.

Note

If the System_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Low Power mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable System HVD. true - Enable System High voltage detector in low power mode. false - Disable System High voltage detector in low power mode.

Return values:

kStatus_Success – Enable/Disable System High Voltage Detect in low power mode successfully.

status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the System Low Voltage Detector in Low Power mode.

Note

If the System_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Low Power mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable System HVD. true - Enable System Low voltage detector in low power mode. false - Disable System Low voltage detector in low power mode.

Return values:

kStatus_Success – Enables System Low Voltage Detect in low power mode successfully.

void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level)#

Set IO VDD Low-Voltage level selection.

This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level must be done after disabling the IO VDD low voltage reset and interrupt.

Parameters:

base – SPC peripheral base address.
level – IO VDD Low-voltage level selection.

void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config)#

Configs IO voltage detect options.

This function config IO voltage detect options.

Note

: Setting both the voltage detect interrupt and reset enable will cause interrupt to be generated on exit from reset. If those conditioned is not desired, interrupt/reset so only one is enabled.

Parameters:

base – SPC peripheral base address.
config – Pointer to spc_voltage_detect_config_t structure.

static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base)#

Lock IO Voltage detect reset setting.

This function locks IO voltage detect reset setting. After invoking this function any configuration of system voltage detect reset will be ignored.

Parameters:

base – SPC peripheral base address.

static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base)#

Unlock IO voltage detect reset setting.

This function unlocks IO voltage detect reset setting. If locks the IO voltage detect reset setting, invoking this function to unlock.

Parameters:

base – SPC peripheral base address.

status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the IO High Voltage Detector in Active mode.

Note

If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Active mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable IO HVD. true - Enable IO High voltage detector in active mode. false - Disable IO High voltage detector in active mode.

Return values:

kStatus_Success – Enable/Disable IO High Voltage Detect successfully.

status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the IO Low Voltage Detector in Active mode.

Note

If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Active mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable IO LVD. true - Enable IO Low voltage detector in active mode. false - Disable IO Low voltage detector in active mode.

Return values:

kStatus_Success – Enable IO Low Voltage Detect successfully.

status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the IO High Voltage Detector in Low Power mode.

Note

If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Low Power mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable IO HVD. true - Enable IO High voltage detector in low power mode. false - Disable IO High voltage detector in low power mode.

Return values:

kStatus_Success – Enable IO High Voltage Detect in low power mode successfully.

status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable)#

Enables/Disables the IO Low Voltage Detector in Low Power mode.

Note

If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled and the drive strength of each regulator must not set to low in Low Power mode.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable IO LVD. true - Enable IO Low voltage detector in low power mode. false - Disable IO Low voltage detector in low power mode.

Return values:

kStatus_Success – Enable/Disable IO Low Voltage Detect in low power mode successfully.

void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask)#

Configs external voltage domains.

This function configs external voltage domains isolation.

Parameters:

base – SPC peripheral base address.
lowPowerIsoMask – The mask of external domains isolate enable during low power mode. Please read the Reference Manual for the Bitmap.
IsoMask – The mask of external domains isolate. Please read the Reference Manual for the Bitmap.

static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base)#

Gets External Domains status.

Parameters:

base – SPC peripheral base address.

Returns:

The status of each external domain.

static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable)#

Enable/Disable Core LDO regulator.

Note

The CORE LDO enable bit is write-once.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable CORE LDO Regulator. true - Enable CORE LDO Regulator. false - Disable CORE LDO Regulator.

static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown)#

Enable/Disable the CORE LDO Regulator pull down in Deep Power Down.

Note

This function only useful when enabled the CORE LDO Regulator.

Parameters:

base – SPC peripheral base address.
pulldown – Enable/Disable CORE LDO pulldown in Deep Power Down mode. true - CORE LDO Regulator will discharge in Deep Power Down mode. false - CORE LDO Regulator will not discharge in Deep Power Down mode.

status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option)#

Configs Core LDO Regulator in Active mode.

Note

The bandgap must be enabled before invoking this function.

Note

To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously.

Parameters:

base – SPC peripheral base address.
option – Pointer to the spc_active_mode_core_ldo_option_t structure.

Return values:

kStatus_Success – Config Core LDO regulator in Active power mode successful.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_BandgapModeWrong – Bandgap should be enabled before invoking this function.
kStatus_SPC_CORELDOLowDriveStrengthIgnore – To set Core LDO as low drive strength, all LVDs/HVDs must be disabled before invoking this function.

status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel)#

Set Core LDO Regulator Voltage level in Active mode.

Note

In active mode, the Core LDO voltage level should only be changed when the Core LDO is in normal drive strength.

Note

Update Core LDO voltage level will set Busy flag, this function return only when busy flag is cleared by hardware

Parameters:

base – SPC peripheral base address.
voltageLevel – Specify the voltage level of CORE LDO Regulator in Active mode, please refer to spc_core_ldo_voltage_level_t.

Return values:

kStatus_SPC_CORELDOVoltageSetFail – The drive strength of Core LDO is not normal.
kStatus_Success – Set Core LDO regulator voltage level in Active power mode successful.

static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base)#

Gets CORE LDO Regulator Voltage level.

This function returns the voltage level of CORE LDO Regulator in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

Voltage level of CORE LDO in type of spc_core_ldo_voltage_level_t enumeration.

status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength)#

Set Core LDO VDD Regulator Drive Strength in Active mode.

Parameters:

base – SPC peripheral base address.
driveStrength – Specify the drive strength of CORE LDO Regulator in Active mode, please refer to spc_core_ldo_drive_strength_t.

Return values:

kStatus_Success – Set Core LDO regulator drive strength in Active power mode successful.
kStatus_SPC_CORELDOLowDriveStrengthIgnore – If any voltage detect enabled, core_ldo’s drive strength can not set to low.
kStatus_SPC_BandgapModeWrong – The selected bandgap mode is not allowed.

static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base)#

Gets CORE LDO VDD Regulator Drive Strength in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

Drive Strength of CORE LDO regulator in Active mode, please refer to spc_core_ldo_drive_strength_t.

status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option)#

Configs CORE LDO Regulator in low power mode.

This function configs CORE LDO Regulator in Low Power mode. If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap must be programmed to select bandgap enabled. Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE LDO Drive Strength set as Normal.

Parameters:

base – SPC peripheral base address.
option – Pointer to the spc_lowpower_mode_core_ldo_option_t structure.

Return values:

kStatus_Success – Config Core LDO regulator in power mode successfully.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_CORELDOLowDriveStrengthIgnore – Set driver strength to low will be ignored.
#kStatus_SPC_CORELDOVoltageSetFail. – Fail to change Core LDO voltage level.

status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel)#

Set Core LDO VDD Regulator Voltage level in Low power mode.

Note

If CORE LDO’s drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power mode must be same.

Note

Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as Normal.

Parameters:

base – SPC peripheral base address.
voltageLevel – Voltage level of CORE LDO Regulator in Low power mode, please refer to spc_core_ldo_voltage_level_t.

Return values:

kStatus_SPC_CORELDOVoltageWrong – Voltage level in active mode and low power mode is not same.
kStatus_Success – Set Core LDO regulator voltage level in Low power mode successful.
kStatus_SPC_CORELDOVoltageSetFail – Fail to update voltage level because drive strength is incorrect.

static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base)#

Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes.

Parameters:

base – SPC peripheral base address.

Returns:

The CORE LDO VDD Regulator’s voltage level.

status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength)#

Set Core LDO VDD Regulator Drive Strength in Low power mode.

Parameters:

base – SPC peripheral base address.
driveStrength – Specify drive strength of CORE LDO in low power mode.

Return values:

kStatus_SPC_CORELDOLowDriveStrengthIgnore – Some voltage detect enabled, CORE LDO’s drive strength can not set as low.
kStatus_Success – Set Core LDO regulator drive strength in Low power mode successful.
kStatus_SPC_BandgapModeWrong – Bandgap is disabled when attempt to set CORE LDO work as normal drive strength.

static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base)#

Gets CORE LDO VDD Drive Strength for Low Power modes.

Parameters:

base – SPC peripheral base address.

Returns:

The CORE LDO’s VDD Drive Strength.

static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable)#

Enable/Disable System LDO regulator.

Note

The SYSTEM LDO enable bit is write-once.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable System LDO Regulator. true - Enable System LDO Regulator. false - Disable System LDO Regulator.

static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink)#

Enable/Disable current sink feature of System LDO Regulator.

Parameters:

base – SPC peripheral base address.
sink – Enable/Disable current sink feature. true - Enable current sink feature of System LDO Regulator. false - Disable current sink feature of System LDO Regulator.

status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option)#

Configs System LDO VDD Regulator in Active mode.

Note

If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed to a value that enables the bandgap.

Note

If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will be ignored.

Note

If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal.

Note

If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. Otherwise it will be fail to regulator to Over Drive Voltage.

Parameters:

base – SPC peripheral base address.
option – Pointer to the spc_active_mode_sys_ldo_option_t structure.

Return values:

kStatus_Success – Config System LDO regulator in Active power mode successful.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_BandgapModeWrong – The bandgap is not enabled before invoking this function.
kStatus_SPC_SYSLDOOverDriveVoltageFail – HVD of System VDD is not disable before setting to Over Drive voltage.
kStatus_SPC_SYSLDOLowDriveStrengthIgnore – Set System LDO VDD regulator’s driver strength to Low will be ignored.

status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel)#

Set System LDO Regulator voltage level in Active mode.

Note

The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the life of chip.

Parameters:

base – SPC peripheral base address.
voltageLevel – Specify the voltage level of System LDO Regulator in Active mode.

Return values:

kStatus_Success – Set System LDO Regulator voltage level in Active mode successfully.
kStatus_SPC_SYSLDOOverDriveVoltageFail – Must disable system LDO high voltage detector before specifing overdrive voltage.

static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base)#

Get System LDO Regulator voltage level in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

System LDO Regulator voltage level in Active mode, please refer to spc_sys_ldo_voltage_level_t.

status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength)#

Set System LDO Regulator Drive Strength in Active mode.

Parameters:

base – SPC peripheral base address.
driveStrength – Specify the drive strength of System LDO Regulator in Active mode.

Return values:

kStatus_Success – Set System LDO Regulator drive strength in Active mode successfully.
kStatus_SPC_SYSLDOLowDriveStrengthIgnore – Attempt to specify low drive strength is ignored due to any voltage detect feature is enabled in active mode.
kStatus_SPC_BandgapModeWrong – Bandgap mode in Active mode must be programmed to a value that enables the bandgap if attempt to specify normal drive strength.

static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base)#

Get System LDO Regulator Drive Strength in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

System LDO regulator drive strength in Active mode, please refer to spc_sys_ldo_drive_strength_t.

status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option)#

Configs System LDO regulator in low power modes.

This function configs System LDO regulator in low power modes. If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power mode must be programmed to a value that enables the Bandgap. If any High voltage detectors or Low Voltage detectors are kept enabled, configuration to set System LDO Regulator drive strength as Low will be ignored.

Parameters:

base – SPC peripheral base address.
option – Pointer to spc_lowpower_mode_sys_ldo_option_t structure.

Return values:

kStatus_Success – Config System LDO regulator in Low Power Mode successfully.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_SYSLDOLowDriveStrengthIgnore – Set driver strength to low will be ignored.

status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength)#

Set System LDO Regulator drive strength in Low Power Mode.

Parameters:

base – SPC peripheral base address.
driveStrength – Specify the drive strength of System LDO Regulator in Low Power Mode.

Return values:

kStatus_Success – Set System LDO Regulator drive strength in Low Power Mode successfully.
kStatus_SPC_SYSLDOLowDriveStrengthIgnore – Attempt to specify low drive strength is ignored due to any voltage detect feature is enabled in low power mode.
kStatus_SPC_BandgapModeWrong – Bandgap mode in low power mode must be programmed to a value that enables the bandgap if attempt to specify normal drive strength.

static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base)#

Get System LDO Regulator drive strength in Low Power Mode.

Parameters:

base – SPC peripheral base address.

Returns:

System LDO regulator drive strength in Low Power Mode, please refer to spc_sys_ldo_drive_strength_t.

static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable)#

Enable/Disable DCDC Regulator.

Note

The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event.

Parameters:

base – SPC peripheral base address.
enable – Enable/Disable DCDC Regulator. true - Enable DCDC Regulator. false - Disable DCDC Regulator.

void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config)#

Config DCDC Burst options.

Parameters:

base – SPC peripheral base address.
config – Pointer to spc_dcdc_burst_config_t structure.

static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base)#

Trigger a software burst request to DCDC.

Parameters:

base – SPC peripheral base address.

static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base)#

Check if burst acknowlege flag is asserted.

Parameters:

base – SPC peripheral base address.

Return values:

false – DCDC burst not complete.
true – DCDC burst complete.

static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base)#

Clear DCDC busrt acknowledge flag.

Parameters:

base – SPC periphral base address.

void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count)#

Set the count value of the reference clock to configure the period of DCDC not active.

Note

This function is only useful when DCDC’s drive strength is set as pulse refresh.

Note

The pulse duration(time between on and off) is: reference clock period * (count + 2).

Parameters:

base – SPC peripheral base address.
count – The count value, 16 bit width.

static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable)#

Enable a bleed resistor to discharge DCDC output when DCDC is disabled.

Parameters:

base – SPC peripheral base address.
enable – Used to enable/disable bleed resistor.

status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option)#

Configs DCDC_CORE Regulator in Active mode.

Note

When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.

Parameters:

base – SPC peripheral base address.
option – Pointer to the spc_active_mode_dcdc_option_t structure.

Return values:

kStatus_Success – Config DCDC regulator in Active power mode successful.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_BandgapModeWrong – Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.

static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel)#

Set DCDC_CORE Regulator voltage level in Active mode.

Note

When changing the DCDC output voltage level, take care to change the CORE LDO voltage level.

Parameters:

base – SPC peripheral base address.
voltageLevel – Specify the DCDC_CORE Regulator voltage level, please refer to spc_dcdc_voltage_level_t.

static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base)#

Get DCDC_CORE Regulator voltage level in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

DCDC_CORE Regulator voltage level, please refer to spc_dcdc_voltage_level_t.

status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength)#

Set DCDC_CORE Regulator drive strength in Active mode.

Note

To set DCDC drive strength as Normal, the bandgap must be enabled.

Parameters:

base – SPC peripheral base address.
driveStrength – Specify the DCDC_CORE regulator drive strength, please refer to spc_dcdc_drive_strength_t.

Return values:

kStatus_Success – Set DCDC_CORE Regulator drive strength in Active mode successfully.
kStatus_SPC_BandgapModeWrong – Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.

static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base)#

Get DCDC_CORE Regulator drive strength in Active mode.

Parameters:

base – SPC peripheral base address.

Returns:

DCDC_CORE Regulator drive strength, please refer to spc_dcdc_drive_strength_t.

status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option)#

Configs DCDC_CORE Regulator in Low power modes.

Note

If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed to a value that enables the Bandgap.

Note

In Deep Power Down mode, DCDC regulator is always turned off.

Parameters:

base – SPC peripheral base address.
option – Pointer to the spc_lowpower_mode_dcdc_option_t structure.

Return values:

kStatus_Success – Config DCDC regulator in low power mode successfully.
kStatus_SPC_Busy – The SPC instance is busy to execute any type of power mode transition.
kStatus_SPC_BandgapModeWrong – The bandgap mode setting in Low Power mode is wrong.

status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength)#

Set DCDC_CORE Regulator drive strength in Low power mode.

Note

To set drive strength as normal, the bandgap must be enabled.

Parameters:

base – SPC peripheral base address.
driveStrength – Specify the DCDC_CORE Regulator drive strength, please refer to spc_dcdc_drive_strength_t.

Return values:

kStatus_Success – Set DCDC_CORE Regulator drive strength in Low power mode successfully.
kStatus_SPC_BandgapModeWrong – Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled.

static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base)#

Get DCDC_CORE Regulator drive strength in Low power mode.

Parameters:

base – SPC peripheral base address.

Returns:

DCDC_CORE Regulator drive strength, please refer to spc_dcdc_drive_strength_t.

static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel)#

Set DCDC_CORE Regulator voltage level in Low power mode.

Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1.

Note

To change DCDC level in Low-Power mode:

Configure LP_CFG[DCDC_VDD_LVL] to desired level;
Configure LP_CFG[DCDC_VDD_DS] to low driver strength;

Note

After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed, if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level.

Parameters:

base – SPC peripheral base address.
voltageLevel – Specify the DCDC_CORE Regulator voltage level, please refer to spc_dcdc_voltage_level_t.

static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base)#

Get DCDC_CORE Regulator voltage level in Low power mode.

Parameters:

base – SPC peripheral base address.

Returns:

DCDC_CORE Regulator voltage level, please refer to spc_dcdc_voltage_level_t.

FSL_SPC_DRIVER_VERSION#: SPC driver version 2.12.1.

SPC status enumeration.

Note

Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual to check.

Values:

enumerator kStatus_SPC_Busy#: The SPC instance is busy executing any type of power mode transition.

enumerator kStatus_SPC_DCDCLowDriveStrengthIgnore#: DCDC Low drive strength setting be ignored for LVD/HVD enabled.

enumerator kStatus_SPC_DCDCPulseRefreshModeIgnore#: DCDC Pulse Refresh Mode drive strength setting be ignored for LVD/HVD enabled.

enumerator kStatus_SPC_SYSLDOOverDriveVoltageFail#: SYS LDO regulate to Over drive voltage failed for SYS LDO HVD must be disabled.

enumerator kStatus_SPC_SYSLDOLowDriveStrengthIgnore#: SYS LDO Low driver strength setting be ignored for LDO LVD/HVD enabled.

enumerator kStatus_SPC_CORELDOLowDriveStrengthIgnore#: CORE LDO Low driver strength setting be ignored for LDO LVD/HVD enabled.

enumerator kStatus_SPC_BandgapModeWrong#: Selected Bandgap Mode wrong.

enumerator kStatus_SPC_CORELDOVoltageWrong#: Core LDO voltage is wrong.

enumerator kStatus_SPC_CORELDOVoltageSetFail#: Core LDO voltage set fail.

enumerator kStatus_SPC_CORELDOVoltageDetectWrong#: Settings of CORE_LDO voltage detection is not allowed.

enumerator kStatus_SPC_DCDCCoreLdoVoltageMisMatch#: Target voltage level of DCDC not equal to CORE_LDO.

enum _spc_voltage_detect_flags#

Voltage Detect Status Flags.

Values:

enumerator kSPC_IOVDDHighVoltageDetectFlag#: IO VDD High-Voltage detect flag.

enumerator kSPC_IOVDDLowVoltageDetectFlag#: IO VDD Low-Voltage detect flag.

enumerator kSPC_SystemVDDHighVoltageDetectFlag#: System VDD High-Voltage detect flag.

enumerator kSPC_SystemVDDLowVoltageDetectFlag#: System VDD Low-Voltage detect flag.

enumerator kSPC_CoreVDDHighVoltageDetectFlag#: Core VDD High-Voltage detect flag.

enumerator kSPC_CoreVDDLowVoltageDetectFlag#: Core VDD Low-Voltage detect flag.

enum _spc_power_domains#

SPC power domain isolation status.

Note

Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to check.

Values:

enumerator kSPC_MAINPowerDomainRetain#: Peripherals and IO pads retain in MAIN Power Domain.

enumerator kSPC_WAKEPowerDomainRetain#: Peripherals and IO pads retain in WAKE Power Domain.

enum _spc_analog_module_control#

The enumeration of all analog module that can be controlled by SPC in active or low-power modes.

Note

Enumerations may not suitable for all devices, please check the specific device’s RM for supported analog modules.

Values:

enumerator kSPC_controlVref#: Enable/disable VREF in active or low-power modes.

enumerator kSPC_controlUsb3vDet#: Enable/disable USB3V_Det in active or low-power modes.

enumerator kSPC_controlVbat#: Enable/disable VBAT in active or low-power modes.

enumerator kSPC_controlDac0#: Enable/disable DAC0 in active or low-power modes.

enumerator kSPC_controlDac1#: Enable/disable DAC1 in active or low-power modes.

enumerator kSPC_controlDac2#: Enable/disable DAC2 in active or low-power modes.

enumerator kSPC_controlOpamp0#: Enable/disable OPAMP0 in active or low-power modes.

enumerator kSPC_controlOpamp1#: Enable/disable OPAMP1 in active or low-power modes.

enumerator kSPC_controlOpamp2#: Enable/disable OPAMP2 in active or low-power modes.

enumerator kSPC_controlOpamp3#: Enable/disable OPAMP3 in active or low-power modes.

enumerator kSPC_controlTsi0#: Enable/disable TSI0 in active or low-power modes.

enumerator kSPC_controlCmp0#: Enable/disable CMP0 in active or low-power modes.

enumerator kSPC_controlCmp1#: Enable/disable CMP1 in active or low-power modes.

enumerator kSPC_controlCmp2#: Enable/disable CMP2 in active or low-power modes.

enumerator kSPC_controlCmp0Dac#: Enable/disable CMP0_DAC in active or low-power modes.

enumerator kSPC_controlCmp1Dac#: Enable/disable CMP1_DAC in active or low-power modes.

enumerator kSPC_controlCmp2Dac#: Enable/disable CMP2_DAC in active or low-power modes.

enumerator kSPC_controlAllModules#: Enable/disable all modules in active or low-power modes.

enum _spc_power_domain_id#

The enumeration of spc power domain, the connected power domain is chip specfic, please refer to chip’s RM for details.

Values:

enumerator kSPC_PowerDomain0#: Power domain0, the connected power domain is chip specific.

enumerator kSPC_PowerDomain1#: Power domain1, the connected power domain is chip specific.

enum _spc_power_domain_low_power_mode#

The enumeration of Power domain’s low power mode.

Values:

enumerator kSPC_SleepWithSYSClockRunning#: Power domain request SLEEP mode with SYS clock running.

enumerator kSPC_DeepSleepWithSysClockOff#: Power domain request deep sleep mode with system clock off.

enumerator kSPC_PowerDownWithSysClockOff#: Power domain request power down mode with system clock off.

enumerator kSPC_DeepPowerDownWithSysClockOff#: Power domain request deep power down mode with system clock off.

enum _spc_lowPower_request_pin_polarity#

SPC low power request output pin polarity.

Values:

enumerator kSPC_HighTruePolarity#: Control the High Polarity of the Low Power Reqest Pin.

enumerator kSPC_LowTruePolarity#: Control the Low Polarity of the Low Power Reqest Pin.

enum _spc_lowPower_request_output_override#

SPC low power request output override.

Values:

enumerator kSPC_LowPowerRequestNotForced#: Not Forced.

enumerator kSPC_LowPowerRequestReserved#: Reserved.

enumerator kSPC_LowPowerRequestForcedLow#: Forced Low (Ignore LowPower request output polarity setting.)

enumerator kSPC_LowPowerRequestForcedHigh#: Forced High (Ignore LowPower request output polarity setting.)

enum _spc_bandgap_mode#

SPC Bandgap mode enumeration in Active mode or Low Power mode.

Values:

enumerator kSPC_BandgapDisabled#: Bandgap disabled.

enumerator kSPC_BandgapEnabledBufferDisabled#: Bandgap enabled with Buffer disabled.

enumerator kSPC_BandgapEnabledBufferEnabled#: Bandgap enabled with Buffer enabled.

enumerator kSPC_BandgapReserved#: Reserved.

enum _spc_dcdc_voltage_level#

DCDC regulator voltage level enumeration in Active mode or Low Power Mode.

Note

kSPC_DCDC_RetentionVoltage not supported for all power modes.

Values:

enumerator kSPC_DCDC_RetentionVoltage#: DCDC_CORE Regulator regulate to retention Voltage(Only supportedin low power modes)

enumerator kSPC_DCDC_MidVoltage#: DCDC_CORE Regulator regulate to Mid Voltage(1.0V).

enumerator kSPC_DCDC_NormalVoltage#: DCDC_CORE Regulator regulate to Normal Voltage(1.1V).

enumerator kSPC_DCDC_OverdriveVoltage#: DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V).

enum _spc_dcdc_drive_strength#

DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode.

Note

Different drive strength differ in these DCDC characterstics: Maximum load current Quiescent current Transient response.

Values:

enumerator kSPC_DCDC_PulseRefreshMode#: DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode, This enum member is only useful for Low Power Mode config, please note that pluse refresh mode is invalid in SLEEP mode.

enumerator kSPC_DCDC_LowDriveStrength#: DCDC_CORE regulator Drive Strength set to low.

enumerator kSPC_DCDC_NormalDriveStrength#: DCDC_CORE regulator Drive Strength set to Normal.

enum _spc_sys_ldo_voltage_level#

SYS LDO regulator voltage level enumeration in Active mode.

Values:

enumerator kSPC_SysLDO_NormalVoltage#: SYS LDO VDD Regulator regulate to Normal Voltage(1.8V).

enumerator kSPC_SysLDO_OverDriveVoltage#: SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V).

enum _spc_sys_ldo_drive_strength#

SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode.

Values:

enumerator kSPC_SysLDO_LowDriveStrength#: SYS LDO VDD regulator Drive Strength set to low.

enumerator kSPC_SysLDO_NormalDriveStrength#: SYS LDO VDD regulator Drive Strength set to Normal.

enum _spc_core_ldo_voltage_level#

Core LDO regulator voltage level enumeration in Active mode or Low Power mode.

Values:

enumerator kSPC_CoreLDO_UnderDriveVoltage#

Deprecated:: , to align with description of latest RM, please use kSPC_Core_LDO_RetentionVoltage as instead.

enumerator kSPC_Core_LDO_RetentionVoltage#: Core LDO VDD regulator regulate to retention voltage, please note that only useful in low power modes and not all devices support this options please refer to devices’ RM for details.

enumerator kSPC_CoreLDO_MidDriveVoltage#: Core LDO VDD regulator regulate to Mid Drive Voltage.

enumerator kSPC_CoreLDO_NormalVoltage#: Core LDO VDD regulator regulate to Normal Voltage.

enumerator kSPC_CoreLDO_OverDriveVoltage#: Core LDO VDD regulator regulate to overdrive Voltage.

enum _spc_core_ldo_drive_strength#

CORE LDO VDD regulator Drive Strength enumeration in Low Power mode.

Values:

enumerator kSPC_CoreLDO_LowDriveStrength#: Core LDO VDD regulator Drive Strength set to low.

enumerator kSPC_CoreLDO_NormalDriveStrength#: Core LDO VDD regulator Drive Strength set to Normal.

enum _spc_low_voltage_level_select#

IO VDD Low-Voltage Level Select.

Values:

enumerator kSPC_LowVoltageNormalLevel#

Deprecated:: , please use kSPC_LowVoltageHighRange as instead.

enumerator kSPC_LowVoltageSafeLevel#

Deprecated:: , please use kSPC_LowVoltageLowRange as instead.

enumerator kSPC_LowVoltageHighRange#: High range LVD threshold.

enumerator kSPC_LowVoltageLowRange#: Low range LVD threshold.

enum _spc_sram_operate_voltage#

The list of the operating voltage for the SRAM’s read/write timing margin.

Values:

enumerator kSPC_sramOperateAt1P0V#: SRAM configured for 1.0V operation.

enumerator kSPC_sramOperateAt1P1V#: SRAM configured for 1.1V operation.

enumerator kSPC_sramOperateAt1P2V#: SRAM configured for 1.2V operation.

typedef enum _spc_power_domain_id spc_power_domain_id_t#: The enumeration of spc power domain, the connected power domain is chip specfic, please refer to chip’s RM for details.

typedef enum _spc_power_domain_low_power_mode spc_power_domain_low_power_mode_t#: The enumeration of Power domain’s low power mode.

typedef enum _spc_lowPower_request_pin_polarity spc_lowpower_request_pin_polarity_t#: SPC low power request output pin polarity.

typedef enum _spc_lowPower_request_output_override spc_lowpower_request_output_override_t#: SPC low power request output override.

typedef enum _spc_bandgap_mode spc_bandgap_mode_t#: SPC Bandgap mode enumeration in Active mode or Low Power mode.

typedef enum _spc_dcdc_voltage_level spc_dcdc_voltage_level_t#: DCDC regulator voltage level enumeration in Active mode or Low Power Mode.

Note

kSPC_DCDC_RetentionVoltage not supported for all power modes.

typedef enum _spc_dcdc_drive_strength spc_dcdc_drive_strength_t#: DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode.

Note

Different drive strength differ in these DCDC characterstics: Maximum load current Quiescent current Transient response.

typedef enum _spc_sys_ldo_voltage_level spc_sys_ldo_voltage_level_t#: SYS LDO regulator voltage level enumeration in Active mode.

typedef enum _spc_sys_ldo_drive_strength spc_sys_ldo_drive_strength_t#: SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode.

typedef enum _spc_core_ldo_voltage_level spc_core_ldo_voltage_level_t#: Core LDO regulator voltage level enumeration in Active mode or Low Power mode.

typedef enum _spc_core_ldo_drive_strength spc_core_ldo_drive_strength_t#: CORE LDO VDD regulator Drive Strength enumeration in Low Power mode.

typedef enum _spc_low_voltage_level_select spc_low_voltage_level_select_t#: IO VDD Low-Voltage Level Select.

typedef enum _spc_sram_operate_voltage spc_sram_operate_voltage_t#: The list of the operating voltage for the SRAM’s read/write timing margin.

typedef struct _spc_sram_voltage_config spc_sram_voltage_config_t#

typedef struct _spc_lowpower_request_config spc_lowpower_request_config_t#: Low Power Request output pin configuration.

typedef struct _spc_active_mode_core_ldo_option spc_active_mode_core_ldo_option_t#: Core LDO regulator options in Active mode.

typedef struct _spc_active_mode_sys_ldo_option spc_active_mode_sys_ldo_option_t#: System LDO regulator options in Active mode.

typedef struct _spc_active_mode_dcdc_option spc_active_mode_dcdc_option_t#: DCDC regulator options in Active mode.

typedef struct _spc_lowpower_mode_core_ldo_option spc_lowpower_mode_core_ldo_option_t#: Core LDO regulator options in Low Power mode.

typedef struct _spc_lowpower_mode_sys_ldo_option spc_lowpower_mode_sys_ldo_option_t#: System LDO regulator options in Low Power mode.

typedef struct _spc_lowpower_mode_dcdc_option spc_lowpower_mode_dcdc_option_t#: DCDC regulator options in Low Power mode.

typedef struct _spc_dcdc_burst_config spc_dcdc_burst_config_t#

DCDC Burst configuration.

Deprecated:: Do not recommend to use this structure.

typedef struct _spc_voltage_detect_option spc_voltage_detect_option_t#: CORE/SYS/IO VDD Voltage Detect options.

typedef struct _spc_core_voltage_detect_config spc_core_voltage_detect_config_t#: Core Voltage Detect configuration.

typedef struct _spc_system_voltage_detect_config spc_system_voltage_detect_config_t#: System Voltage Detect Configuration.

typedef struct _spc_io_voltage_detect_config spc_io_voltage_detect_config_t#: IO Voltage Detect Configuration.

typedef struct _spc_active_mode_regulators_config spc_active_mode_regulators_config_t#: Active mode configuration.

typedef struct _spc_lowpower_mode_regulators_config spc_lowpower_mode_regulators_config_t#: Low Power Mode configuration.

SPC_EVD_CFG_REG_EVDISO_SHIFT#

SPC_EVD_CFG_REG_EVDLPISO_SHIFT#

SPC_EVD_CFG_REG_EVDSTAT_SHIFT#

SPC_EVD_CFG_REG_EVDISO(x)#

SPC_EVD_CFG_REG_EVDLPISO(x)#

SPC_EVD_CFG_REG_EVDSTAT(x)#

struct _spc_sram_voltage_config#

Public Members

spc_sram_operate_voltage_t operateVoltage#: Specifies the operating voltage for the SRAM’s read/write timing margin.

bool requestVoltageUpdate#: Used to control whether request an SRAM trim value change.

struct _spc_lowpower_request_config#

#include <fsl_spc.h>

Low Power Request output pin configuration.

Public Members

bool enable#: Low Power Request Output enable.

spc_lowpower_request_pin_polarity_t polarity#: Low Power Request Output pin polarity select.

spc_lowpower_request_output_override_t override#: Low Power Request Output Override.

struct _spc_active_mode_core_ldo_option#

#include <fsl_spc.h>

Core LDO regulator options in Active mode.

Public Members

spc_core_ldo_voltage_level_t CoreLDOVoltage#: Core LDO Regulator Voltage Level selection in Active mode.

spc_core_ldo_drive_strength_t CoreLDODriveStrength#: Core LDO Regulator Drive Strength selection in Active mode

struct _spc_active_mode_sys_ldo_option#

#include <fsl_spc.h>

System LDO regulator options in Active mode.

Public Members

spc_sys_ldo_voltage_level_t SysLDOVoltage#: System LDO Regulator Voltage Level selection in Active mode.

spc_sys_ldo_drive_strength_t SysLDODriveStrength#: System LDO Regulator Drive Strength selection in Active mode.

struct _spc_active_mode_dcdc_option#

#include <fsl_spc.h>

DCDC regulator options in Active mode.

Public Members

spc_dcdc_voltage_level_t DCDCVoltage#: DCDC Regulator Voltage Level selection in Active mode.

spc_dcdc_drive_strength_t DCDCDriveStrength#: DCDC_CORE Regulator Drive Strength selection in Active mode.

struct _spc_lowpower_mode_core_ldo_option#

#include <fsl_spc.h>

Core LDO regulator options in Low Power mode.

Public Members

spc_core_ldo_voltage_level_t CoreLDOVoltage#: Core LDO Regulator Voltage Level selection in Low Power mode.

spc_core_ldo_drive_strength_t CoreLDODriveStrength#: Core LDO Regulator Drive Strength selection in Low Power mode

struct _spc_lowpower_mode_sys_ldo_option#

#include <fsl_spc.h>

System LDO regulator options in Low Power mode.

Public Members

spc_sys_ldo_drive_strength_t SysLDODriveStrength#: System LDO Regulator Drive Strength selection in Low Power mode.

struct _spc_lowpower_mode_dcdc_option#

#include <fsl_spc.h>

DCDC regulator options in Low Power mode.

Public Members

spc_dcdc_voltage_level_t DCDCVoltage#: DCDC Regulator Voltage Level selection in Low Power mode.

spc_dcdc_drive_strength_t DCDCDriveStrength#: DCDC_CORE Regulator Drive Strength selection in Low Power mode.

struct _spc_dcdc_burst_config#

#include <fsl_spc.h>

DCDC Burst configuration.

Deprecated:: Do not recommend to use this structure.

Public Members

bool sofwareBurstRequest#: Enable/Disable DCDC Software Burst Request.

bool externalBurstRequest#: Enable/Disable DCDC External Burst Request.

bool stabilizeBurstFreq#: Enable/Disable DCDC frequency stabilization.

uint8_t freq#: The frequency of the current burst.

struct _spc_voltage_detect_option#

#include <fsl_spc.h>

CORE/SYS/IO VDD Voltage Detect options.

Public Members

bool HVDInterruptEnable#: CORE/SYS/IO VDD High Voltage Detect interrupt enable.

bool HVDResetEnable#: CORE/SYS/IO VDD High Voltage Detect reset enable.

bool LVDInterruptEnable#: CORE/SYS/IO VDD Low Voltage Detect interrupt enable.

bool LVDResetEnable#: CORE/SYS/IO VDD Low Voltage Detect reset enable.

struct _spc_core_voltage_detect_config#

#include <fsl_spc.h>

Core Voltage Detect configuration.

Public Members

spc_voltage_detect_option_t option#: Core VDD Voltage Detect option.

struct _spc_system_voltage_detect_config#

#include <fsl_spc.h>

System Voltage Detect Configuration.

Public Members

spc_voltage_detect_option_t option#: System VDD Voltage Detect option.

spc_low_voltage_level_select_t level#

Deprecated:: , reserved for all devices, will removed in next release.

struct _spc_io_voltage_detect_config#

#include <fsl_spc.h>

IO Voltage Detect Configuration.

Public Members

spc_voltage_detect_option_t option#: IO VDD Voltage Detect option.

spc_low_voltage_level_select_t level#: IO VDD Low-voltage level selection.

struct _spc_active_mode_regulators_config#

#include <fsl_spc.h>

Active mode configuration.

Public Members

spc_bandgap_mode_t bandgapMode#: Specify bandgap mode in active mode.

bool lpBuff#: Enable/disable CMP bandgap buffer.

spc_active_mode_dcdc_option_t DCDCOption#: Specify DCDC configurations in active mode.

spc_active_mode_sys_ldo_option_t SysLDOOption#: Specify System LDO configurations in active mode.

spc_active_mode_core_ldo_option_t CoreLDOOption#: Specify Core LDO configurations in active mode.

struct _spc_lowpower_mode_regulators_config#

#include <fsl_spc.h>

Low Power Mode configuration.

Public Members

bool lpIREF#: Enable/disable low power IREF in low power modes.

spc_bandgap_mode_t bandgapMode#: Specify bandgap mode in low power modes.

bool lpBuff#: Enable/disable CMP bandgap buffer in low power modes.

bool CoreIVS#: Enable/disable CORE VDD internal voltage scaling.

spc_lowpower_mode_dcdc_option_t DCDCOption#: Specify DCDC configurations in low power modes.

spc_lowpower_mode_sys_ldo_option_t SysLDOOption#: Specify system LDO configurations in low power modes.

spc_lowpower_mode_core_ldo_option_t CoreLDOOption#: Specify core LDO configurations in low power modes.

MCX_VBAT: Smart Power Switch#

The enumeration of VBAT module status.

Values:

enumerator kStatus_VBAT_Fro16kNotEnabled#: Internal 16kHz free running oscillator not enabled.

enumerator kStatus_VBAT_BandgapNotEnabled#: Bandgap not enabled.

enumerator kStatus_VBAT_WrongCapacitanceValue#: Wrong capacitance for selected oscillator mode.

enumerator kStatus_VBAT_ClockMonitorLocked#: Clock monitor locked.

enumerator kStatus_VBAT_OSC32KNotReady#: OSC32K not ready.

enumerator kStatus_VBAT_LDONotReady#: LDO not ready.

enumerator kStatus_VBAT_TamperLocked#: Tamper locked.

enum _vbat_status_flag#

The enumeration of VBAT status flags.

Values:

enumerator kVBAT_StatusFlagPORDetect#: VBAT domain has been reset

enumerator kVBAT_StatusFlagWakeupPin#: A falling edge is detected on the wakeup pin.

enumerator kVBAT_StatusFlagBandgapTimer0#: Bandgap Timer0 period reached.

enumerator kVBAT_StatusFlagBandgapTimer1#: Bandgap Timer1 period reached.

enumerator kVBAT_StatusFlagLdoReady#: LDO is enabled and ready.

enumerator kVBAT_StatusFlagOsc32kReady#: OSC32k is enabled and clock is ready.

enumerator kVBAT_StatusFlagInterrupt0Detect#: Interrupt 0 asserted.

enumerator kVBAT_StatusFlagInterrupt1Detect#: Interrupt 1 asserted.

enumerator kVBAT_StatusFlagInterrupt2Detect#: Interrupt 2 asserted.

enumerator kVBAT_StatusFlagInterrupt3Detect#: Interrupt 3 asserted.

enum _vbat_interrupt_enable#

The enumeration of VBAT interrupt enable.

Values:

enumerator kVBAT_InterruptEnablePORDetect#: Enable POR detect interrupt.

enumerator kVBAT_InterruptEnableWakeupPin#: Enable the interrupt when a falling edge is detected on the wakeup pin.

enumerator kVBAT_InterruptEnableBandgapTimer0#: Enable the interrupt if Bandgap Timer0 period reached.

enumerator kVBAT_InterruptEnableBandgapTimer1#: Enable the interrupt if Bandgap Timer1 period reached.

enumerator kVBAT_InterruptEnableLdoReady#: Enable LDO ready interrupt.

enumerator kVBAT_InterruptEnableOsc32kReady#: Enable OSC32K ready interrupt.

enumerator kVBAT_InterruptEnableInterrupt0#: Enable the interrupt0.

enumerator kVBAT_InterruptEnableInterrupt1#: Enable the interrupt1.

enumerator kVBAT_InterruptEnableInterrupt2#: Enable the interrupt2.

enumerator kVBAT_InterruptEnableInterrupt3#: Enable the interrupt3.

enumerator kVBAT_AllInterruptsEnable#: Enable all interrupts.

enum _vbat_wakeup_enable#

The enumeration of VBAT wakeup enable.

Values:

enumerator kVBAT_WakeupEnablePORDetect#: Enable POR detect wakeup.

enumerator kVBAT_WakeupEnableWakeupPin#: Enable wakeup feature when a falling edge is detected on the wakeup pin.

enumerator kVBAT_WakeupEnableBandgapTimer0#: Enable wakeup feature when bandgap timer0 period reached.

enumerator kVBAT_WakeupEnableBandgapTimer1#: Enable wakeup feature when bandgap timer1 period reached.

enumerator kVBAT_WakeupEnableLdoReady#: Enable wakeup when LDO ready.

enumerator kVBAT_WakeupEnableOsc32kReady#: Enable wakeup when OSC32k ready.

enumerator kVBAT_WakeupEnableInterrupt0#: Enable wakeup when interrupt0 asserted.

enumerator kVBAT_WakeupEnableInterrupt1#: Enable wakeup when interrupt1 asserted.

enumerator kVBAT_WakeupEnableInterrupt2#: Enable wakeup when interrupt2 asserted.

enumerator kVBAT_WakeupEnableInterrupt3#: Enable wakeup when interrupt3 asserted.

enumerator kVBAT_AllWakeupsEnable#: Enable all wakeup.

enum _vbat_tamper_enable#

The enumeration of VBAT tamper enable.

Values:

enumerator kVBAT_TamperEnablePOR#: Enable tamper if POR asserted in STATUS register.

enumerator kVBAT_TamperEnableClockDetect#: Enable tamper if clock monitor detect an error.

enumerator kVBAT_TamperEnableConfigDetect#: Enable tamper if configuration error detected.

enumerator kVBAT_TamperEnableVoltageDetect#: Enable tamper if voltage monitor detect an error.

enumerator kVBAT_TamperEnableTemperatureDetect#: Enable tamper if temperature monitor detect an error.

enumerator kVBAT_TamperEnableSec0Detect#: Enable tamper if security input 0 detect an error.

enum _vbat_bandgap_timer_id#

The enumeration of bandgap timer id, VBAT support two bandgap timers.

Values:

enumerator kVBAT_BandgapTimer0#: Bandgap Timer0.

enumerator kVBAT_BandgapTimer1#: Bandgap Timer1.

enum _vbat_clock_enable#

The enumeration of connections for OSC32K/FRO32K output clock to other modules.

Values:

enumerator kVBAT_EnableClockToDomain0#: Enable clock to power domain0.

enumerator kVBAT_EnableClockToDomain1#: Enable clock to power domain1.

enumerator kVBAT_EnableClockToDomain2#: Enable clock to power domain2.

enumerator kVBAT_EnableClockToDomain3#: Enable clock to power domain3.

enum _vbat_ram_array#

The enumeration of SRAM arrays that controlled by VBAT. .

Values:

enumerator kVBAT_SramArray0#: Specify SRAM array0 that controlled by VBAT.

enumerator kVBAT_SramArray1#: Specify SRAM array1 that controlled by VBAT.

enumerator kVBAT_SramArray2#: Specify SRAM array2 that controlled by VBAT.

enumerator kVBAT_SramArray3#: Specify SRAM array3 that controlled by VBAT.

enum _vbat_bandgap_refresh_period#

The enumeration of bandgap refresh period.

Values:

enumerator kVBAT_BandgapRefresh7P8125ms#: Bandgap refresh every 7.8125ms.

enumerator kVBAT_BandgapRefresh15P625ms#: Bandgap refresh every 15.625ms.

enumerator kVBAT_BandgapRefresh31P25ms#: Bandgap refresh every 31.25ms.

enumerator kVBAT_BandgapRefresh62P5ms#: Bandgap refresh every 62.5ms.

enum _vbat_bandgap_timer0_timeout_period#

The enumeration of bandgap timer0 timeout period.

Values:

enumerator kVBAT_BangapTimer0Timeout1s#: Bandgap timer0 timerout every 1s.

enumerator kVBAT_BangapTimer0Timeout500ms#: Bandgap timer0 timerout every 500ms.

enumerator kVBAT_BangapTimer0Timeout250ms#: Bandgap timer0 timerout every 250ms.

enumerator kVBAT_BangapTimer0Timeout125ms#: Bandgap timer0 timerout every 125ms.

enumerator kVBAT_BangapTimer0Timeout62P5ms#: Bandgap timer0 timerout every 62.5ms.

enumerator kVBAT_BangapTimer0Timeout31P25ms#: Bandgap timer0 timerout every 31.25ms.

enum _vbat_osc32k_operate_mode#

The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on.

Values:

enumerator kVBAT_Osc32kEnabledToTransconductanceMode#: Set to transconductance mode.

enumerator kVBAT_Osc32kEnabledToLowPowerBackupMode#: Set to low power backup mode.

enumerator kVBAT_Osc32kEnabledToLowPowerSwitchedMode#: Set to low power switched mode.

enum _vbat_osc32k_load_capacitance_select#

The enumeration of OSC32K load capacitance.

Values:

enumerator kVBAT_Osc32kCrystalLoadCap0pF#: Internal capacitance bank is enabled, set the internal capacitance to 0 pF.

enumerator kVBAT_Osc32kCrystalLoadCap2pF#: Internal capacitance bank is enabled, set the internal capacitance to 2 pF.

enumerator kVBAT_Osc32kCrystalLoadCap4pF#: Internal capacitance bank is enabled, set the internal capacitance to 4 pF.

enumerator kVBAT_Osc32kCrystalLoadCap6pF#: Internal capacitance bank is enabled, set the internal capacitance to 6 pF.

enumerator kVBAT_Osc32kCrystalLoadCap8pF#: Internal capacitance bank is enabled, set the internal capacitance to 8 pF.

enumerator kVBAT_Osc32kCrystalLoadCap10pF#: Internal capacitance bank is enabled, set the internal capacitance to 10 pF.

enumerator kVBAT_Osc32kCrystalLoadCap12pF#: Internal capacitance bank is enabled, set the internal capacitance to 12 pF.

enumerator kVBAT_Osc32kCrystalLoadCap14pF#: Internal capacitance bank is enabled, set the internal capacitance to 14 pF.

enumerator kVBAT_Osc32kCrystalLoadCap16pF#: Internal capacitance bank is enabled, set the internal capacitance to 16 pF.

enumerator kVBAT_Osc32kCrystalLoadCap18pF#: Internal capacitance bank is enabled, set the internal capacitance to 18 pF.

enumerator kVBAT_Osc32kCrystalLoadCap20pF#: Internal capacitance bank is enabled, set the internal capacitance to 20 pF.

enumerator kVBAT_Osc32kCrystalLoadCap22pF#: Internal capacitance bank is enabled, set the internal capacitance to 22 pF.

enumerator kVBAT_Osc32kCrystalLoadCap24pF#: Internal capacitance bank is enabled, set the internal capacitance to 24 pF.

enumerator kVBAT_Osc32kCrystalLoadCap26pF#: Internal capacitance bank is enabled, set the internal capacitance to 26 pF.

enumerator kVBAT_Osc32kCrystalLoadCap28pF#: Internal capacitance bank is enabled, set the internal capacitance to 28 pF.

enumerator kVBAT_Osc32kCrystalLoadCap30pF#: Internal capacitance bank is enabled, set the internal capacitance to 30 pF.

enumerator kVBAT_Osc32kCrystalLoadCapBankDisabled#: Internal capacitance bank is disabled.

enum _vbat_osc32k_start_up_time#

The enumeration of start-up time of the oscillator.

Values:

enumerator kVBAT_Osc32kStartUpTime8Sec#: Configure the start-up time as 8 seconds.

enumerator kVBAT_Osc32kStartUpTime4Sec#: Configure the start-up time as 4 seconds.

enumerator kVBAT_Osc32kStartUpTime2Sec#: Configure the start-up time as 2 seconds.

enumerator kVBAT_Osc32kStartUpTime1Sec#: Configure the start-up time as 1 seconds.

enumerator kVBAT_Osc32kStartUpTime0P5Sec#: Configure the start-up time as 0.5 seconds.

enumerator kVBAT_Osc32kStartUpTime0P25Sec#: Configure the start-up time as 0.25 seconds.

enumerator kVBAT_Osc32kStartUpTime0P125Sec#: Configure the start-up time as 0.125 seconds.

enumerator kVBAT_Osc32kStartUpTime0P5MSec#: Configure the start-up time as 0.5 milliseconds.

enum _vbat_internal_module_supply#

The enumeration of VBAT module supplies.

Values:

enumerator kVBAT_ModuleSuppliedByVddBat#: VDD_BAT supplies VBAT modules.

enumerator kVBAT_ModuleSuppliedByVddSys#: VDD_SYS supplies VBAT modules.

enum _vbat_clock_monitor_divide_trim#

The enumeration of VBAT clock monitor divide trim value.

Values:

enumerator kVBAT_ClockMonitorOperateAt1kHz#: Clock monitor operates at 1 kHz.

enumerator kVBAT_ClockMonitorOperateAt64Hz#: Clock monitor operates at 64 Hz.

enum _vbat_clock_monitor_freq_trim#

The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert.

Values:

enumerator kVBAT_ClockMonitorAssert2Cycle#: Clock monitor assert 2 cycles after expected edge.

enumerator kVBAT_ClockMonitorAssert4Cycle#: Clock monitor assert 4 cycles after expected edge.

enumerator kVBAT_ClockMonitorAssert6Cycle#: Clock monitor assert 8 cycles after expected edge.

enumerator kVBAT_ClockMonitorAssert8Cycle#: Clock monitor assert 8 cycles after expected edge.

typedef enum _vbat_bandgap_refresh_period vbat_bandgap_refresh_period_t#: The enumeration of bandgap refresh period.

typedef enum _vbat_bandgap_timer0_timeout_period vbat_bandgap_timer0_timeout_period_t#: The enumeration of bandgap timer0 timeout period.

typedef enum _vbat_osc32k_operate_mode vbat_osc32k_operate_mode_t#: The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on.

typedef enum _vbat_osc32k_load_capacitance_select vbat_osc32k_load_capacitance_select_t#: The enumeration of OSC32K load capacitance.

typedef enum _vbat_osc32k_start_up_time vbat_osc32k_start_up_time_t#: The enumeration of start-up time of the oscillator.

typedef enum _vbat_internal_module_supply vbat_internal_module_supply_t#: The enumeration of VBAT module supplies.

typedef enum _vbat_clock_monitor_divide_trim vbat_clock_monitor_divide_trim_t#: The enumeration of VBAT clock monitor divide trim value.

typedef enum _vbat_clock_monitor_freq_trim vbat_clock_monitor_freq_trim_t#: The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert.

typedef struct _vbat_fro16k_config vbat_fro16k_config_t#: The structure of internal 16kHz free running oscillator attributes.

typedef struct _vbat_clock_monitor_config vbat_clock_monitor_config_t#: The structure of internal clock monitor, including divide trim and frequency trim.

typedef struct _vbat_tamper_config vbat_tamper_config_t#: The structure of Tamper configuration.

FSL_VBAT_DRIVER_VERSION#: VBAT driver version 2.6.0.

VBAT_LDORAMC_RET_MASK#

VBAT_LDORAMC_RET_SHIFT#

VBAT_LDORAMC_RET(x)#

kVBAT_EnableClockToVddBat#

kVBAT_EnableClockToVddSys#

kVBAT_EnableClockToVddWake#

kVBAT_EnableClockToVddMain#

void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config)#

Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output.

Parameters:

base – VBAT peripheral base address.
config – Pointer to vbat_fro16k_config_t structure.

static inline void VBAT_EnableFRO16k(VBAT_Type *base, bool enable)#

Enable/disable internal 16kHz free running oscillator.

Parameters:

base – VBAT peripheral base address.
enable – Used to enable/disable 16kHz FRO.
- true Enable internal 16kHz free running oscillator.
- false Disable internal 16kHz free running oscillator.

static inline bool VBAT_CheckFRO16kEnabled(VBAT_Type *base)#

Check if internal 16kHz free running oscillator is enabled.

Parameters:

base – VBAT peripheral base address.

Return values:

true – The internal 16kHz Free running oscillator is enabled.
false – The internal 16kHz Free running oscillator is enabled.

static inline void VBAT_UngateFRO16k(VBAT_Type *base, uint8_t connectionsMask)#

Enable FRO16kHz output clock to selected modules.

Parameters:

base – VBAT peripheral base address.
connectionsMask – The mask of modules that FRO16k is connected, should be the OR’ed value of vbat_clock_enable_t.

static inline void VBAT_GateFRO16k(VBAT_Type *base, uint8_t connectionsMask)#

Disable FRO16kHz output clock to selected modules.

Parameters:

base – VBAT peripheral base address.
connectionsMask – The OR’ed value of vbat_clock_enable_t.

static inline void VBAT_LockFRO16kSettings(VBAT_Type *base)#

Lock settings of internal 16kHz free running oscillator, please note that if locked 16kHz FRO’s settings can not be updated until the next POR.

Note

Please note that the operation to ungate/gate FRO 16kHz output clock can not be locked by this function.

Parameters:

base – VBAT peripheral base address.

static inline bool VBAT_CheckFRO16kSettingsLocked(VBAT_Type *base)#

Check if FRO16K settings are locked.

Parameters:

base – VBAT peripheral base address.

Returns:

true in case of FRO16k settings are locked, false in case of FRO16k settings are not locked.

static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable)#

Enable/disable 32K Crystal Oscillator.

Parameters:

base – VBAT peripheral base address.
enable – Used to enable/disable 32k Crystal Oscillator:
- true Enable crystal oscillator and polling status register to check clock is ready.
- false Disable crystal oscillator.

static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass)#

Bypass 32k crystal oscillator, the clock is still output by oscillator but this clock is the same as clock provided on EXTAL pin.

Note

In bypass mode, oscillator must be enabled; To exit bypass mode, oscillator must be disabled.

Parameters:

base – VBAT peripheral base address.
enableBypass – Used to enter/exit bypass mode:
- true Enter into bypass mode;
- false Exit bypass mode.

static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse, uint8_t fine)#

Adjust 32k crystal oscillator amplifier gain.

Parameters:

base – VBAT peripheral base address.
coarse – Specify amplifier coarse trim value.
fine – Specify amplifier fine trim value.

status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, vbat_osc32k_operate_mode_t operateMode, vbat_osc32k_load_capacitance_select_t xtalCap, vbat_osc32k_load_capacitance_select_t extalCap)#

Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin.

Parameters:

base – VBAT peripheral base address.
operateMode – Specify the crystal oscillator mode, please refer to vbat_osc32k_operate_mode_t.
xtalCap – Specify the internal capacitance for the XTAL pin from the capacitor bank.
extalCap – Specify the internal capacitance for the EXTAL pin from the capacitor bank.

Return values:

kStatus_VBAT_WrongCapacitanceValue – The load capacitance value to set is not align with operate mode’s requirements.
kStatus_Success – Success to set operate mode and load capacitance.

static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime)#

Trim 32k crystal oscillator startup time.

Parameters:

base – VBAT peripheral base address.
startupTime – Specify the startup time of the oscillator.

static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue)#

Set crystal oscillator comparator trim value when oscillator is set as low power switch mode.

Parameters:

base – VBAT peripheral base address.
comparatorTrimValue – Comparator trim value, ranges from 0 to 7.

static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue)#

Set crystal oscillator delay trim value when oscillator is set as low power switch mode.

Parameters:

base – VBAT peripheral base address.
delayTrimValue – Delay trim value, ranges from 0 to 15.

static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue)#

Set crystal oscillator capacitor trim value when oscillator is set as low power switch mode.

Parameters:

base – VBAT peripheral base address.
capacitorTrimValue – Capacitor value to trim, ranges from 0 to 3.

static inline void VBAT_LookOsc32kSettings(VBAT_Type *base)#

Lock Osc32k settings, after locked all writes to the Oscillator registers are blocked.

Parameters:

base – VBAT peripheral base address.

static inline void VBAT_UnlockOsc32kSettings(VBAT_Type *base)#

Unlock Osc32k settings.

Parameters:

base – VBAT peripheral base address.

static inline bool VBAT_CheckOsc32kSettingsLocked(VBAT_Type *base)#

Check if osc32k settings are locked.

Parameters:

base – VBAT peripheral base address.

Returns:

true in case of osc32k settings are locked, false in case of osc32k settings are not locked.

static inline void VBAT_UngateOsc32k(VBAT_Type *base, uint8_t connectionsMask)#

Enable OSC32k output clock to selected modules.

Parameters:

base – VBAT peripheral base address.
connectionsMask – The OR’ed value of vbat_clock_enable_t.

static inline void VBAT_GateOsc32k(VBAT_Type *base, uint8_t connectionsMask)#

Disable OSC32k output clock to selected modules.

Parameters:

base – VBAT peripheral base address.
connectionsMask – The OR’ed value of vbat_clock_enable_t.

status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable)#

Enable/disable Bandgap.

Note

The FRO16K must be enabled before enabling the bandgap.

Note

This setting can be locked by VBAT_LockRamLdoSettings() function.

Parameters:

base – VBAT peripheral base address.
enable – Used to enable/disable bandgap.
- true Enable the bandgap.
- false Disable the bandgap.

Return values:

kStatus_Success – Success to enable/disable the bandgap.
kStatus_VBAT_Fro16kNotEnabled – Fail to enable the bandgap due to FRO16k is not enabled previously.

static inline bool VBAT_CheckBandgapEnabled(VBAT_Type *base)#

Check if bandgap is enabled.

Parameters:

base – VBAT peripheral base address.

Return values:

true – The bandgap is enabled.
false – The bandgap is disabled.

static inline void VBAT_EnableBandgapRefreshMode(VBAT_Type *base, bool enableRefreshMode)#

Enable/disable bandgap low power refresh mode.

Note

For lowest power consumption, refresh mode must be enabled.

Note

This setting can be locked by VBAT_LockRamLdoSettings() function.

Parameters:

base – VBAT peripheral base address.
enableRefreshMode – Used to enable/disable bandgap low power refresh mode.
- true Enable bandgap low power refresh mode.
- false Disable bandgap low power refresh mode.

status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable)#

Enable/disable Backup RAM Regulator(RAM_LDO).

Note

This setting can be locked by VBAT_LockRamLdoSettings() function.

Parameters:

base – VBAT peripheral base address.
enable – Used to enable/disable RAM_LDO.
- true Enable backup SRAM regulator.
- false Disable backup SRAM regulator.

Return values:

kStatusSuccess – Success to enable/disable backup SRAM regulator.
kStatus_VBAT_Fro16kNotEnabled – Fail to enable backup SRAM regulator due to FRO16k is not enabled previously.
kStatus_VBAT_BandgapNotEnabled – Fail to enable backup SRAM regulator due to the bandgap is not enabled previously.

static inline void VBAT_LockRamLdoSettings(VBAT_Type *base)#

Lock settings of RAM_LDO, please note that if locked then RAM_LDO’s settings can not be updated until the next POR.

Parameters:

base – VBAT peripheral base address.

static inline bool VBAT_CheckRamLdoSettingsLocked(VBAT_Type *base)#

Check if RAM_LDO settings is locked.

Parameters:

base – VBAT peripheral base address.

Returns:

true in case of RAM_LDO settings are locked, false in case of RAM_LDO settings are unlocked.

status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base)#

Switch the SRAM to be powered by LDO_RAM.

Note

This function can be used to switch the SRAM to the VBAT retention supply at any time, but please note that the SRAM must not be accessed during this time.

Note

Invoke this function to switch power supply before switching off external power.

Note

RAM_LDO must be enabled before invoking this function.

Note

To access the SRAM arrays retained by the LDO_RAM, please invoke VBAT_SwitchSRAMPowerBySocSupply(), after external power is switched back on.

Parameters:

base – VBAT peripheral base address.

Return values:

kStatusSuccess – Success to Switch SRAM powered by VBAT.
kStatus_VBAT_Fro16kNotEnabled – Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously.

static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base)#

Switch the RAM to be powered by Soc Supply in software mode.

Parameters:

base – VBAT peripheral base address.

static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)#

Power off selected SRAM array in low power modes.

Parameters:

base – VBAT peripheral base address.
sramMask – The mask of SRAM array to power off, should be the OR’ed value of vbat_ram_array_t.

static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)#

Retain selected SRAM array in low power modes.

Parameters:

base – VBAT peripheral base address.
sramMask – The mask of SRAM array to retain, should be the OR’ed value of vbat_ram_array_t.

static inline void VBAT_EnableSRAMIsolation(VBAT_Type *base, bool enable)#

Enable/disable SRAM isolation.

Parameters:

base – VBAT peripheral base address.
enable – Used to enable/disable SRAM violation.
- true SRAM will be isolated.
- false SRAM state follows the SoC power modes.

status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask)#

Enable/disable Bandgap timer.

Note

The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k.

Parameters:

base – VBAT peripheral base address.
enable – Used to enable/disable bandgap timer.
timerIdMask – The mask of bandgap timer Id, should be the OR’ed value of vbat_bandgap_timer_id_t.

Return values:

kStatus_Success – Success to enable/disable selected bandgap timer.
kStatus_VBAT_Fro16kNotEnabled – Fail to enable/disable selected bandgap timer due to FRO16k not enabled previously.
kStatus_VBAT_BandgapNotEnabled – Fail to enable/disable selected bandgap timer due to bandgap not enabled previously.

void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod)#

Set bandgap timer0 timeout value.

Note

The timeout value can only be changed when the timer is disabled.

Parameters:

base – VBAT peripheral base address.
timeoutPeriod – Bandgap timer timeout value, please refer to vbat_bandgap_timer0_timeout_period_t.

void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod)#

Set bandgap timer1 timeout value.

Note

The timeout value can only be changed when the timer is disabled.

Parameters:

base – VBAT peripheral base address.
timeoutPeriod – The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s.

static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_internal_module_supply_t supply)#

Control the VBAT internal switch in active mode, VBAT modules can be suppiled by VDD_BAT and VDD_SYS.

Parameters:

base – VBAT peripheral base address.
supply – Used to control the VBAT internal switch.

static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base)#

Get VBAT module supply in active mode.

Parameters:

base – VBAT peripheral base address.

Returns:

VDD_SYS supplies VBAT modules or VDD_BAT supplies VBAT modules, in type of vbat_internal_module_supply_t.

static inline void VBAT_SwitchVBATModuleSupplyLowPowerMode(VBAT_Type *base, vbat_internal_module_supply_t supply)#

Control the VBAT internal switch in low power modes.

Note

If VBAT modules are supplied by VDD_SYS in low power modes, VBAT module will also supplied by VDD_SYS in active mode.

Parameters:

base – VBAT peripheral base address.
supply – Used to specify which voltage input supply VBAT modules in low power mode.

static inline void VBAT_LockSwitchControl(VBAT_Type *base)#

Lock switch control, if locked all writes to the switch registers will be blocked.

Parameters:

base – VBAT peripheral base address.

static inline void VBAT_UnlockSwitchControl(VBAT_Type *base)#

Unlock switch control.

Parameters:

base – VBAT peripheral base address.

static inline bool VBAT_CheckSwitchControlLocked(VBAT_Type *base)#

Check if switch control is locked.

Parameters:

base – VBAT peripheral base address.

Return values:

false – switch control is not locked.
true – switch control is locked, any writes to related registers are blocked.

status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config)#

Initialize the VBAT clock monitor, enable clock monitor and set the clock monitor configuration.

Note

Both FRO16K and OSC32K should be enabled and stable before invoking this function.

Parameters:

base – VBAT peripheral base address.
config – Pointer to vbat_clock_monitor_config_t structure.

Return values:

kStatus_Success – Clock monitor is initialized successfully.
kStatus_VBAT_Fro16kNotEnabled – FRO16K is not enabled.
kStatus_VBAT_Osc32kNotReady – OSC32K is not ready.
kStatus_VBAT_ClockMonitorLocked – Clock monitor is locked.

status_t VBAT_DeinitMonitor(VBAT_Type *base)#

Deinitialize the VBAT clock monitor.

Parameters:

base – VBAT peripheral base address.

Return values:

kStatus_Success – Clock monitor is de-initialized successfully.
kStatus_VBAT_ClockMonitorLocked – Control of Clock monitor is locked.

static inline void VBAT_EnableClockMonitor(VBAT_Type *base, bool enable)#

Enable/disable clock monitor.

false: disable clock monitor.

Parameters:

base – VBAT peripheral base address.
enable – Switcher to enable/disable clock monitor:
- true: enable clock monitor;

static inline void VBAT_SetClockMonitorDivideTrim(VBAT_Type *base, vbat_clock_monitor_divide_trim_t divideTrim)#

Set clock monitor’s divide trim, avaiable value is kVBAT_ClockMonitorOperateAt1kHz and kVBAT_ClockMonitorOperateAt64Hz.

Parameters:

base – VBAT peripheral base address.
divideTrim – Specify divide trim value, please refer to vbat_clock_monitor_divide_trim_t.

static inline void VBAT_SetClockMonitorFrequencyTrim(VBAT_Type *base, vbat_clock_monitor_freq_trim_t freqTrim)#

Set clock monitor’s frequency trim, avaiable value is kVBAT_ClockMonitorAssert2Cycle, kVBAT_ClockMonitorAssert4Cycle, kVBAT_ClockMonitorAssert6Cycle and kVBAT_ClockMonitorAssert8Cycle.

Parameters:

base – VBAT peripheral base address.
freqTrim – Specify frequency trim value, please refer to vbat_clock_monitor_freq_trim_t.

static inline void VBAT_LockClockMonitorControl(VBAT_Type *base)#

Lock clock monitor enable/disable control.

Note

If locked, it is not allowed to change clock monitor enable/disable control.

Parameters:

base – VBAT peripheral base address.

static inline void VBAT_UnlockClockMonitorControl(VBAT_Type *base)#

Unlock clock monitor enable/disable control.

Parameters:

base – VBTA peripheral base address.

static inline bool VBAT_CheckClockMonitorControlLocked(VBAT_Type *base)#

Check if clock monitor enable/disable control is locked.

Note

If locked, it is not allowed to change clock monitor enable/disable control.

Parameters:

base – VBAT peripheral base address.

Return values:

false – clock monitor enable/disable control is not locked.
true – clock monitor enable/disable control is locked, any writes to related registers are blocked.

status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config)#

Initialize tamper control.

Note

Both FRO16K and bandgap should be enabled before calling this function.

Parameters:

base – VBAT peripheral base address.
config – Pointer to vbat_tamper_config_t structure.

Return values:

kStatus_Success – Tamper is initialized successfully.
kStatus_VBAT_TamperLocked – Tamper control is locked.
kStatus_VBAT_BandgapNotEnabled – Bandgap is not enabled.
kStatus_VBAT_Fro16kNotEnabled – FRO 16K is not enabled.

status_t VBAT_DeinitTamper(VBAT_Type *base)#

De-initialize tamper control.

Parameters:

base – VBAT peripheral base address.

Return values:

kStatus_Success – Tamper is de-initialized successfully.
kStatus_VBAT_TamperLocked – Tamper control is locked.

static inline void VBAT_EnableTamper(VBAT_Type *base, uint32_t tamperEnableMask)#

Enable tampers for VBAT.

Parameters:

base – VBAT peripheral base address.
tamperEnableMask – Mask of tamper to be enabled, should be the OR’ed value of _vbat_tamper_enable.

static inline void VBAT_DisableTamper(VBAT_Type *base, uint32_t tamperEnableMask)#

Disable tampers for VBAT.

Parameters:

base – VBAT peripheral base address.
tamperEnableMask – Mask of tamper to be disabled, should be the OR’ed value of _vbat_tamper_enable.

static inline uint32_t VBAT_GetTamperEnableInfo(VBAT_Type *base)#

Get tamper enable information.

Parameters:

base – VBAT peripheral base address.

Returns:

Mask of tamper enable information, should be the OR’ed value of _vbat_tamper_enable.

static inline void VBAT_LockTamperControl(VBAT_Type *base)#

Lock tamper control, if locked, it is not allowed to change tamper control.

Parameters:

base – VBAT peripheral base address.

static inline void VBAT_UnlockTamperControl(VBAT_Type *base)#

Unlock tamper control.

Parameters:

base – VBAT peripheral base address.

static inline bool VBAT_CheckTamperControlLocked(VBAT_Type *base)#

Check if tamper control is locked.

Parameters:

base – VBAT peripheral base address.

Return values:

false – Tamper control is not locked.
true – Tamper control is locked, any writes to related registers are blocked.

static inline uint32_t VBAT_GetStatusFlags(VBAT_Type *base)#

Get VBAT status flags.

Parameters:

base – VBAT peripheral base address.

Returns:

The asserted status flags, should be the OR’ed value of vbat_status_flag_t.

static inline void VBAT_ClearStatusFlags(VBAT_Type *base, uint32_t mask)#

Clear VBAT status flags.

Parameters:

base – VBAT peripheral base address.
mask – The mask of status flags to be cleared, should be the OR’ed value of vbat_status_flag_t except kVBAT_StatusFlagLdoReady, kVBAT_StatusFlagOsc32kReady, kVBAT_StatusFlagInterrupt0Detect, kVBAT_StatusFlagInterrupt1Detect, kVBAT_StatusFlagInterrupt2Detect, kVBAT_StatusFlagInterrupt3Detect.

static inline void VBAT_EnableInterrupts(VBAT_Type *base, uint32_t mask)#

Enable interrupts for the VBAT module, such as POR detect interrupt, Wakeup Pin interrupt and so on.

Parameters:

base – VBAT peripheral base address.
mask – The mask of interrupts to be enabled, should be the OR’ed value of vbat_interrupt_enable_t.

static inline void VBAT_DisableInterrupts(VBAT_Type *base, uint32_t mask)#

Disable interrupts for the VBAT module, such as POR detect interrupt, wakeup pin interrupt and so on.

Parameters:

base – VBAT peripheral base address.
mask – The mask of interrupts to be disabled, should be the OR’ed value of vbat_interrupt_enable_t.

static inline void VBAT_EnableWakeup(VBAT_Type *base, uint32_t mask)#

Enable wakeup for the VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on.

Parameters:

base – VBAT peripheral base address.
mask – The mask of enumerators in vbat_wakeup_enable_t.

static inline void VBAT_DisableWakeup(VBAT_Type *base, uint32_t mask)#

Disable wakeup for VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on.

Parameters:

base – VBAT peripheral base address.
mask – The mask of enumerators in vbat_wakeup_enable_t.

static inline void VBAT_LockInterruptWakeupSettings(VBAT_Type *base)#

Lock VBAT interrupt and wakeup settings, please note that if locked the interrupt and wakeup settings can not be updated until the next POR.

Parameters:

base – VBAT peripheral base address.

static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert)#

Set the default state of the WAKEUP_b pin output when no enabled wakeup source is asserted.

Parameters:

base – VBAT peripheral base address.
assert – Used to set default state of the WAKEUP_b pin output:
- true WAKEUP_b output state is logic one;
- false WAKEUP_b output state is logic zero.

struct _vbat_fro16k_config#

#include <fsl_vbat.h>

The structure of internal 16kHz free running oscillator attributes.

Public Members

bool enableFRO16k#: Enable/disable internal 16kHz free running oscillator.

uint8_t enabledConnectionsMask#: The mask of connected modules to enable FRO16k clock output.

struct _vbat_clock_monitor_config#

#include <fsl_vbat.h>

The structure of internal clock monitor, including divide trim and frequency trim.

Public Members

vbat_clock_monitor_freq_trim_t freqTrim#: Frequency trim value used to adjust the clock monitor assert, please refer to vbat_clock_monitor_freq_trim_t.

bool lock#: Lock the clock monitor control after enabled.

struct _vbat_tamper_config#

#include <fsl_vbat.h>

The structure of Tamper configuration.

Public Members

bool enableVoltageDetect#: Enable/disable voltage detection.

bool enableTemperatureDetect#: Enable/disable temperature detection.

bool lock#: Lock the tamper control after enabled.

OPAMP: Operational Amplifier#

uint32_t OPAMP_GetInstance(OPAMP_Type *base)#

Get the instance index for an OPAMP peripheral base address.

Parameters:

base – OPAMP peripheral base address.

Returns:

Instance number (0-based).

void OPAMP_GetDefaultConfig(opamp_config_t *config)#

Populate an opamp_config_t with default values.

Default values:

config->biasCurrent     = kOPAMP_BiasCurrentRatio1;
config->vosTrim         = kOPAMP_VosTrim0mV;
config->gain            = kOPAMP_Gain3;
config->capCompensation = kOPAMP_CapCompensationGain3;
config->offsetSel       = kOPAMP_OffsetSelVddaDiv2;

Parameters:

config – Pointer to configuration structure; must not be NULL.

status_t OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config)#

Initialize the OPAMP module.

Enables the peripheral clock, releases reset, and writes all CTRL configuration fields (IREF_CONFIG, VOS_TRIM, GAIN_CONFIG, CC_CONFIG, OFFSET_SEL) The OPAMP output is NOT enabled; call OPAMP_Enable after initialization when the application is ready to start the amplifier.

Parameters:

base – OPAMP peripheral base address.
config – Pointer to configuration structure; must not be NULL.

Return values:

kStatus_Success – if initialization is successful.
kStatus_InvalidArgument – if the base address is invalid.

status_t OPAMP_Deinit(OPAMP_Type *base)#

De-initialize the OPAMP module.

Clears the ENA bit, disables the peripheral clock, and asserts reset.

Parameters:

base – OPAMP peripheral base address.

Return values:

kStatus_Success – if deinitialization is successful.
kStatus_InvalidArgument – if the base address is invalid.

static inline void OPAMP_Enable(OPAMP_Type *base)#

Enable the OPAMP output.

Call this after OPAMP_Init when the application is ready to start the amplifier.

Parameters:

base – OPAMP peripheral base address.

static inline void OPAMP_Disable(OPAMP_Type *base)#

Disable the OPAMP output.

The peripheral clock and configuration registers are preserved; call OPAMP_Enable to restart the amplifier without re-initializing.

Parameters:

base – OPAMP peripheral base address.

FSL_OPAMP_DRIVER_VERSION#: OPAMP driver version.

enum _opamp_bias_current#

OPAMP bias current ratio configuration.

Values:

enumerator kOPAMP_BiasCurrentRatio1#: Bias current ratio = 1.

enumerator kOPAMP_BiasCurrentRatio1_4#: Bias current ratio = 1/4.

enumerator kOPAMP_BiasCurrentRatio1_2#: Bias current ratio = 1/2.

enumerator kOPAMP_BiasCurrentRatio3_2#: Bias current ratio = 3/2.

enum _opamp_gain#

OPAMP gain configuration.

Values:

enumerator kOPAMP_Gain3#: OPAMP gain = 3.

enumerator kOPAMP_Gain4#: OPAMP gain = 4.

enumerator kOPAMP_Gain5#: OPAMP gain = 5.

enumerator kOPAMP_Gain6_5#: OPAMP gain = 6.5.

enumerator kOPAMP_Gain9#: OPAMP gain = 9.

enumerator kOPAMP_Gain11#: OPAMP gain = 11.

enumerator kOPAMP_Gain14#: OPAMP gain = 14.

enumerator kOPAMP_Gain19#: OPAMP gain = 19.

enum _opamp_cap_compensation#

OPAMP capacitance compensation configuration.

Note

CC_CONFIG must be set to match the selected GAIN_CONFIG. Refer to the device reference manual for the required pairing.

Values:

enumerator kOPAMP_CapCompensationGain3#: Capacitance compensation for gain = 3.

enumerator kOPAMP_CapCompensationGain4#: Capacitance compensation for gain = 4.

enumerator kOPAMP_CapCompensationGain5#: Capacitance compensation for gain = 5.

enumerator kOPAMP_CapCompensationGain6_5#: Capacitance compensation for gain = 6.5.

enumerator kOPAMP_CapCompensationGain9#: Capacitance compensation for gain = 9.

enumerator kOPAMP_CapCompensationGain11#: Capacitance compensation for gain = 11.

enumerator kOPAMP_CapCompensationGain14#: Capacitance compensation for gain = 14.

enumerator kOPAMP_CapCompensationGain19#: Capacitance compensation for gain = 19.

enum _opamp_offset_sel#

OPAMP offset voltage reference selection.

Values:

enumerator kOPAMP_OffsetSelVddaDiv2#: Vref = VDDA / 2.

enumerator kOPAMP_OffsetSelVddaDiv4#: Vref = VDDA / 4.

enumerator kOPAMP_OffsetSelVddaDiv8#: Vref = VDDA / 8.

enum _opamp_vos_trim#

OPAMP input offset voltage trim.

Values 0–7 all produce 0 V offset; values 8–15 select a non-zero trim. Positive values shift the output up; negative values shift it down.

Values:

enumerator kOPAMP_VosTrim0mV#: Input offset voltage = 0 mV (reset default).

enumerator kOPAMP_VosTrimPos1p5mV#: Input offset voltage = +1.5 mV.

enumerator kOPAMP_VosTrimPos3mV#: Input offset voltage = +3 mV.

enumerator kOPAMP_VosTrimPos4p5mV#: Input offset voltage = +4.5 mV.

enumerator kOPAMP_VosTrimPos6mV#: Input offset voltage = +6 mV.

enumerator kOPAMP_VosTrimNeg1p5mV#: Input offset voltage = -1.5 mV.

enumerator kOPAMP_VosTrimNeg3mV#: Input offset voltage = -3 mV.

enumerator kOPAMP_VosTrimNeg4p5mV#: Input offset voltage = -4.5 mV.

enumerator kOPAMP_VosTrimNeg6mV#: Input offset voltage = -6 mV.

typedef enum _opamp_bias_current opamp_bias_current_t#: OPAMP bias current ratio configuration.

typedef enum _opamp_gain opamp_gain_t#: OPAMP gain configuration.

typedef enum _opamp_cap_compensation opamp_cap_compensation_t#: OPAMP capacitance compensation configuration.

Note

CC_CONFIG must be set to match the selected GAIN_CONFIG. Refer to the device reference manual for the required pairing.

typedef enum _opamp_offset_sel opamp_offset_sel_t#: OPAMP offset voltage reference selection.

typedef enum _opamp_vos_trim opamp_vos_trim_t#

OPAMP input offset voltage trim.

Values 0–7 all produce 0 V offset; values 8–15 select a non-zero trim. Positive values shift the output up; negative values shift it down.

typedef struct _opamp_config opamp_config_t#: OPAMP configuration structure.

struct _opamp_config#

#include <fsl_opamp.h>

OPAMP configuration structure.

Public Members

opamp_gain_t gain#: Gain configuration.

opamp_offset_sel_t offsetSel#: Offset voltage reference.

opamp_vos_trim_t vosTrim#: Input offset voltage trim.

opamp_bias_current_t biasCurrent#: Bias current ratio.

opamp_cap_compensation_t capCompensation#: Capacitance compensation; must match gain.

PHD: Phase Detector#

uint32_t PHD_GetInstance(PHD_Type *base)#

Get the instance for PHD module.

Parameters:

base – PHD base address

Returns:

Instance number if valid base address is provided, otherwise returns 0xFFFFFFFF

void PHD_GetDefaultConfig(phd_config_t *config)#

Fills a phd_config_t with safe power-on defaults.

config->enableComparatorInStopMode = false;
config->hysteresisLevel            = kPHD_HysteresisLevel0;
config->clockSource                = kPHD_FuncClockSource0;
config->enableExternalNeutral      = false;
config->enableInternalNeutral      = false;
config->enableVirtualNetwork       = false;
config->ibiasTrim                  = kPHD_IbiasTrimValue0;
config->filterCount                = kPHD_FilterCountBypass;
config->filterPeriod               = 0U;

Parameters:

config – Pointer to a phd_config_t structure. Must not be NULL.

status_t PHD_Init(PHD_Type *base, const phd_config_t *config)#

Initialises the PHD module.

Enables the peripheral clock, releases reset, and programs PHASECTRL from config via read-modify-write. CMP_EN is forced to 0 regardless of any prior register state. Call PHD_ConfigComparator0/1/2() to set up individual channels, then PHD_EnableComparator() to start the module.

Parameters:

base – PHD peripheral base address.
config – Pointer to a phd_config_t structure. Must not be NULL.

Return values:

kStatus_Success – Initialisation successful.
kStatus_InvalidArgument – base is not a valid PHD address.

status_t PHD_DeInit(PHD_Type *base)#

Deinitialize the PHD module.

Clears CMP_EN, then gates the peripheral clock and asserts reset.

Parameters:

base – PHD peripheral base address.

Return values:

kStatus_Success – if deinitialization is successful.
kStatus_InvalidArgument – if the base address is invalid.

void PHD_GetDefaultComparatorConfig(phd_comparator_config_t *config)#

Fills a phd_comparator_config_t with power-on defaults.

config->enableOutputPin  = false;
config->outputSelect     = kPHD_OutputFiltered;
config->invertOutput     = false;
config->enableWindowMode = false;
config->enableSampleMode = false;

Parameters:

config – Pointer to a phd_comparator_config_t structure. Must not be NULL.

void PHD_ConfigComparator0(PHD_Type *base, const phd_comparator_config_t *config)#

Configures phase comparator 0 (PHCMP0CR).

Clears any startup-glitch flags (CFF, CFR) in PHCMP0SCR, then writes PHCMP0CR via read-modify-write. Call this before asserting CMP_EN.

Parameters:

base – PHD peripheral base address.
config – Pointer to a phd_comparator_config_t structure. Must not be NULL.

void PHD_ConfigComparator1(PHD_Type *base, const phd_comparator_config_t *config)#

Configures phase comparator 1 (PHCMP1CR).

Clears any startup-glitch flags (CFF, CFR) in PHCMP1SCR, then writes PHCMP1CR via read-modify-write. Call this before asserting CMP_EN.

Parameters:

base – PHD peripheral base address.
config – Pointer to a phd_comparator_config_t structure. Must not be NULL.

void PHD_ConfigComparator2(PHD_Type *base, const phd_comparator_config_t *config)#

Configures phase comparator 2 (PHCMP2CR).

Clears any startup-glitch flags (CFF, CFR) in PHCMP2SCR, then writes PHCMP2CR via read-modify-write. Call this before asserting CMP_EN.

Parameters:

base – PHD peripheral base address.
config – Pointer to a phd_comparator_config_t structure. Must not be NULL.

static inline void PHD_EnableComparator(PHD_Type *base)#

Enables the PHD comparator analog block (PHASECTRL[CMP_EN]).

Call this after PHD_Init() and all PHD_ConfigComparatorN() calls are complete.

Parameters:

base – PHD peripheral base address.

static inline void PHD_DisableComparator(PHD_Type *base)#

Disables the PHD comparator analog block (PHASECTRL[CMP_EN]).

Disabling CMP_EN automatically clears all CFF/CFR flags in hardware.

Parameters:

base – PHD peripheral base address.

static inline void PHD_SetPhaseSelect(PHD_Type *base, uint32_t phaseMask)#

Selects which phase windings are connected to the virtual neutral network.

Parameters:

base – PHD peripheral base address.
phaseMask – OR-combination of phd_phase_select_t values. Pass 0 to disconnect all phases.

static inline void PHD_EnableComparator0Interrupts(PHD_Type *base, uint32_t mask)#

Enables interrupts for phase comparator 0 (PHCMP0SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of phd_comparator_interrupt_t values.

static inline void PHD_DisableComparator0Interrupts(PHD_Type *base, uint32_t mask)#

Disables interrupts for phase comparator 0 (PHCMP0SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of phd_comparator_interrupt_t values.

static inline void PHD_EnableComparator1Interrupts(PHD_Type *base, uint32_t mask)#

Enables interrupts for phase comparator 1 (PHCMP1SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of phd_comparator_interrupt_t values.

static inline void PHD_DisableComparator1Interrupts(PHD_Type *base, uint32_t mask)#

Disables interrupts for phase comparator 1 (PHCMP1SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of phd_comparator_interrupt_t values.

static inline void PHD_EnableComparator2Interrupts(PHD_Type *base, uint32_t mask)#

Enables interrupts for phase comparator 2 (PHCMP2SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of phd_comparator_interrupt_t values.

static inline void PHD_DisableComparator2Interrupts(PHD_Type *base, uint32_t mask)#

Disables interrupts for phase comparator 2 (PHCMP2SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of phd_comparator_interrupt_t values.

static inline uint32_t PHD_GetComparator0StatusFlags(PHD_Type *base)#

Returns the status flags for phase comparator 0 (PHCMP0SCR).

Parameters:

base – PHD peripheral base address.

Returns:

OR-combination of phd_comparator_status_flag_t values currently asserted.

static inline void PHD_ClearComparator0StatusFlags(PHD_Type *base, uint32_t mask)#

Clears W1C status flags for phase comparator 0 (PHCMP0SCR).

COUT is read-only and is masked out; only CFF and CFR are cleared.

Parameters:

base – PHD peripheral base address.
mask – OR-combination of kPHD_ComparatorFallingFlag and/or kPHD_ComparatorRisingFlag.

static inline uint32_t PHD_GetComparator1StatusFlags(PHD_Type *base)#

Returns the status flags for phase comparator 1 (PHCMP1SCR).

Parameters:

base – PHD peripheral base address.

Returns:

OR-combination of phd_comparator_status_flag_t values currently asserted.

static inline void PHD_ClearComparator1StatusFlags(PHD_Type *base, uint32_t mask)#

Clears W1C status flags for phase comparator 1 (PHCMP1SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of kPHD_ComparatorFallingFlag and/or kPHD_ComparatorRisingFlag.

static inline uint32_t PHD_GetComparator2StatusFlags(PHD_Type *base)#

Returns the status flags for phase comparator 2 (PHCMP2SCR).

Parameters:

base – PHD peripheral base address.

Returns:

OR-combination of phd_comparator_status_flag_t values currently asserted.

static inline void PHD_ClearComparator2StatusFlags(PHD_Type *base, uint32_t mask)#

Clears W1C status flags for phase comparator 2 (PHCMP2SCR).

Parameters:

base – PHD peripheral base address.
mask – OR-combination of kPHD_ComparatorFallingFlag and/or kPHD_ComparatorRisingFlag.

static inline uint8_t PHD_GetPhaseStatus(PHD_Type *base)#

Returns the current phase detector output word (PHASESTAT[PHASE]).

Each bit corresponds to one comparator’s filtered output (COUT): bit 0 = PHCMP0, bit 1 = PHCMP1, bit 2 = PHCMP2.

Parameters:

base – PHD peripheral base address.

Returns:

3-bit phase status value.

FSL_PHD_DRIVER_VERSION#: PHD driver version 2.0.0.

enum _phd_hysteresis#

PHD comparator hysteresis level.

Selects the internally generated hysteresis for the comparator hard block (PHASECTRL[HYSTCTR]). See chip data sheet to get the actual hysteresis value with each level.

Values:

enumerator kPHD_HysteresisLevel0#: Analog comparator hysteresis level 0.

enumerator kPHD_HysteresisLevel1#: Analog comparator hysteresis level 1.

enumerator kPHD_HysteresisLevel2#: Analog comparator hysteresis level 2.

enumerator kPHD_HysteresisLevel3#: Analog comparator hysteresis level 3.

enum _phd_clock_source#

PHD functional clock source (PHASECTRL[FUNC_CLK_SEL]).

See the chip-specific PHD information for the clock assigned to each source.

Values:

enumerator kPHD_FuncClockSource0#: Functional clock source 0.

enumerator kPHD_FuncClockSource1#: Functional clock source 1.

enumerator kPHD_FuncClockSource2#: Functional clock source 2.

enumerator kPHD_FuncClockSource3#: Functional clock source 3.

enum _phd_filter_count#

PHD filter sample count (PHASECTRL[FILT_CNT]).

Number of consecutive matching samples required before the filter propagates a state change. Zero bypasses the filter (COUT = COUTA).

Values:

enumerator kPHD_FilterCountBypass#: Filter bypassed: COUT = COUTA.

enumerator kPHD_FilterCount1#: 1 consecutive sample.

enumerator kPHD_FilterCount2#: 2 consecutive samples.

enumerator kPHD_FilterCount3#: 3 consecutive samples.

enumerator kPHD_FilterCount4#: 4 consecutive samples.

enumerator kPHD_FilterCount5#: 5 consecutive samples.

enumerator kPHD_FilterCount6#: 6 consecutive samples.

enumerator kPHD_FilterCount7#: 7 consecutive samples.

enum _phd_comparator_output_select#

Comparator output path selection (PHCMPnCR[COUT_SEL]).

Values:

enumerator kPHD_OutputFiltered#: Use COUT (filtered output) for CMPO.

enumerator kPHD_OutputUnfiltered#: Use COUTA (unfiltered output) for CMPO.

enum _phd_ibias_trim#

PHD IBIAS trim value selection (PHASECTRL[IBIAS_TRIM]).

Values:

enumerator kPHD_IbiasTrimValue0#: IBIAS trim value 0.

enumerator kPHD_IbiasTrimValue1#: IBIAS trim value 1.

enum _phd_phase_select#

PHD phase selection mask for PHD_SetPhaseSelect() (PHASECTRL[PHSEL0/1/2]).

OR together the phases to be connected to the virtual neutral network.

Values:

enumerator kPHD_Phase0#: Virtual network phase 0 (PHSEL0).

enumerator kPHD_Phase1#: Virtual network phase 1 (PHSEL1).

enumerator kPHD_Phase2#: Virtual network phase 2 (PHSEL2).

enum _phd_comparator_interrupt#

PHD comparator interrupt enable mask (PHCMPnSCR bits 4–5).

OR together the desired interrupt sources and pass to PHD_EnableComparatorNInterrupts() / PHD_DisableComparatorNInterrupts().

Values:

enumerator kPHD_ComparatorFallingInterruptEnable#: Falling-edge interrupt enable (CFF_IE).

enumerator kPHD_ComparatorRisingInterruptEnable#: Rising-edge interrupt enable (CFR_IE).

enum _phd_comparator_status_flag#

PHD comparator status flag mask (PHCMPnSCR bits 0–2).

OR together the desired flags and pass to PHD_GetComparatorNStatusFlags() / PHD_ClearComparatorNStatusFlags(). COUT is read-only; CFF and CFR are write-1-to-clear (W1C).

Values:

enumerator kPHD_ComparatorOutputFlag#: Current comparator output value (read-only).

enumerator kPHD_ComparatorFallingFlag#: Falling edge detected on comparator output (W1C).

enumerator kPHD_ComparatorRisingFlag#: Rising edge detected on comparator output (W1C).

typedef enum _phd_hysteresis phd_hysteresis_t#

PHD comparator hysteresis level.

Selects the internally generated hysteresis for the comparator hard block (PHASECTRL[HYSTCTR]). See chip data sheet to get the actual hysteresis value with each level.

typedef enum _phd_clock_source phd_clock_source_t#

PHD functional clock source (PHASECTRL[FUNC_CLK_SEL]).

See the chip-specific PHD information for the clock assigned to each source.

typedef enum _phd_filter_count phd_filter_count_t#

PHD filter sample count (PHASECTRL[FILT_CNT]).

Number of consecutive matching samples required before the filter propagates a state change. Zero bypasses the filter (COUT = COUTA).

typedef enum _phd_comparator_output_select phd_comparator_output_select_t#: Comparator output path selection (PHCMPnCR[COUT_SEL]).

typedef enum _phd_ibias_trim phd_ibias_trim_t#: PHD IBIAS trim value selection (PHASECTRL[IBIAS_TRIM]).

typedef enum _phd_phase_select phd_phase_select_t#

PHD phase selection mask for PHD_SetPhaseSelect() (PHASECTRL[PHSEL0/1/2]).

OR together the phases to be connected to the virtual neutral network.

typedef struct _phd_config phd_config_t#

PHD module configuration structure (PHASECTRL).

Covers the static PHASECTRL fields set at initialisation. CMP_EN is controlled by PHD_EnableComparator() / PHD_DisableComparator(). PHSEL0/1/2 are runtime-dynamic and controlled by PHD_SetPhaseSelect().

typedef struct _phd_comparator_config phd_comparator_config_t#

Per-comparator configuration structure (PHCMPnCR).

Shared by PHD_ConfigComparator0(), PHD_ConfigComparator1(), and PHD_ConfigComparator2(). SAMPLE_EN takes precedence over WINDOW_EN when both are set (hardware behavior).

typedef enum _phd_comparator_interrupt phd_comparator_interrupt_t#

PHD comparator interrupt enable mask (PHCMPnSCR bits 4–5).

OR together the desired interrupt sources and pass to PHD_EnableComparatorNInterrupts() / PHD_DisableComparatorNInterrupts().

typedef enum _phd_comparator_status_flag phd_comparator_status_flag_t#

PHD comparator status flag mask (PHCMPnSCR bits 0–2).

OR together the desired flags and pass to PHD_GetComparatorNStatusFlags() / PHD_ClearComparatorNStatusFlags(). COUT is read-only; CFF and CFR are write-1-to-clear (W1C).

struct _phd_config#

#include <fsl_phd.h>

PHD module configuration structure (PHASECTRL).

Public Members

bool enableComparatorInStopMode#: Allow comparator to run in stop/deep-sleep mode (CMP_STOP_EN).

phd_hysteresis_t hysteresisLevel#: Comparator hysteresis level (HYSTCTR).

phd_clock_source_t clockSource#: Functional clock source for window/filter logic (FUNC_CLK_SEL).

bool enableExternalNeutral#: Connect virtual neutral to external reference pin (EXTSEL).

bool enableInternalNeutral#: Connect virtual neutral to on-chip 8-bit DAC (INTSEL).

bool enableVirtualNetwork#: Enable virtual resistor network circuit (VNEN).

phd_ibias_trim_t ibiasTrim#: IBIAS trim value selection (IBIAS_TRIM).

phd_filter_count_t filterCount#: Filter sample count; kPHD_FilterCountBypass disables filter (FILT_CNT).

uint8_t filterPeriod#: Filter sample period in functional clock cycles (FILT_PER). 0 bypasses filter. No effect when SAMPLE_EN = 1.

struct _phd_comparator_config#

#include <fsl_phd.h>

Per-comparator configuration structure (PHCMPnCR).

Shared by PHD_ConfigComparator0(), PHD_ConfigComparator1(), and PHD_ConfigComparator2(). SAMPLE_EN takes precedence over WINDOW_EN when both are set (hardware behavior).

Public Members

bool enableOutputPin#: Make comparator output available on external pin (COUT_PEN).

phd_comparator_output_select_t outputSelect#: Select COUT (filtered) or COUTA (unfiltered) for CMPO (COUT_SEL).

bool invertOutput#: Invert comparator output polarity (COUT_INV).

bool enableWindowMode#: Enable windowed-comparator mode (WINDOW_EN). Valid only when enableSampleMode is false.

bool enableSampleMode#: Enable sampled-comparator mode (SAMPLE_EN). Takes precedence over enableWindowMode.

PIT: Periodic Interrupt Timer (PIT) Driver#

void PIT_Init(PIT_Type *base, const pit_config_t *psConfig)#

Ungates the PIT clock, configures the PIT features. The configurations are:

Clock source selection for PIT module
Prescaler configuration to the input clock source
PIT period interval
PIT slave mode enable/disable
Interrupt enable/disable
PIT timer enable/disable
Preset Polarity positive edge/negative edge

Note

This API should be called at the beginning of the application using the PIT driver and call PIT_StartTimer() API to start PIT timer.

Parameters:

base – PIT peripheral base address
psConfig – Pointer to the user’s PIT config structure

void PIT_Deinit(PIT_Type *base)#

Gates the PIT clock and disables the PIT module.

Parameters:

base – PIT peripheral base address

void PIT_GetDefaultConfig(pit_config_t *psConfig)#

Fill in the PIT config structure with the default settings.

This function initializes the PIT configuration structure to default values.

psConfig->eClockSource = kPIT_CountClockSource0;
psConfig->bEnableTimer = false;
psConfig->bEnableSlaveMode = false;
psConfig->ePrescaler = kPIT_PrescalerDivBy1;
psConfig->bEnableInterrupt = false;
psConfig->u32PeriodCount = 0xFFFFFFFFU;
psConfig->bEnableNegativeEdge = false;
psConfig->sPresetFilter.u16FilterSamplePeriod = 0x0U;
psConfig->sPresetFilter.u16FilterSampleCount = 0x0U;
psConfig->sPresetFilter.bFilterClock = true;
psConfig->sPresetFilter.eFilterPrescalerPeripheral = kPIT_PrescalerDivBy1;
psConfig->sSyncSource.u8StretchCount = 0x0U;
psConfig->sSyncSource.eSyncOutSel = kPIT_Syncout_Default;

Parameters:

psConfig – Pointer to user’s PIT config structure.

static inline void PIT_EnableSlaveMode(PIT_Type *base, bool bEnable)#

Enable/Disable PIT slave mode.

Parameters:

base – PIT peripheral base address
bEnable – enable/disable slave mode

static inline void PIT_SetTimerPrescaler(PIT_Type *base, pit_prescaler_value_t ePrescaler)#

Sets the PIT clock prescaler.

Parameters:

base – PIT peripheral base address
ePrescaler – Timer prescaler value

static inline void PIT_SetTimerPeriod(PIT_Type *base, uint32_t u32PeriodCount)#

Sets the timer period in units of count.

Timers begin counting from 0 until it reaches the value set by this function, then it generates an interrupt and counter resumes counting from 0 again.

Note

Users can call the utility macros provided in fsl_common.h to convert to ticks.

Parameters:

base – PIT peripheral base address
u32PeriodCount – Timer period in units of ticks, use macro definition MSEC_TO_COUNT to convert value in ms to count of ticks, the PIT clock rate is source clock divide prescaler.

static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base)#

Reads the current timer counting value.

This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note

Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec.

Parameters:

base – PIT peripheral base address

Returns:

Current timer counting value in ticks, use macro definition COUNT_TO_MSEC to convert value in ticks to count of millisecond, the PIT clock rate is source clock divide prescaler.

static inline void PIT_StartTimer(PIT_Type *base)#

Starts the timer counting.

After calling this function, timers load period value, count down to 0 and then load the respective start value again. Each time a timer reaches 0, it generates a trigger pulse and sets the timeout interrupt flag.

Parameters:

base – PIT peripheral base address

static inline void PIT_StopTimer(PIT_Type *base)#

Stops the timer counting.

This function stops timer counting, and the counter remains at or returns to a 0 value.

Parameters:

base – PIT peripheral base address

static inline void PIT_EnableInterrupt(PIT_Type *base)#

Enables the PIT interrupts.

Parameters:

base – PIT peripheral base address

static inline void PIT_DisableInterrupt(PIT_Type *base)#

Disables the selected PIT interrupts.

Parameters:

base – PIT peripheral base address

static inline uint16_t PIT_GetStatusFlags(PIT_Type *base)#

Gets the PIT status flags.

Parameters:

base – PIT peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration _pit_status_flags

static inline void PIT_ClearStatusFlags(PIT_Type *base)#

Clears the PIT status flags.

Parameters:

base – PIT peripheral base address

static inline void PIT_SetPresetFiltConfig(PIT_Type *base, const pit_config_filt_t psConfig)#

Set FILT configurations.

Parameters:

base – PIT peripheral base address
psConfig – Pointer to user’s PIT FILT config structure

static inline void PIT_SetSyncOutConfig(PIT_Type *base, const pit_config_ctrl2_t psConfig)#

Set Sync configurations.

Parameters:

base – PIT peripheral base address
psConfig – Pointer to user’s PIT SYNC config structure

FSL_PIT_DRIVER_VERSION#: PIT driver version.

enum _pit_prescaler_value#

PIT clock prescaler values.

Values:

enumerator kPIT_PrescalerDivBy1#: Clock divided by 1

enumerator kPIT_PrescalerDivBy2#: Clock divided by 2

enumerator kPIT_PrescalerDivBy4#: Clock divided by 4

enumerator kPIT_PrescalerDivBy8#: Clock divided by 8

enumerator kPIT_PrescalerDivBy16#: Clock divided by 16

enumerator kPIT_PrescalerDivBy32#: Clock divided by 32

enumerator kPIT_PrescalerDivBy64#: Clock divided by 64

enumerator kPIT_PrescalerDivBy128#: Clock divided by 128

enumerator kPIT_PrescalerDivBy256#: Clock divided by 256

enumerator kPIT_PrescalerDivBy512#: Clock divided by 512

enumerator kPIT_PrescalerDivBy1024#: Clock divided by 1024

enumerator kPIT_PrescalerDivBy2048#: Clock divided by 2048

enumerator kPIT_PrescalerDivBy4096#: Clock divided by 4096

enumerator kPIT_PrescalerDivBy8192#: Clock divided by 8192

enumerator kPIT_PrescalerDivBy16384#: Clock divided by 16384

enumerator kPIT_PrescalerDivBy32768#: Clock divided by 32768

enum _pit_status_flags#

List of PIT status flags.

Values:

enumerator kPIT_Timer_RollOverFlag#: Timer roll over flag

enum _pit_syncout_mode#

List of SYNC_OUT output mode.

Values:

enumerator kPIT_Syncout_Default#: SYNC_OUT takes affect when PIT counter equals to the MODULO value (default)

enumerator kPIT_Syncout_Toggle#: SYNC_OUT is in toggle mode

typedef enum _pit_prescaler_value pit_prescaler_value_t#: PIT clock prescaler values.

typedef enum _pit_syncout_mode pit_syncout_mode_t#: List of SYNC_OUT output mode.

typedef struct _pit_config_filt pit_config_filt_t#

PIT FILT configuration structure.

This structure holds the configuration settings for the PIT FILT register. To initialize this structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a pointer to your config structure instance.

The configuration structure can be made constant so it resides in flash.

typedef struct _pit_config_ctrl2 pit_config_ctrl2_t#

PIT CTRL2 configuration structure.

This structure holds the configuration settings for the PIT CTRL2 register. To initialize this structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a pointer to your config structure instance.

The configuration structure can be made constant so it resides in flash.

typedef struct _pit_config pit_config_t#

PIT configuration structure.

This structure holds the configuration settings for the PIT peripheral. To initialize this structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a pointer to your config structure instance.

The configuration structure can be made constant so it resides in flash.

struct _pit_config_filt#

#include <fsl_pit.h>

PIT FILT configuration structure.

The configuration structure can be made constant so it resides in flash.

Public Members

bool bFilterClock#: Filter Clock Source selection.

pit_prescaler_value_t eFilterPrescalerPeripheral#: Sets the peripheral clock prescaler.

uint8_t u16FilterSampleCount#: Input Filter Sample Count.

uint8_t u16FilterSamplePeriod#: Input Filter Sample Period.

struct _pit_config_ctrl2#

#include <fsl_pit.h>

PIT CTRL2 configuration structure.

The configuration structure can be made constant so it resides in flash.

Public Members

uint8_t u8StretchCount#: The cycle number to be stretched for SYNC_OUT signal.

pit_syncout_mode_t eSyncOutSel#: Select the output mode of SYNC_OUT.

struct _pit_config#

#include <fsl_pit.h>

PIT configuration structure.

The configuration structure can be made constant so it resides in flash.

Public Members

pit_prescaler_value_t ePrescaler#: Clock prescaler value

bool bEnableInterrupt#: Enable PIT Roll-Over Interrupt

bool bEnableSlaveMode#: Enable the PIT module in slave mode, in which mode the timer will be triggered by master PIT enable.

bool bEnableTimer#: PIT timer enable flag, which is false by default

pit_count_clock_source_t eClockSource#: Specify the PIT count clock source

uint32_t u32PeriodCount#: Timer period in clock cycles, Use macro definition MSEC_TO_COUNT to convert value in ms to count of ticks, the COP clock rate is source clock divide prescaler.

bool bEnableNegativeEdge#: choose the polarity of Preset input.

pit_config_filt_t sPresetFilter#: Specify the PIT preset filter source

pit_config_ctrl2_t sSyncSource#: Specify the PIT Sync source

The Driver Change Log#

PIT Peripheral and Driver Overview#

PORT: Port Control and Interrupts#

static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)#

Get PORT version information.

Parameters:

base – PORT peripheral base pointer
info – PORT version information

static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)#

Get PORT version information.

Note

: PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and PORTC_CONFIG[RANGE] does not take effect.

Parameters:

base – PORT peripheral base pointer
range – port voltage range

static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)#

Sets the port PCR register.

This is an example to define an input pin or output pin PCR configuration.

// Define a digital input pin PCR configuration
port_pin_config_t config = {
     kPORT_PullUp,
     kPORT_FastSlewRate,
     kPORT_PassiveFilterDisable,
     kPORT_OpenDrainDisable,
     kPORT_LowDriveStrength,
     kPORT_MuxAsGpio,
     kPORT_UnLockRegister,
};

Parameters:

base – PORT peripheral base pointer.
pin – PORT pin number.
config – PORT PCR register configuration structure.

static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)#

Sets the port PCR register for multiple pins.

This is an example to define input pins or output pins PCR configuration.

Define a digital input pin PCR configuration
port_pin_config_t config = {
     kPORT_PullUp ,
     kPORT_PullEnable,
     kPORT_FastSlewRate,
     kPORT_PassiveFilterDisable,
     kPORT_OpenDrainDisable,
     kPORT_LowDriveStrength,
     kPORT_MuxAsGpio,
     kPORT_UnlockRegister,
};

Parameters:

base – PORT peripheral base pointer.
mask – PORT pin number macro.
config – PORT PCR register configuration structure.

static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)#

Configures the pin muxing.

Note

: This function is NOT recommended to use together with the PORT_SetPinsConfig, because the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is reset to zero : kPORT_PinDisabledOrAnalog). This function is recommended to use to reset the pin mux

Parameters:

base – PORT peripheral base pointer.
pin – PORT pin number.
mux – pin muxing slot selection.
- kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
- kPORT_MuxAsGpio : Set as GPIO.
- kPORT_MuxAlt2 : chip-specific.
- kPORT_MuxAlt3 : chip-specific.
- kPORT_MuxAlt4 : chip-specific.
- kPORT_MuxAlt5 : chip-specific.
- kPORT_MuxAlt6 : chip-specific.
- kPORT_MuxAlt7 : chip-specific.

static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)#

Enables the digital filter in one port, each bit of the 32-bit register represents one pin.

Parameters:

base – PORT peripheral base pointer.
mask – PORT pin number macro.
enable – PORT digital filter configuration.

static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)#

Sets the digital filter in one port, each bit of the 32-bit register represents one pin.

Parameters:

base – PORT peripheral base pointer.
config – PORT digital filter configuration structure.

static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)#

Configures the port pin drive strength.

Parameters:

base – PORT peripheral base pointer.
pin – PORT pin number.
strength – PORT pin drive strength
- kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
- kPORT_HighDriveStrength = 1U - High-drive strength is configured.

static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)#

Enables the port pin double drive strength.

Parameters:

base – PORT peripheral base pointer.
pin – PORT pin number.
enable – PORT pin drive strength configuration.

static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)#

Configures the port pin pull value.

Parameters:

base – PORT peripheral base pointer.
pin – PORT pin number.
value – PORT pin pull value
- kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.
- kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.

static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)#

Get EFT detect flags.

Parameters:

base – PORT peripheral base pointer

Returns:

EFT detect flags

static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)#

Enable EFT detect interrupts.

Parameters:

base – PORT peripheral base pointer
interrupt – EFT detect interrupt

static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)#

Disable EFT detect interrupts.

Parameters:

base – PORT peripheral base pointer
interrupt – EFT detect interrupt

static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)#

Clear all low EFT detector.

Note

: Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the PORTB_EDCR does not take effect.

Parameters:

base – PORT peripheral base pointer

static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)#

Clear all high EFT detector.

Parameters:

base – PORT peripheral base pointer

FSL_PORT_DRIVER_VERSION#: PORT driver version.

enum _port_pull#

Internal resistor pull feature selection.

Values:

enumerator kPORT_PullDisable#: Internal pull-up/down resistor is disabled.

enumerator kPORT_PullDown#: Internal pull-down resistor is enabled.

enumerator kPORT_PullUp#: Internal pull-up resistor is enabled.

enum _port_pull_value#

Internal resistor pull value selection.

Values:

enumerator kPORT_LowPullResistor#: Low internal pull resistor value is selected.

enumerator kPORT_HighPullResistor#: High internal pull resistor value is selected.

enum _port_slew_rate#

Slew rate selection.

Values:

enumerator kPORT_FastSlewRate#: Fast slew rate is configured.

enumerator kPORT_SlowSlewRate#: Slow slew rate is configured.

enum _port_open_drain_enable#

Open Drain feature enable/disable.

Values:

enumerator kPORT_OpenDrainDisable#: Open drain output is disabled.

enumerator kPORT_OpenDrainEnable#: Open drain output is enabled.

enum _port_passive_filter_enable#

Passive filter feature enable/disable.

Values:

enumerator kPORT_PassiveFilterDisable#: Passive input filter is disabled.

enumerator kPORT_PassiveFilterEnable#: Passive input filter is enabled.

enum _port_drive_strength#

Configures the drive strength.

Values:

enumerator kPORT_LowDriveStrength#: Low-drive strength is configured.

enumerator kPORT_HighDriveStrength#: High-drive strength is configured.

enum _port_drive_strength1#

Configures the drive strength1.

Values:

enumerator kPORT_NormalDriveStrength#: Normal drive strength

enumerator kPORT_DoubleDriveStrength#: Double drive strength

enum _port_input_buffer#

input buffer disable/enable.

Values:

enumerator kPORT_InputBufferDisable#: Digital input is disabled

enumerator kPORT_InputBufferEnable#: Digital input is enabled

enum _port_invet_input#

Digital input is not inverted or it is inverted.

Values:

enumerator kPORT_InputNormal#: Digital input is not inverted

enumerator kPORT_InputInvert#: Digital input is inverted

enum _port_lock_register#

Unlock/lock the pin control register field[15:0].

Values:

enumerator kPORT_UnlockRegister#: Pin Control Register fields [15:0] are not locked.

enumerator kPORT_LockRegister#: Pin Control Register fields [15:0] are locked.

enum _port_mux#

Pin mux selection.

Values:

enumerator kPORT_PinDisabledOrAnalog#: Corresponding pin is disabled, but is used as an analog pin.

enumerator kPORT_MuxAsGpio#: Corresponding pin is configured as GPIO.

enumerator kPORT_MuxAlt0#: Chip-specific

enumerator kPORT_MuxAlt1#: Chip-specific

enumerator kPORT_MuxAlt2#: Chip-specific

enumerator kPORT_MuxAlt3#: Chip-specific

enumerator kPORT_MuxAlt4#: Chip-specific

enumerator kPORT_MuxAlt5#: Chip-specific

enumerator kPORT_MuxAlt6#: Chip-specific

enumerator kPORT_MuxAlt7#: Chip-specific

enumerator kPORT_MuxAlt8#: Chip-specific

enumerator kPORT_MuxAlt9#: Chip-specific

enumerator kPORT_MuxAlt10#: Chip-specific

enumerator kPORT_MuxAlt11#: Chip-specific

enumerator kPORT_MuxAlt12#: Chip-specific

enumerator kPORT_MuxAlt13#: Chip-specific

enumerator kPORT_MuxAlt14#: Chip-specific

enumerator kPORT_MuxAlt15#: Chip-specific

enum _port_digital_filter_clock_source#

Digital filter clock source selection.

Values:

enumerator kPORT_BusClock#: Digital filters are clocked by the bus clock.

enumerator kPORT_LpoClock#: Digital filters are clocked by the 1 kHz LPO clock.

enum _port_voltage_range#

PORT voltage range.

Values:

enumerator kPORT_VoltageRange1Dot71V_3Dot6V#: Port voltage range is 1.71 V - 3.6 V.

enumerator kPORT_VoltageRange2Dot70V_3Dot6V#: Port voltage range is 2.70 V - 3.6 V.

typedef enum _port_mux port_mux_t#: Pin mux selection.

typedef enum _port_digital_filter_clock_source port_digital_filter_clock_source_t#: Digital filter clock source selection.

typedef struct _port_digital_filter_config port_digital_filter_config_t#: PORT digital filter feature configuration definition.

typedef struct _port_pin_config port_pin_config_t#: PORT pin configuration structure.

typedef struct _port_version_info port_version_info_t#: PORT version information.

typedef enum _port_voltage_range port_voltage_range_t#: PORT voltage range.

FSL_COMPONENT_ID#

struct _port_digital_filter_config#

#include <fsl_port.h>

PORT digital filter feature configuration definition.

Public Members

uint32_t digitalFilterWidth#: Set digital filter width

port_digital_filter_clock_source_t clockSource#: Set digital filter clockSource

struct _port_pin_config#

#include <fsl_port.h>

PORT pin configuration structure.

Public Members

uint16_t pullSelect#: No-pull/pull-down/pull-up select

uint16_t pullValueSelect#: Pull value select

uint16_t slewRate#: Fast/slow slew rate Configure

uint16_t passiveFilterEnable#: Passive filter enable/disable

uint16_t openDrainEnable#: Open drain enable/disable

uint16_t driveStrength#: Fast/slow drive strength configure

uint16_t driveStrength1#: Normal/Double drive strength enable/disable

uint16_t inputBuffer#: Input Buffer Configure

uint16_t invertInput#: Invert Input Configure

uint16_t lockRegister#: Lock/unlock the PCR field[15:0]

struct _port_version_info#

#include <fsl_port.h>

PORT version information.

Public Members

uint16_t feature#: Feature Specification Number.

uint8_t minor#: Minor Version Number.

uint8_t major#: Major Version Number.

PWM: Pulse Width Modulator#

status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config)#

Ungates the PWM submodule clock and configures the peripheral for basic operation.

This API should be called at the beginning of the application using the PWM driver. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. When output PWMX in center aligned mode, VAL1 register controls both PWM period and PWMX duty cycle, PWMA and PWMB output will be corrupted. But edge aligned PWMX output do not have such limit. In master reload counter initialization mode, PWM period is depended by period of set LDOK in submodule 0 because this operation will reload register. Submodule 0 counter initialization cannot be master sync or master reload.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
config – Pointer to user’s PWM config structure.

Returns:

kStatus_Success means success; else failed.

void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule)#

Gate the PWM submodule clock.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to deinitialize

void PWM_GetDefaultConfig(pwm_config_t *config)#

Fill in the PWM config struct with the default settings.

The default values are:

config->enableDebugMode = false;
config->enableWait = false;
config->reloadSelect = kPWM_LocalReload;
config->clockSource = kPWM_BusClock;
config->prescale = kPWM_Prescale_Divide_1;
config->initializationControl = kPWM_Initialize_LocalSync;
config->forceTrigger = kPWM_Force_Local;
config->reloadFrequency = kPWM_LoadEveryOportunity;
config->reloadLogic = kPWM_ReloadImmediate;
config->pairOperation = kPWM_Independent;

Parameters:

config – Pointer to user’s PWM config structure.

status_t PWM_SetupPwm(PWM_Type *base, pwm_submodule_t subModule, const pwm_signal_param_t *chnlParams, uint8_t numOfChnls, pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)#

Sets up the PWM signals for a PWM submodule.

The function initializes the submodule according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. When user select PWMX, user must choose edge aligned output, becasue there are some limitation on center aligned PWMX output. Due to edge aligned PWMX is negative true signal, need to configure PWMX active low true level to get correct duty cycle. The half cycle point will not be exactly in the middle of the PWM cycle when PWMX enabled.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
chnlParams – Array of PWM channel parameters to configure the channel(s).
numOfChnls – Number of channels to configure, this should be the size of the array passed in. Array size should not be more than 3 as each submodule has 3 pins to output PWM.
mode – PWM operation mode, options available in enumeration pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 prescaler value instead of submodule0 source clock.

Returns:

Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise

status_t PWM_SetupPwmPhaseShift(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, uint8_t shiftvalue, bool doSync)#

Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – PWM main counter clock in Hz.
shiftvalue – Phase shift value, range in 0 ~ 50
doSync – true: Set LDOK bit for the submodule list; false: LDOK bit don’t set, need to call PWM_SetPwmLdok to sync update.

Returns:

Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise

void PWM_UpdatePwmDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint8_t dutyCyclePercent)#

Updates the PWM signal’s dutycycle.

The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmSignal – Signal (PWM A, PWM B, PWM X) to update
currPwmMode – The current PWM mode set during PWM setup
dutyCyclePercent – New PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)

void PWM_UpdatePwmDutycycleHighAccuracy(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle)#

Updates the PWM signal’s dutycycle with 16-bit accuracy.

The function updates the PWM dutycyle to the new value that is passed in. If the dead time insertion logic is enabled then the pulse period is reduced by the dead time period specified by the user.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmSignal – Signal (PWM A, PWM B, PWM X) to update
currPwmMode – The current PWM mode set during PWM setup
dutyCycle – New PWM pulse width, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle)

void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t pulseCnt, uint16_t dutyCycle)#

Update the PWM signal’s period and dutycycle for a PWM submodule.

The function updates PWM signal period generated by a specific submodule according to the parameters passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle or update new dutycycle. Call this function in local sync control mode because PWM period is depended by

INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time period specified by the user. PWM signal will not be generated if its period is less than dead time duration.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmSignal – Signal (PWM A or PWM B) to update
currPwmMode – The current PWM mode set during PWM setup, options available in enumeration pwm_mode_t
pulseCnt – New PWM period, value should be between 0 to 65535 0=minimum PWM period… 65535=maximum PWM period
dutyCycle – New PWM pulse width of channel, value should be between 0 to 65535 0=inactive signal(0% duty cycle)… 65535=active signal (100% duty cycle) You can keep original duty cycle or update new duty cycle

static inline void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)#

Enables the selected PWM interrupts.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t

static inline void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)#

Disables the selected PWM interrupts.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwm_interrupt_enable_t

static inline uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule)#

Gets the enabled PWM interrupts.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration pwm_interrupt_enable_t

static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, pwm_submodule_t subModule, pwm_watermark_control_t pwm_watermark_control)#

Capture DMA Enable Source Select.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwm_watermark_control – PWM FIFO watermark and control

static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, pwm_submodule_t subModule, pwm_dma_source_select_t pwm_dma_source_select)#

Capture DMA Enable Source Select.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwm_dma_source_select – PWM capture DMA enable source select

static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate)#

Enables or disables the selected PWM DMA Capture read request.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The DMA to enable or disable. This is a logical OR of members of the enumeration pwm_dma_enable_t
activate – true: Enable DMA read request; false: Disable DMA read request

static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate)#

Enables or disables the PWM DMA write request.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
activate – true: Enable DMA write request; false: Disable DMA write request

static inline uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule)#

Gets the PWM status flags.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure

Returns:

The status flags. This is the logical OR of members of the enumeration pwm_status_flags_t

static inline void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask)#

Clears the PWM status flags.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
mask – The status flags to clear. This is a logical OR of members of the enumeration pwm_status_flags_t

static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart)#

Starts the PWM counter for a single or multiple submodules.

Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple submodules at the same time.

Parameters:

base – PWM peripheral base address
subModulesToStart – PWM submodules to start. This is a logical OR of members of the enumeration pwm_module_control_t

static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop)#

Stops the PWM counter for a single or multiple submodules.

Clears the Run bit which resets the submodule’s counter. This function can stop multiple submodules at the same time.

Parameters:

base – PWM peripheral base address
subModulesToStop – PWM submodules to stop. This is a logical OR of members of the enumeration pwm_module_control_t

FSL_PWM_DRIVER_VERSION#: Version 2.10.1

enum _pwm_submodule#

List of PWM submodules.

Values:

enumerator kPWM_Module_0#: Submodule 0

enumerator kPWM_Module_1#: Submodule 1

enumerator kPWM_Module_2#: Submodule 2

enum _pwm_channels#

List of PWM channels in each module.

Values:

enumerator kPWM_PwmB#

enumerator kPWM_PwmA#

enumerator kPWM_PwmX#

enum _pwm_value_register#

List of PWM value registers.

Values:

enumerator kPWM_ValueRegister_0#: PWM Value0 register

enumerator kPWM_ValueRegister_1#: PWM Value1 register

enumerator kPWM_ValueRegister_2#: PWM Value2 register

enumerator kPWM_ValueRegister_3#: PWM Value3 register

enumerator kPWM_ValueRegister_4#: PWM Value4 register

enumerator kPWM_ValueRegister_5#: PWM Value5 register

enum _pwm_value_register_mask#

List of PWM value registers mask.

Values:

enumerator kPWM_ValueRegisterMask_0#: PWM Value0 register mask

enumerator kPWM_ValueRegisterMask_1#: PWM Value1 register mask

enumerator kPWM_ValueRegisterMask_2#: PWM Value2 register mask

enumerator kPWM_ValueRegisterMask_3#: PWM Value3 register mask

enumerator kPWM_ValueRegisterMask_4#: PWM Value4 register mask

enumerator kPWM_ValueRegisterMask_5#: PWM Value5 register mask

enum _pwm_clock_source#

PWM clock source selection.

Values:

enumerator kPWM_BusClock#: Device specific IPBus clock, refer reference manual for frequency

enumerator kPWM_ExternalClock#: EXT_CLK is used as the clock

enumerator kPWM_Submodule0Clock#: Clock of the submodule 0 (AUX_CLK) is used as the source clock

enum _pwm_clock_prescale#

PWM prescaler factor selection for clock source.

Values:

enumerator kPWM_Prescale_Divide_1#: PWM clock frequency = fclk/1

enumerator kPWM_Prescale_Divide_2#: PWM clock frequency = fclk/2

enumerator kPWM_Prescale_Divide_4#: PWM clock frequency = fclk/4

enumerator kPWM_Prescale_Divide_8#: PWM clock frequency = fclk/8

enumerator kPWM_Prescale_Divide_16#: PWM clock frequency = fclk/16

enumerator kPWM_Prescale_Divide_32#: PWM clock frequency = fclk/32

enumerator kPWM_Prescale_Divide_64#: PWM clock frequency = fclk/64

enumerator kPWM_Prescale_Divide_128#: PWM clock frequency = fclk/128

enum _pwm_force_output_trigger#

Options that can trigger a PWM FORCE_OUT.

Values:

enumerator kPWM_Force_Local#: The local force signal, CTRL2[FORCE], from the submodule is used to force updates

enumerator kPWM_Force_Master#: The master force signal from submodule 0 is used to force updates

enumerator kPWM_Force_LocalReload#: The local reload signal from this submodule is used to force updates without regard to the state of LDOK

enumerator kPWM_Force_MasterReload#: The master reload signal from submodule 0 is used to force updates if LDOK is set

enumerator kPWM_Force_LocalSync#: The local sync signal from this submodule is used to force updates

enumerator kPWM_Force_MasterSync#: The master sync signal from submodule0 is used to force updates

enumerator kPWM_Force_External#: The external force signal, EXT_FORCE, from outside the PWM module causes updates

enumerator kPWM_Force_ExternalSync#: The external sync signal, EXT_SYNC, from outside the PWM module causes updates

enum _pwm_output_state#

PWM channel output status.

Values:

enumerator kPWM_HighState#: The output state of PWM channel is high

enumerator kPWM_LowState#: The output state of PWM channel is low

enumerator kPWM_NormalState#: The output state of PWM channel is normal

enumerator kPWM_InvertState#: The output state of PWM channel is invert

enumerator kPWM_MaskState#: The output state of PWM channel is mask

enum _pwm_init_source#

PWM counter initialization options.

Values:

enumerator kPWM_Initialize_LocalSync#: Local sync causes initialization

enumerator kPWM_Initialize_MasterReload#: Master reload from submodule 0 causes initialization

enumerator kPWM_Initialize_MasterSync#: Master sync from submodule 0 causes initialization

enumerator kPWM_Initialize_ExtSync#: EXT_SYNC causes initialization

enum _pwm_load_frequency#

PWM load frequency selection.

Values:

enumerator kPWM_LoadEveryOportunity#: Every PWM opportunity

enumerator kPWM_LoadEvery2Oportunity#: Every 2 PWM opportunities

enumerator kPWM_LoadEvery3Oportunity#: Every 3 PWM opportunities

enumerator kPWM_LoadEvery4Oportunity#: Every 4 PWM opportunities

enumerator kPWM_LoadEvery5Oportunity#: Every 5 PWM opportunities

enumerator kPWM_LoadEvery6Oportunity#: Every 6 PWM opportunities

enumerator kPWM_LoadEvery7Oportunity#: Every 7 PWM opportunities

enumerator kPWM_LoadEvery8Oportunity#: Every 8 PWM opportunities

enumerator kPWM_LoadEvery9Oportunity#: Every 9 PWM opportunities

enumerator kPWM_LoadEvery10Oportunity#: Every 10 PWM opportunities

enumerator kPWM_LoadEvery11Oportunity#: Every 11 PWM opportunities

enumerator kPWM_LoadEvery12Oportunity#: Every 12 PWM opportunities

enumerator kPWM_LoadEvery13Oportunity#: Every 13 PWM opportunities

enumerator kPWM_LoadEvery14Oportunity#: Every 14 PWM opportunities

enumerator kPWM_LoadEvery15Oportunity#: Every 15 PWM opportunities

enumerator kPWM_LoadEvery16Oportunity#: Every 16 PWM opportunities

enum _pwm_fault_input#

List of PWM fault selections.

Values:

enumerator kPWM_Fault_0#: Fault 0 input pin

enumerator kPWM_Fault_1#: Fault 1 input pin

enumerator kPWM_Fault_2#: Fault 2 input pin

enumerator kPWM_Fault_3#: Fault 3 input pin

enum _pwm_fault_disable#

List of PWM fault disable mapping selections.

Values:

enumerator kPWM_FaultDisable_0#: Fault 0 disable mapping

enumerator kPWM_FaultDisable_1#: Fault 1 disable mapping

enumerator kPWM_FaultDisable_2#: Fault 2 disable mapping

enumerator kPWM_FaultDisable_3#: Fault 3 disable mapping

enum _pwm_fault_channels#

List of PWM fault channels.

Values:

enumerator kPWM_faultchannel_0#

enum _pwm_input_capture_edge#

PWM capture edge select.

Values:

enumerator kPWM_Disable#: Disabled

enumerator kPWM_FallingEdge#: Capture on falling edge only

enumerator kPWM_RisingEdge#: Capture on rising edge only

enumerator kPWM_RiseAndFallEdge#: Capture on rising or falling edge

enum _pwm_force_signal#

PWM output options when a FORCE_OUT signal is asserted.

Values:

enumerator kPWM_UsePwm#: Generated PWM signal is used by the deadtime logic.

enumerator kPWM_InvertedPwm#: Inverted PWM signal is used by the deadtime logic.

enumerator kPWM_SoftwareControl#: Software controlled value is used by the deadtime logic.

enumerator kPWM_UseExternal#: PWM_EXTA signal is used by the deadtime logic.

enum _pwm_chnl_pair_operation#

Options available for the PWM A & B pair operation.

Values:

enumerator kPWM_Independent#: PWM A & PWM B operate as 2 independent channels

enumerator kPWM_ComplementaryPwmA#: PWM A & PWM B are complementary channels, PWM A generates the signal

enumerator kPWM_ComplementaryPwmB#: PWM A & PWM B are complementary channels, PWM B generates the signal

enum _pwm_register_reload#

Options available on how to load the buffered-registers with new values.

Values:

enumerator kPWM_ReloadImmediate#: Buffered-registers get loaded with new values as soon as LDOK bit is set

enumerator kPWM_ReloadPwmHalfCycle#: Registers loaded on a PWM half cycle

enumerator kPWM_ReloadPwmFullCycle#: Registers loaded on a PWM full cycle

enumerator kPWM_ReloadPwmHalfAndFullCycle#: Registers loaded on a PWM half & full cycle

enum _pwm_fault_recovery_mode#

Options available on how to re-enable the PWM output when recovering from a fault.

Values:

enumerator kPWM_NoRecovery#: PWM output will stay inactive

enumerator kPWM_RecoverHalfCycle#: PWM output re-enabled at the first half cycle

enumerator kPWM_RecoverFullCycle#: PWM output re-enabled at the first full cycle

enumerator kPWM_RecoverHalfAndFullCycle#: PWM output re-enabled at the first half or full cycle

enum _pwm_interrupt_enable#

List of PWM interrupt options.

Values:

enumerator kPWM_CompareVal0InterruptEnable#: PWM VAL0 compare interrupt

enumerator kPWM_CompareVal1InterruptEnable#: PWM VAL1 compare interrupt

enumerator kPWM_CompareVal2InterruptEnable#: PWM VAL2 compare interrupt

enumerator kPWM_CompareVal3InterruptEnable#: PWM VAL3 compare interrupt

enumerator kPWM_CompareVal4InterruptEnable#: PWM VAL4 compare interrupt

enumerator kPWM_CompareVal5InterruptEnable#: PWM VAL5 compare interrupt

enumerator kPWM_CaptureX0InterruptEnable#: PWM capture X0 interrupt

enumerator kPWM_CaptureX1InterruptEnable#: PWM capture X1 interrupt

enumerator kPWM_CaptureB0InterruptEnable#: PWM capture B0 interrupt

enumerator kPWM_CaptureB1InterruptEnable#: PWM capture B1 interrupt

enumerator kPWM_CaptureA0InterruptEnable#: PWM capture A0 interrupt

enumerator kPWM_CaptureA1InterruptEnable#: PWM capture A1 interrupt

enumerator kPWM_ReloadInterruptEnable#: PWM reload interrupt

enumerator kPWM_ReloadErrorInterruptEnable#: PWM reload error interrupt

enumerator kPWM_Fault0InterruptEnable#: PWM fault 0 interrupt

enumerator kPWM_Fault1InterruptEnable#: PWM fault 1 interrupt

enumerator kPWM_Fault2InterruptEnable#: PWM fault 2 interrupt

enumerator kPWM_Fault3InterruptEnable#: PWM fault 3 interrupt

enum _pwm_status_flags#

List of PWM status flags.

Values:

enumerator kPWM_CompareVal0Flag#: PWM VAL0 compare flag

enumerator kPWM_CompareVal1Flag#: PWM VAL1 compare flag

enumerator kPWM_CompareVal2Flag#: PWM VAL2 compare flag

enumerator kPWM_CompareVal3Flag#: PWM VAL3 compare flag

enumerator kPWM_CompareVal4Flag#: PWM VAL4 compare flag

enumerator kPWM_CompareVal5Flag#: PWM VAL5 compare flag

enumerator kPWM_CaptureX0Flag#: PWM capture X0 flag

enumerator kPWM_CaptureX1Flag#: PWM capture X1 flag

enumerator kPWM_CaptureB0Flag#: PWM capture B0 flag

enumerator kPWM_CaptureB1Flag#: PWM capture B1 flag

enumerator kPWM_CaptureA0Flag#: PWM capture A0 flag

enumerator kPWM_CaptureA1Flag#: PWM capture A1 flag

enumerator kPWM_ReloadFlag#: PWM reload flag

enumerator kPWM_ReloadErrorFlag#: PWM reload error flag

enumerator kPWM_RegUpdatedFlag#: PWM registers updated flag

enumerator kPWM_Fault0Flag#: PWM fault 0 flag

enumerator kPWM_Fault1Flag#: PWM fault 1 flag

enumerator kPWM_Fault2Flag#: PWM fault 2 flag

enumerator kPWM_Fault3Flag#: PWM fault 3 flag

enum _pwm_dma_enable#

List of PWM DMA options.

Values:

enumerator kPWM_CaptureX0DMAEnable#: PWM capture X0 DMA

enumerator kPWM_CaptureX1DMAEnable#: PWM capture X1 DMA

enumerator kPWM_CaptureB0DMAEnable#: PWM capture B0 DMA

enumerator kPWM_CaptureB1DMAEnable#: PWM capture B1 DMA

enumerator kPWM_CaptureA0DMAEnable#: PWM capture A0 DMA

enumerator kPWM_CaptureA1DMAEnable#: PWM capture A1 DMA

enum _pwm_dma_source_select#

List of PWM capture DMA enable source select.

Values:

enumerator kPWM_DMARequestDisable#: Read DMA requests disabled

enumerator kPWM_DMAWatermarksEnable#: Exceeding a FIFO watermark sets the DMA read request

enumerator kPWM_DMALocalSync#: A local sync (VAL1 matches counter) sets the read DMA request

enumerator kPWM_DMALocalReload#: A local reload (STS[RF] being set) sets the read DMA request

enum _pwm_watermark_control#

PWM FIFO Watermark AND Control.

Values:

enumerator kPWM_FIFOWatermarksOR#: Selected FIFO watermarks are OR’ed together

enumerator kPWM_FIFOWatermarksAND#: Selected FIFO watermarks are AND’ed together

enum _pwm_mode#

PWM operation mode.

Values:

enumerator kPWM_SignedCenterAligned#: Signed center-aligned

enumerator kPWM_CenterAligned#: Unsigned cente-aligned

enumerator kPWM_SignedEdgeAligned#: Signed edge-aligned

enumerator kPWM_EdgeAligned#: Unsigned edge-aligned

enum _pwm_level_select#

PWM output pulse mode, high-true or low-true.

Values:

enumerator kPWM_HighTrue#: High level represents “on” or “active” state

enumerator kPWM_LowTrue#: Low level represents “on” or “active” state

enum _pwm_fault_state#

PWM output fault status.

Values:

enumerator kPWM_PwmFaultState0#: Output is forced to logic 0 state prior to consideration of output polarity control.

enumerator kPWM_PwmFaultState1#: Output is forced to logic 1 state prior to consideration of output polarity control.

enumerator kPWM_PwmFaultState2#: Output is tristated.

enumerator kPWM_PwmFaultState3#: Output is tristated.

enum _pwm_reload_source_select#

PWM reload source select.

Values:

enumerator kPWM_LocalReload#: The local reload signal is used to reload registers

enumerator kPWM_MasterReload#: The master reload signal (from submodule 0) is used to reload

enum _pwm_fault_clear#

PWM fault clearing options.

Values:

enumerator kPWM_Automatic#: Automatic fault clearing

enumerator kPWM_ManualNormal#: Manual fault clearing with no fault safety mode

enumerator kPWM_ManualSafety#: Manual fault clearing with fault safety mode

enum _pwm_module_control#

Options for submodule master control operation.

Values:

enumerator kPWM_Control_Module_0#: Control submodule 0’s start/stop,buffer reload operation

enumerator kPWM_Control_Module_1#: Control submodule 1’s start/stop,buffer reload operation

enumerator kPWM_Control_Module_2#: Control submodule 2’s start/stop,buffer reload operation

enumerator kPWM_Control_Module_3#: Control submodule 3’s start/stop,buffer reload operation

typedef enum _pwm_submodule pwm_submodule_t#: List of PWM submodules.

typedef enum _pwm_channels pwm_channels_t#: List of PWM channels in each module.

typedef enum _pwm_value_register pwm_value_register_t#: List of PWM value registers.

typedef enum _pwm_clock_source pwm_clock_source_t#: PWM clock source selection.

typedef enum _pwm_clock_prescale pwm_clock_prescale_t#: PWM prescaler factor selection for clock source.

typedef enum _pwm_force_output_trigger pwm_force_output_trigger_t#: Options that can trigger a PWM FORCE_OUT.

typedef enum _pwm_output_state pwm_output_state_t#: PWM channel output status.

typedef enum _pwm_init_source pwm_init_source_t#: PWM counter initialization options.

typedef enum _pwm_load_frequency pwm_load_frequency_t#: PWM load frequency selection.

typedef enum _pwm_fault_input pwm_fault_input_t#: List of PWM fault selections.

typedef enum _pwm_fault_disable pwm_fault_disable_t#: List of PWM fault disable mapping selections.

typedef enum _pwm_fault_channels pwm_fault_channels_t#: List of PWM fault channels.

typedef enum _pwm_input_capture_edge pwm_input_capture_edge_t#: PWM capture edge select.

typedef enum _pwm_force_signal pwm_force_signal_t#: PWM output options when a FORCE_OUT signal is asserted.

typedef enum _pwm_chnl_pair_operation pwm_chnl_pair_operation_t#: Options available for the PWM A & B pair operation.

typedef enum _pwm_register_reload pwm_register_reload_t#: Options available on how to load the buffered-registers with new values.

typedef enum _pwm_fault_recovery_mode pwm_fault_recovery_mode_t#: Options available on how to re-enable the PWM output when recovering from a fault.

typedef enum _pwm_interrupt_enable pwm_interrupt_enable_t#: List of PWM interrupt options.

typedef enum _pwm_status_flags pwm_status_flags_t#: List of PWM status flags.

typedef enum _pwm_dma_enable pwm_dma_enable_t#: List of PWM DMA options.

typedef enum _pwm_dma_source_select pwm_dma_source_select_t#: List of PWM capture DMA enable source select.

typedef enum _pwm_watermark_control pwm_watermark_control_t#: PWM FIFO Watermark AND Control.

typedef enum _pwm_mode pwm_mode_t#: PWM operation mode.

typedef enum _pwm_level_select pwm_level_select_t#: PWM output pulse mode, high-true or low-true.

typedef enum _pwm_fault_state pwm_fault_state_t#: PWM output fault status.

typedef enum _pwm_reload_source_select pwm_reload_source_select_t#: PWM reload source select.

typedef enum _pwm_fault_clear pwm_fault_clear_t#: PWM fault clearing options.

typedef enum _pwm_module_control pwm_module_control_t#: Options for submodule master control operation.

typedef struct _pwm_signal_param pwm_signal_param_t#: Structure for the user to define the PWM signal characteristics.

typedef struct _pwm_config pwm_config_t#

PWM config structure.

This structure holds the configuration settings for the PWM peripheral. To initialize this structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

typedef struct _pwm_fault_input_filter_param pwm_fault_input_filter_param_t#: Structure for the user to configure the fault input filter.

typedef struct _pwm_fault_param pwm_fault_param_t#: Structure is used to hold the parameters to configure a PWM fault.

typedef struct _pwm_input_capture_param pwm_input_capture_param_t#: Structure is used to hold parameters to configure the capture capability of a signal pin.

void PWM_SetupInputCapture(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, const pwm_input_capture_param_t *inputCaptureParams)#

Sets up the PWM input capture.

Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function sets up the capture parameters for each pin and enables the pin for input capture operation.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel in the submodule to setup
inputCaptureParams – Parameters passed in to set up the input pin

status_t PWM_GetInputCaptureValue(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, uint8_t captureIndex, uint16_t *captureValue)#

Read the capture value.

This function reads the capture value stored in channel’s capture value register. It should be called when a valid edge is detected on the input capture pin(related capture flag is set). The capture circuit has two input capture registers per channel for first edge and second edge capture.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to read from (PWM A, PWM B, or PWM X)
captureIndex – Capture register to read (0 for first edge capture, 1 for second edge capture)

Returns:

Returns kStatus_InvalidArgument if pwmChannel does not support capture feature; kStatus_Success otherwise

void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams)#

Sets up the PWM fault channel 0 input filter.

Parameters:

base – PWM peripheral base address
faultInputFilterParams – Parameters passed in to set up the fault input filter.

void PWM_SetupFaultInputFilterExt(PWM_Type *base, pwm_fault_channels_t faultChannel, const pwm_fault_input_filter_param_t *faultInputFilterParams)#

Sets up the PWM fault input filter.

Parameters:

base – PWM peripheral base address
faultChannel – PWM fault channel to configure.
faultInputFilterParams – Parameters passed in to set up the fault input filter.

void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)#

Sets up the PWM fault channel 0 protection.

Parameters:

base – PWM peripheral base address
faultNum – PWM fault to configure.
faultParams – Pointer to the PWM fault config structure

void PWM_SetupFaultsExt(PWM_Type *base, pwm_fault_channels_t faultChannel, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams)#

Sets up the PWM fault protection.

Parameters:

base – PWM peripheral base address
faultChannel – PWM fault channel to configure.
faultNum – PWM fault to configure.
faultParams – Pointer to the PWM fault config structure

void PWM_FaultDefaultConfig(pwm_fault_param_t *config)#

Fill in the PWM fault config struct with the default settings.

The default values are:

config->faultClearingMode = kPWM_Automatic;
config->faultLevel = false;
config->enableCombinationalPath = true;
config->recoverMode = kPWM_NoRecovery;

Parameters:

config – Pointer to user’s PWM fault config structure.

void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode)#

Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted.

The user specifies which channel to configure by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel to configure
mode – Signal to output when a FORCE_OUT is triggered

static inline void PWM_EnableLocalForce(PWM_Type *base, pwm_submodule_t subModule)#

Enables local software force initialization on a PWM submodule.

This function performs a software-controlled initialization, causes a FORCE_OUT event which latches all double-buffered fields (DTSRCSEL, MCTRL[IPOL], SWCOUT) into their active registers and, if MCTRL[LDOK] is set, also triggers a register reload.

Call this function after updating the desired buffered registers (e.g. after PWM_SetupForceSignal()) to apply the new values synchronously.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to enable local force on

void PWM_UpdateCurrentPolarity(PWM_Type *base, pwm_submodule_t subModule, pwm_chnl_pair_operation_t polarity)#

Updates the current polarity (MCTRL[IPOL]) for a PWM submodule.

MCTRL[IPOL] is a double-buffered field. This function only writes the shadow register; the value does NOT take effect until a FORCE_OUT event occurs. Call PWM_EnableLocalForce() after this function to apply all pending changes atomically in one FORCE_OUT event.

Only meaningful when the submodule operates in complementary mode (CTRL2[INDEP] = 0).

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
polarity – kPWM_ComplementaryPwmA: PWM23 (VAL2/VAL3) drives the complementary pair kPWM_ComplementaryPwmB: PWM45 (VAL4/VAL5) drives the complementary pair

static inline void PWM_SetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, uint16_t value)#

Set the PWM VALx registers.

This function allows the user to write value into VAL registers directly. And it will destroying the PWM clock period set by the PWM_SetupPwm()/PWM_SetupPwmPhaseShift() functions. Due to VALx registers are bufferd, the new value will not active uless call PWM_SetPwmLdok() and the reload point is reached.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegister – VALx register that will be writen new value
value – Value that will been write into VALx register

static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister)#

Get the PWM VALx registers.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegister – VALx register that will be read value

Returns:

The VALx register value

static inline void PWM_OutputTriggerEnable(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister, bool activate)#

Enables or disables the PWM output trigger.

This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated when the counter matches VAL 1, VAL 3, or VAL 5 register.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegister – Value register that will activate the trigger
activate – true: Enable the trigger; false: Disable the trigger

static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)#

Enables the PWM output trigger.

This function allows the user to enable one or more (VAL0-5) PWM trigger.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegisterMask – Value register mask that will activate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask

static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask)#

Disables the PWM output trigger.

This function allows the user to disables one or more (VAL0-5) PWM trigger.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
valueRegisterMask – Value register mask that will Deactivate one or more (VAL0-5) trigger enumeration _pwm_value_register_mask

static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value)#

Sets the software control output for a pin to high or low.

The user specifies which channel to modify by supplying the submodule number and whether to modify PWM A or PWM B within that submodule.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel to configure
value – true: Supply a logic 1, false: Supply a logic 0.

static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value)#

Sets or clears the PWM LDOK bit on a single or multiple submodules.

Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the values are loaded at the next PWM reload point. This function can issue the load command to multiple submodules at the same time.

Parameters:

base – PWM peripheral base address
subModulesToUpdate – PWM submodules to update with buffered values. This is a logical OR of members of the enumeration pwm_module_control_t
value – true: Set LDOK bit for the submodule list; false: Clear LDOK bit

static inline void PWM_SetPwmFaultState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_state_t faultState)#

Set PWM output fault status.

These bits determine the fault state for the PWM_A output in fault conditions and STOP mode. It may also define the output state in WAIT and DEBUG modes depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. This function can update PWM output fault status.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – Channel to configure
faultState – PWM output fault status

static inline void PWM_SetupFaultDisableMap(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_fault_channels_t pwm_fault_channels, uint16_t value)#

Set PWM fault disable mapping.

Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned off if there is a logic 1 on an FAULTx input and a 1 in the corresponding bit of this field. A reset sets all bits in this field.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
pwm_fault_channels – PWM fault channel to configure
value – Fault disable mapping mask value enumeration pwm_fault_disable_t

static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)#

Set PWM output enable.

This feature allows the user to enable the PWM Output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.

Parameters:

base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure

static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule)#

Set PWM output disable.

This feature allows the user to disable the PWM output. Recommend to invoke this API after PWM and fault configuration. But invoke this API before configure MCTRL register is okay, such as set LDOK or start timer.

Parameters:

base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure

uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel)#

Get the dutycycle value.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure

Returns:

Current channel dutycycle value.

status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus)#

Set PWM output in idle status (high or low).

Note

This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported.

Parameters:

base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure
idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.

Returns:

kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success

void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler)#

Set the pwm submodule prescaler.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
prescaler – Set prescaler value

void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero)#

This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0.

Parameters:

base – PWM peripheral base address
pwmChannel – PWM channel to configure
subModule – PWM submodule to configure
forcetozero – True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal function.

void PWM_SetChannelOutput(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_output_state_t outputstate)#

This function set the output state of the PWM pin as requested for the current cycle.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
outputstate – Set pwm output state, see pwm_output_state_t.

status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles)#

This function set the phase delay from the master sync signal of submodule 0.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
delayCycles – Number of cycles delayed from submodule 0.

Returns:

kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; kStatus_Success if set phase delay success

static inline void PWM_SetFilterSampleCount(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSampleCount)#

This function set the number of consecutive samples that must agree prior to the input filter.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
filterSampleCount – Number of consecutive samples.

static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint8_t filterSamplePeriod)#

This function set the sampling period of the fault pin input filter.

Parameters:

base – PWM peripheral base address
subModule – PWM submodule to configure
pwmChannel – PWM channel to configure
filterSamplePeriod – Sampling period of input filter.

PWM_SUBMODULE_SWCONTROL_WIDTH#: Number of bits per submodule for software output control

PWM_SUBMODULE_CHANNEL#: Submodule channels include PWMA, PWMB, PWMX.

struct _pwm_signal_param#

#include <fsl_pwm.h>

Structure for the user to define the PWM signal characteristics.

Public Members

pwm_channels_t pwmChannel#: PWM channel being configured; PWM A or PWM B

uint8_t dutyCyclePercent#: PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=always active signal (100% duty cycle)

pwm_level_select_t level#: PWM output active level select

uint16_t deadtimeValue#: The deadtime value; only used if channel pair is operating in complementary mode

pwm_fault_state_t faultState#: PWM output fault status

bool pwmchannelenable#: Enable PWM output

struct _pwm_config#

#include <fsl_pwm.h>

PWM config structure.

The config struct can be made const so it resides in flash

Public Members

bool enableDebugMode#: true: PWM continues to run in debug mode; false: PWM is paused in debug mode

pwm_init_source_t initializationControl#: Option to initialize the counter

pwm_clock_source_t clockSource#: Clock source for the counter

pwm_clock_prescale_t prescale#: Pre-scaler to divide down the clock

pwm_chnl_pair_operation_t pairOperation#: Channel pair in indepedent or complementary mode

pwm_register_reload_t reloadLogic#: PWM Reload logic setup

pwm_reload_source_select_t reloadSelect#: Reload source select

pwm_load_frequency_t reloadFrequency#: Specifies when to reload, used when user’s choice is not immediate reload

pwm_force_output_trigger_t forceTrigger#: Specify which signal will trigger a FORCE_OUT

struct _pwm_fault_input_filter_param#

#include <fsl_pwm.h>

Structure for the user to configure the fault input filter.

Public Members

uint8_t faultFilterCount#: Fault filter count

uint8_t faultFilterPeriod#: Fault filter period;value of 0 will bypass the filter

bool faultGlitchStretch#: Fault Glitch Stretch Enable: A logic 1 means that input fault signals will be stretched to at least 2 IPBus clock cycles

struct _pwm_fault_param#

#include <fsl_pwm.h>

Structure is used to hold the parameters to configure a PWM fault.

Public Members

pwm_fault_clear_t faultClearingMode#: Fault clearing mode to use

bool faultLevel#: true: Logic 1 indicates fault; false: Logic 0 indicates fault

bool enableCombinationalPath#: true: Combinational Path from fault input is enabled; false: No combination path is available

pwm_fault_recovery_mode_t recoverMode#: Specify when to re-enable the PWM output

struct _pwm_input_capture_param#

#include <fsl_pwm.h>

Structure is used to hold parameters to configure the capture capability of a signal pin.

Public Members

bool captureInputSel#: true: Use the edge counter signal as source false: Use the raw input signal from the pin as source

uint8_t edgeCompareValue#: Compare value, used only if edge counter is used as source

pwm_input_capture_edge_t edge0#: Specify which edge causes a capture for input circuitry 0

pwm_input_capture_edge_t edge1#: Specify which edge causes a capture for input circuitry 1

bool enableOneShotCapture#: true: Use one-shot capture mode; false: Use free-running capture mode

uint8_t fifoWatermark#: Watermark level for capture FIFO. The capture flags in the status register will set if the word count in the FIFO is greater than this watermark level

PWT: Pulse Width Timer#

void PWT_Init(PWT_Type *base, const pwt_config_t *config)#

Ungates the PWT clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the PWT driver.

Parameters:

base – PWT peripheral base address
config – Pointer to the user configuration structure.

void PWT_Deinit(PWT_Type *base)#

Gates the PWT clock.

Parameters:

base – PWT peripheral base address

void PWT_GetDefaultConfig(pwt_config_t *config)#

Fills in the PWT configuration structure with the default settings.

The default values are:

config->clockSource = kPWT_BusClock;
config->prescale = kPWT_Prescale_Divide_1;
config->inputSelect = kPWT_InputPort_0;
config->enableFirstCounterLoad = false;

Parameters:

config – Pointer to the user configuration structure.

static inline void PWT_EnableInterrupts(PWT_Type *base, uint32_t mask)#

Enables the selected PWT interrupts.

Parameters:

base – PWT peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwt_interrupt_enable_t

static inline void PWT_DisableInterrupts(PWT_Type *base, uint32_t mask)#

Disables the selected PWT interrupts.

Parameters:

base – PWT peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration pwt_interrupt_enable_t

static inline uint32_t PWT_GetEnabledInterrupts(PWT_Type *base)#

Gets the enabled PWT interrupts.

Parameters:

base – PWT peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration pwt_interrupt_enable_t

static inline uint32_t PWT_GetStatusFlags(PWT_Type *base)#

Gets the PWT status flags.

Parameters:

base – PWT peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration pwt_status_flags_t

static inline void PWT_ClearStatusFlags(PWT_Type *base, uint32_t mask)#

Clears the PWT status flags.

Parameters:

base – PWT peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration pwt_status_flags_t

static inline void PWT_StartTimer(PWT_Type *base)#

Starts the PWT counter.

Parameters:

base – PWT peripheral base address

static inline void PWT_StopTimer(PWT_Type *base)#

Stops the PWT counter.

Parameters:

base – PWT peripheral base address

enum _pwt_clock_source#

PWT clock source selection.

Values:

enumerator kPWT_BusClock#: The Bus clock is used as the clock source of PWT counter

enumerator kPWT_AlternativeClock#: Alternative clock is used as the clock source of PWT counter

enum _pwt_clock_prescale#

PWT prescaler factor selection for clock source.

Values:

enumerator kPWT_Prescale_Divide_1#: PWT clock divided by 1

enumerator kPWT_Prescale_Divide_2#: PWT clock divided by 2

enumerator kPWT_Prescale_Divide_4#: PWT clock divided by 4

enumerator kPWT_Prescale_Divide_8#: PWT clock divided by 8

enumerator kPWT_Prescale_Divide_16#: PWT clock divided by 16

enumerator kPWT_Prescale_Divide_32#: PWT clock divided by 32

enumerator kPWT_Prescale_Divide_64#: PWT clock divided by 64

enumerator kPWT_Prescale_Divide_128#: PWT clock divided by 128

enum _pwt_input_select#

PWT input port selection.

Values:

enumerator kPWT_InputPort_0#: PWT input comes from PWTIN[0]

enumerator kPWT_InputPort_1#: PWT input comes from PWTIN[1]

enumerator kPWT_InputPort_2#: PWT input comes from PWTIN[2]

enumerator kPWT_InputPort_3#: PWT input comes from PWTIN[3]

enum _pwt_interrupt_enable#

List of PWT interrupts.

Values:

enumerator kPWT_PulseWidthReadyInterruptEnable#: Pulse width data ready interrupt

enumerator kPWT_CounterOverflowInterruptEnable#: Counter overflow interrupt

enum _pwt_status_flags#

List of PWT flags.

Values:

enumerator kPWT_CounterOverflowFlag#: Counter overflow flag

enumerator kPWT_PulseWidthValidFlag#: Pulse width valid flag

enumerator kPWT_InputToggleFlag#: PWTIN toggle flag (write-1-to-clear)

typedef enum _pwt_clock_source pwt_clock_source_t#: PWT clock source selection.

typedef enum _pwt_clock_prescale pwt_clock_prescale_t#: PWT prescaler factor selection for clock source.

typedef enum _pwt_input_select pwt_input_select_t#: PWT input port selection.

typedef struct _pwt_config pwt_config_t#

PWT configuration structure.

This structure holds the configuration settings for the PWT peripheral. To initialize this structure to reasonable defaults, call the PWT_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

static inline uint16_t PWT_GetCurrentTimerCount(PWT_Type *base)#

Reads the current counter value.

This function returns the timer counting value

Parameters:

base – PWT peripheral base address

Returns:

Current 16-bit timer counter value

static inline uint16_t PWT_ReadPositivePulseWidth(PWT_Type *base)#

Reads the positive pulse width.

This function reads the low and high registers and returns the 16-bit positive pulse width

Parameters:

base – PWT peripheral base address.

Returns:

The 16-bit positive pulse width.

static inline uint16_t PWT_ReadNegativePulseWidth(PWT_Type *base)#

Reads the negative pulse width.

This function reads the low and high registers and returns the 16-bit negative pulse width

Parameters:

base – PWT peripheral base address.

Returns:

The 16-bit negative pulse width.

static inline void PWT_Reset(PWT_Type *base)#

Performs a software reset on the PWT module.

Parameters:

base – PWT peripheral base address

static inline uint8_t PWT_GetInputLevel(PWT_Type *base)#

Gets the current PWTIN input level.

This function returns the level of the selected PWTIN input at the point when counter overflow occurs.

Parameters:

base – PWT peripheral base address.

Returns:

The PWTIN input level: 0 for low, 1 for high.

FSL_PWT_DRIVER_VERSION#: Version 2.0.3

struct _pwt_config#

#include <fsl_pwt.h>

PWT configuration structure.

The configuration structure can be made constant so as to reside in flash.

Public Members

pwt_clock_source_t clockSource#: Clock source for the counter

pwt_clock_prescale_t prescale#: Pre-scaler to divide down the clock

pwt_input_select_t inputSelect#: PWT Pulse input port selection

bool enableFirstCounterLoad#: true: Load the first counter value to registers; false: Do not load first counter value

QTMR: Quad Timer Driver#

void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)#

Ungates the Quad Timer clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application using the Quad Timer driver.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
config – Pointer to user’s Quad Timer config structure

void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)#

Stops the counter and gates the Quad Timer clock.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

void QTMR_GetDefaultConfig(qtmr_config_t *config)#

Fill in the Quad Timer config struct with the default settings.

The default values are:

config->debugMode = kQTMR_RunNormalInDebug;
config->enableExternalForce = false;
config->enableMasterMode = false;
config->faultFilterCount = 0;
config->faultFilterPeriod = 0;
config->primarySource = kQTMR_ClockDivide_2;
config->secondarySource = kQTMR_Counter0InputPin;

Parameters:

config – Pointer to user’s Quad Timer config structure.

void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)#

Enables the selected Quad Timer interrupts.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t

void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)#

Disables the selected Quad Timer interrupts.

Parameters:

base – Quad Timer peripheral base addres
channel – Quad Timer channel number
mask – The interrupts to enable. This is a logical OR of members of the enumeration qtmr_interrupt_enable_t

uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)#

Gets the enabled Quad Timer interrupts.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration qtmr_interrupt_enable_t

uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)#

Gets the Quad Timer status flags.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

Returns:

The status flags. This is the logical OR of members of the enumeration qtmr_status_flags_t

void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)#

Clears the Quad Timer status flags.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The status flags to clear. This is a logical OR of members of the enumeration qtmr_status_flags_t

void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks)#

Sets the timer period in ticks.

Timers counts from initial value till it equals the count value set here. The counter will then reinitialize to the value specified in the Load register.

Note

This function will write the time period in ticks to COMP1 or COMP2 register depending on the count direction
User can call the utility macros provided in fsl_common.h to convert to ticks
This function supports cases, providing only primary source clock without secondary source clock.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
ticks – Timer period in units of ticks

void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t ticks)#

Set compare value.

This function sets the value used for comparison with the counter value.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
ticks – Timer period in units of ticks.

static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t value)#

Set load value.

This function sets the value used to initialize the counter after a counter comparison.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
value – Load register initialization value.

static inline uint32_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel)#

Reads the current timer counting value.

This function returns the real-time timer counting value, in a range from 0 to a timer period.

Note

User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

Returns:

Current counter value in ticks

static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource)#

Starts the Quad Timer counter.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
clockSource – Quad Timer clock source

static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel)#

Stops the Quad Timer counter.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)#

Enable the Quad Timer DMA.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t

void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)#

Disable the Quad Timer DMA.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
mask – The DMA to enable. This is a logical OR of members of the enumeration qtmr_dma_enable_t

FSL_QTMR_DRIVER_VERSION#: Version

enum _qtmr_primary_count_source#

Quad Timer primary clock source selection.

Values:

enumerator kQTMR_ClockCounter0InputPin#: Use counter 0 input pin

enumerator kQTMR_ClockCounter1InputPin#: Use counter 1 input pin

enumerator kQTMR_ClockCounter2InputPin#: Use counter 2 input pin

enumerator kQTMR_ClockCounter3InputPin#: Use counter 3 input pin

enumerator kQTMR_ClockCounter0Output#: Use counter 0 output

enumerator kQTMR_ClockCounter1Output#: Use counter 1 output

enumerator kQTMR_ClockCounter2Output#: Use counter 2 output

enumerator kQTMR_ClockCounter3Output#: Use counter 3 output

enumerator kQTMR_ClockDivide_1#: IP bus clock divide by 1 prescaler

enumerator kQTMR_ClockDivide_2#: IP bus clock divide by 2 prescaler

enumerator kQTMR_ClockDivide_4#: IP bus clock divide by 4 prescaler

enumerator kQTMR_ClockDivide_8#: IP bus clock divide by 8 prescaler

enumerator kQTMR_ClockDivide_16#: IP bus clock divide by 16 prescaler

enumerator kQTMR_ClockDivide_32#: IP bus clock divide by 32 prescaler

enumerator kQTMR_ClockDivide_64#: IP bus clock divide by 64 prescaler

enumerator kQTMR_ClockDivide_128#: IP bus clock divide by 128 prescaler

enum _qtmr_input_source#

Quad Timer input sources selection.

Values:

enumerator kQTMR_Counter0InputPin#: Use counter 0 input pin

enumerator kQTMR_Counter1InputPin#: Use counter 1 input pin

enumerator kQTMR_Counter2InputPin#: Use counter 2 input pin

enumerator kQTMR_Counter3InputPin#: Use counter 3 input pin

enum _qtmr_counting_mode#

Quad Timer counting mode selection.

Values:

enumerator kQTMR_NoOperation#: No operation

enumerator kQTMR_PriSrcRiseEdge#: Count rising edges of primary source

enumerator kQTMR_PriSrcRiseAndFallEdge#: Count rising and falling edges of primary source

enumerator kQTMR_PriSrcRiseEdgeSecInpHigh#: Count rise edges of pri SRC while sec inp high active

enumerator kQTMR_QuadCountMode#: Quadrature count mode, uses pri and sec sources

enumerator kQTMR_PriSrcRiseEdgeSecDir#: Count rising edges of pri SRC; sec SRC specifies dir

enumerator kQTMR_SecSrcTrigPriCnt#: Edge of sec SRC trigger primary count until compare

enumerator kQTMR_CascadeCount#: Cascaded count mode (up/down)

enum _qtmr_pwm_out_state#

Quad Timer PWM output state.

Values:

enumerator kQTMR_PwmLow#: The output state of PWM channel is low

enumerator kQTMR_PwmHigh#: The output state of PWM channel is low

enum _qtmr_output_mode#

Quad Timer output mode selection.

Values:

enumerator kQTMR_AssertWhenCountActive#: Assert OFLAG while counter is active

enumerator kQTMR_ClearOnCompare#: Clear OFLAG on successful compare

enumerator kQTMR_SetOnCompare#: Set OFLAG on successful compare

enumerator kQTMR_ToggleOnCompare#: Toggle OFLAG on successful compare

enumerator kQTMR_ToggleOnAltCompareReg#: Toggle OFLAG using alternating compare registers

enumerator kQTMR_SetOnCompareClearOnSecSrcInp#: Set OFLAG on compare, clear on sec SRC input edge

enumerator kQTMR_SetOnCompareClearOnCountRoll#: Set OFLAG on compare, clear on counter rollover

enumerator kQTMR_EnableGateClock#: Enable gated clock output while count is active

enum _qtmr_input_capture_edge#

Quad Timer input capture edge mode, rising edge, or falling edge.

Values:

enumerator kQTMR_NoCapture#: Capture is disabled

enumerator kQTMR_RisingEdge#: Capture on rising edge (IPS=0) or falling edge (IPS=1)

enumerator kQTMR_FallingEdge#: Capture on falling edge (IPS=0) or rising edge (IPS=1)

enumerator kQTMR_RisingAndFallingEdge#: Capture on both edges

enum _qtmr_preload_control#

Quad Timer input capture edge mode, rising edge, or falling edge.

Values:

enumerator kQTMR_NoPreload#: Never preload

enumerator kQTMR_LoadOnComp1#: Load upon successful compare with value in COMP1

enumerator kQTMR_LoadOnComp2#: Load upon successful compare with value in COMP2

enum _qtmr_debug_action#

List of Quad Timer run options when in Debug mode.

Values:

enumerator kQTMR_RunNormalInDebug#: Continue with normal operation

enumerator kQTMR_HaltCounter#: Halt counter

enumerator kQTMR_ForceOutToZero#: Force output to logic 0

enumerator kQTMR_HaltCountForceOutZero#: Halt counter and force output to logic 0

enum _qtmr_interrupt_enable#

List of Quad Timer interrupts.

Values:

enumerator kQTMR_CompareInterruptEnable#: Compare interrupt.

enumerator kQTMR_Compare1InterruptEnable#: Compare 1 interrupt.

enumerator kQTMR_Compare2InterruptEnable#: Compare 2 interrupt.

enumerator kQTMR_OverflowInterruptEnable#: Timer overflow interrupt.

enumerator kQTMR_EdgeInterruptEnable#: Input edge interrupt.

enum _qtmr_status_flags#

List of Quad Timer flags.

Values:

enumerator kQTMR_CompareFlag#: Compare flag

enumerator kQTMR_Compare1Flag#: Compare 1 flag

enumerator kQTMR_Compare2Flag#: Compare 2 flag

enumerator kQTMR_OverflowFlag#: Timer overflow flag

enumerator kQTMR_EdgeFlag#: Input edge flag

enum _qtmr_channel_selection#

List of channel selection.

Values:

enumerator kQTMR_Channel_0#: TMR Channel 0

enumerator kQTMR_Channel_1#: TMR Channel 1

enumerator kQTMR_Channel_2#: TMR Channel 2

enumerator kQTMR_Channel_3#: TMR Channel 3

enum _qtmr_dma_enable#

List of Quad Timer DMA enable.

Values:

enumerator kQTMR_InputEdgeFlagDmaEnable#: Input Edge Flag DMA Enable.

enumerator kQTMR_ComparatorPreload1DmaEnable#: Comparator Preload Register 1 DMA Enable.

enumerator kQTMR_ComparatorPreload2DmaEnable#: Comparator Preload Register 2 DMA Enable.

typedef uint32_t qtmrRegType#

typedef enum _qtmr_primary_count_source qtmr_primary_count_source_t#: Quad Timer primary clock source selection.

typedef enum _qtmr_input_source qtmr_input_source_t#: Quad Timer input sources selection.

typedef enum _qtmr_counting_mode qtmr_counting_mode_t#: Quad Timer counting mode selection.

typedef enum _qtmr_pwm_out_state qtmr_pwm_out_state_t#: Quad Timer PWM output state.

typedef enum _qtmr_output_mode qtmr_output_mode_t#: Quad Timer output mode selection.

typedef enum _qtmr_input_capture_edge qtmr_input_capture_edge_t#: Quad Timer input capture edge mode, rising edge, or falling edge.

typedef enum _qtmr_preload_control qtmr_preload_control_t#: Quad Timer input capture edge mode, rising edge, or falling edge.

typedef enum _qtmr_debug_action qtmr_debug_action_t#: List of Quad Timer run options when in Debug mode.

typedef enum _qtmr_interrupt_enable qtmr_interrupt_enable_t#: List of Quad Timer interrupts.

typedef enum _qtmr_status_flags qtmr_status_flags_t#: List of Quad Timer flags.

typedef enum _qtmr_channel_selection qtmr_channel_selection_t#: List of channel selection.

typedef enum _qtmr_dma_enable qtmr_dma_enable_t#: List of Quad Timer DMA enable.

typedef struct _qtmr_config qtmr_config_t#

Quad Timer config structure.

This structure holds the configuration settings for the Quad Timer peripheral. To initialize this structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a pointer to your config structure instance.

The config struct can be made const so it resides in flash

status_t QTMR_SetupPwm(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)#

Sets up Quad timer module for PWM signal output.

The function initializes the timer module according to the parameters passed in by the user. The function also sets up the value compare registers to match the PWM signal requirements.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
pwmFreqHz – PWM signal frequency in Hz
dutyCyclePercent – PWM pulse width, value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)
outputPolarity – true: invert polarity of the output signal, false: no inversion
srcClock_Hz – Main counter clock in Hz.

Returns:

Returns an error if there was error setting up the signal.

void QTMR_SetupInputCapture(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_input_source_t capturePin, bool inputPolarity, bool reloadOnCapture, qtmr_input_capture_edge_t captureMode)#

Allows the user to count the source clock cycles until a capture event arrives.

The count is stored in the capture register.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
capturePin – Pin through which we receive the input signal to trigger the capture
inputPolarity – true: invert polarity of the input signal, false: no inversion
reloadOnCapture – true: reload the counter when an input capture occurs, false: no reload
captureMode – Specifies which edge of the input signal triggers a capture

void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus)#

Set PWM output in idle status (high or low).

Note

When the PWM is set again, the counting needs to be restarted.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
idleStatus – True: PWM output is high in idle status; false: PWM output is low in idle status.

static inline qtmr_pwm_out_state_t QTMR_GetPwmOutputStatus(TMR_Type *base, qtmr_channel_selection_t channel)#

Get the channel output status.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

Returns:

Current channel output status.

uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel)#

Get the PWM channel dutycycle value.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number

Returns:

Current channel dutycycle value.

void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_primary_count_source_t prescaler)#

This function set the value of the prescaler on QTimer channels.

Parameters:

base – Quad Timer peripheral base address
channel – Quad Timer channel number
prescaler – Set prescaler value

TMR_CSCTRL_OFLAG_MASK#

TMR_CSCTRL_OFLAG_SHIFT#

struct _qtmr_config#

#include <fsl_qtmr.h>

Quad Timer config structure.

The config struct can be made const so it resides in flash

Public Members

qtmr_primary_count_source_t primarySource#: Specify the primary count source

qtmr_input_source_t secondarySource#: Specify the secondary count source

bool enableMasterMode#: true: Broadcast compare function output to other counters; false no broadcast

bool enableExternalForce#: true: Compare from another counter force state of OFLAG signal false: OFLAG controlled by local counter

uint8_t faultFilterCount#: Fault filter count

uint8_t faultFilterPeriod#: Fault filter period;value of 0 will bypass the filter

qtmr_debug_action_t debugMode#: Operation in Debug mode

TRDC: Trusted Resource Domain Controller#

void TRDC_Init(TRDC_Type *base)#

Initializes the TRDC module.

This function enables the TRDC clock.

Parameters:

base – TRDC peripheral base address.

void TRDC_Deinit(TRDC_Type *base)#

De-initializes the TRDC module.

This function disables the TRDC clock.

Parameters:

base – TRDC peripheral base address.

static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)#

Gets the domain ID of the current bus master.

Parameters:

base – TRDC peripheral base address.

Returns:

Domain ID of current bus master.

void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config)#

Gets the TRDC hardware configuration.

This function gets the TRDC hardware configurations, including number of bus masters, number of domains, number of MRCs and number of PACs.

Parameters:

base – TRDC peripheral base address.
config – Pointer to the structure to get the configuration.

static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)#

Sets the TRDC DAC(Domain Assignment Controllers) global valid.

Once enabled, it will remain enabled until next reset.

Parameters:

base – TRDC peripheral base address.

static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum)#

Locks the bus master domain assignment register.

This function locks the master domain assignment. After it is locked, the register can’t be changed until next reset.

Parameters:

base – TRDC peripheral base address.
master – Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.
regNum – Which register to configure, processor master can have more than one register for the MDAC configuration.
assignIndex – Which assignment register to lock.

static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid)#

Sets the master domain assignment as valid or invalid.

This function sets the master domain assignment as valid or invalid.

Parameters:

base – TRDC peripheral base address.
master – Which master to configure.
regNum – Which register to configure, processor master can have more than one register for the MDAC configuration.
assignIndex – Index for the domain assignment register.
valid – True to set valid, false to set invalid.

void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment)#

Gets the default master domain assignment for the processor bus master.

This function gets the default master domain assignment for the processor bus master. It should only be used for the processor bus masters, such as CORE0. This function sets the assignment as follows:

assignment->domainId           = 0U;
assignment->domainIdSelect     = kTRDC_DidMda;
assignment->lock               = 0U;

Parameters:

domainAssignment – Pointer to the assignment structure.

void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment)#

Gets the default master domain assignment for non-processor bus master.

This function gets the default master domain assignment for non-processor bus master. It should only be used for the non-processor bus masters, such as DMA. This function sets the assignment as follows:

assignment->domainId            = 0U;
assignment->privilegeAttr       = kTRDC_ForceUser;
assignment->secureAttr       = kTRDC_ForceSecure;
assignment->bypassDomainId      = 0U;
assignment->lock                = 0U;

Parameters:

domainAssignment – Pointer to the assignment structure.

void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum, const trdc_processor_domain_assignment_t *domainAssignment)#

Sets the processor bus master domain assignment.

This function sets the processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to set.

Example: Set domain assignment for core 0.

trdc_processor_domain_assignment_t processorAssignment;

TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);

processorAssignment.domainId = 0;
processorAssignment.xxx      = xxx;
TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);

Parameters:

base – TRDC peripheral base address.
master – Which master to configure, refer to trdc_master_t in processor header file.
regNum – Which register to configure, processor master can have more than one register for the MDAC configuration.
domainAssignment – Pointer to the assignment structure.

void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, uint8_t master, const trdc_non_processor_domain_assignment_t *domainAssignment)#

Sets the non-processor bus master domain assignment.

This function sets the non-processor master domain assignment as valid. One bus master might have multiple domain assignment registers. The parameter assignIndex specifies which assignment register to set.

Example: Set domain assignment for DMA0.

trdc_non_processor_domain_assignment_t nonProcessorAssignment;

TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
nonProcessorAssignment.domainId = 1;
nonProcessorAssignment.xxx      = xxx;

TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);

Parameters:

base – TRDC peripheral base address.
master – Which master to configure, refer to trdc_master_t in processor header file.
domainAssignment – Pointer to the assignment structure.

static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base)#

Gets the bit map of the bus master(s) that is(are) sourcing a PID register.

This function sets the non-processor master domain assignment as valid.

Parameters:

base – TRDC peripheral base address.

Returns:

the bit map of the master(s). Bit 1 sets indicates bus master 1.

void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig)#

Sets the current Process identifier(PID) for processor core.

Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. Secure privileged software saves and restores the PID as part of any context switch. This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality.

Parameters:

base – TRDC peripheral base address.
master – Which processor master to configure, refer to trdc_master_t in processor header file.
pidConfig – Pointer to the configuration structure.

void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration)#

Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.

config->lockSecureVTOR    = false;
config->lockNonsecureVTOR = false;
config->lockSecureMPU     = false;
config->lockNonsecureMPU  = false;
config->lockSAU           = false;

Parameters:

domainAssignment – Pointer to the configuration structure.

void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration)#

Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.

Example: Lock the secure and non-secure MPU registers.

trdc_idau_config_t idauConfiguration;

TRDC_GetDefaultIDAUConfig(&idauConfiguration);

idauConfiguration.lockSecureMPU = true;
idauConfiguration.lockNonsecureMPU      = true;
TRDC_SetIDAU(TRDC, &idauConfiguration);

Parameters:

base – TRDC peripheral base address.
domainAssignment – Pointer to the configuration structure.

static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)#

Enables/disables the FLW(flash logical window) function.

Parameters:

base – TRDC peripheral base address.
enable – True to enable, false to disable.

static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)#

Locks FLW registers. Once locked the registers can noy be updated until next reset.

Parameters:

base – TRDC peripheral base address.

static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)#

Gets the FLW physical base address.

Parameters:

base – TRDC peripheral base address.

Returns:

Physical address of the FLW function.

static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)#

Sets the FLW size.

Parameters:

base – TRDC peripheral base address.
size – Size of the FLW in unit of 32k bytes.

void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration)#

Gets the default FLW(Flsh Logical Window) configuration.

config->blockCount    = false;
config->arrayBaseAddr = false;
config->lock     = false;
config->enable  = false;

Parameters:

flwConfiguration – Pointer to the configuration structure.

void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration)#

Sets the FLW function’s configuration.

trdc_flw_config_t flwConfiguration;

TRDC_GetDefaultIDAUConfig(&flwConfiguration);

flwConfiguration.blockCount = 32U;
flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
TRDC_SetIDAU(TRDC, &flwConfiguration);

Parameters:

base – TRDC peripheral base address.
flwConfiguration – Pointer to the configuration structure.

status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error)#

Gets and clears the first domain error of the current domain.

This function gets the first access violation information for the current domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.

Parameters:

base – TRDC peripheral base address.
error – Pointer to the error information.

Returns:

If the access violation is captured, this function returns the kStatus_Success. The error information can be obtained from the parameter error. If no access violation is captured, this function returns the kStatus_NoData.

status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId)#

Gets and clears the first domain error of the specific domain.

This function gets the first access violation information for the specific domain and clears the pending flag. There might be multiple access violations pending for the current domain. This function only processes the first error.

Parameters:

base – TRDC peripheral base address.
error – Pointer to the error information.
domainId – The error of which domain to get and clear.

Returns:

static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)#

Sets the TRDC MRC(Memory Region Checkers) global valid.

Once enabled, it will remain enabled until next reset.

Parameters:

base – TRDC peripheral base address.

static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)#

Gets the TRDC MRC(Memory Region Checkers) region number valid.

Parameters:

base – TRDC peripheral base address.

Returns:

the region number of the given MRC instance

void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mrcIdx, uint8_t regIdx)#

Sets the memory access configuration for one of the access control register of one MRC.

Example: Enable the secure operations and lock the configuration for MRC0 region 1.

trdc_memory_access_control_config_t config;

config.securePrivX = true;
config.securePrivW = true;
config.securePrivR = true;
config.lock = true;
TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);

Parameters:

base – TRDC peripheral base address.
config – Pointer to the configuration structure.
mrcIdx – MRC index.
regIdx – Register number.

void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable)#

Enables the update of the selected domians.

After the domians’ update are enabled, their regions’ NSE bits can be set or clear.

Parameters:

base – TRDC peripheral base address.
mrcIdx – MRC index.
domianMask – Bit mask of the domains to be enabled.
enable – True to enable, false to disable.

void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)#

Sets the NSE bits of the selected regions for domains.

This function sets the NSE bits for the selected regions for the domains whose update are enabled.

Parameters:

base – TRDC peripheral base address.
mrcIdx – MRC index.
regionMask – Bit mask of the regions whose NSE bits to set.

void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)#

Clears the NSE bits of the selected regions for domains.

This function clears the NSE bits for the selected regions for the domains whose update are enabled.

Parameters:

base – TRDC peripheral base address.
mrcIdx – MRC index.
regionMask – Bit mask of the regions whose NSE bits to clear.

void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask)#

Clears the NSE bits for all the regions of the selected domains.

This function clears the NSE bits for all regions of selected domains whose update are enabled.

Parameters:

base – TRDC peripheral base address.
mrcIdx – MRC index.
domainMask – Bit mask of the domians whose NSE bits to clear.

void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config)#

Sets the configuration for one of the region descriptor per domain per MRC instnce.

This function sets the configuration for one of the region descriptor, including the start and end address of the region, memory access control policy and valid.

Parameters:

base – TRDC peripheral base address.
config – Pointer to region descriptor configuration structure.

static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)#

Sets the TRDC MBC(Memory Block Checkers) global valid.

Once enabled, it will remain enabled until next reset.

Parameters:

base – TRDC peripheral base address.

void TRDC_GetMbcHardwareConfig(TRDC_Type *base, trdc_slave_memory_hardware_config_t *config, uint8_t mbcIdx, uint8_t slvIdx)#

Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).

Parameters:

base – TRDC peripheral base address.
config – Pointer to the structure to get the configuration.
mbcIdx – MBC number.
slvIdx – Slave number.

void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx)#

Sets the NSR update configuration for one of the MBC instance.

After set the NSE configuration, the configured memory area can be updateby NSE set/clear.

Parameters:

base – TRDC peripheral base address.
config – Pointer to NSE update configuration structure.
mbcIdx – MBC index.

void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)#

Sets the NSE bits of the selected configuration words according to NSE update configuration.

This function sets the NSE bits of the word for the configured regio, memory.

Parameters:

base – TRDC peripheral base address.
mbcIdx – MBC index.
bitMask – Mask of the bits whose NSE bits to set.

void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)#

Clears the NSE bits of the selected configuration words according to NSE update configuration.

This function sets the NSE bits of the word for the configured regio, memory.

Parameters:

base – TRDC peripheral base address.
mbcIdx – MBC index.
bitMask – Mask of the bits whose NSE bits to clear.

void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave)#

Clears all configuration words’ NSE bits of the selected domain and memory.

Parameters:

base – TRDC peripheral base address.
mbcIdx – MBC index.
domainMask – Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.
slaveMask – Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1’s NSE bits.

void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, const trdc_memory_access_control_config_t *config, uint8_t mbcIdx, uint8_t rgdIdx)#

Sets the memory access configuration for one of the region descriptor of one MBC.

Example: Enable the secure operations and lock the configuration for MRC0 region 1.

trdc_memory_access_control_config_t config;

config.securePrivX = true;
config.securePrivW = true;
config.securePrivR = true;
config.lock = true;
TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);

Parameters:

base – TRDC peripheral base address.
config – Pointer to the configuration structure.
mbcIdx – MBC index.
rgdIdx – Region descriptor number.

void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config)#

Sets the configuration for one of the memory block per domain per MBC instnce.

This function sets the configuration for one of the memory block, including the memory access control policy and nse enable.

Parameters:

base – TRDC peripheral base address.
config – Pointer to memory block configuration structure.

enum _trdc_did_sel#

TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation.

Values:

enumerator kTRDC_DidMda#: Use MDAn[2:0] as DID.

enumerator kTRDC_DidInput#: Use the input DID (DID_in) as DID.

enumerator kTRDC_DidMdaAndInput#: Use MDAn[2] concatenated with DID_in[1:0] as DID.

enumerator kTRDC_DidReserved#: Reserved.

enum _trdc_secure_attr#

TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment.

Values:

enumerator kTRDC_ForceSecure#: Force the bus attribute for this master to secure.

enumerator kTRDC_ForceNonSecure#: Force the bus attribute for this master to non-secure.

enumerator kTRDC_MasterSecure#: Use the bus master’s secure/nonsecure attribute directly.

enumerator kTRDC_MasterSecure1#: Use the bus master’s secure/nonsecure attribute directly.

enum _trdc_pid_domain_hit_config#

The configuration of domain hit evaluation of PID.

Values:

enumerator kTRDC_pidDomainHitNone0#: No PID is included in the domain hit evaluation.

enumerator kTRDC_pidDomainHitNone1#: No PID is included in the domain hit evaluation.

enumerator kTRDC_pidDomainHitInclusive#: The PID is included in the domain hit evaluation when (PID & ~PIDM).

enumerator kTRDC_pidDomainHitExclusive#: The PID is included in the domain hit evaluation when ~(PID & ~PIDM).

enum _trdc_privilege_attr#

TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment.

Values:

enumerator kTRDC_ForceUser#: Force the bus attribute for this master to user.

enumerator kTRDC_ForcePrivilege#: Force the bus attribute for this master to privileged.

enumerator kTRDC_MasterPrivilege#: Use the bus master’s attribute directly.

enumerator kTRDC_MasterPrivilege1#: Use the bus master’s attribute directly.

enum _trdc_pid_lock#

PID lock configuration.

Values:

enumerator kTRDC_PidUnlocked0#: The PID value can be updated by any secure priviledged write.

enumerator kTRDC_PidUnlocked1#: The PID value can be updated by any secure priviledged write.

enumerator kTRDC_PidUnlocked2#: The PID value can be updated by any secure priviledged write from the bus master that first configured this register.

enumerator kTRDC_PidLocked#: The PID value is locked until next reset.

enum _trdc_controller#

TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.

Values:

enumerator kTRDC_MemBlockController0#: Memory block checker 0.

enumerator kTRDC_MemBlockController1#: Memory block checker 1.

enumerator kTRDC_MemBlockController2#: Memory block checker 2.

enumerator kTRDC_MemBlockController3#: Memory block checker 3.

enumerator kTRDC_MemRegionChecker0#: Memory region checker 0.

enumerator kTRDC_MemRegionChecker1#: Memory region checker 1.

enumerator kTRDC_MemRegionChecker2#: Memory region checker 2.

enumerator kTRDC_MemRegionChecker3#: Memory region checker 3.

enumerator kTRDC_MemRegionChecker4#: Memory region checker 4.

enumerator kTRDC_MemRegionChecker5#: Memory region checker 5.

enumerator kTRDC_MemRegionChecker6#: Memory region checker 6.

enum _trdc_error_state#

TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].

Values:

enumerator kTRDC_ErrorStateNone#: No access violation detected.

enumerator kTRDC_ErrorStateNone1#: No access violation detected.

enumerator kTRDC_ErrorStateSingle#: Single access violation detected.

enumerator kTRDC_ErrorStateMulti#: Multiple access violation detected.

enum _trdc_error_attr#

TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].

Values:

enumerator kTRDC_ErrorSecureUserInst#: Secure user mode, instruction fetch access.

enumerator kTRDC_ErrorSecureUserData#: Secure user mode, data access.

enumerator kTRDC_ErrorSecurePrivilegeInst#: Secure privileged mode, instruction fetch access.

enumerator kTRDC_ErrorSecurePrivilegeData#: Secure privileged mode, data access.

enumerator kTRDC_ErrorNonSecureUserInst#: NonSecure user mode, instruction fetch access.

enumerator kTRDC_ErrorNonSecureUserData#: NonSecure user mode, data access.

enumerator kTRDC_ErrorNonSecurePrivilegeInst#: NonSecure privileged mode, instruction fetch access.

enumerator kTRDC_ErrorNonSecurePrivilegeData#: NonSecure privileged mode, data access.

enum _trdc_error_type#

TRDC domain error access type definition TRDC_DERR_W1_n[ERW].

Values:

enumerator kTRDC_ErrorTypeRead#: Error occurs on read reference.

enumerator kTRDC_ErrorTypeWrite#: Error occurs on write reference.

enum _trdc_region_descriptor#

The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions.

Values:

enumerator kTRDC_RegionDescriptor0#: Region descriptor 0.

enumerator kTRDC_RegionDescriptor1#: Region descriptor 1.

enumerator kTRDC_RegionDescriptor2#: Region descriptor 2.

enumerator kTRDC_RegionDescriptor3#: Region descriptor 3.

enumerator kTRDC_RegionDescriptor4#: Region descriptor 4.

enumerator kTRDC_RegionDescriptor5#: Region descriptor 5.

enumerator kTRDC_RegionDescriptor6#: Region descriptor 6.

enumerator kTRDC_RegionDescriptor7#: Region descriptor 7.

enumerator kTRDC_RegionDescriptor8#: Region descriptor 8.

enumerator kTRDC_RegionDescriptor9#: Region descriptor 9.

enumerator kTRDC_RegionDescriptor10#: Region descriptor 10.

enumerator kTRDC_RegionDescriptor11#: Region descriptor 11.

enumerator kTRDC_RegionDescriptor12#: Region descriptor 12.

enumerator kTRDC_RegionDescriptor13#: Region descriptor 13.

enumerator kTRDC_RegionDescriptor14#: Region descriptor 14.

enumerator kTRDC_RegionDescriptor15#: Region descriptor 15.

enum _trdc_MRC_domain#

The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or several domains.

Values:

enumerator kTRDC_MrcDomain0#: Domain 0.

enumerator kTRDC_MrcDomain1#: Domain 1.

enumerator kTRDC_MrcDomain2#: Domain 2.

enumerator kTRDC_MrcDomain3#: Domain 3.

enumerator kTRDC_MrcDomain4#: Domain 4.

enumerator kTRDC_MrcDomain5#: Domain 5.

enumerator kTRDC_MrcDomain6#: Domain 6.

enumerator kTRDC_MrcDomain7#: Domain 7.

enumerator kTRDC_MrcDomain8#: Domain 8.

enumerator kTRDC_MrcDomain9#: Domain 9.

enumerator kTRDC_MrcDomain10#: Domain 10.

enumerator kTRDC_MrcDomain11#: Domain 11.

enumerator kTRDC_MrcDomain12#: Domain 12.

enumerator kTRDC_MrcDomain13#: Domain 13.

enumerator kTRDC_MrcDomain14#: Domain 14.

enumerator kTRDC_MrcDomain15#: Domain 15.

enum _trdc_MBC_domain#

The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several domains.

Values:

enumerator kTRDC_MbcDomain0#: Domain 0.

enumerator kTRDC_MbcDomain1#: Domain 1.

enumerator kTRDC_MbcDomain2#: Domain 2.

enumerator kTRDC_MbcDomain3#: Domain 3.

enumerator kTRDC_MbcDomain4#: Domain 4.

enumerator kTRDC_MbcDomain5#: Domain 5.

enumerator kTRDC_MbcDomain6#: Domain 6.

enumerator kTRDC_MbcDomain7#: Domain 7.

enum _trdc_MBC_memory#

The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or several memory block.

Values:

enumerator kTRDC_MbcSlaveMemory0#: Memory 0.

enumerator kTRDC_MbcSlaveMemory1#: Memory 1.

enumerator kTRDC_MbcSlaveMemory2#: Memory 2.

enumerator kTRDC_MbcSlaveMemory3#: Memory 3.

enum _trdc_MBC_bit#

The MBC bit enumeration, used to form a mask to set/clear configured words’ NSE.

Values:

enumerator kTRDC_MbcBit0#: Bit 0.

enumerator kTRDC_MbcBit1#: Bit 1.

enumerator kTRDC_MbcBit2#: Bit 2.

enumerator kTRDC_MbcBit3#: Bit 3.

enumerator kTRDC_MbcBit4#: Bit 4.

enumerator kTRDC_MbcBit5#: Bit 5.

enumerator kTRDC_MbcBit6#: Bit 6.

enumerator kTRDC_MbcBit7#: Bit 7.

enumerator kTRDC_MbcBit8#: Bit 8.

enumerator kTRDC_MbcBit9#: Bit 9.

enumerator kTRDC_MbcBit10#: Bit 10.

enumerator kTRDC_MbcBit11#: Bit 11.

enumerator kTRDC_MbcBit12#: Bit 12.

enumerator kTRDC_MbcBit13#: Bit 13.

enumerator kTRDC_MbcBit14#: Bit 14.

enumerator kTRDC_MbcBit15#: Bit 15.

enumerator kTRDC_MbcBit16#: Bit 16.

enumerator kTRDC_MbcBit17#: Bit 17.

enumerator kTRDC_MbcBit18#: Bit 18.

enumerator kTRDC_MbcBit19#: Bit 19.

enumerator kTRDC_MbcBit20#: Bit 20.

enumerator kTRDC_MbcBit21#: Bit 21.

enumerator kTRDC_MbcBit22#: Bit 22.

enumerator kTRDC_MbcBit23#: Bit 23.

enumerator kTRDC_MbcBit24#: Bit 24.

enumerator kTRDC_MbcBit25#: Bit 25.

enumerator kTRDC_MbcBit26#: Bit 26.

enumerator kTRDC_MbcBit27#: Bit 27.

enumerator kTRDC_MbcBit28#: Bit 28.

enumerator kTRDC_MbcBit29#: Bit 29.

enumerator kTRDC_MbcBit30#: Bit 30.

enumerator kTRDC_MbcBit31#: Bit 31.

typedef struct _trdc_hardware_config trdc_hardware_config_t#: TRDC hardware configuration.

typedef struct _trdc_slave_memory_hardware_config trdc_slave_memory_hardware_config_t#: Hardware configuration of the two slave memories within each MBC(memory block checker).

typedef enum _trdc_did_sel trdc_did_sel_t#: TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for domain hit evaluation.

typedef enum _trdc_secure_attr trdc_secure_attr_t#: TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for bus master domain assignment.

typedef enum _trdc_pid_domain_hit_config trdc_pid_domain_hit_config_t#: The configuration of domain hit evaluation of PID.

typedef struct _trdc_processor_domain_assignment trdc_processor_domain_assignment_t#: Domain assignment for the processor bus master.

typedef enum _trdc_privilege_attr trdc_privilege_attr_t#: TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor bus master domain assignment.

typedef struct _trdc_non_processor_domain_assignment trdc_non_processor_domain_assignment_t#: Domain assignment for the non-processor bus master.

typedef enum _trdc_pid_lock trdc_pid_lock_t#: PID lock configuration.

typedef struct _trdc_pid_config trdc_pid_config_t#: Process identifier(PID) configuration for processor cores.

typedef struct _trdc_idau_config trdc_idau_config_t#: IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.

typedef struct _trdc_flw_config trdc_flw_config_t#: FLW(Flash Logical Window) configuration.

typedef enum _trdc_controller trdc_controller_t#: TRDC controller definition for domain error check. Each TRDC instance may have different MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.

typedef enum _trdc_error_state trdc_error_state_t#: TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].

typedef enum _trdc_error_attr trdc_error_attr_t#: TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].

typedef enum _trdc_error_type trdc_error_type_t#: TRDC domain error access type definition TRDC_DERR_W1_n[ERW].

typedef struct _trdc_domain_error trdc_domain_error_t#: TRDC domain error definition.

typedef struct _trdc_memory_access_control_config trdc_memory_access_control_config_t#: Memory access control configuration for MBC/MRC.

typedef struct _trdc_mrc_region_descriptor_config trdc_mrc_region_descriptor_config_t#: The configuration of each region descriptor per domain per MRC instance.

typedef struct _trdc_mbc_nse_update_config trdc_mbc_nse_update_config_t#: The configuration of MBC NSE update.

typedef struct _trdc_mbc_memory_block_config trdc_mbc_memory_block_config_t#: The configuration of each memory block per domain per MBC instance.

FSL_TRDC_DRIVER_VERSION#

struct _trdc_hardware_config#

#include <fsl_trdc.h>

TRDC hardware configuration.

Public Members

uint8_t masterNumber#: Number of bus masters.

uint8_t domainNumber#: Number of domains.

uint8_t mbcNumber#: Number of MBCs.

uint8_t mrcNumber#: Number of MRCs.

struct _trdc_slave_memory_hardware_config#

#include <fsl_trdc.h>

Hardware configuration of the two slave memories within each MBC(memory block checker).

Public Members

uint32_t blockNum#: Number of blocks.

uint32_t blockSize#: Block size.

struct _trdc_processor_domain_assignment#

#include <fsl_trdc.h>

Domain assignment for the processor bus master.

Public Members

uint32_t domainId#: Domain ID.

uint32_t domainIdSelect#: Domain ID select method, see trdc_did_sel_t.

uint32_t pidDomainHitConfig#: The configuration of the domain hit evaluation for PID, see trdc_pid_domain_hit_config_t.

uint32_t pidMask#: The mask combined with PID, so multiple PID can be included as part of the domain hit determination. Set to 0 to disable.

uint32_t secureAttr#: Secure attribute, see trdc_secure_attr_t.

uint32_t pid#: The process identifier, combined with pidMask to form the domain hit determination.

uint32_t __pad0__#: Reserved.

uint32_t lock#: Lock the register.

uint32_t __pad1__#: Reserved.

struct _trdc_non_processor_domain_assignment#

#include <fsl_trdc.h>

Domain assignment for the non-processor bus master.

Public Members

uint32_t domainId#: Domain ID.

uint32_t privilegeAttr#: Privileged attribute, see trdc_privilege_attr_t.

uint32_t secureAttr#: Secure attribute, see trdc_secure_attr_t.

uint32_t bypassDomainId#: Bypass domain ID.

uint32_t __pad0__#: Reserved.

uint32_t lock#: Lock the register.

uint32_t __pad1__#: Reserved.

struct _trdc_pid_config#

#include <fsl_trdc.h>

Process identifier(PID) configuration for processor cores.

Public Members

uint32_t pid#: The process identifier of the executing task. The highest bit can be used to define secure/nonsecure attribute of the task.

uint32_t __pad0__#: Reserved.

uint32_t lock#: How to lock the register, see trdc_pid_lock_t.

uint32_t __pad1__#: Reserved.

struct _trdc_idau_config#

#include <fsl_trdc.h>

IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.

Public Members

uint32_t __pad0__#: Reserved.

uint32_t lockSecureVTOR#: Disable writes to secure VTOR(Vector Table Offset Register).

uint32_t lockNonsecureVTOR#: Disable writes to non-secure VTOR, Application interrupt and Reset Control Registers.

uint32_t lockSecureMPU#: Disable writes to secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor in Secure state.

uint32_t lockNonsecureMPU#: Disable writes to non-secure MPU(Memory Protection Unit) from software or from a debug agent connected to the processor.

uint32_t lockSAU#: Disable writes to SAU(Security Attribution Unit) registers.

uint32_t __pad1__#: Reserved.

struct _trdc_flw_config#

#include <fsl_trdc.h>

FLW(Flash Logical Window) configuration.

Public Members

uint16_t blockCount#: Block count of the Flash Logic Window in 32KByte blocks.

uint32_t arrayBaseAddr#: Flash array base address of the Flash Logical Window.

bool lock#: Disable writes to FLW registers.

bool enable#: Enable FLW function.

struct _trdc_domain_error#

#include <fsl_trdc.h>

TRDC domain error definition.

Public Members

trdc_controller_t controller#: Which controller captured access violation.

uint32_t address#: Access address that generated access violation.

trdc_error_state_t errorState#: Error state.

trdc_error_attr_t errorAttr#: Error attribute.

trdc_error_type_t errorType#: Error type.

uint8_t errorPort#: Error port.

uint8_t domainId#: Domain ID.

uint8_t slaveMemoryIdx#: The slave memory index. Only apply when violation in MBC.

struct _trdc_memory_access_control_config#

#include <fsl_trdc.h>

Memory access control configuration for MBC/MRC.

Public Members

uint32_t nonsecureUsrX#: Allow nonsecure user execute access.

uint32_t nonsecureUsrW#: Allow nonsecure user write access.

uint32_t nonsecureUsrR#: Allow nonsecure user read access.

uint32_t __pad0__#: Reserved.

uint32_t nonsecurePrivX#: Allow nonsecure privilege execute access.

uint32_t nonsecurePrivW#: Allow nonsecure privilege write access.

uint32_t nonsecurePrivR#: Allow nonsecure privilege read access.

uint32_t __pad1__#: Reserved.

uint32_t secureUsrX#: Allow secure user execute access.

uint32_t secureUsrW#: Allow secure user write access.

uint32_t secureUsrR#: Allow secure user read access.

uint32_t __pad2__#: Reserved.

uint32_t securePrivX#: Allownsecure privilege execute access.

uint32_t securePrivW#: Allownsecure privilege write access.

uint32_t securePrivR#: Allownsecure privilege read access.

uint32_t __pad3__#: Reserved.

uint32_t lock#: Lock the configuration until next reset, only apply to access control register 0.

struct _trdc_mrc_region_descriptor_config#

#include <fsl_trdc.h>

The configuration of each region descriptor per domain per MRC instance.

Public Members

uint8_t memoryAccessControlSelect#: Select one of the 8 access control policies for this region, for access cotrol policies see trdc_memory_access_control_config_t.

uint32_t startAddr#: Physical start address.

bool valid#: Lock the register.

bool nseEnable#: Enable non-secure accesses and disable secure accesses.

uint32_t endAddr#: Physical start address.

uint8_t mrcIdx#: The index of the MRC for this configuration to take effect.

uint8_t domainIdx#: The index of the domain for this configuration to take effect.

uint8_t regionIdx#: The index of the region for this configuration to take effect.

struct _trdc_mbc_nse_update_config#

#include <fsl_trdc.h>

The configuration of MBC NSE update.

Public Members

uint32_t __pad0__#: Reserved.

uint32_t wordIdx#: MBC configuration word index to be updated.

uint32_t __pad1__#: Reserved.

uint32_t memorySelect#: Bit mask of the selected memory to be updated. _trdc_MBC_memory.

uint32_t __pad2__#: Reserved.

uint32_t domianSelect#: Bit mask of the selected domain to be updated. _trdc_MBC_domain.

uint32_t __pad3__#: Reserved.

uint32_t autoIncrement#: Whether to increment the word index after current word is updated using this configuration.

struct _trdc_mbc_memory_block_config#

#include <fsl_trdc.h>

The configuration of each memory block per domain per MBC instance.

Public Members

uint32_t memoryAccessControlSelect#: Select one of the 8 access control policies for this memory block, for access cotrol policies see trdc_memory_access_control_config_t.

uint32_t nseEnable#: Enable non-secure accesses and disable secure accesses.

uint32_t mbcIdx#: The index of the MBC for this configuration to take effect.

uint32_t domainIdx#: The index of the domain for this configuration to take effect.

uint32_t slaveMemoryIdx#: The index of the slave memory for this configuration to take effect.

uint32_t memoryBlockIdx#: The index of the memory block for this configuration to take effect.

Trdc_core#

typedef struct _TRDC_General_Type TRDC_General_Type#: TRDC general configuration register definition.

typedef struct _TRDC_FLW_Type TRDC_FLW_Type#: TRDC flash logical control register definition.

typedef struct _TRDC_DomainError_Type TRDC_DomainError_Type#: TRDC domain error register definition.

typedef struct _TRDC_DomainAssignment_Type TRDC_DomainAssignment_Type#: TRDC master domain assignment register definition.

typedef struct _TRDC_MBC_Type TRDC_MBC_Type#: TRDC MBC control register definition.

typedef struct _TRDC_MRC_Type TRDC_MRC_Type#: TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word].

TRDC_GENERAL_BASE(base)#: TRDC base address convert macro.

TRDC_FLW_BASE(base)#

TRDC_DOMAIN_ERROR_BASE(base)#

TRDC_DOMAIN_ASSIGNMENT_BASE(base)#

TRDC_MBC_BASE(base, instance)#

TRDC_MRC_BASE(base, instance)#

struct _TRDC_General_Type#

#include <fsl_trdc_core.h>

TRDC general configuration register definition.

Public Members

__IO uint32_t TRDC_CR: TRDC Register, offset: 0x0

__I uint32_t TRDC_HWCFG0: TRDC Hardware Configuration Register 0, offset: 0xF0

__I uint32_t TRDC_HWCFG1: TRDC Hardware Configuration Register 1, offset: 0xF4

__I uint32_t TRDC_HWCFG2: TRDC Hardware Configuration Register 2, offset: 0xF8

__I uint32_t TRDC_HWCFG3: TRDC Hardware Configuration Register 3, offset: 0xFC

__I uint8_t DACFG [8]: Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1

__IO uint32_t TRDC_IDAU_CR: TRDC IDAU Control Register, offset: 0x1C0

struct _TRDC_FLW_Type#

#include <fsl_trdc_core.h>

TRDC flash logical control register definition.

Public Members

__IO uint32_t TRDC_FLW_CTL: TRDC FLW Control, offset: 0x1E0

__I uint32_t TRDC_FLW_PBASE: TRDC FLW Physical Base, offset: 0x1E4

__IO uint32_t TRDC_FLW_ABASE: TRDC FLW Array Base, offset: 0x1E8

__IO uint32_t TRDC_FLW_BCNT: TRDC FLW Block Count, offset: 0x1EC

struct _TRDC_DomainError_Type#

#include <fsl_trdc_core.h>

TRDC domain error register definition.

Public Members

__IO uint32_t TRDC_FDID: TRDC Fault Domain ID, offset: 0x1FC

__I uint32_t TRDC_DERRLOC [16]: TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4

struct _TRDC_DomainAssignment_Type#

#include <fsl_trdc_core.h>

TRDC master domain assignment register definition.

Public Members

__IO uint32_t PID [8]: Process Identifier, array offset: 0x700, array step: 0x4

struct _TRDC_MBC_Type#

#include <fsl_trdc_core.h>

TRDC MBC control register definition.

Public Members

__I uint32_t MBC_MEM_GLBCFG [4]: MBC Global Configuration Register, array offset: 0x10000, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_NSE_BLK_INDEX: MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000

__O uint32_t MBC_NSE_BLK_SET: MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000

__O uint32_t MBC_NSE_BLK_CLR: MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000

__O uint32_t MBC_NSE_BLK_CLR_ALL: MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000

__IO uint32_t MBC_MEMN_GLBAC [8]: MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10040, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10180, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x101A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x101D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10240, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10380, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x103A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x103D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10440, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10580, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x105A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x105D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10640, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10780, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x107A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x107D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10840, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10980, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x109A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x109D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10A40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10B80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10BA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10BD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10C40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10D80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10DA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10DD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x10E40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10F80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10FA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x10FD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11040, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11180, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x111A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x111D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11240, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11380, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x113A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x113D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11440, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11540, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11580, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x115A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x115D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11640, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11740, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11780, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x117A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x117D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11840, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11940, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11980, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x119A8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x119D0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11A40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11B80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11BA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11BD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11C40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11D80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11DA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11DD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W [64]: MBC Memory Block Configuration Word, array offset: 0x11E40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W [16]: MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11F80, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11FA8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W [8]: MBC Memory Block Configuration Word, array offset: 0x11FD0, array step: index*0x2000, index2*0x4

__IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W [2]: MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array step: index*0x2000, index2*0x4

struct _TRDC_MRC_Type#

#include <fsl_trdc_core.h>

TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word].

Public Members

__I uint32_t MRC_GLBCFG: MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000

__IO uint32_t MRC_NSE_RGN_INDIRECT: MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000

__O uint32_t MRC_NSE_RGN_SET: MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000

__O uint32_t MRC_NSE_RGN_CLR: MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000

__O uint32_t MRC_NSE_RGN_CLR_ALL: MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000

__IO uint32_t MRC_GLBAC [8]: MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4

__IO uint32_t MRC_DOM0_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14040, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM0_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000

__IO uint32_t MRC_DOM1_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14140, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM1_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000

__IO uint32_t MRC_DOM2_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14240, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM2_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000

__IO uint32_t MRC_DOM3_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14340, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM3_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000

__IO uint32_t MRC_DOM4_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14440, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM4_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000

__IO uint32_t MRC_DOM5_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14540, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM5_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000

__IO uint32_t MRC_DOM6_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14640, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM6_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000

__IO uint32_t MRC_DOM7_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14740, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM7_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000

__IO uint32_t MRC_DOM8_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14840, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM8_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000

__IO uint32_t MRC_DOM9_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14940, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM9_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000

__IO uint32_t MRC_DOM10_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM10_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000

__IO uint32_t MRC_DOM11_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM11_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000

__IO uint32_t MRC_DOM12_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM12_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000

__IO uint32_t MRC_DOM13_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM13_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000

__IO uint32_t MRC_DOM14_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM14_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000

__IO uint32_t MRC_DOM15_RGD_W [16][2]: MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4

__IO uint32_t MRC_DOM15_RGD_NSE: MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000

struct MBC_DERR#

Public Members

__I uint32_t W0: MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10

__I uint32_t W1: MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10

__O uint32_t W3: MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10

struct MRC_DERR#

Public Members

__I uint32_t W0: MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10

__I uint32_t W1: MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10

__O uint32_t W3: MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10

union __unnamed33__#

Public Members

struct _TRDC_DomainAssignment_Type MDA_DFMT0[8]#

struct _TRDC_DomainAssignment_Type MDA_DFMT1[8]#

struct MDA_DFMT0

Public Members

__IO uint32_t MDA_W_DFMT0 [8]: DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4

struct MDA_DFMT1

Public Members

__IO uint32_t MDA_W_DFMT1 [1]: DAC Master Domain Assignment Register, array offset: 0x800, array step: index*0x20, index2*0x4

WUU: Wakeup Unit driver#

void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config)#

Enables and Configs External WakeUp Pins.

This function enables/disables the external pin as wakeup input. What’s more this function configs pins options, including edge detection wakeup event and operate mode.

Parameters:

base – MUU peripheral base address.
pinIndex – The index of the external input pin. See Reference Manual for the details.
config – Pointer to wuu_external_wakeup_pin_config_t structure.

void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex)#

Disable and clear external wakeup pin settings.

Parameters:

base – MUU peripheral base address.
pinIndex – The index of the external input pin.

static inline uint32_t WUU_GetExternalWakeUpPinsFlag(WUU_Type *base)#

Gets External Wakeup pin flags.

This function return the external wakeup pin flags.

Parameters:

base – WUU peripheral base address.

Returns:

Wakeup flags for all external wakeup pins.

static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask)#

Clears External WakeUp Pin flags.

This function clears external wakeup pins flags based on the mask.

Parameters:

base – WUU peripheral base address.
mask – The mask of Wakeup pin index to be cleared.

void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event)#

Config Internal modules’ event as the wake up soures.

This function configs the internal modules event as the wake up sources.

Parameters:

base – WUU peripheral base address.
moduleIndex – The selected internal module. See the Reference Manual for the details.
event – Select interrupt or DMA/Trigger of the internal module as the wake up source.

void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event)#

Disable an on-chip internal modules’ event as the wakeup sources.

Parameters:

base – WUU peripheral base address.
moduleIndex – The selected internal module. See the Reference Manual for the details.
event – The event(interrupt or DMA/trigger) of the internal module to disable.

static inline uint32_t WUU_GetModuleInterruptFlag(WUU_Type *base)#

Get wakeup flags for internal wakeup modules.

Parameters:

base – WUU peripheral base address.

Returns:

Wakeup flags for all internal wakeup modules.

static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t moduleIndex)#

Gets the internal module wakeup source flag.

This function checks the flag to detect whether the system is woken up by specific on-chip module interrupt.

Parameters:

base – WWU peripheral base address.
moduleIndex – A module index, which starts from 0.

Returns:

True if the specific pin is a wake up source.

void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config)#

Configs and Enables Pin filters.

This function configs Pin filter, including pin select, filer operate mode filer wakeup event and filter edge detection.

Parameters:

base – WUU peripheral base address.
filterIndex – The index of the pin filer.
config – Pointer to wuu_pin_filter_config_t structure.

bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex)#

Gets the pin filter configuration.

This function gets the pin filter flag.

Parameters:

base – WUU peripheral base address.
filterIndex – A pin filter index, which starts from 1.

Returns:

True if the flag is a source of the existing low-leakage power mode.

void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex)#

Clears the pin filter configuration.

This function clears the pin filter flag.

Parameters:

base – WUU peripheral base address.
filterIndex – A pin filter index to clear the flag, starting from 1.

bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex)#

brief Gets the external wakeup source flag.

This function checks the external pin flag to detect whether the MCU is woken up by the specific pin.

param base WUU peripheral base address. param pinIndex A pin index, which starts from 0. return True if the specific pin is a wakeup source.

void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex)#

brief Clears the external wakeup source flag.

This function clears the external wakeup source flag for a specific pin.

param base WUU peripheral base address. param pinIndex A pin index, which starts from 0.

FSL_WUU_DRIVER_VERSION#: Defines WUU driver version 2.4.2.

enum _wuu_external_pin_edge_detection#

External WakeUp pin edge detection enumeration.

Values:

enumerator kWUU_ExternalPinDisable#: External input Pin disabled as wake up input.

enumerator kWUU_ExternalPinRisingEdge#: External input Pin enabled with the rising edge detection.

enumerator kWUU_ExternalPinFallingEdge#: External input Pin enabled with the falling edge detection.

enumerator kWUU_ExternalPinAnyEdge#: External input Pin enabled with any change detection.

enum _wuu_external_wakeup_pin_event#

External input wake up pin event enumeration.

Values:

enumerator kWUU_ExternalPinInterrupt#: External input Pin configured as interrupt.

enumerator kWUU_ExternalPinDMARequest#: External input Pin configured as DMA request.

enumerator kWUU_ExternalPinTriggerEvent#: External input Pin configured as Trigger event.

enum _wuu_external_wakeup_pin_mode#

External input wake up pin mode enumeration.

Values:

enumerator kWUU_ExternalPinActiveDSPD#: External input Pin is active only during Deep Sleep/Power Down Mode. NOTE: This enumerations has been deprecated, please switch to kWUU_ExternalPinActiveLowLeakage.

enumerator kWUU_ExternalPinActiveLowLeakageMode#: External input Pin is active only during low-leakage power modes.

enumerator kWUU_ExternalPinActiveAlways#: External input Pin is active during all power modes.

enum _wuu_internal_wakeup_module_event#

Internal module wake up event enumeration.

Values:

enumerator kWUU_InternalModuleInterrupt#: Internal modules’ interrupt as a wakeup source.

enumerator kWUU_InternalModuleDMATrigger#: Internal modules’ DMA/Trigger as a wakeup source.

enum _wuu_filter_edge#

Pin filter edge enumeration.

Values:

enumerator kWUU_FilterDisabled#: Filter disabled.

enumerator kWUU_FilterPosedgeEnable#: Filter posedge detect enabled.

enumerator kWUU_FilterNegedgeEnable#: Filter negedge detect enabled.

enumerator kWUU_FilterAnyEdge#: Filter any edge detect enabled.

enum _wuu_filter_event#

Pin Filter event enumeration.

Values:

enumerator kWUU_FilterInterrupt#: Filter output configured as interrupt.

enumerator kWUU_FilterDMARequest#: Filter output configured as DMA request.

enumerator kWUU_FilterTriggerEvent#: Filter output configured as Trigger event.

enum _wuu_filter_mode#

Pin filter mode enumeration.

Values:

enumerator kWUU_FilterActiveDSPD#: External input pin filter is active only during Deep Sleep/Power Down Mode. NOTE: This enumerations has been deprecated, please switch to kWUU_FilterActiveLowLeakage.

enumerator kWUU_FilterActiveLowLeakageMode#: External input pin filter is active only during low-leakage power modes.

enumerator kWUU_FilterActiveAlways#: External input Pin filter is active during all power modes.

typedef enum _wuu_external_pin_edge_detection wuu_external_pin_edge_detection_t#: External WakeUp pin edge detection enumeration.

typedef enum _wuu_external_wakeup_pin_event wuu_external_wakeup_pin_event_t#: External input wake up pin event enumeration.

typedef enum _wuu_external_wakeup_pin_mode wuu_external_wakeup_pin_mode_t#: External input wake up pin mode enumeration.

typedef enum _wuu_internal_wakeup_module_event wuu_internal_wakeup_module_event_t#: Internal module wake up event enumeration.

typedef enum _wuu_filter_edge wuu_filter_edge_t#: Pin filter edge enumeration.

typedef enum _wuu_filter_event wuu_filter_event_t#: Pin Filter event enumeration.

typedef enum _wuu_filter_mode wuu_filter_mode_t#: Pin filter mode enumeration.

typedef struct _wuu_external_wakeup_pin_config wuu_external_wakeup_pin_config_t#: External WakeUp pin configuration.

typedef struct _wuu_pin_filter_config wuu_pin_filter_config_t#: Pin Filter configuration.

struct _wuu_external_wakeup_pin_config#

#include <fsl_wuu.h>

External WakeUp pin configuration.

Public Members

wuu_external_pin_edge_detection_t edge#: External Input pin edge detection.

wuu_external_wakeup_pin_event_t event#: External Input wakeup Pin event

wuu_external_wakeup_pin_mode_t mode#: External Input wakeup Pin operate mode.

struct _wuu_pin_filter_config#

#include <fsl_wuu.h>

Pin Filter configuration.

Public Members

uint32_t pinIndex#: The index of wakeup pin to be muxxed into filter.

wuu_filter_edge_t edge#: The edge of the pin digital filter.

wuu_filter_event_t event#: The event of the filter output.

wuu_filter_mode_t mode#: The mode of the filter operate.

WWDT: Windowed Watchdog Timer Driver#

void WWDT_GetDefaultConfig(wwdt_config_t *config)#

Initializes WWDT configure structure.

This function initializes the WWDT configure structure to default value. The default value are:

config->enableWwdt = true;
config->enableWatchdogReset = false;
config->enableWatchdogProtect = false;
config->enableLockOscillator = false;
config->windowValue = 0xFFFFFFU;
config->timeoutValue = 0xFFFFFFU;
config->warningValue = 0;

See also

wwdt_config_t

Parameters:

config – Pointer to WWDT config structure.

void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)#

Initializes the WWDT.

This function initializes the WWDT. When called, the WWDT runs according to the configuration.

Example:

wwdt_config_t config;
WWDT_GetDefaultConfig(&config);
config.timeoutValue = 0x7ffU;
WWDT_Init(wwdt_base,&config);

Parameters:

base – WWDT peripheral base address
config – The configuration of WWDT

void WWDT_Deinit(WWDT_Type *base)#

Shuts down the WWDT.

This function shuts down the WWDT.

Parameters:

base – WWDT peripheral base address

static inline void WWDT_Enable(WWDT_Type *base)#

Enables the WWDT module.

This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.

Parameters:

base – WWDT peripheral base address

static inline void WWDT_Disable(WWDT_Type *base)#

Disables the WWDT module.

Deprecated:: Do not use this function. It will be deleted in next release version, for once the bit field of WDEN written with a 1, it can not be re-written with a 0.

This function write value into WWDT_MOD register to disable the WWDT.

Parameters:

base – WWDT peripheral base address

static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)#

Gets all WWDT status flags.

This function gets all status flags.

Example for getting Timeout Flag:

uint32_t status;
status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;

Parameters:

base – WWDT peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration _wwdt_status_flags_t

void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)#

Clear WWDT flag.

This function clears WWDT status flag.

Example for clearing warning flag:

WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);

Parameters:

base – WWDT peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration _wwdt_status_flags_t

static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)#

Set the WWDT warning value.

The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter is no longer greater than the value defined by WARNINT, an interrupt will be generated after the subsequent WDCLK.

Parameters:

base – WWDT peripheral base address
warningValue – WWDT warning value.

static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)#

Set the WWDT timeout value.

This function sets the timeout value. Every time a feed sequence occurs the value in the TC register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change the timeout value before the watchdog counter is below the warning and window values will cause a watchdog reset and set the WDTOF flag.

Parameters:

base – WWDT peripheral base address
timeoutCount – WWDT timeout value, count of WWDT clock tick.

static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)#

Sets the WWDT window value.

The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer value) so windowing is not in effect.

Parameters:

base – WWDT peripheral base address
windowValue – WWDT window value.

void WWDT_Refresh(WWDT_Type *base)#

Refreshes the WWDT timer.

This function feeds the WWDT. This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.

Parameters:

base – WWDT peripheral base address

FSL_WWDT_DRIVER_VERSION#: Defines WWDT driver version.

WWDT_FIRST_WORD_OF_REFRESH#: First word of refresh sequence

WWDT_SECOND_WORD_OF_REFRESH#: Second word of refresh sequence

enum _wwdt_status_flags_t#

WWDT status flags.

This structure contains the WWDT status flags for use in the WWDT functions.

Values:

enumerator kWWDT_TimeoutFlag#: Time-out flag, set when the timer times out

enumerator kWWDT_WarningFlag#: Warning interrupt flag, set when timer is below the value WDWARNINT

typedef struct _wwdt_config wwdt_config_t#: Describes WWDT configuration structure.

struct _wwdt_config#

#include <fsl_wwdt.h>

Describes WWDT configuration structure.

Public Members

bool enableWwdt#: Enables or disables WWDT

bool enableWatchdogReset#: true: Watchdog timeout will cause a chip reset false: Watchdog timeout will not cause a chip reset

bool enableWatchdogProtect#: true: Enable watchdog protect i.e timeout value can only be changed after counter is below warning & window values false: Disable watchdog protect; timeout value can be changed at any time

uint32_t windowValue#: Window value, set this to 0xFFFFFF if windowing is not in effect

uint32_t timeoutValue#: Timeout value

uint32_t warningValue#: Watchdog time counter value that will generate a warning interrupt. Set this to 0 for no warning

uint32_t clockFreq_Hz#: Watchdog clock source frequency.

Xbar#

void XBAR_Init(xbar_instance_t xbarInstance)#

Initializes the XBAR modules.

This function un-gates the XBAR clock.

Parameters:

xbarInstance – XBAR peripheral address.

void XBAR_Deinit(xbar_instance_t xbarInstance)#

Shutdown the XBAR modules.

This function disables XBAR clock.

Parameters:

xbarInstance – XBAR peripheral address.

status_t XBAR_SetSignalsConnection(xbar_input_signal_t input, xbar_output_signal_t output)#

Set connection between the selected XBAR_IN[*] input and the XBAR_OUT[*] output signal.

This function connects the XBAR input to the selected XBAR output. If more than one XBAR module is available, only the inputs and outputs from the same module can be connected.

Example:

XBAR_SetSignalsConnection(kXBAR_DSC1_InputLogicLow, kXBAR_DSC1_OutputTriggerSyncIn0);

Parameters:

input – XBAR input signal.
output – XBAR output signal.

Return values:

kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.

status_t XBAR_ClearOutputStatusFlag(xbar_output_signal_t output)#

Clears the edge detection status flags.

Parameters:

output – XBAR output signal.

Return values:

kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.

status_t XBAR_GetOutputStatusFlag(xbar_output_signal_t output, bool *flag)#

Gets the active edge detection status.

This function gets the active edge detect status of all XBAR_OUTs. If the active edge occurs, the return value is asserted. When the interrupt or the DMA functionality is enabled for the XBAR_OUTx, this field is 1 when the interrupt or DMA request is asserted and 0 when the interrupt or DMA request has been cleared.

Parameters:

output – XBAR output signal.
flag – get XBAR output status flag.

Return values:

kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.

status_t XBAR_SetOutputSignalConfig(xbar_output_signal_t output, const xbar_control_config_t *controlConfig)#

Configures the XBAR control register.

This function configures an XBAR control register. The active edge detection and the DMA/IRQ function on the corresponding XBAR output can be set.

Example:

xbar_control_config_t userConfig;
userConfig.activeEdge = kXBAR_EdgeRising;
userConfig.requestType = kXBAR_RequestInterruptEnable;
XBAR_SetOutputSignalConfig(kXBARA_OutputDMAMUX18, &userConfig);

Parameters:

output – XBAR output signal.
controlConfig – Pointer to structure that keeps configuration of control register.

Return values:

kStatus_Success – Signal connection set successfully.
kStatus_InvalidArgument – Failed because of invalid argument.

status_t XBAR_LockSelReg(xbar_output_signal_t output)#

Lock the XBAR SEL register.

When locked, the register can’t be written until reset the XBAR module.

Parameters:

output – XBAR output signal.

Return values:

kStatus_Success – Register locked successfully.
kStatus_InvalidArgument – Failed because of invalid argument.

status_t XBAR_LockCtrlReg(xbar_output_signal_t output)#

Lock the XBAR CTRL register.

When locked, the register can’t be written until reset the XBAR module.

Parameters:

output – XBAR output signal.

Return values:

kStatus_Success – Register locked successfully.
kStatus_InvalidArgument – Failed because of invalid argument.

enum _xbar_active_edge#

XBAR active edge for detection.

Values:

enumerator kXBAR_EdgeNone#: Edge detection status bit never asserts.

enumerator kXBAR_EdgeRising#: Edge detection status bit asserts on rising edges.

enumerator kXBAR_EdgeFalling#: Edge detection status bit asserts on falling edges.

enumerator kXBAR_EdgeRisingAndFalling#: Edge detection status bit asserts on rising and falling edges.

enumerator kXBAR_EdgeMax#: Max value.

enum _xbar_request#

Defines the XBAR DMA and interrupt configurations.

Values:

enumerator kXBAR_RequestDisable#: Interrupt and DMA are disabled.

enumerator kXBAR_RequestDMAEnable#: DMA enabled, interrupt disabled.

enumerator kXBAR_RequestInterruptEnable#: Interrupt enabled, DMA disabled.

enumerator kXBAR_RequestMax#: Max value.

typedef uint16_t xbar_reg_t#

typedef enum _xbar_active_edge xbar_active_edge_t#: XBAR active edge for detection.

typedef enum _xbar_request xbar_request_t#: Defines the XBAR DMA and interrupt configurations.

typedef struct _xbar_control_config xbar_control_config_t#

Defines the configuration structure of the XBAR control register.

This structure keeps the configuration of XBAR control register for one output. Control registers are available only for a few outputs. Not every XBAR module has control registers.

FSL_XBAR_DRIVER_VERSION#

struct xbar_info_t#: #include <fsl_xbar.h>

Find the instance index from base address and register offset mappings.

struct _xbar_control_config#

#include <fsl_xbar.h>

Defines the configuration structure of the XBAR control register.

This structure keeps the configuration of XBAR control register for one output. Control registers are available only for a few outputs. Not every XBAR module has control registers.

Public Members

xbar_active_edge_t activeEdge#: Active edge to be detected.

xbar_request_t requestType#: Selects DMA/Interrupt request.

MCXC353

Contents

MCXC353#

AOI: Crossbar AND/OR/INVERT Driver#

CRC: Cyclic Redundancy Check Driver#

DualADC: Dual Analog-to-Digital Converter#

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

eDMA core Driver#

eDMA soc Driver#

EIM: error injection module#

ERM: error recording module#

FGPIO Driver#

C40ESP3 Flash Driver#

FlexPWM: Enhanced Flex Pulse Width Modulator#

FREQME: Frequency Measurement#

FTM: FlexTimer Driver#

GPIO: General-Purpose Input/Output Driver#

GPIO Driver#

HSCMP: High Speed Analog Comparator Driver#

Common Driver#

Lpc_freqme#

LPI2C: Low Power Inter-Integrated Circuit Driver#

LPI2C Master Driver#

LPI2C Master DMA Driver#

LPI2C Slave Driver#

LPSPI: Low Power Serial Peripheral Interface#

LPSPI Peripheral driver#

LPSPI eDMA Driver#

LPUART: Low Power Universal Asynchronous Receiver/Transmitter Driver#

LPUART Driver#

LPUART eDMA Driver#

MAU: Math Accelerator Unit Driver#

MCX_CMC: Core Mode Controller Driver#

MCX_SPC: System Power Control driver#

MCX_VBAT: Smart Power Switch#

OPAMP: Operational Amplifier#

PHD: Phase Detector#

PIT: Periodic Interrupt Timer (PIT) Driver#

The Driver Change Log#

PIT Peripheral and Driver Overview#

PORT: Port Control and Interrupts#

PWM: Pulse Width Modulator#

PWT: Pulse Width Timer#

QTMR: Quad Timer Driver#

TRDC: Trusted Resource Domain Controller#

Trdc_core#

WUU: Wakeup Unit driver#

WWDT: Windowed Watchdog Timer Driver#

Xbar#