MCXA156

MCXA156#

AOI: Crossbar AND/OR/INVERT Driver#

void AOI_Init(AOI_Type *base)#

Initializes an AOI instance for operation.

This function un-gates the AOI clock.

Parameters:

base – AOI peripheral address.

void AOI_Deinit(AOI_Type *base)#

Deinitializes an AOI instance for operation.

This function shutdowns AOI module.

Parameters:

base – AOI peripheral address.

void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)#

Gets the Boolean evaluation associated.

This function returns the Boolean evaluation associated.

Example:

aoi_event_config_t demoEventLogicStruct;

AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Index of the event which will be set of type aoi_event_t.
config – Selected input configuration .

void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)#

Configures an AOI event.

This function configures an AOI event according to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) of all product terms (0, 1, 2, and 3) of a desired event.

Example:

aoi_event_config_t demoEventLogicStruct;

demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
demoEventLogicStruct.PT0DC = kAOI_LogicOne;

demoEventLogicStruct.PT1AC = kAOI_LogicZero;
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
demoEventLogicStruct.PT1DC = kAOI_LogicOne;

demoEventLogicStruct.PT2AC = kAOI_LogicZero;
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
demoEventLogicStruct.PT2DC = kAOI_LogicOne;

demoEventLogicStruct.PT3AC = kAOI_LogicZero;
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
demoEventLogicStruct.PT3DC = kAOI_LogicOne;

AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);

Parameters:

base – AOI peripheral address.
event – Event which will be configured of type aoi_event_t.
eventConfig – Pointer to type aoi_event_config_t structure. The user is responsible for filling out the members of this structure and passing the pointer to this function.

FSL_AOI_DRIVER_VERSION#: Version 2.0.2.

enum _aoi_input_config#

AOI input configurations.

The selection item represents the Boolean evaluations.

Values:

enumerator kAOI_LogicZero#: Forces the input to logical zero.

enumerator kAOI_InputSignal#: Passes the input signal.

enumerator kAOI_InvInputSignal#: Inverts the input signal.

enumerator kAOI_LogicOne#: Forces the input to logical one.

enum _aoi_event#

AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

Values:

enumerator kAOI_Event0#: Event 0 index

enumerator kAOI_Event1#: Event 1 index

enumerator kAOI_Event2#: Event 2 index

enumerator kAOI_Event3#: Event 3 index

typedef enum _aoi_input_config aoi_input_config_t#

AOI input configurations.

The selection item represents the Boolean evaluations.

typedef enum _aoi_event aoi_event_t#: AOI event indexes, where an event is the collection of the four product terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).

typedef struct _aoi_event_config aoi_event_config_t#

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

AOI#: AOI peripheral address

struct _aoi_event_config#

#include <fsl_aoi.h>

AOI event configuration structure.

Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make whole event configuration.

Public Members

aoi_input_config_t PT0AC#: Product term 0 input A

aoi_input_config_t PT0BC#: Product term 0 input B

aoi_input_config_t PT0CC#: Product term 0 input C

aoi_input_config_t PT0DC#: Product term 0 input D

aoi_input_config_t PT1AC#: Product term 1 input A

aoi_input_config_t PT1BC#: Product term 1 input B

aoi_input_config_t PT1CC#: Product term 1 input C

aoi_input_config_t PT1DC#: Product term 1 input D

aoi_input_config_t PT2AC#: Product term 2 input A

aoi_input_config_t PT2BC#: Product term 2 input B

aoi_input_config_t PT2CC#: Product term 2 input C

aoi_input_config_t PT2DC#: Product term 2 input D

aoi_input_config_t PT3AC#: Product term 3 input A

aoi_input_config_t PT3BC#: Product term 3 input B

aoi_input_config_t PT3CC#: Product term 3 input C

aoi_input_config_t PT3DC#: Product term 3 input D

CACHE: LPCAC CACHE Memory Controller#

static inline void L1CACHE_EnableCodeCache(void)#: Enables the processor code bus cache.

static inline void L1CACHE_DisableCodeCache(void)#: Disables the processor code bus cache.

static inline void L1CACHE_InvalidateCodeCache(void)#: Clears cache.

Note

LPCAC_CTRL[CLR_LPCAC] is a sticky bit: writing 1 clears (invalidates) the cache, and the cache is held cleared until the bit is written back to 0. This function therefore sets the bit and then clears it, with a memory barrier in between, so the cache is invalidated and left in a valid (operational) state.

static inline void L1CACHE_EnableAllocation(void)#: Enables allocation.

static inline void L1CACHE_DisableAllocation(void)#: Disables allocation.

static inline void L1CACHE_EnableParity(void)#: Enables parity.

static inline void L1CACHE_DisableParity(void)#: Disable parity.

FSL_CACHE_LPCAC_DRIVER_VERSION#: cache driver version

CDOG#

status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)#

Initialize CDOG.

This function initializes CDOG block and setting.

Parameters:

base – CDOG peripheral base address
conf – CDOG configuration structure

Returns:

Status of the init operation

void CDOG_Deinit(CDOG_Type *base)#

Deinitialize CDOG.

This function deinitializes CDOG secure counter.

Parameters:

base – CDOG peripheral base address

void CDOG_GetDefaultConfig(cdog_config_t *conf)#

Sets the default configuration of CDOG.

This function initialize CDOG config structure to default values.

Parameters:

conf – CDOG configuration structure

void CDOG_Stop(CDOG_Type *base, uint32_t stop)#

Stops secure counter and instruction timer.

This function stops instruction timer and secure counter. This also change state od CDOG to IDLE.

Parameters:

base – CDOG peripheral base address
stop – expected value which will be compared with value of secure counter

void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)#

Sets secure counter and instruction timer values.

This function sets value in RELOAD and START registers for instruction timer and secure counter

Parameters:

base – CDOG peripheral base address
reload – reload value
start – start value

void CDOG_Check(CDOG_Type *base, uint32_t check)#

Checks secure counter.

This function compares stop value in handler with secure counter value by writting to RELOAD refister.

Parameters:

base – CDOG peripheral base address
check – expected (stop) value

void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)#

Sets secure counter and instruction timer values.

This function sets value in STOP, RELOAD and START registers for instruction timer and secure counter.

Parameters:

base – CDOG peripheral base address
stop – expected value which will be compared with value of secure counter
reload – reload value for instruction timer
start – start value for secure timer

void CDOG_Add(CDOG_Type *base, uint32_t add)#

Add value to secure counter.

This function add specified value to secure counter.

Parameters:

base – CDOG peripheral base address.
add – Value to be added.

void CDOG_Add1(CDOG_Type *base)#

Add 1 to secure counter.

This function add 1 to secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Add16(CDOG_Type *base)#

Add 16 to secure counter.

This function add 16 to secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Add256(CDOG_Type *base)#

Add 256 to secure counter.

This function add 256 to secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Sub(CDOG_Type *base, uint32_t sub)#

brief Substract value to secure counter

This function substract specified value to secure counter.

param base CDOG peripheral base address. param sub Value to be substracted.

void CDOG_Sub1(CDOG_Type *base)#

Substract 1 from secure counter.

This function substract specified 1 from secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Sub16(CDOG_Type *base)#

Substract 16 from secure counter.

This function substract specified 16 from secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_Sub256(CDOG_Type *base)#

Substract 256 from secure counter.

This function substract specified 256 from secure counter.

Parameters:

base – CDOG peripheral base address.

void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)#

Set the CDOG persistent word.

Parameters:

base – CDOG peripheral base address.
value – The value to be written.

uint32_t CDOG_ReadPersistent(CDOG_Type *base)#

Get the CDOG persistent word.

Parameters:

base – CDOG peripheral base address.

Returns:

The persistent word.

FSL_CDOG_DRIVER_VERSION#

Defines CDOG driver version 2.1.3.

Change log:

Version 2.1.3
- Re-design multiple instance IRQs and Clocks
- Add fix for RESTART command errata
Version 2.1.2
- Support multiple IRQs
- Fix default CONTROL values
Version 2.1.1
- Remove bit CONTROL[CONTROL_CTRL]
Version 2.1.0
- Rename CWT to CDOG
Version 2.0.2
- Fix MISRA-2012 issues
Version 2.0.1
- Fix doxygen issues
Version 2.0.0
- initial version

enum __cdog_debug_Action_ctrl_enum#

Values:

enumerator kCDOG_DebugHaltCtrl_Run#

enumerator kCDOG_DebugHaltCtrl_Pause#

enum __cdog_irq_pause_ctrl_enum#

Values:

enumerator kCDOG_IrqPauseCtrl_Run#

enumerator kCDOG_IrqPauseCtrl_Pause#

enum __cdog_fault_ctrl_enum#

Values:

enumerator kCDOG_FaultCtrl_EnableReset#

enumerator kCDOG_FaultCtrl_EnableInterrupt#

enumerator kCDOG_FaultCtrl_NoAction#

enum __code_lock_ctrl_enum#

Values:

enumerator kCDOG_LockCtrl_Lock#

enumerator kCDOG_LockCtrl_Unlock#

typedef uint32_t secure_counter_t#

SC_ADD(add)#

SC_ADD1#

SC_ADD16#

SC_ADD256#

SC_SUB(sub)#

SC_SUB1#

SC_SUB16#

SC_SUB256#

SC_CHECK(val)#

struct cdog_config_t#

Clock Driver#

enum _clock_ip_name#

Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

Values:

enumerator kCLOCK_InputMux#: Clock gate name: INPUTMUX0

enumerator kCLOCK_GateINPUTMUX0#: Clock gate name: INPUTMUX0

enumerator kCLOCK_GateI3C0#: Clock gate name: I3C0

enumerator kCLOCK_GateCTIMER0#: Clock gate name: CTIMER0

enumerator kCLOCK_GateCTIMER1#: Clock gate name: CTIMER1

enumerator kCLOCK_GateCTIMER2#: Clock gate name: CTIMER2

enumerator kCLOCK_GateCTIMER3#: Clock gate name: CTIMER3

enumerator kCLOCK_GateCTIMER4#: Clock gate name: CTIMER4

enumerator kCLOCK_GateFREQME#: Clock gate name: FREQME

enumerator kCLOCK_GateUTICK0#: Clock gate name: UTICK0

enumerator kCLOCK_GateWWDT0#: Clock gate name: WWDT0

enumerator kCLOCK_GateDMA#: Clock gate name: DMA

enumerator kCLOCK_GateAOI0#: Clock gate name: AOI0

enumerator kCLOCK_GateCRC0#: Clock gate name: CRC0

enumerator kCLOCK_Crc0#: Clock gate name: CRC0

enumerator kCLOCK_GateEIM0#: Clock gate name: EIM0

enumerator kCLOCK_GateERM0#: Clock gate name: ERM0

enumerator kCLOCK_GateFMC#: Clock gate name: FMC

enumerator kCLOCK_GateAOI1#: Clock gate name: AOI1

enumerator kCLOCK_GateFLEXIO0#: Clock gate name: FLEXIO0

enumerator kCLOCK_GateLPI2C0#: Clock gate name: LPI2C0

enumerator kCLOCK_GateLPI2C1#: Clock gate name: LPI2C1

enumerator kCLOCK_GateLPSPI0#: Clock gate name: LPSPI0

enumerator kCLOCK_GateLPSPI1#: Clock gate name: LPSPI1

enumerator kCLOCK_GateLPUART0#: Clock gate name: LPUART0

enumerator kCLOCK_GateLPUART1#: Clock gate name: LPUART1

enumerator kCLOCK_GateLPUART2#: Clock gate name: LPUART2

enumerator kCLOCK_GateLPUART3#: Clock gate name: LPUART3

enumerator kCLOCK_GateLPUART4#: Clock gate name: LPUART4

enumerator kCLOCK_GateUSB0#: Clock gate name: USB0

enumerator kCLOCK_GateQDC0#: Clock gate name: QDC0

enumerator kCLOCK_GateQDC1#: Clock gate name: QDC1

enumerator kCLOCK_GateFLEXPWM0#: Clock gate name: FLEXPWM0

enumerator kCLOCK_GateFLEXPWM1#: Clock gate name: FLEXPWM1

enumerator kCLOCK_GateOSTIMER0#: Clock gate name: OSTIMER0

enumerator kCLOCK_GateADC0#: Clock gate name: ADC0

enumerator kCLOCK_GateADC1#: Clock gate name: ADC1

enumerator kCLOCK_GateCMP0#: Clock gate name: CMP0

enumerator kCLOCK_GateCMP1#: Clock gate name: CMP1

enumerator kCLOCK_GateDAC0#: Clock gate name: DAC0

enumerator kCLOCK_GateOPAMP0#: Clock gate name: OPAMP0

enumerator kCLOCK_GatePORT0#: Clock gate name: PORT0

enumerator kCLOCK_GatePORT1#: Clock gate name: PORT1

enumerator kCLOCK_GatePORT2#: Clock gate name: PORT2

enumerator kCLOCK_GatePORT3#: Clock gate name: PORT3

enumerator kCLOCK_GatePORT4#: Clock gate name: PORT4

enumerator kCLOCK_GateFLEXCAN0#: Clock gate name: FLEXCAN0

enumerator kCLOCK_GateLPI2C2#: Clock gate name: LPI2C2

enumerator kCLOCK_GateLPI2C3#: Clock gate name: LPI2C3

enumerator kCLOCK_GateMTR#: Clock gate name: MTR

enumerator kCLOCK_GateTCU#: Clock gate name: TCU

enumerator kCLOCK_GateRAMA#: Clock gate name: RAMA

enumerator kCLOCK_GateRAMB#: Clock gate name: RAMB

enumerator kCLOCK_GateGPIO0#: Clock gate name: GPIO0

enumerator kCLOCK_GateGPIO1#: Clock gate name: GPIO1

enumerator kCLOCK_GateGPIO2#: Clock gate name: GPIO2

enumerator kCLOCK_GateGPIO3#: Clock gate name: GPIO3

enumerator kCLOCK_GateGPIO4#: Clock gate name: GPIO4

enumerator kCLOCK_GateROMC#: Clock gate name: ROMC

enumerator kCLOCK_GatePWM0SM0#: Clock gate name: FlexPWM0 SM0

enumerator kCLOCK_GatePWM0SM1#: Clock gate name: FlexPWM0 SM1

enumerator kCLOCK_GatePWM0SM2#: Clock gate name: FlexPWM0 SM2

enumerator kCLOCK_GatePWM1SM0#: Clock gate name: FlexPWM1 SM0

enumerator kCLOCK_GatePWM1SM1#: Clock gate name: FlexPWM1 SM1

enumerator kCLOCK_GatePWM1SM2#: Clock gate name: FlexPWM1 SM2

enumerator kCLOCK_GateNotAvail#: Clock gate name: None

enum _clock_name#

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_MainClk#: MAIN_CLK

enumerator kCLOCK_CoreSysClk#: Core/system clock(CPU_CLK)

enumerator kCLOCK_SYSTEM_CLK#: AHB clock

enumerator kCLOCK_BusClk#: Bus clock (AHB clock)

enumerator kCLOCK_ExtClk#: External Clock

enumerator kCLOCK_FroHf#: FRO192

enumerator kCLOCK_FroHfDiv#: Divided by FRO192

enumerator kCLOCK_Clk48M#: CLK48M

enumerator kCLOCK_Fro12M#: FRO12M

enumerator kCLOCK_Clk1M#: CLK1M

enumerator kCLOCK_Fro16K#: FRO16K

enumerator kCLOCK_Clk16K0#: CLK16K[0]

enumerator kCLOCK_Clk16K1#: CLK16K[1]

enumerator kCLOCK_SLOW_CLK#: SYSTEM_CLK divided by 4

enum _clock_select_name#

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_SelI3C0_FCLK#

enumerator kCLOCK_SelCTIMER0#

enumerator kCLOCK_SelCTIMER1#

enumerator kCLOCK_SelCTIMER2#

enumerator kCLOCK_SelCTIMER3#

enumerator kCLOCK_SelCTIMER4#

enumerator kCLOCK_SelFLEXIO0#

enumerator kCLOCK_SelLPI2C0#

enumerator kCLOCK_SelLPI2C1#

enumerator kCLOCK_SelLPSPI0#

enumerator kCLOCK_SelLPSPI1#

enumerator kCLOCK_SelLPUART0#

enumerator kCLOCK_SelLPUART1#

enumerator kCLOCK_SelLPUART2#

enumerator kCLOCK_SelLPUART3#

enumerator kCLOCK_SelLPUART4#

enumerator kCLOCK_SelUSB0#

enumerator kCLOCK_SelLPTMR0#

enumerator kCLOCK_SelOSTIMER0#

enumerator kCLOCK_SelADC0#

enumerator kCLOCK_SelADC1#

enumerator kCLOCK_SelCMP0_RR#

enumerator kCLOCK_SelCMP1_RR#

enumerator kCLOCK_SelDAC0#

enumerator kCLOCK_SelFLEXCAN0#

enumerator kCLOCK_SelLPI2C2#

enumerator kCLOCK_SelLPI2C3#

enumerator kCLOCK_SelTRACE#

enumerator kCLOCK_SelCLKOUT#

enumerator kCLOCK_SelSCGSCS#: SCG SCS clock selection

enumerator kCLOCK_SelMax#: MAX clock selection

enum _clock_attach_id#

The enumerator of clock attach Id.

Values:

enumerator kCLK_IN_to_MAIN_CLK#: Attach clk_in to MAIN_CLK.

enumerator kFRO12M_to_MAIN_CLK#: Attach FRO_12M to MAIN_CLK.

enumerator kFRO_HF_to_MAIN_CLK#: Attach FRO_HF to MAIN_CLK.

enumerator kCLK_16K_to_MAIN_CLK#: Attach CLK_16K[1] to MAIN_CLK.

enumerator kNONE_to_MAIN_CLK#: Attach NONE to MAIN_CLK.

enumerator kFRO12M_to_I3C0FCLK#: Attach FRO12M to I3C0FCLK.

enumerator kFRO_HF_DIV_to_I3C0FCLK#: Attach FRO_HF_DIV to I3C0FCLK.

enumerator kCLK_IN_to_I3C0FCLK#: Attach CLK_IN to I3C0FCLK.

enumerator kCLK_1M_to_I3C0FCLK#: Attach CLK_1M to I3C0FCLK.

enumerator kNONE_to_I3C0FCLK#: Attach NONE to I3C0FCLK.

enumerator kFRO12M_to_CTIMER0#: Attach FRO12M to CTIMER0.

enumerator kFRO_HF_to_CTIMER0#: Attach FRO_HF to CTIMER0.

enumerator kCLK_IN_to_CTIMER0#: Attach CLK_IN to CTIMER0.

enumerator kCLK_16K_to_CTIMER0#: Attach CLK_16K to CTIMER0.

enumerator kCLK_1M_to_CTIMER0#: Attach CLK_1M to CTIMER0.

enumerator kNONE_to_CTIMER0#: Attach NONE to CTIMER0.

enumerator kFRO12M_to_CTIMER1#: Attach FRO12M to CTIMER1.

enumerator kFRO_HF_to_CTIMER1#: Attach FRO_HF to CTIMER1.

enumerator kCLK_IN_to_CTIMER1#: Attach CLK_IN to CTIMER1.

enumerator kCLK_16K_to_CTIMER1#: Attach CLK_16K to CTIMER1.

enumerator kCLK_1M_to_CTIMER1#: Attach CLK_1M to CTIMER1.

enumerator kNONE_to_CTIMER1#: Attach NONE to CTIMER1.

enumerator kFRO12M_to_CTIMER2#: Attach FRO12M to CTIMER2.

enumerator kFRO_HF_to_CTIMER2#: Attach FRO_HF to CTIMER2.

enumerator kCLK_IN_to_CTIMER2#: Attach CLK_IN to CTIMER2.

enumerator kCLK_16K_to_CTIMER2#: Attach CLK_16K to CTIMER2.

enumerator kCLK_1M_to_CTIMER2#: Attach CLK_1M to CTIMER2.

enumerator kNONE_to_CTIMER2#: Attach NONE to CTIMER2.

enumerator kFRO12M_to_CTIMER3#: Attach FRO12M to CTIMER3.

enumerator kFRO_HF_to_CTIMER3#: Attach FRO_HF to CTIMER3.

enumerator kCLK_IN_to_CTIMER3#: Attach CLK_IN to CTIMER3.

enumerator kCLK_16K_to_CTIMER3#: Attach CLK_16K to CTIMER3.

enumerator kCLK_1M_to_CTIMER3#: Attach CLK_1M to CTIMER3.

enumerator kNONE_to_CTIMER3#: Attach NONE to CTIMER3.

enumerator kFRO12M_to_CTIMER4#: Attach FRO12M to CTIMER4.

enumerator kFRO_HF_to_CTIMER4#: Attach FRO_HF to CTIMER4.

enumerator kCLK_IN_to_CTIMER4#: Attach CLK_IN to CTIMER4.

enumerator kCLK_16K_to_CTIMER4#: Attach CLK_16K to CTIMER4.

enumerator kCLK_1M_to_CTIMER4#: Attach CLK_1M to CTIMER4.

enumerator kNONE_to_CTIMER4#: Attach NONE to CTIMER4.

enumerator kFRO12M_to_FLEXIO0#: Attach FRO12M to FLEXIO0.

enumerator kFRO_HF_to_FLEXIO0#: Attach FRO_HF to FLEXIO0.

enumerator kCLK_IN_to_FLEXIO0#: Attach CLK_IN to FLEXIO0.

enumerator kCLK_1M_to_FLEXIO0#: Attach CLK_1M to FLEXIO0.

enumerator kNONE_to_FLEXIO0#: Attach NONE to FLEXIO0.

enumerator kFRO_HF_DIV_to_FLEXCAN0#: Attach FRO_HF_DIV to FLEXCAN0.

enumerator kCLK_IN_to_FLEXCAN0#: Attach CLK_IN to FLEXCAN0.

enumerator kNONE_to_FLEXCAN0#: Attach NONE to FLEXCAN0.

enumerator kFRO12M_to_DAC0#: Attach FRO12M to DAC0.

enumerator kFRO_HF_DIV_to_DAC0#: Attach FRO_HF_DIV to DAC0.

enumerator kCLK_IN_to_DAC0#: Attach CLK_IN to DAC0.

enumerator kCLK_1M_to_DAC0#: Attach CLK_1M to DAC0.

enumerator kNONE_to_DAC0#: Attach NONE to DAC0.

enumerator kFRO12M_to_LPI2C0#: Attach FRO12M to LPI2C0.

enumerator kFRO_HF_DIV_to_LPI2C0#: Attach FRO_HF_DIV to LPI2C0.

enumerator kCLK_IN_to_LPI2C0#: Attach CLK_IN to LPI2C0.

enumerator kCLK_1M_to_LPI2C0#: Attach CLK_1M to LPI2C0.

enumerator kNONE_to_LPI2C0#: Attach NONE to LPI2C0.

enumerator kFRO12M_to_LPI2C1#: Attach FRO12M to LPI2C1.

enumerator kFRO_HF_DIV_to_LPI2C1#: Attach FRO_HF_DIV to LPI2C1.

enumerator kCLK_IN_to_LPI2C1#: Attach CLK_IN to LPI2C1.

enumerator kCLK_1M_to_LPI2C1#: Attach CLK_1M to LPI2C1.

enumerator kNONE_to_LPI2C1#: Attach NONE to LPI2C1.

enumerator kFRO12M_to_LPI2C2#: Attach FRO12M to LPI2C2.

enumerator kFRO_HF_DIV_to_LPI2C2#: Attach FRO_HF_DIV to LPI2C2.

enumerator kCLK_IN_to_LPI2C2#: Attach CLK_IN to LPI2C2.

enumerator kCLK_1M_to_LPI2C2#: Attach CLK_1M to LPI2C2.

enumerator kNONE_to_LPI2C2#: Attach NONE to LPI2C2.

enumerator kFRO12M_to_LPI2C3#: Attach FRO12M to LPI2C3.

enumerator kFRO_HF_DIV_to_LPI2C3#: Attach FRO_HF_DIV to LPI2C3.

enumerator kCLK_IN_to_LPI2C3#: Attach CLK_IN to LPI2C3.

enumerator kCLK_1M_to_LPI2C3#: Attach CLK_1M to LPI2C3.

enumerator kNONE_to_LPI2C3#: Attach NONE to LPI2C3.

enumerator kFRO12M_to_LPSPI0#: Attach FRO12M to LPSPI0.

enumerator kFRO_HF_DIV_to_LPSPI0#: Attach FRO_HF_DIV to LPSPI0.

enumerator kCLK_IN_to_LPSPI0#: Attach CLK_IN to LPSPI0.

enumerator kCLK_1M_to_LPSPI0#: Attach CLK_1M to LPSPI0.

enumerator kNONE_to_LPSPI0#: Attach NONE to LPSPI0.

enumerator kFRO12M_to_LPSPI1#: Attach FRO12M to LPSPI1.

enumerator kFRO_HF_DIV_to_LPSPI1#: Attach FRO_HF_DIV to LPSPI1.

enumerator kCLK_IN_to_LPSPI1#: Attach CLK_IN to LPSPI1.

enumerator kCLK_1M_to_LPSPI1#: Attach CLK_1M to LPSPI1.

enumerator kNONE_to_LPSPI1#: Attach NONE to LPSPI1.

enumerator kFRO12M_to_LPUART0#: Attach FRO12M to LPUART0.

enumerator kFRO_HF_DIV_to_LPUART0#: Attach FRO_HF_DIV to LPUART0.

enumerator kCLK_IN_to_LPUART0#: Attach CLK_IN to LPUART0.

enumerator kCLK_16K_to_LPUART0#: Attach CLK_16K to LPUART0.

enumerator kCLK_1M_to_LPUART0#: Attach CLK_1M to LPUART0.

enumerator kNONE_to_LPUART0#: Attach NONE to LPUART0.

enumerator kFRO12M_to_LPUART1#: Attach FRO12M to LPUART1.

enumerator kFRO_HF_DIV_to_LPUART1#: Attach FRO_HF_DIV to LPUART1.

enumerator kCLK_IN_to_LPUART1#: Attach CLK_IN to LPUART1.

enumerator kCLK_16K_to_LPUART1#: Attach CLK_16K to LPUART1.

enumerator kCLK_1M_to_LPUART1#: Attach CLK_1M to LPUART1.

enumerator kNONE_to_LPUART1#: Attach NONE to LPUART1.

enumerator kFRO12M_to_LPUART2#: Attach FRO12M to LPUART2.

enumerator kFRO_HF_DIV_to_LPUART2#: Attach FRO_HF_DIV to LPUART2.

enumerator kCLK_IN_to_LPUART2#: Attach CLK_IN to LPUART2.

enumerator kCLK_16K_to_LPUART2#: Attach CLK_16K to LPUART2.

enumerator kCLK_1M_to_LPUART2#: Attach CLK_1M to LPUART2.

enumerator kNONE_to_LPUART2#: Attach NONE to LPUART2.

enumerator kFRO12M_to_LPUART3#: Attach FRO12M to LPUART2.

enumerator kFRO_HF_DIV_to_LPUART3#: Attach FRO_HF_DIV to LPUART2.

enumerator kCLK_IN_to_LPUART3#: Attach CLK_IN to LPUART2.

enumerator kCLK_16K_to_LPUART3#: Attach CLK_16K to LPUART2.

enumerator kCLK_1M_to_LPUART3#: Attach CLK_1M to LPUART2.

enumerator kNONE_to_LPUART3#: Attach NONE to LPUART2.

enumerator kFRO12M_to_LPUART4#: Attach FRO12M to LPUART4.

enumerator kFRO_HF_DIV_to_LPUART4#: Attach FRO_HF_DIV to LPUART4.

enumerator kCLK_IN_to_LPUART4#: Attach CLK_IN to LPUART4.

enumerator kCLK_16K_to_LPUART4#: Attach CLK_16K to LPUART4.

enumerator kCLK_1M_to_LPUART4#: Attach CLK_1M to LPUART4.

enumerator kNONE_to_LPUART4#: Attach NONE to LPUART4.

enumerator kCLK_48M_to_USB0#: Attach FRO12M to USB0.

enumerator kCLK_IN_to_USB0#: Attach CLK_IN to USB0.

enumerator kNONE_to_USB0#: Attach NONE to USB0.

enumerator kFRO12M_to_LPTMR0#: Attach FRO12M to LPTMR0.

enumerator kFRO_HF_DIV_to_LPTMR0#: Attach FRO_HF_DIV to LPTMR0.

enumerator kCLK_IN_to_LPTMR0#: Attach CLK_IN to LPTMR0.

enumerator kCLK_1M_to_LPTMR0#: Attach CLK_1M to LPTMR0.

enumerator kNONE_to_LPTMR0#: Attach NONE to LPTMR0.

enumerator kCLK_16K_to_OSTIMER#: Attach FRO16K to OSTIMER0.

enumerator kCLK_1M_to_OSTIMER#: Attach CLK_1M to OSTIMER0.

enumerator kNONE_to_OSTIMER#: Attach NONE to OSTIMER0.

enumerator kFRO12M_to_ADC0#: Attach FRO12M to ADC0.

enumerator kFRO_HF_to_ADC0#: Attach FRO_HF to ADC0.

enumerator kCLK_IN_to_ADC0#: Attach CLK_IN to ADC0.

enumerator kCLK_1M_to_ADC0#: Attach CLK_1M to ADC0.

enumerator kNONE_to_ADC0#: Attach NONE to ADC0.

enumerator kFRO12M_to_ADC1#: Attach FRO12M to ADC1.

enumerator kFRO_HF_to_ADC1#: Attach FRO_HF to ADC1.

enumerator kCLK_IN_to_ADC1#: Attach CLK_IN to ADC1.

enumerator kCLK_1M_to_ADC1#: Attach CLK_1M to ADC1.

enumerator kNONE_to_ADC1#: Attach NONE to ADC1.

enumerator kFRO12M_to_CMP0#: Attach FRO12M to CMP0.

enumerator kFRO_HF_DIV_to_CMP0#: Attach FRO_HF_DIV to CMP0.

enumerator kCLK_IN_to_CMP0#: Attach CLK_IN to CMP0.

enumerator kCLK_1M_to_CMP0#: Attach CLK_1M to CMP0.

enumerator kNONE_to_CMP0#: Attach NONE to CMP0.

enumerator kFRO12M_to_CMP1#: Attach FRO12M to CMP1.

enumerator kFRO_HF_DIV_to_CMP1#: Attach FRO_HF_DIV to CMP1.

enumerator kCLK_IN_to_CMP1#: Attach CLK_IN to CMP1.

enumerator kCLK_1M_to_CMP1#: Attach CLK_1M to CMP1.

enumerator kNONE_to_CMP1#: Attach NONE to CMP1.

enumerator kCPU_CLK_to_TRACE#: Attach CPU_CLK to TRACE.

enumerator kCLK_1M_to_TRACE#: Attach CLK_1M to TRACE.

enumerator kCLK_16K_to_TRACE#: Attach CLK_16K to TRACE.

enumerator kNONE_to_TRACE#: Attach NONE to TRACE.

enumerator kFRO12M_to_CLKOUT#: Attach FRO12M to CLKOUT.

enumerator kFRO_HF_DIV_to_CLKOUT#: Attach FRO_HF_DIV to CLKOUT.

enumerator kCLK_IN_to_CLKOUT#: Attach CLK_IN to CLKOUT.

enumerator kCLK_16K_to_CLKOUT#: Attach CLK_16K to CLKOUT.

enumerator kSLOW_CLK_to_CLKOUT#: Attach SLOW_CLK to CLKOUT.

enumerator kNONE_to_CLKOUT#: Attach NONE to CLKOUT.

enumerator kNONE_to_NONE#: Attach NONE to NONE.

enum _clock_div_name#

Clock dividers.

Values:

enumerator kCLOCK_DivI3C0_FCLK#: I3C0_FCLK clock divider

enumerator kCLOCK_DivCTIMER0#: CTIMER0 clock divider

enumerator kCLOCK_DivCTIMER1#: CTIMER1 clock divider

enumerator kCLOCK_DivCTIMER2#: CTIMER2 clock divider

enumerator kCLOCK_DivCTIMER3#: CTIMER3 clock divider

enumerator kCLOCK_DivCTIMER4#: CTIMER4 clock divider

enumerator kCLOCK_DivWWDT0#: WWDT0 clock divider

enumerator kCLOCK_DivFLEXIO0#: FLEXIO0 clock divider

enumerator kCLOCK_DivLPI2C0#: LPI2C0 clock divider

enumerator kCLOCK_DivLPI2C1#: LPI2C1 clock divider

enumerator kCLOCK_DivLPSPI0#: LPSPI0 clock divider

enumerator kCLOCK_DivLPSPI1#: LPSPI1 clock divider

enumerator kCLOCK_DivLPUART0#: LPUART0 clock divider

enumerator kCLOCK_DivLPUART1#: LPUART1 clock divider

enumerator kCLOCK_DivLPUART2#: LPUART2 clock divider

enumerator kCLOCK_DivLPUART3#: LPUART3 clock divider

enumerator kCLOCK_DivLPUART4#: LPUART4 clock divider

enumerator kCLOCK_DivLPTMR0#: LPTMR0 clock divider

enumerator kCLOCK_DivADC0#: ADC0 clock divider

enumerator kCLOCK_DivADC1#: ADC1 clock divider

enumerator kCLOCK_DivCMP0_FUNC#: CMP0_FUNC clock divider

enumerator kCLOCK_DivCMP0_RR#: CMP0_RR clock divider

enumerator kCLOCK_DivCMP1_FUNC#: CMP1_FUNC clock divider

enumerator kCLOCK_DivCMP1_RR#: CMP1_RR clock divider

enumerator kCLOCK_DivDAC0#: DAC0 clock divider

enumerator kCLOCK_DivFLEXCAN0#: FLEXCAN0 clock divider

enumerator kCLOCK_DivLPI2C2#: LPI2C2 clock divider

enumerator kCLOCK_DivLPI2C3#: LPI2C3 clock divider

enumerator kCLOCK_DivDBG_TRACE#: DBG_TRACE clock divider

enumerator kCLOCK_DivTRACE#: DBG_TRACE clock divider

enumerator kCLOCK_DivCLKOUT#: CLKOUT clock divider

enumerator kCLOCK_DivFRO_HF_DIV#: FRO_HF_DIV clock divider

enumerator kCLOCK_DivSLOWCLK#: SLOWCLK clock divider

enumerator kCLOCK_DivAHBCLK#: System clock divider

enumerator kCLOCK_DivMax#: MAX clock divider

enum _firc_trim_mode#

firc trim mode.

Values:

enumerator kSCG_FircTrimNonUpdate#: Trim enable but not enable trim value update. In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure firc_trim_config_t.

enumerator kSCG_FircTrimUpdate#: Trim enable and trim value update enable. In this mode, the trim value is auto update.

enum _firc_trim_src#

firc trim source.

Values:

enumerator kSCG_FircTrimSrcUsb0#: USB0 start of frame (1kHz).

enumerator kSCG_FircTrimSrcSysOsc#: System OSC.

enum _sirc_trim_mode#

sirc trim mode.

Values:

enumerator kSCG_SircTrimNonUpdate#: Trim enable but not enable trim value update. In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure sirc_trim_config_t.

enumerator kSCG_SircTrimUpdate#: Trim enable and trim value update enable. In this mode, the trim value is auto update.

enum _sirc_trim_src#

sirc trim source.

Values:

enumerator kNoTrimSrc#: No external tirm source.

enumerator kSCG_SircTrimSrcSysOsc#: System OSC.

enum _scg_sosc_monitor_mode#

SCG system OSC monitor mode.

Values:

enumerator kSCG_SysOscMonitorDisable#: Monitor disabled.

enumerator kSCG_SysOscMonitorInt#: Interrupt when the SOSC error is detected.

enumerator kSCG_SysOscMonitorReset#: Reset when the SOSC error is detected.

enum _clke_16k#

firc trim source.

Values:

enumerator kCLKE_16K_SYSTEM#: To VSYS domain.

enumerator kCLKE_16K_COREMAIN#: To VDD_CORE domain.

typedef enum _clock_ip_name clock_ip_name_t#: Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

typedef enum _clock_name clock_name_t#: Clock name used to get clock frequency.

typedef enum _clock_select_name clock_select_name_t#: Clock name used to get clock frequency.

typedef enum _clock_attach_id clock_attach_id_t#: The enumerator of clock attach Id.

typedef enum _clock_div_name clock_div_name_t#: Clock dividers.

typedef enum _firc_trim_mode firc_trim_mode_t#: firc trim mode.

typedef enum _firc_trim_src firc_trim_src_t#: firc trim source.

typedef struct _firc_trim_config firc_trim_config_t#: firc trim configuration.

typedef enum _sirc_trim_mode sirc_trim_mode_t#: sirc trim mode.

typedef enum _sirc_trim_src sirc_trim_src_t#: sirc trim source.

typedef struct _sirc_trim_config sirc_trim_config_t#: sirc trim configuration.

typedef enum _scg_sosc_monitor_mode scg_sosc_monitor_mode_t#: SCG system OSC monitor mode.

typedef enum _clke_16k clke_16k_t#: firc trim source.

static inline void CLOCK_EnableClock(clock_ip_name_t clk)#

Enable the clock for specific IP.

Parameters:

clk – : Clock to be enabled.

Returns:

Nothing

static inline void CLOCK_DisableClock(clock_ip_name_t clk)#

Disable the clock for specific IP.

Parameters:

clk – : Clock to be Disabled.

Returns:

Nothing

void CLOCK_AttachClk(clock_attach_id_t connection)#

Configure the clock selection muxes.

Parameters:

connection – : Clock to be configured.

Returns:

Nothing

clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection)#

Get the actual clock attach id. This fuction uses the offset in input attach id, then it reads the actual source value in the register and combine the offset to obtain an actual attach id.

Parameters:

connection – : Clock attach id to get.

Returns:

Clock source value.

void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value)#

Set the clock select value. This fuction set the peripheral clock select value.

Parameters:

sel_name – : Clock select.
value – : value to be set.

uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name)#

Get the clock select value. This fuction get the peripheral clock select value.

Parameters:

sel_name – : Clock select.

Returns:

Clock source value.

void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value)#

Setup peripheral clock dividers.

Parameters:

div_name – : Clock divider name
value – : Value to be divided

Returns:

Nothing

uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name)#

Get peripheral clock dividers.

Parameters:

div_name – : Clock divider name

Returns:

peripheral clock dividers

void CLOCK_HaltClockDiv(clock_div_name_t div_name)#

Halt peripheral clock dividers.

Parameters:

div_name – : Clock divider name

Returns:

Nothing

status_t CLOCK_SetupFROHFClocking(uint32_t iFreq)#

Initialize the FROHF to given frequency (48,64,96,192). This function turns on FIRC and select the given frequency as the source of fro_hf.

Parameters:

iFreq – : Desired frequency.

Returns:

returns success or fail status.

status_t CLOCK_SetupFRO12MClocking(void)#

Initialize the FRO12M. This function turns on FRO12M.

Returns:: returns success or fail status.

status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)#

Initialize the FRO16K. This function turns on FRO16K.

Parameters:

clk_16k_enable_mask – 0-3 0b00: disable both clk_16k0 and clk_16k1 0b01: only enable clk_16k0 0b10: only enable clk_16k1 0b11: enable both clk_16k0 and clk_16k1

Returns:

returns success or fail status.

status_t CLOCK_SetupExtClocking(uint32_t iFreq)#

Initialize the external osc clock to given frequency.

Parameters:

iFreq – : Desired frequency (must be equal to exact rate in Hz)

Returns:

returns success or fail status.

status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)#

Initialize the external reference clock to given frequency.

Parameters:

iFreq – : Desired frequency (must be equal to exact rate in Hz)

Returns:

returns success or fail status.

uint32_t CLOCK_GetFreq(clock_name_t clockName)#

Return Frequency of selected clock.

Returns:: Frequency of selected clock

uint32_t CLOCK_GetCoreSysClkFreq(void)#

Return Frequency of core.

Returns:: Frequency of the core

uint32_t CLOCK_GetI3CFClkFreq(void)#

Return Frequency of I3C FCLK.

Returns:: Frequency of I3C FCLK.

uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)#

Return Frequency of CTimer functional Clock.

Returns:: Frequency of CTimer functional Clock

uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id)#

Return Frequency of LPI2C0 functional Clock.

Returns:: Frequency of LPI2C0 functional Clock

uint32_t CLOCK_GetLpspiClkFreq(uint32_t id)#

Return Frequency of LPSPI functional Clock.

Returns:: Frequency of LPSPI functional Clock

uint32_t CLOCK_GetLpuartClkFreq(uint32_t id)#

Return Frequency of LPUART functional Clock.

Returns:: Frequency of LPUART functional Clock

uint32_t CLOCK_GetLptmrClkFreq(void)#

Return Frequency of LPTMR functional Clock.

Returns:: Frequency of LPTMR functional Clock

uint32_t CLOCK_GetOstimerClkFreq(void)#

Return Frequency of OSTIMER.

Returns:: Frequency of OSTIMER Clock

uint32_t CLOCK_GetAdcClkFreq(uint32_t id)#

Return Frequency of Adc Clock.

Returns:: Frequency of Adc.

uint32_t CLOCK_GetDacClkFreq(void)#

Return Frequency of Dac Clock.

Returns:: Frequency of Dac.

uint32_t CLOCK_GetCmpFClkFreq(uint32_t id)#

Return Frequency of CMP Function Clock.

Returns:: Frequency of CMP Function.

uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id)#

Return Frequency of CMP Round Robin Clock.

Returns:: Frequency of CMP Round Robin.

uint32_t CLOCK_GetTraceClkFreq(void)#

Return Frequency of Trace Clock.

Returns:: Frequency of Trace.

uint32_t CLOCK_GetClkoutClkFreq(void)#

Return Frequency of CLKOUT Clock.

Returns:: Frequency of CLKOUT.

uint32_t CLOCK_GetWwdtClkFreq(void)#: brief Return Frequency of WWDT Clock return Frequency of WWDT.

uint32_t CLOCK_GetFlexioClkFreq(void)#

Return Frequency of FLEXIO FCLK.

Returns:: Frequency of FLEXIO FCLK.

uint32_t CLOCK_GetFlexcanClkFreq(void)#

Return Frequency of FlexCAN FCLK.

Returns:: Frequency of FlexCAN FCLK.

status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config)#

Setup FROHF trim.

Parameters:

config – : FROHF trim value

Returns:

returns success or fail status.

status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config)#

Setup FRO 12M trim.

Parameters:

config – : FRO 12M trim value

Returns:

returns success or fail status.

void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode)#

Sets the system OSC monitor mode.

This function sets the system OSC monitor mode. The mode can be disabled, it can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters:

mode – Monitor mode to set.

bool CLOCK_EnableUsbfsClock(void)#: brief Enable USB FS clock. Enable USB Full Speed clock.

FSL_CLOCK_DRIVER_VERSION#: CLOCK driver version 2.0.0.

FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL#

Configure whether driver controls clock.

When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could control the clock out of the driver.

Note

All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY#

CLK_GATE_REG_OFFSET(value)#: Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

CLK_GATE_BIT_SHIFT(value)#

REG_PWM0SUBCTL#

REG_PWM1SUBCTL#

AOI_CLOCKS#: Clock ip name array for AOI.

CRC_CLOCKS#: Clock ip name array for CRC.

CTIMER_CLOCKS#: Clock ip name array for CTIMER.

LPDAC_CLOCKS#: Clock ip name array for DAC.

DMA_CLOCKS#: Clock ip name array for DMA.

EDMA_CLOCKS#: Clock gate name array for EDMA.

ERM_CLOCKS#: Clock ip name array for ERM.

EIM_CLOCKS#: Clock ip name array for EIM.

FLEXCAN_CLOCKS#: Clock ip name array for FLEXCAN.

FLEXIO_CLOCKS#: Clock ip name array for FLEXIO.

FREQME_CLOCKS#: Clock ip name array for FREQME.

GPIO_CLOCKS#: Clock ip name array for GPIO.

I3C_CLOCKS#: Clock ip name array for I3C.

INPUTMUX_CLOCKS#: Clock ip name array for INPUTMUX.

LPCMP_CLOCKS#: Clock ip name array for GPIO.

LPADC_CLOCKS#: Clock ip name array for LPADC.

LPUART_CLOCKS#: Clock ip name array for LPUART.

LPI2C_CLOCKS#: Clock ip name array for LPI2C.

LPSPI_CLOCKS#: Clock ip name array for LSPI.

MTR_CLOCKS#: Clock ip name array for MTR.

OSTIMER_CLOCKS#: Clock ip name array for OSTIMER.

OPAMP_CLOCKS#: Clock ip name array for DAC.

PWM_CLOCKS#: Clock ip name array for PWM.

QDC_CLOCKS#: Clock ip name array for QDC.

UTICK_CLOCKS#: Clock ip name array for UTICK.

WWDT_CLOCKS#: Clock ip name array for WWDT.

BUS_CLK#: Peripherals clock source definition.

CLK_ATTACH_REG_OFFSET(value)#

Clock Mux Switches The encoding is as follows each connection identified is 32bits wide while 24bits are valuable starting from LSB upwards.

[4 bits for choice, 0 means invalid choice] [8 bits mux ID]*

CLK_ATTACH_CLK_SEL(value)#

CLK_ATTACH_MUX(reg, sel)#

firc_trim_mode_t trimMode#: Trim mode.

firc_trim_src_t trimSrc#: Trim source.

uint16_t trimDiv#: Divider of SOSC.

uint8_t trimCoar#: Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate.

uint8_t trimFine#: Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate.

sirc_trim_mode_t trimMode: Trim mode.

sirc_trim_src_t trimSrc: Trim source.

uint16_t trimDiv: Divider of SOSC.

uint8_t cltrim#: Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate.

uint8_t ccotrim#: Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate.

struct _firc_trim_config#: #include <fsl_clock.h>

firc trim configuration.

struct _sirc_trim_config#: #include <fsl_clock.h>

sirc trim configuration.

CRC: Cyclic Redundancy Check Driver#

FSL_CRC_DRIVER_VERSION#

CRC driver version. Version 2.1.0.

Current version: 2.1.0

Change log:

Version 2.1.0
- Choosing CRC clocks from CRC clock array according to instance instead of hardcoded value.
Version 2.0.5
- Fix CERT-C issue with boolean-to-unsigned integer conversion.
Version 2.0.4
- Release peripheral from reset if necessary in init function.
Version 2.0.3
- Fix MISRA issues
Version 2.0.2
- Fix MISRA issues
Version 2.0.1
- move DATA and DATALL macro definition from header file to source file

enum _crc_bits#

CRC bit width.

Values:

enumerator kCrcBits16#: Generate 16-bit CRC code

enumerator kCrcBits32#: Generate 32-bit CRC code

enum _crc_result#

CRC result type.

Values:

enumerator kCrcFinalChecksum#: CRC data register read value is the final checksum. Reflect out and final xor protocol features are applied.

enumerator kCrcIntermediateChecksum#: CRC data register read value is intermediate checksum (raw value). Reflect out and final xor protocol feature are not applied. Intermediate checksum can be used as a seed for CRC_Init() to continue adding data to this checksum.

typedef enum _crc_bits crc_bits_t#: CRC bit width.

typedef enum _crc_result crc_result_t#: CRC result type.

typedef struct _crc_config crc_config_t#

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

void CRC_Init(CRC_Type *base, const crc_config_t *config)#

Enables and configures the CRC peripheral module.

This function enables the clock gate in the SIM module for the CRC peripheral. It also configures the CRC module and starts a checksum computation by writing the seed.

Parameters:

base – CRC peripheral address.
config – CRC module configuration structure.

void CRC_Deinit(CRC_Type *base)#

Disables the CRC peripheral module.

This function disables the clock gate in the SIM module for the CRC peripheral.

Parameters:

base – CRC peripheral address.

void CRC_GetDefaultConfig(crc_config_t *config)#

Loads default values to the CRC protocol configuration structure.

Loads default values to the CRC protocol configuration structure. The default values are as follows.

config->polynomial = 0x1021;
config->seed = 0xFFFF;
config->reflectIn = false;
config->reflectOut = false;
config->complementChecksum = false;
config->crcBits = kCrcBits16;
config->crcResult = kCrcFinalChecksum;

Parameters:

config – CRC protocol configuration structure.

void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)#

Writes data to the CRC module.

Writes input data buffer bytes to the CRC data register. The configured type of transpose is applied.

Parameters:

base – CRC peripheral address.
data – Input data stream, MSByte in data[0].
dataSize – Size in bytes of the input data buffer.

uint32_t CRC_Get32bitResult(CRC_Type *base)#

Reads the 32-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

base – CRC peripheral address.

Returns:

An intermediate or the final 32-bit checksum, after configured transpose and complement operations.

uint16_t CRC_Get16bitResult(CRC_Type *base)#

Reads a 16-bit checksum from the CRC module.

Reads the CRC data register (either an intermediate or the final checksum). The configured type of transpose and complement is applied.

Parameters:

base – CRC peripheral address.

Returns:

An intermediate or the final 16-bit checksum, after configured transpose and complement operations.

CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT#: Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault.

struct _crc_config#

#include <fsl_crc.h>

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

Public Members

uint32_t polynomial#: CRC Polynomial, MSBit first. Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1

uint32_t seed#: Starting checksum value

bool reflectIn#: Reflect bits on input.

bool reflectOut#: Reflect bits on output.

bool complementChecksum#: True if the result shall be complement of the actual checksum.

crc_bits_t crcBits#: Selects 16- or 32- bit CRC protocol.

crc_result_t crcResult#: Selects final or intermediate checksum return from CRC_Get16bitResult() or CRC_Get32bitResult()

CTIMER: Standard counter/timers#

void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)#

Ungates the clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application before using the driver.

Parameters:

base – Ctimer peripheral base address
config – Pointer to the user configuration structure.

void CTIMER_Deinit(CTIMER_Type *base)#

Gates the timer clock.

Parameters:

base – Ctimer peripheral base address

void CTIMER_GetDefaultConfig(ctimer_config_t *config)#

Fills in the timers configuration structure with the default settings.

The default values are:

config->mode = kCTIMER_TimerMode;
config->input = kCTIMER_Capture_0;
config->prescale = 0;

Parameters:

config – Pointer to the user configuration structure.

status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)#

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM period

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
pwmPeriod – PWM period match value
pulsePeriod – Pulse width match value
enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

Returns:

kStatus_Success on success kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle If PWM pulse width register value is larger than 0xFFFFFFFF.

status_t CTIMER_SetupPwm(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool enableInt)#

Configures the PWM signal parameters.

Note

When setting PWM output from multiple output pins, all should use the same PWM frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
dutyCyclePercent – PWM pulse width; the value should be between 0 to 100
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – Timer counter clock in Hz
enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)#

Updates the pulse period of an active PWM signal.

Parameters:

base – Ctimer peripheral base address
matchChannel – Match pin to be used to output the PWM signal
pulsePeriod – New PWM pulse width match value

status_t CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)#

Updates the duty cycle of an active PWM signal.

Note

Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. This function can manually assign the specified channel to set the PWM cycle.

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
dutyCyclePercent – New PWM pulse width; the value should be between 0 to 100

Returns:

kStatus_Success on success kStatus_Fail If PWM pulse width register value is larger than 0xFFFFFFFF.

static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)#

Enables the selected Timer interrupts.

Parameters:

base – Ctimer peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)#

Disables the selected Timer interrupts.

Parameters:

base – Ctimer peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)#

Gets the enabled Timer interrupts.

Parameters:

base – Ctimer peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)#

Gets the Timer status flags.

Parameters:

base – Ctimer peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)#

Clears the Timer status flags.

Parameters:

base – Ctimer peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_StartTimer(CTIMER_Type *base)#

Starts the Timer counter.

Parameters:

base – Ctimer peripheral base address

static inline void CTIMER_StopTimer(CTIMER_Type *base)#

Stops the Timer counter.

Parameters:

base – Ctimer peripheral base address

FSL_CTIMER_DRIVER_VERSION#: Version 2.3.6

enum _ctimer_capture_channel#

List of Timer capture channels.

Values:

enumerator kCTIMER_Capture_0#: Timer capture channel 0

enumerator kCTIMER_Capture_1#: Timer capture channel 1

enumerator kCTIMER_Capture_3#: Timer capture channel 3

enum _ctimer_capture_edge#

List of capture edge options.

Values:

enumerator kCTIMER_Capture_RiseEdge#: Capture on rising edge

enumerator kCTIMER_Capture_FallEdge#: Capture on falling edge

enumerator kCTIMER_Capture_BothEdge#: Capture on rising and falling edge

enum _ctimer_match#

List of Timer match registers.

Values:

enumerator kCTIMER_Match_0#: Timer match register 0

enumerator kCTIMER_Match_1#: Timer match register 1

enumerator kCTIMER_Match_2#: Timer match register 2

enumerator kCTIMER_Match_3#: Timer match register 3

enum _ctimer_external_match#

List of external match.

Values:

enumerator kCTIMER_External_Match_0#: External match 0

enumerator kCTIMER_External_Match_1#: External match 1

enumerator kCTIMER_External_Match_2#: External match 2

enumerator kCTIMER_External_Match_3#: External match 3

enum _ctimer_match_output_control#

List of output control options.

Values:

enumerator kCTIMER_Output_NoAction#: No action is taken

enumerator kCTIMER_Output_Clear#: Clear the EM bit/output to 0

enumerator kCTIMER_Output_Set#: Set the EM bit/output to 1

enumerator kCTIMER_Output_Toggle#: Toggle the EM bit/output

enum _ctimer_timer_mode#

List of Timer modes.

Values:

enumerator kCTIMER_TimerMode#

enumerator kCTIMER_IncreaseOnRiseEdge#

enumerator kCTIMER_IncreaseOnFallEdge#

enumerator kCTIMER_IncreaseOnBothEdge#

enum _ctimer_interrupt_enable#

List of Timer interrupts.

Values:

enumerator kCTIMER_Match0InterruptEnable#: Match 0 interrupt

enumerator kCTIMER_Match1InterruptEnable#: Match 1 interrupt

enumerator kCTIMER_Match2InterruptEnable#: Match 2 interrupt

enumerator kCTIMER_Match3InterruptEnable#: Match 3 interrupt

enum _ctimer_status_flags#

List of Timer flags.

Values:

enumerator kCTIMER_Match0Flag#: Match 0 interrupt flag

enumerator kCTIMER_Match1Flag#: Match 1 interrupt flag

enumerator kCTIMER_Match2Flag#: Match 2 interrupt flag

enumerator kCTIMER_Match3Flag#: Match 3 interrupt flag

enum ctimer_callback_type_t#

Callback type when registering for a callback. When registering a callback an array of function pointers is passed the size could be 1 or 8, the callback type will tell that.

Values:

enumerator kCTIMER_SingleCallback#: Single Callback type where there is only one callback for the timer. based on the status flags different channels needs to be handled differently

enumerator kCTIMER_MultipleCallback#: Multiple Callback type where there can be 8 valid callbacks, one per channel. for both match/capture

typedef enum _ctimer_capture_channel ctimer_capture_channel_t#: List of Timer capture channels.

typedef enum _ctimer_capture_edge ctimer_capture_edge_t#: List of capture edge options.

typedef enum _ctimer_match ctimer_match_t#: List of Timer match registers.

typedef enum _ctimer_external_match ctimer_external_match_t#: List of external match.

typedef enum _ctimer_match_output_control ctimer_match_output_control_t#: List of output control options.

typedef enum _ctimer_timer_mode ctimer_timer_mode_t#: List of Timer modes.

typedef enum _ctimer_interrupt_enable ctimer_interrupt_enable_t#: List of Timer interrupts.

typedef enum _ctimer_status_flags ctimer_status_flags_t#: List of Timer flags.

typedef void (*ctimer_callback_t)(uint32_t flags)#

typedef struct _ctimer_match_config ctimer_match_config_t#

Match configuration.

This structure holds the configuration settings for each match register.

typedef struct _ctimer_config ctimer_config_t#

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)#

Setup the match register.

User configuration is used to setup the match value and action to be taken when a match occurs.

Parameters:

base – Ctimer peripheral base address
matchChannel – Match register to configure
config – Pointer to the match configuration structure

uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel)#

Get the status of output match.

This function gets the status of output MAT, whether or not this output is connected to a pin. This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

Parameters:

base – Ctimer peripheral base address
matchChannel – External match channel, user can obtain the status of multiple match channels at the same time by using the logic of “|” enumeration ctimer_external_match_t

Returns:

The mask of external match channel status flags. Users need to use the _ctimer_external_match type to decode the return variables.

void CTIMER_SetupCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, ctimer_capture_edge_t edge, bool enableInt)#

Setup the capture.

Parameters:

base – Ctimer peripheral base address
capture – Capture channel to configure
edge – Edge on the channel that will trigger a capture
enableInt – Flag to enable channel interrupts, if enabled then the registered call back is called upon capture

static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)#

Get the timer count value from TC register.

Parameters:

base – Ctimer peripheral base address.

Returns:

return the timer count value.

void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)#

This function configures CTimer Callback in following modes:

Single Callback: cb_func should be pointer to callback function pointer For example: ctimer_callback_t ctimer_callback = pwm_match_callback; CTIMER_RegisterCallBack(CTIMER, &ctimer_callback, kCTIMER_SingleCallback);
Multiple Callback: cb_func should be pointer to array of callback function pointers Each element corresponds to Interrupt Flag in IR register. For example: ctimer_callback_t ctimer_callback_table[] = { ctimer_match0_callback, NULL, NULL, ctimer_match3_callback, NULL, NULL, NULL, NULL}; CTIMER_RegisterCallBack(CTIMER, &ctimer_callback_table[0], kCTIMER_MultipleCallback);

Parameters:

base – Ctimer peripheral base address
cb_func – Pointer to callback function pointer
cb_type – callback function type, singular or multiple

static inline void CTIMER_Reset(CTIMER_Type *base)#

Reset the counter.

The timer counter and prescale counter are reset on the next positive edge of the APB clock.

Parameters:

base – Ctimer peripheral base address

static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale)#

Setup the timer prescale value.

Specifies the maximum value for the Prescale Counter.

Parameters:

base – Ctimer peripheral base address
prescale – Prescale value

static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture)#

Get capture channel value.

Get the counter/timer value on the corresponding capture channel.

Parameters:

base – Ctimer peripheral base address
capture – Select capture channel

Returns:

The timer count capture value.

static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)#

Enable reset match channel.

Set the specified match channel reset operation.

Parameters:

base – Ctimer peripheral base address
match – match channel used
enable – Enable match channel reset operation.

static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)#

Enable stop match channel.

Set the specified match channel stop operation.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
enable – Enable match channel stop operation.

static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable)#

Enable reload channel falling edge.

Enable the specified match channel reload match shadow value.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
enable – Enable .

static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)#

Enable capture channel rising edge.

Sets the specified capture channel for rising edge capture.

Parameters:

base – Ctimer peripheral base address.
capture – capture channel used.
enable – Enable rising edge capture.

static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)#

Enable capture channel falling edge.

Sets the specified capture channel for falling edge capture.

Parameters:

base – Ctimer peripheral base address.
capture – capture channel used.
enable – Enable falling edge capture.

static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue)#

Set the specified match shadow channel.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
matchvalue – Reload the value of the corresponding match register.

struct _ctimer_match_config#

#include <fsl_ctimer.h>

Match configuration.

This structure holds the configuration settings for each match register.

Public Members

uint32_t matchValue#: This is stored in the match register

bool enableCounterReset#: true: Match will reset the counter false: Match will not reser the counter

bool enableCounterStop#: true: Match will stop the counter false: Match will not stop the counter

ctimer_match_output_control_t outControl#: Action to be taken on a match on the EM bit/output

bool outPinInitState#: Initial value of the EM bit/output

bool enableInterrupt#: true: Generate interrupt upon match false: Do not generate interrupt on match

struct _ctimer_config#

#include <fsl_ctimer.h>

Timer configuration structure.

The configuration structure can be made constant so as to reside in flash.

Public Members

ctimer_timer_mode_t mode#: Timer mode

ctimer_capture_channel_t input#: Input channel to increment the timer, used only in timer modes that rely on this input signal to increment TC

uint32_t prescale#: Prescale value

DAC: Digital-to-Analog Converter Driver#

void DAC_Init(LPDAC_Type *base, const dac_config_t *config)#

Initialize the DAC module with common configuartion.

The clock will be enabled in this function.

Parameters:

base – DAC peripheral base address.
config – Pointer to configuration structure.

void DAC_GetDefaultConfig(dac_config_t *config)#

Get the default settings for initialization’s configuration.

This function initializes the user configuration structure to a default value. The default values are:

config->fifoWatermarkLevel = 0U;
config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode;
config->fifoWorkMode = kDAC_FIFODisabled;
config->enableLowPowerMode = false;
config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1;

Parameters:

config – Pointer to configuration structure.

void DAC_Deinit(LPDAC_Type *base)#

De-initialize the DAC module.

The clock will be disabled in this function.

Parameters:

base – DAC peripheral base address.

static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask)#

Assert the reset control to part hardware.

This function is to assert the reset control to part hardware. Responding part hardware would remain reset untill cleared by software.

Parameters:

base – DAC peripheral base address.
mask – The reset control mask, see to _dac_reset_control_t.

static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask)#

Clear the reset control to part hardware.

This function is to clear the reset control to part hardware. Responding part hardware would work after the reset control is cleared by software.

Parameters:

base – DAC peripheral base address.
mask – The reset control mask, see to _dac_reset_control_t.

static inline void DAC_Enable(LPDAC_Type *base, bool enable)#

Enable the DAC hardware system or not.

This function is to start the Programmable Reference Generator operation or not.

Parameters:

base – DAC peripheral base address.
enable – Assertion of indicated event.

static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask)#

Enable the interrupts.

Parameters:

base – DAC peripheral base address.
mask – Mask value of indicated interrupt events. See to _dac_interrupt_enable.

static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask)#

Disable the interrupts.

Parameters:

base – DAC peripheral base address.
mask – Mask value of indicated interrupt events. See to _dac_interrupt_enable.

static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable)#

Enable the DMA switchers or not.

Parameters:

base – DAC peripheral base address.
mask – Mask value of indicated DMA requeset. See to _dac_dma_enable.
enable – Enable the DMA or not.

static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base)#

Get status flags of DAC module.

Parameters:

base – DAC peripheral base address.

Returns:

Mask value of status flags. See to _dac_status_flags.

static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags)#

Clear status flags of DAC module.

Parameters:

base – DAC peripheral base address.
flags – Mask value of status flags to be cleared. See to _dac_status_flags.

static inline void DAC_SetData(LPDAC_Type *base, uint32_t value)#

Set data into the entry of FIFO buffer.

Parameters:

base – DAC peripheral base address.
value – Setting value into FIFO buffer.

static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base)#

Get the value of the FIFO write pointer.

Parameters:

base – DAC peripheral base address.

Returns:

Current value of the FIFO write pointer.

static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base)#

Get the value of the FIFO read pointer.

Parameters:

base – DAC peripheral base address.

Returns:

Current value of the FIFO read pointer.

static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)#

Do software trigger to FIFO when in software mode.

Parameters:

base – DAC peripheral base address.

FSL_DAC_DRIVER_VERSION#: DAC driver version 2.2.0.

DAC reset control.

Values:

enumerator kDAC_ResetFIFO#: Resets the FIFO pointers and flags.

enumerator kDAC_ResetLogic#: Resets all DAC registers and internal logic.

DAC interrupts.

Values:

enumerator kDAC_FIFOFullInterruptEnable#: FIFO full interrupt enable.

enumerator kDAC_FIFOEmptyInterruptEnable#: FIFO empty interrupt enable.

enumerator kDAC_FIFOWatermarkInterruptEnable#: FIFO watermark interrupt enable.

enumerator kDAC_SwingBackInterruptEnable#: Swing back one cycle complete interrupt enable.

enumerator kDAC_FIFOOverflowInterruptEnable#: FIFO overflow interrupt enable.

enumerator kDAC_FIFOUnderflowInterruptEnable#: FIFO underflow interrupt enable.

enumerator kDAC_PeriodTriggerCompleteInterruptEnable#: Period trigger mode conversion complete interrupt enable

DAC DMA switchers.

Values:

enumerator kDAC_FIFOEmptyDMAEnable#: FIFO empty DMA enable.

enumerator kDAC_FIFOWatermarkDMAEnable#: FIFO watermark DMA enable.

DAC status flags.

Values:

enumerator kDAC_FIFOUnderflowFlag#: This flag means that there is a new trigger after the buffer is empty. The FIFO read pointer will not increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1 to it.

enumerator kDAC_FIFOOverflowFlag#: This flag indicates that data is intended to write into FIFO after the buffer is full. The writer pointer will not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it.

enumerator kDAC_FIFOSwingBackFlag#: This flag indicates that the DAC has completed one period of conversion in swing back mode. It means that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is cleared by writing a 1 to it.

enumerator kDAC_FIFOWatermarkFlag#: This field is set if the remaining data in FIFO is less than or equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is cleared automatically when the data in FIFO is more than the setting value of watermark.

enumerator kDAC_FIFOEmptyFlag#: FIFO empty flag.

enumerator kDAC_FIFOFullFlag#: FIFO full flag.

enumerator kDAC_PeriodTriggerCompleteFlag#: Period trigger mode conversion complete flag.

enum _dac_fifo_trigger_mode#

DAC FIFO trigger mode.

Values:

enumerator kDAC_FIFOTriggerByHardwareMode#: Buffer would be triggered by hardware.

enumerator kDAC_FIFOTriggerBySoftwareMode#: Buffer would be triggered by software.

enum _dac_fifo_work_mode#

DAC FIFO work mode.

Values:

enumerator kDAC_FIFODisabled#: FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion.

enumerator kDAC_FIFOWorkAsNormalMode#: FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion.

enumerator kDAC_FIFOWorkAsSwingMode#: In swing mode, the read pointer swings between the writer pointer and zero. That is, the trigger increases the read pointer till reach the writer pointer and decreases the read pointer till zero, and so on. The FIFO empty/full/watermark flag will not update during swing back mode.

enumerator kDAC_FIFOWorkAsPeriodTriggerMode#: In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1] RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero, there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST.

enumerator kDAC_FIFOWorkAsPeriodTriggerAndSwingMode#: Periodically trigger DAC and swing back.

enum _dac_reference_voltage_source#

DAC reference voltage source.

Values:

enumerator kDAC_ReferenceVoltageSourceAlt1#: The DAC selects VREFH_INT as the reference voltage.

enumerator kDAC_ReferenceVoltageSourceAlt2#: The DAC selects VREFH_EXT as the reference voltage.

enum _dac_reference_current_source#

Values:

enumerator kDAC_ReferenceCurrentSourcePtat#

enumerator kDAC_ReferenceCurrentSourceInternal#

enumerator kDAC_ReferenceCurrentSourceZtc#

enum _dac_reference_current_trim#

Values:

enumerator kDAC_ReferenceCurrentTrimMinus25Percent#: Internal current value -25%.

enumerator kDAC_ReferenceCurrentTrimMinus125Percent#: Internal current value -12.5%.

enumerator kDAC_ReferenceCurrentTrimTypical#: Typical internal current value.

enumerator kDAC_ReferenceCurrentTrimPlus125Percent#: Internal current value +12.5%.

enumerator kDAC_ReferenceCurrentTrimPlus25Percent#: Internal current value +25%.

typedef enum _dac_fifo_trigger_mode dac_fifo_trigger_mode_t#: DAC FIFO trigger mode.

typedef enum _dac_fifo_work_mode dac_fifo_work_mode_t#: DAC FIFO work mode.

typedef enum _dac_reference_voltage_source dac_reference_voltage_source_t#: DAC reference voltage source.

typedef enum _dac_reference_current_source dac_reference_current_source_t#

typedef enum _dac_reference_current_trim dac_reference_current_trim_t#

typedef struct _dac_config dac_config_t#: DAC configuration structure.

struct _dac_config#

#include <fsl_dac.h>

DAC configuration structure.

Public Members

uint32_t fifoWatermarkLevel#: FIFO’s watermark, the max value can be the hardware FIFO size.

dac_fifo_trigger_mode_t fifoTriggerMode#: Select the trigger mode for FIFO.

dac_fifo_work_mode_t fifoWorkMode#: Select the work mode for FIFO.

bool enableOpampBuffer#: Opamp is used as buffer.

bool enableAnalogOutputBufferBypass#: Bypass the DAC analog output buffer.

bool enableLowerLowPowerMode#: Enable the lower low power mode.

uint32_t periodicTriggerNumber#: There will be ‘periodicTriggerNumber’ internal triggers following the first hardware/software trigger. So there will be ‘periodicTriggerNumber + 1’ conversions in total. If set to zero, there will be infinite triggers following the first hw/sw trigger, until the GCR[PTGEN] is cleared.

uint32_t periodicTriggerWidth#: Control the periodic trigger frequency. There will be ‘periodicTriggerWidth + 1’ RCLK cycles between each periodic trigger. The periodic trigger frequency should be configured to not larger than the analog conversion speed.

uint32_t syncTime#: RCLK cycles before data latch. accessible range is 0-15. It is used to configure the DAC sync cycles which is helpful to reduce glitch on the output. The sync time is (LATCH_CYC+1) RCLK cycles. User should configure this register according to the RCLK frequency. The recommended sync time is at least 40ns.

dac_reference_current_source_t referenceCurrentSource#: Select the internal reference current source.

dac_reference_current_trim_t referenceCurrentTrim#: Select the internal reference current trim.

dac_reference_voltage_source_t referenceVoltageSource#: Select the reference voltage source.

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

void EDMA_Init(EDMA_Type *base, const edma_config_t *config)#

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure. All emda enabled request will be cleared in this function.

Note

This function enables the minor loop map feature.

Parameters:

base – eDMA peripheral base address.
config – A pointer to the configuration structure, see “edma_config_t”.

void EDMA_Deinit(EDMA_Type *base)#

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters:

base – eDMA peripheral base address.

void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd)#

Push content of TCD structure into hardware TCD register.

Parameters:

base – EDMA peripheral base address.
channel – EDMA channel number.
tcd – Point to TCD structure.

void EDMA_GetDefaultConfig(edma_config_t *config)#

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;

Parameters:

config – A pointer to the eDMA configuration structure.

void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig)#

EDMA Channel initialization.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelConfig – pointer to user’s eDMA4 channel config structure, see edma_channel_config_t for detail.

static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, uint32_t channel, edma_channel_memory_attribute_t writeAttribute, edma_channel_memory_attribute_t readAttribute)#

Set channel memory attribute.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
writeAttribute – Attributes associated with a write transaction.
readAttribute – Attributes associated with a read transaction.

static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position)#

Set channel sign extension.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
position – A non-zero value specifing the sign extend bit position. If 0, sign extension is disabled.

static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize)#

Set channel swap size.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
swapSize – Swap occurs with respect to the specified transfer size. If 0, swap is disabled.

static inline void EDMA_SetChannelAccessType(EDMA_Type *base, uint32_t channel, edma_channel_access_type_t channelAccessType)#

Set channel access type.

Parameters:

base – eDMA4 peripheral base address.
channel – eDMA4 channel number.
channelAccessType – eDMA4’s transactions type on the system bus when the channel is active.

static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, uint32_t channelRequestSource)#

Set channel request source.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
channelRequestSource – eDMA hardware service request source for the channel. User need to use the dma_request_source_t type as the input parameter. Note that devices may use other enum type to express dma request source and User can fined it in SOC header or fsl_edma_soc.h.

static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel)#

Gets the channel identification and attribute information on the system bus interface.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of the channel system bus information. Users need to use the _edma_channel_sys_bus_info type to decode the return variables.

static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable)#

Set channel master ID replication.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – true is enable, false is disable.

static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, uint32_t channel, edma_channel_protection_level_t level)#

Set channel security level.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
level – security level.

void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel)#

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Note

This function must not be called while the channel transfer is ongoing or it causes unpredictable results.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

void EDMA_SetTransferConfig(EDMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)#

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
edma_tcd_t tcd;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);

Note

If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)#

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
config – A pointer to the minor offset configuration structure.

void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)#

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number
config – A pointer to the channel preemption configuration structure.

void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)#

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
type – A channel link type, which can be one of the following:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)#

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)#

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable)#

Enables an async request for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable)#

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
enable – The command to enable (true) or disable (false).

void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)#

Enables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask)#

Disables the interrupt source for the eDMA transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset)#

Configures the eDMA channel TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
channel – edma channel number.
sourceOffset – source address offset will be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer)#

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_ConfigChannelSoftwareTCDExt

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdReset(edma_tcd_t *tcd)#

Sets all fields to default values for the TCD structure.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdResetExt

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)#

Configures the eDMA TCD transfer attribute.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetTransferConfigExt

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The TCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)#

Configures the eDMA TCD minor offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMinorOffsetConfigExt

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)#

Sets the channel link for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetChannelLinkExt

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)#

Sets the bandwidth for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetBandWidthExt

Parameters:

tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)#

Sets the source modulo and the destination modulo for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetModuloExt

Parameters:

tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)#

Sets the auto stop request for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableAutoStopRequestExt

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)#

Enables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdEnableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)#

Disables the interrupt source for the eDMA TCD.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdDisableInterruptsExt

Parameters:

tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)#

Configures the eDMA TCD major offset feature.

@Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API EDMA_TcdSetMajorOffsetConfigExt

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer)#

Sets TCD fields according to the user’s channel transfer configuration structure, edma_transfer_config_t.

Application should be careful about the TCD pool buffer storage class,

For the platform has cache, the software TCD should be put in non cache section
The TCD pool buffer should have a consistent storage class.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
transfer – channel transfer configuration pointer.

void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd)#

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Note

This function enables the auto stop request feature.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)#

Configures the eDMA TCD transfer attribute.

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);

Note

TCD address should be 32 bytes aligned or it causes an eDMA error.

Note

If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.
config – Pointer to eDMA transfer configuration structure.
nextTcd – Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.

void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config)#

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
config – A pointer to the minor offset configuration structure.

void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)#

Sets the channel link for the eDMA TCD.

Note

Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
type – Channel link type, it can be one of:
- kEDMA_LinkNone
- kEDMA_MinorLink
- kEDMA_MajorLink
linkedChannel – The linked channel number.

static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)#

Sets the bandwidth for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
bandWidth – A bandwidth setting, which can be one of the following:
- kEDMABandwidthStallNone
- kEDMABandwidthStall4Cycle
- kEDMABandwidthStall8Cycle

void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)#

Sets the source modulo and the destination modulo for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
srcModulo – A source modulo value.
destModulo – A destination modulo value.

static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)#

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
tcd – A pointer to the TCD structure.
enable – The command to enable (true) or disable (false).

void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)#

Enables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask)#

Disables the interrupt source for the eDMA TCD.

Parameters:

base – eDMA peripheral base address.
tcd – Point to the TCD structure.
mask – The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset)#

Configures the eDMA TCD major offset feature.

Adjustment value added to the source address at the completion of the major iteration count

Parameters:

base – eDMA peripheral base address.
tcd – A point to the TCD structure.
sourceOffset – source address offset wiil be applied to source address after major loop done.
destOffset – destination address offset will be applied to source address after major loop done.

static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel)#

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel)#

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)#

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel)#

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Note

1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

Major loop count which has not been transferred yet for the current TCD.

static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base)#

Gets the eDMA channel error status flags.

Parameters:

base – eDMA peripheral base address.

Returns:

The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel)#

Gets the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.

Returns:

The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask)#

Clears the eDMA channel status flags.

Parameters:

base – eDMA peripheral base address.
channel – eDMA channel number.
mask – The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

status_t EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel)#

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters:

handle – eDMA handle pointer. The eDMA handle stores callback function and parameters.
base – eDMA peripheral base address.
channel – eDMA channel number.

Return values:

kStatus_Success –
kStatus_InvalidArgument –

void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)#

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters:

handle – eDMA handle pointer.
tcdPool – A memory pool to store TCDs. It must be 32 bytes aligned.
tcdSize – The number of TCD slots.

void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)#

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters:

handle – eDMA handle pointer.
callback – eDMA callback function pointer.
userData – A parameter for the callback function.

void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes)#

Prepares the eDMA transfer structure configurations.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE). User can check if 128 bytes support is available for specific instance by FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.

void EDMA_PrepareTransfer(edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)#

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

config – The user configuration structure of type edma_transfer_t.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
type – eDMA transfer type.

void EDMA_PrepareTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd, void *srcAddr, uint32_t srcWidth, int16_t srcOffset, void *destAddr, uint32_t destWidth, int16_t destOffset, uint32_t bytesEachRequest, uint32_t transferBytes, edma_tcd_t *nextTcd)#

Prepares the eDMA transfer content descriptor.

This function prepares the transfer content descriptor structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.
srcAddr – eDMA transfer source address.
srcWidth – eDMA transfer source address width(bytes).
srcOffset – source address offset.
destAddr – eDMA transfer destination address.
destWidth – eDMA transfer destination address width(bytes).
destOffset – destination address offset.
bytesEachRequest – eDMA transfer bytes per channel request.
transferBytes – eDMA transfer bytes to be transferred.
nextTcd – eDMA transfer linked TCD address.

status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd)#

Submits the eDMA transfer content descriptor.

This function submits the eDMA transfer request according to the transfer content descriptor. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Typical user case:

submit single transfer

edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit static link transfer,

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ....)
EDMA_PrepareTransferTCD(handle, &tcd[1], ....)
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

submit dynamic link transfer

edma_tcd_t tcdpool[2];
EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2);
edma_tcd_t tcd;
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_PrepareTransferTCD(handle, tcd, ....)
EDMA_SubmitTransferTCD(handle, tcd)
EDMA_StartTransfer(handle)

submit loop transfer

edma_tcd_t tcd[2];
EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1])
EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0])
EDMA_SubmitTransferTCD(handle, &tcd[0])
EDMA_StartTransfer(handle)

Parameters:

handle – eDMA handle pointer.
tcd – Pointer to eDMA transfer content descriptor structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)#

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters:

handle – eDMA handle pointer.
config – Pointer to eDMA transfer configuration structure.

Return values:

kStatus_EDMA_Success – It means submit transfer request succeed.
kStatus_EDMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_Busy – It means the given channel is busy, need to submit request later.

status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount)#

Submits the eDMA scatter gather transfer configurations.

The function is target for submit loop transfer request, the ring transfer request means that the transfer request TAIL is link to HEAD, such as, A->B->C->D->A, or A->A

To use the ring transfer feature, the application should allocate several transfer object, such as

edma_channel_transfer_config_t transfer[2];
EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U);

Then eDMA driver will link transfer[0] and transfer[1] to each other

Note

Application should check the return value of this function to avoid transfer request submit failed

Parameters:

handle – eDMA handle pointer
transfer – pointer to user’s eDMA channel configure structure, see edma_channel_transfer_config_t for detail
transferLoopCount – the count of the transfer ring, if loop count is 1, that means that the one will link to itself.

Return values:

kStatus_Success – It means submit transfer request succeed
kStatus_EDMA_Busy – channel is in busy status
kStatus_InvalidArgument – Invalid Argument

void EDMA_StartTransfer(edma_handle_t *handle)#

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters:

handle – eDMA handle pointer.

void EDMA_StopTransfer(edma_handle_t *handle)#

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters:

handle – eDMA handle pointer.

void EDMA_AbortTransfer(edma_handle_t *handle)#

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters:

handle – DMA handle pointer.

static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)#

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The unused tcd slot number.

static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)#

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters:

handle – DMA handle pointer.

Returns:

The next TCD address.

void EDMA_HandleIRQ(edma_handle_t *handle)#

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the “tcdUsed” updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the “eDMA basic data flow” in the eDMA Functional description section of the Reference Manual for further details.

Parameters:

handle – eDMA handle pointer.

void EDMA_TcdInit(EDMA_Type *base, edma_tcd_t *tcdRegs)#

Initialize all fields to 0 for the TCD structure.

This function initialize all fields for this TCD structure to 0.

Parameters:

base – eDMA peripheral base address.
tcd – Pointer to the TCD structure.

FSL_EDMA_DRIVER_VERSION#

eDMA driver version

Version 2.10.14.

_edma_transfer_status eDMA transfer status

Values:

enumerator kStatus_EDMA_QueueFull#: TCD queue is full.

enumerator kStatus_EDMA_Busy#: Channel is busy and can’t handle the transfer request.

enum _edma_transfer_size#

eDMA transfer configuration

Values:

enumerator kEDMA_TransferSize1Bytes#: Source/Destination data transfer size is 1 byte every time

enumerator kEDMA_TransferSize2Bytes#: Source/Destination data transfer size is 2 bytes every time

enumerator kEDMA_TransferSize4Bytes#: Source/Destination data transfer size is 4 bytes every time

enumerator kEDMA_TransferSize8Bytes#: Source/Destination data transfer size is 8 bytes every time

enumerator kEDMA_TransferSize16Bytes#: Source/Destination data transfer size is 16 bytes every time

enumerator kEDMA_TransferSize32Bytes#: Source/Destination data transfer size is 32 bytes every time

enumerator kEDMA_TransferSize64Bytes#: Source/Destination data transfer size is 64 bytes every time

enumerator kEDMA_TransferSize128Bytes#: Source/Destination data transfer size is 128 bytes every time

enum _edma_modulo#

eDMA modulo configuration

Values:

enumerator kEDMA_ModuloDisable#: Disable modulo

enumerator kEDMA_Modulo2bytes#: Circular buffer size is 2 bytes.

enumerator kEDMA_Modulo4bytes#: Circular buffer size is 4 bytes.

enumerator kEDMA_Modulo8bytes#: Circular buffer size is 8 bytes.

enumerator kEDMA_Modulo16bytes#: Circular buffer size is 16 bytes.

enumerator kEDMA_Modulo32bytes#: Circular buffer size is 32 bytes.

enumerator kEDMA_Modulo64bytes#: Circular buffer size is 64 bytes.

enumerator kEDMA_Modulo128bytes#: Circular buffer size is 128 bytes.

enumerator kEDMA_Modulo256bytes#: Circular buffer size is 256 bytes.

enumerator kEDMA_Modulo512bytes#: Circular buffer size is 512 bytes.

enumerator kEDMA_Modulo1Kbytes#: Circular buffer size is 1 K bytes.

enumerator kEDMA_Modulo2Kbytes#: Circular buffer size is 2 K bytes.

enumerator kEDMA_Modulo4Kbytes#: Circular buffer size is 4 K bytes.

enumerator kEDMA_Modulo8Kbytes#: Circular buffer size is 8 K bytes.

enumerator kEDMA_Modulo16Kbytes#: Circular buffer size is 16 K bytes.

enumerator kEDMA_Modulo32Kbytes#: Circular buffer size is 32 K bytes.

enumerator kEDMA_Modulo64Kbytes#: Circular buffer size is 64 K bytes.

enumerator kEDMA_Modulo128Kbytes#: Circular buffer size is 128 K bytes.

enumerator kEDMA_Modulo256Kbytes#: Circular buffer size is 256 K bytes.

enumerator kEDMA_Modulo512Kbytes#: Circular buffer size is 512 K bytes.

enumerator kEDMA_Modulo1Mbytes#: Circular buffer size is 1 M bytes.

enumerator kEDMA_Modulo2Mbytes#: Circular buffer size is 2 M bytes.

enumerator kEDMA_Modulo4Mbytes#: Circular buffer size is 4 M bytes.

enumerator kEDMA_Modulo8Mbytes#: Circular buffer size is 8 M bytes.

enumerator kEDMA_Modulo16Mbytes#: Circular buffer size is 16 M bytes.

enumerator kEDMA_Modulo32Mbytes#: Circular buffer size is 32 M bytes.

enumerator kEDMA_Modulo64Mbytes#: Circular buffer size is 64 M bytes.

enumerator kEDMA_Modulo128Mbytes#: Circular buffer size is 128 M bytes.

enumerator kEDMA_Modulo256Mbytes#: Circular buffer size is 256 M bytes.

enumerator kEDMA_Modulo512Mbytes#: Circular buffer size is 512 M bytes.

enumerator kEDMA_Modulo1Gbytes#: Circular buffer size is 1 G bytes.

enumerator kEDMA_Modulo2Gbytes#: Circular buffer size is 2 G bytes.

enum _edma_bandwidth#

Bandwidth control.

Values:

enumerator kEDMA_BandwidthStallNone#: No eDMA engine stalls.

enumerator kEDMA_BandwidthStall4Cycle#: eDMA engine stalls for 4 cycles after each read/write.

enumerator kEDMA_BandwidthStall8Cycle#: eDMA engine stalls for 8 cycles after each read/write.

enum _edma_channel_link_type#

Channel link type.

Values:

enumerator kEDMA_LinkNone#: No channel link

enumerator kEDMA_MinorLink#: Channel link after each minor loop

enumerator kEDMA_MajorLink#: Channel link while major loop count exhausted

_edma_channel_status_flags eDMA channel status flags.

Values:

enumerator kEDMA_DoneFlag#: DONE flag, set while transfer finished, CITER value exhausted

enumerator kEDMA_ErrorFlag#: eDMA error flag, an error occurred in a transfer

enumerator kEDMA_InterruptFlag#: eDMA interrupt flag, set while an interrupt occurred of this channel

_edma_error_status_flags eDMA channel error status flags.

Values:

enumerator kEDMA_DestinationBusErrorFlag#: Bus error on destination address

enumerator kEDMA_SourceBusErrorFlag#: Bus error on the source address

enumerator kEDMA_ScatterGatherErrorFlag#: Error on the Scatter/Gather address, not 32byte aligned.

enumerator kEDMA_NbytesErrorFlag#: NBYTES/CITER configuration error

enumerator kEDMA_DestinationOffsetErrorFlag#: Destination offset not aligned with destination size

enumerator kEDMA_DestinationAddressErrorFlag#: Destination address not aligned with destination size

enumerator kEDMA_SourceOffsetErrorFlag#: Source offset not aligned with source size

enumerator kEDMA_SourceAddressErrorFlag#: Source address not aligned with source size

enumerator kEDMA_ErrorChannelFlag#: Error channel number of the cancelled channel number

enumerator kEDMA_TransferCanceledFlag#: Transfer cancelled

enumerator kEDMA_ValidFlag#: No error occurred, this bit is 0. Otherwise, it is 1.

_edma_interrupt_enable eDMA interrupt source

Values:

enumerator kEDMA_ErrorInterruptEnable#: Enable interrupt while channel error occurs.

enumerator kEDMA_MajorInterruptEnable#: Enable interrupt while major count exhausted.

enumerator kEDMA_HalfInterruptEnable#: Enable interrupt while major count to half value.

enum _edma_transfer_type#

eDMA transfer type

Values:

enumerator kEDMA_MemoryToMemory#: Transfer from memory to memory

enumerator kEDMA_PeripheralToMemory#: Transfer from peripheral to memory

enumerator kEDMA_MemoryToPeripheral#: Transfer from memory to peripheral

enumerator kEDMA_PeripheralToPeripheral#: Transfer from Peripheral to peripheral

enum edma_channel_memory_attribute#

eDMA channel memory attribute

Values:

enumerator kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer#: No write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadNoCacheBufferable#: No write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableNoBuffer#: No write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteNoReadCacheableBufferable#: No write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheNoBuffer#: No write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadNoCacheBufferable#: No write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableNoBuffer#: No write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelNoWriteReadCacheableBufferable#: No write allocate, read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheNoBuffer#: write allocate, no read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadNoCacheBufferable#: write allocate, no read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableNoBuffer#: write allocate, no read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteNoReadCacheableBufferable#: write allocate, no read allocate, cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheNoBuffer#: write allocate, read allocate, non-cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadNoCacheBufferable#: write allocate, read allocate, non-cacheable, bufferable.

enumerator kEDMA_ChannelWriteReadCacheableNoBuffer#: write allocate, read allocate, cacheable, non-bufferable.

enumerator kEDMA_ChannelWriteReadCacheableBufferable#: write allocate, read allocate, cacheable, bufferable.

enum _edma_channel_swap_size#

eDMA4 channel swap size

Values:

enumerator kEDMA_ChannelSwapDisabled#: Swap is disabled.

enumerator kEDMA_ChannelReadWith8bitSwap#: Swap occurs with respect to the read 8bit.

enumerator kEDMA_ChannelReadWith16bitSwap#: Swap occurs with respect to the read 16bit.

enumerator kEDMA_ChannelReadWith32bitSwap#: Swap occurs with respect to the read 32bit.

enumerator kEDMA_ChannelWriteWith8bitSwap#: Swap occurs with respect to the write 8bit.

enumerator kEDMA_ChannelWriteWith16bitSwap#: Swap occurs with respect to the write 16bit.

enumerator kEDMA_ChannelWriteWith32bitSwap#: Swap occurs with respect to the write 32bit.

eDMA channel system bus information, _edma_channel_sys_bus_info

Values:

enumerator kEDMA_PrivilegedAccessLevel#: Privileged Access Level for DMA transfers. 0b - User protection level; 1b - Privileged protection level.

enumerator kEDMA_MasterId#: DMA’s master ID when channel is active and master ID replication is enabled.

enum _edma_channel_access_type#

eDMA4 channel access type

Values:

enumerator kEDMA_ChannelDataAccess#: Data access for eDMA4 transfers.

enumerator kEDMA_ChannelInstructionAccess#: Instruction access for eDMA4 transfers.

enum _edma_channel_protection_level#

eDMA4 channel protection level

Values:

enumerator kEDMA_ChannelProtectionLevelUser#: user protection level for eDMA transfers.

enumerator kEDMA_ChannelProtectionLevelPrivileged#: Privileged protection level eDMA transfers.

typedef enum _edma_transfer_size edma_transfer_size_t#: eDMA transfer configuration

typedef enum _edma_modulo edma_modulo_t#: eDMA modulo configuration

typedef enum _edma_bandwidth edma_bandwidth_t#: Bandwidth control.

typedef enum _edma_channel_link_type edma_channel_link_type_t#: Channel link type.

typedef enum _edma_transfer_type edma_transfer_type_t#: eDMA transfer type

typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t#: eDMA channel priority configuration

typedef struct _edma_minor_offset_config edma_minor_offset_config_t#: eDMA minor offset configuration

typedef enum edma_channel_memory_attribute edma_channel_memory_attribute_t#: eDMA channel memory attribute

typedef enum _edma_channel_swap_size edma_channel_swap_size_t#: eDMA4 channel swap size

typedef enum _edma_channel_access_type edma_channel_access_type_t#: eDMA4 channel access type

typedef enum _edma_channel_protection_level edma_channel_protection_level_t#: eDMA4 channel protection level

typedef struct _edma_channel_config edma_channel_config_t#: eDMA4 channel configuration

typedef edma_core_tcd_t edma_tcd_t#

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

typedef struct _edma_transfer_config edma_transfer_config_t#

eDMA channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

1.To perform a simple transfer, below members should be initialized at least .srcAddr - source address .dstAddr - destination address .srcWidthOfEachTransfer - data width of source address .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination address as each destination write is completed enablchannelRequest - channel request can be enabled together with transfer configure submission

2.The transfer configuration structure also support advance feature: Programmable source/destination address range(MODULO) Programmable minor loop offset Programmable major loop offset Programmable channel chain feature Programmable channel transfer control descriptor link feature

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the eDMA interfaces will generate assert error.

typedef struct _edma_config edma_config_t#: eDMA global configuration structure.

typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)#

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Param handle:: EDMA handle pointer, users shall not touch the values inside.
Param userData:: The callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
Param transferDone:: If the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
Param tcds:: How many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

typedef struct _edma_handle edma_handle_t#: eDMA transfer handle structure

FSL_EDMA_DRIVER_UNIFIED#

eDMA driver name.

This is the unified eDMA driver serving the eDMA3, eDMA4 and eDMA5 IP versions. Its Kconfig component is driver.edma_unified; the historical driver.edma4 component and the FSL_EDMA_DRIVER_EDMA4 macro are retained as deprecated aliases for backward compatibility. The version-specific edma4_* / edma5_* identifiers inside this driver refer to the corresponding IP TCD layout, not to the component name.

FSL_EDMA_DRIVER_EDMA4#: Deprecated alias of FSL_EDMA_DRIVER_UNIFIED; use FSL_EDMA_DRIVER_UNIFIED.

EDMA_ALLOCATE_TCD(name, number)#: Macro used for allocate edma TCD.

DMA_DCHPRI_INDEX(channel)#: Compute the offset unit from DCHPRI3.

struct _edma_channel_Preemption_config#

#include <fsl_edma.h>

eDMA channel priority configuration

Public Members

bool enableChannelPreemption#: If true: a channel can be suspended by other channel with higher priority

bool enablePreemptAbility#: If true: a channel can suspend other channel with low priority

uint8_t channelPriority#: Channel priority

struct _edma_minor_offset_config#

#include <fsl_edma.h>

eDMA minor offset configuration

Public Members

bool enableSrcMinorOffset#: Enable(true) or Disable(false) source minor loop offset.

bool enableDestMinorOffset#: Enable(true) or Disable(false) destination minor loop offset.

uint32_t minorOffset#: Offset for a minor loop mapping.

struct _edma_channel_config#

#include <fsl_edma.h>

eDMA4 channel configuration

Public Members

edma_channel_Preemption_config_t channelPreemptionConfig#: channel preemption configuration

edma_channel_memory_attribute_t channelReadMemoryAttribute#: channel memory read attribute configuration

edma_channel_memory_attribute_t channelWriteMemoryAttribute#: channel memory write attribute configuration

edma_channel_swap_size_t channelSwapSize#: channel swap size configuration

edma_channel_access_type_t channelAccessType#: channel access type configuration

uint8_t channelDataSignExtensionBitPosition#: channel data sign extension bit psition configuration

uint32_t channelRequestSource#: hardware service request source for the channel

bool enableMasterIDReplication#: enable master ID replication

edma_channel_protection_level_t protectionLevel#: protection level

struct _edma_transfer_config#

#include <fsl_edma.h>

eDMA channel transfer configuration

The transfer configuration structure support full feature configuration of the transfer control descriptor.

Note

User should pay attention to the transfer size alignment limitation

the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0
the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width
the totalBytes should align with the bytesEachRequest
the srcAddr should align with the srcWidthOfEachTransfer
the dstAddr should align with the dstWidthOfEachTransfer
the srcAddr should align with srcAddrModulo if modulo feature is enabled
the dstAddr should align with dstAddrModulo if modulo feature is enabled If anyone of above condition can not be satisfied, the eDMA interfaces will generate assert error.

Public Members

uint32_t srcAddr#: Source data address.

uint32_t destAddr#: Destination data address.

edma_transfer_size_t srcTransferSize#: Source data transfer size.

edma_transfer_size_t destTransferSize#: Destination data transfer size.

int16_t srcOffset#: Sign-extended offset value in byte unit applied to the current source address to form the next-state value as each source read is completed

int16_t destOffset#: Sign-extended offset value in byte unit applied to the current destination address to form the next-state value as each destination write is completed.

uint32_t minorLoopBytes#: bytes in each minor loop or each request range: 1 - (2^30 -1) when minor loop mapping is enabled range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor loop offset is enabled range: 1 - (2^32 - 1) when minor loop mapping is disabled

uint32_t majorLoopCounts#: minor loop counts in each major loop, should be 1 at least for each transfer range: (0 - (2^15 - 1)) when minor loop channel link is disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled total bytes in a transfer = minorLoopCountsEachMajorLoop * bytesEachMinorLoop

uint16_t enabledInterruptMask#: channel interrupt to enable, can be OR’ed value of _edma_interrupt_enable

edma_modulo_t srcAddrModulo#: source circular data queue range

int32_t srcMajorLoopOffset#: source major loop offset

edma_modulo_t dstAddrModulo#: destination circular data queue range

int32_t dstMajorLoopOffset#: destination major loop offset

bool enableSrcMinorLoopOffset#: enable source minor loop offset

bool enableDstMinorLoopOffset#: enable dest minor loop offset

int32_t minorLoopOffset#: burst offset, the offset will be applied after minor loop update

bool enableChannelMajorLoopLink#: channel link when major loop complete

uint32_t majorLoopLinkChannel#: major loop link channel number

bool enableChannelMinorLoopLink#: channel link when minor loop complete

uint32_t minorLoopLinkChannel#: minor loop link channel number

edma_tcd_t *linkTCD#: pointer to the link transfer control descriptor

struct _edma_config#

#include <fsl_edma.h>

eDMA global configuration structure.

Public Members

bool enableMasterIdReplication#: Enable (true) master ID replication. If Master ID replication is disabled, the privileged protection level (supervisor mode) for eDMA4 transfers is used.

bool enableGlobalChannelLink#: Enable(true) channel linking is available and controlled by each channel’s link settings.

bool enableHaltOnError#: Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

bool enableDebugMode#: Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of a new channel. Executing channels are allowed to complete.

bool enableRoundRobinArbitration#: Enable(true) channel linking is available and controlled by each channel’s link settings.

edma_channel_config_t *channelConfig[1]#: channel preemption configuration

struct _edma_handle#

#include <fsl_edma.h>

eDMA transfer handle structure

Public Members

edma_callback callback#: Callback function for major count exhausted.

void *userData#: Callback function parameter.

EDMA_ChannelType *channelBase#: eDMA peripheral channel base address.

EDMA_Type *base#: eDMA peripheral base address

EDMA_TCDType *tcdBase#: eDMA peripheral tcd base address.

edma_tcd_t *tcdPool#: Pointer to memory stored TCDs.

uint32_t channel#: eDMA channel number.

volatile int8_t header#: The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

volatile int8_t tail#: The last TCD index. Should point to the next TCD to be stored into the memory pool.

volatile int8_t tcdUsed#: The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

volatile int8_t tcdSize#: The total number of TCD slots in the queue.

eDMA core Driver#

enum _edma_tcd_type#

eDMA tcd flag type

Values:

enumerator kEDMA_EDMA4Flag#: Data access for eDMA4 transfers.

enumerator kEDMA_EDMA5Flag#: Instruction access for eDMA4 transfers.

typedef struct _edma_core_mp edma_core_mp_t#: edma core channel struture definition

typedef struct _edma_core_channel edma_core_channel_t#: edma core channel struture definition

typedef enum _edma_tcd_type edma_tcd_type_t#: eDMA tcd flag type

typedef struct _edma5_core_tcd edma5_core_tcd_t#: edma5 core TCD struture definition

typedef struct _edma4_core_tcd edma4_core_tcd_t#: edma4 core TCD struture definition

typedef struct _edma_core_tcd edma_core_tcd_t#: edma core TCD struture definition

typedef edma_core_channel_t EDMA_ChannelType#: EDMA typedef.

typedef edma_core_tcd_t EDMA_TCDType#

typedef void EDMA_Type#

DMA_CORE_MP_CSR_EDBG_MASK#

DMA_CORE_MP_CSR_ERCA_MASK#

DMA_CORE_MP_CSR_HAE_MASK#

DMA_CORE_MP_CSR_HALT_MASK#

DMA_CORE_MP_CSR_GCLC_MASK#

DMA_CORE_MP_CSR_GMRC_MASK#

DMA_CORE_MP_CSR_EDBG(x)#

DMA_CORE_MP_CSR_ERCA(x)#

DMA_CORE_MP_CSR_HAE(x)#

DMA_CORE_MP_CSR_HALT(x)#

DMA_CORE_MP_CSR_GCLC(x)#

DMA_CORE_MP_CSR_GMRC(x)#

DMA_CSR_INTMAJOR_MASK#

DMA_CSR_INTHALF_MASK#

DMA_CSR_DREQ_MASK#

DMA_CSR_ESG_MASK#

DMA_CSR_BWC_MASK#

DMA_CSR_BWC(x)#

DMA_CSR_START_MASK#

DMA_CITER_ELINKNO_CITER_MASK#

DMA_BITER_ELINKNO_BITER_MASK#

DMA_CITER_ELINKNO_CITER_SHIFT#

DMA_CITER_ELINKYES_CITER_MASK#

DMA_CITER_ELINKYES_CITER_SHIFT#

DMA_ATTR_SMOD_MASK#

DMA_ATTR_DMOD_MASK#

DMA_ATTR_SSIZE_MASK#

DMA_ATTR_SSIZE_SHIFT#

DMA_ATTR_DSIZE_MASK#

DMA_ATTR_DSIZE_SHIFT#

DMA_CITER_ELINKNO_ELINK_MASK#

DMA_CSR_MAJORELINK_MASK#

DMA_BITER_ELINKYES_ELINK_MASK#

DMA_CITER_ELINKYES_ELINK_MASK#

DMA_CSR_MAJORLINKCH_MASK#

DMA_BITER_ELINKYES_LINKCH_MASK#

DMA_CITER_ELINKYES_LINKCH_MASK#

DMA_NBYTES_MLOFFYES_MLOFF_MASK#

DMA_NBYTES_MLOFFYES_DMLOE_MASK#

DMA_NBYTES_MLOFFYES_SMLOE_MASK#

DMA_NBYTES_MLOFFNO_NBYTES_MASK#

DMA_ATTR_DMOD(x)#

DMA_ATTR_SMOD(x)#

DMA_BITER_ELINKYES_LINKCH(x)#

DMA_CITER_ELINKYES_LINKCH(x)#

DMA_NBYTES_MLOFFYES_MLOFF(x)#

DMA_NBYTES_MLOFFYES_DMLOE(x)#

DMA_NBYTES_MLOFFYES_SMLOE(x)#

DMA_NBYTES_MLOFFNO_NBYTES(x)#

DMA_NBYTES_MLOFFYES_NBYTES(x)#

DMA_ATTR_DSIZE(x)#

DMA_ATTR_SSIZE(x)#

DMA_CSR_DREQ(x)#

DMA_CSR_MAJORLINKCH(x)#

DMA_CH_MATTR_WCACHE(x)#

DMA_CH_MATTR_RCACHE(x)#

DMA_CH_CSR_SIGNEXT_MASK#

DMA_CH_CSR_SIGNEXT_SHIFT#

DMA_CH_CSR_SWAP_MASK#

DMA_CH_CSR_SWAP_SHIFT#

DMA_CH_SBR_INSTR_MASK#

DMA_CH_SBR_INSTR_SHIFT#

DMA_CH_SBR_EMI_MASK#

DMA_CH_SBR_EMI_SHIFT#

DMA_CH_MUX_SOURCE(x)#

DMA_ERR_DBE_FLAG#: DMA error flag.

DMA_ERR_SBE_FLAG#

DMA_ERR_SGE_FLAG#

DMA_ERR_NCE_FLAG#

DMA_ERR_DOE_FLAG#

DMA_ERR_DAE_FLAG#

DMA_ERR_SOE_FLAG#

DMA_ERR_SAE_FLAG#

DMA_ERR_ERRCHAN_FLAG#

DMA_ERR_ECX_FLAG#

DMA_ERR_FLAG#

DMA_CLEAR_DONE_STATUS(base, channel)#: get/clear DONE bit

DMA_GET_DONE_STATUS(base, channel)#

DMA_ENABLE_ERROR_INT(base, channel)#: enable/disable error interupt

DMA_DISABLE_ERROR_INT(base, channel)#

DMA_CLEAR_ERROR_STATUS(base, channel)#: get/clear error status

DMA_GET_ERROR_STATUS(base, channel)#

DMA_CLEAR_INT_STATUS(base, channel)#: get/clear INT status

DMA_GET_INT_STATUS(base, channel)#

DMA_ENABLE_MAJOR_INT(base, channel)#: enable/dsiable MAJOR/HALF INT

DMA_ENABLE_HALF_INT(base, channel)#

DMA_DISABLE_MAJOR_INT(base, channel)#

DMA_DISABLE_HALF_INT(base, channel)#

EDMA_TCD_ALIGN_SIZE#: EDMA tcd align size.

EDMA_CORE_BASE(base)#: EDMA base address convert macro.

EDMA_MP_BASE(base)#

EDMA_CHANNEL_BASE(base, channel)#

EDMA_TCD_BASE(base, channel)#

EDMA_TCD_TYPE(x)#: EDMA TCD type macro.

EDMA_TCD_SADDR(tcd, flag)#: EDMA TCD address convert macro.

EDMA_TCD_SOFF(tcd, flag)#

EDMA_TCD_ATTR(tcd, flag)#

EDMA_TCD_NBYTES(tcd, flag)#

EDMA_TCD_SLAST(tcd, flag)#

EDMA_TCD_DADDR(tcd, flag)#

EDMA_TCD_DOFF(tcd, flag)#

EDMA_TCD_CITER(tcd, flag)#

EDMA_TCD_DLAST_SGA(tcd, flag)#

EDMA_TCD_CSR(tcd, flag)#

EDMA_TCD_BITER(tcd, flag)#

struct _edma_core_mp#

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t MP_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t MP_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

struct _edma_core_channel#

#include <fsl_edma_core.h>

edma core channel struture definition

Public Members

__IO uint32_t CH_CSR: Channel Control and Status, array offset: 0x10000, array step: 0x10000

__IO uint32_t CH_ES: Channel Error Status, array offset: 0x10004, array step: 0x10000

__IO uint32_t CH_INT: Channel Interrupt Status, array offset: 0x10008, array step: 0x10000

__IO uint32_t CH_SBR: Channel System Bus, array offset: 0x1000C, array step: 0x10000

__IO uint32_t CH_PRI: Channel Priority, array offset: 0x10010, array step: 0x10000

struct _edma5_core_tcd#

#include <fsl_edma_core.h>

edma5 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint32_t SADDR_HIGH: SADDR HIGH register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t SLAST_SDA_HIGH: SLAST SDA HIGH register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint32_t DADDR_HIGH: DADDR HIGH register, used for destination address

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint32_t DLAST_SGA_HIGH: DLASTSGA HIGH register, next tcd address used in scatter-gather mode

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

uint8_t RESERVED[16]#: Aligned 64 bytes

struct _edma4_core_tcd#

#include <fsl_edma_core.h>

edma4 core TCD struture definition

Public Members

__IO uint32_t SADDR: SADDR register, used to save source address

__IO uint16_t SOFF: SOFF register, save offset bytes every transfer

__IO uint16_t ATTR: ATTR register, source/destination transfer size and modulo

__IO uint32_t NBYTES: Nbytes register, minor loop length in bytes

__IO uint32_t SLAST: SLAST register

__IO uint32_t DADDR: DADDR register, used for destination address

__IO uint16_t DOFF: DOFF register, used for destination offset

__IO uint16_t CITER: CITER register, current minor loop numbers, for unfinished minor loop.

__IO uint32_t DLAST_SGA: DLASTSGA register, next tcd address used in scatter-gather mode

__IO uint16_t CSR: CSR register, for TCD control status

__IO uint16_t BITER: BITER register, begin minor loop count.

struct _edma_core_tcd#: #include <fsl_edma_core.h>

edma core TCD struture definition

union MP_REGS#

Public Members

struct _edma_core_mp EDMA5_REG#

struct EDMA5_REG

Public Members

__IO uint32_t MP_INT_LOW: Channel Control and Status, array offset: 0x10008, array step: 0x10000

__I uint32_t MP_INT_HIGH: Channel Control and Status, array offset: 0x1000C, array step: 0x10000

__I uint32_t MP_HRS_LOW: Channel Control and Status, array offset: 0x10010, array step: 0x10000

__I uint32_t MP_HRS_HIGH: Channel Control and Status, array offset: 0x10014, array step: 0x10000

__IO uint32_t MP_STOPCH: Channel Control and Status, array offset: 0x10020, array step: 0x10000

__I uint32_t MP_SSR_LOW: Channel Control and Status, array offset: 0x10030, array step: 0x10000

__I uint32_t MP_SSR_HIGH: Channel Control and Status, array offset: 0x10034, array step: 0x10000

__IO uint32_t CH_GRPRI [64]: Channel Control and Status, array offset: 0x10100, array step: 0x10000

__IO uint32_t CH_MUX [64]: Channel Control and Status, array offset: 0x10200, array step: 0x10000

__IO uint32_t CH_PROT [64]: Channel Control and Status, array offset: 0x10400, array step: 0x10000

union CH_REGS#

Public Members

struct _edma_core_channel EDMA5_REG#

struct _edma_core_channel EDMA4_REG#

struct EDMA5_REG

Public Members

__IO uint32_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

struct EDMA4_REG

Public Members

__IO uint32_t CH_MUX: Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000

__IO uint16_t CH_MATTR: Memory Attributes Register, array offset: 0x10018, array step: 0x8000

union TCD_REGS#

Public Members

edma4_core_tcd_t edma4_tcd#

eDMA soc Driver#

FSL_EDMA_SOC_DRIVER_VERSION#: Driver version 2.0.0.

FSL_EDMA_SOC_IP_DMA3#: DMA IP version.

FSL_EDMA_SOC_IP_DMA4#

EDMA_BASE_PTRS#: DMA base table.

EDMA_CHN_IRQS#

EDMA_CHANNEL_OFFSET#: EDMA base address convert macro.

EDMA_CHANNEL_ARRAY_STEP(base)#

EIM: error injection module#

FSL_EIM_DRIVER_VERSION#: Driver version.

void EIM_Init(EIM_Type *base)#

EIM module initialization function.

Parameters:

base – EIM base address.

void EIM_Deinit(EIM_Type *base)#: De-initializes the EIM.

EQDC: Enhanced Quadrature Encoder/Decoder#

void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)#

Initializes the EQDC module.

This function initializes the EQDC by enabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.
psConfig – Pointer to configuration structure.

void EQDC_GetDefaultConfig(eqdc_config_t *psConfig)#

Gets an available pre-defined configuration.

The default value are:

psConfig->enableReverseDirection              = false;
psConfig->countOnce                           = false;
psConfig->operateMode                         = kEQDC_QuadratureDecodeOperationMode;
psConfig->countMode                           = kEQDC_QuadratureX4;
psConfig->homeEnableInitPosCounterMode        = kEQDC_HomeInitPosCounterDisabled;
psConfig->indexPresetInitPosCounterMode       = kEQDC_IndexInitPosCounterDisabled;
psConfig->enableIndexInitPositionCounter      = false;
psConfig->enableDma                           = false;
psConfig->bufferedRegisterLoadMode            = false;
psConfig->enableTriggerInitPositionCounter    = false;
psConfig->enableTriggerClearPositionRegisters = false;
psConfig->enableTriggerHoldPositionRegisters  = false;
psConfig->enableWatchdog                      = false;
psConfig->watchdogTimeoutValue                = 0xFFFFU;
psConfig->filterPhaseA                        = 0U;
psConfig->filterPhaseB                        = 0U;
psConfig->filterIndPre                        = 0U;
psConfig->filterHomEna                        = 0U;
psConfig->filterClockSourceselection          = false;
psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
psConfig->filterSamplePeriod                  = 0U;
psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
psConfig->positionCompareValue[0]                = 0xFFFFFFFFU;
psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
psConfig->revolutionCountCondition            = kEQDC_RevolutionCountOnIndexPulse;
psConfig->positionModulusValue                = 0U;
psConfig->positionInitialValue                = 0U;
psConfig->positionCounterValue                = 0U;
psConfig->enablePeriodMeasurement             = false;
psConfig->prescaler                           = kEQDC_Prescaler1;
psConfig->enabledInterruptsMask               = 0U;

Parameters:

psConfig – Pointer to configuration structure.

void EQDC_Deinit(EQDC_Type *base)#

De-initializes the EQDC module.

This function deinitializes the EQDC by disabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.

void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)#

Initializes the mode of operation.

This function initializes mode of operation by enabling the IP bus clock (optional).

Parameters:

base – EQDC peripheral base address.
operateMode – Select operation mode.

static inline void EQDC_SetCountMode(EQDC_Type *base, eqdc_count_mode_t countMode)#

Initializes the mode of count.

These bits control the basic counting and behavior of Position Counter and Position Difference Counter. Setting CTRL[REV] to 1 can reverse the counting direction. 1.In quadrature Mode (CTRL[PH1] = 0): 00b - CM0: Normal/Reverse Quadrature X4 01b - CM1: Normal/Reverse Quadrature X2 10b - CM2: Normal/Reverse Quadrature X1 11b - CM3: Reserved 2.In Single Phase Mode (CTRL[PH1] = 1): 00b - CM0: UP/DOWN Pulse Count Mode 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB is low and counts down when PHASEB is high 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when PHASEB is low and counts down when PHASEB is high 11b - CM3: Reserved

Parameters:

base – EQDC peripheral base address.
countMode – Select count mode.

static inline void EQDC_EnableWatchdog(EQDC_Type *base, bool bEnable)#

Enable watchdog for EQDC module.

Parameters:

base – EQDC peripheral base address
bEnable – Enables or disables the watchdog

static inline void EQDC_SetWatchdogTimeout(EQDC_Type *base, uint16_t u16Timeout)#

Set watchdog timeout value.

Parameters:

base – EQDC peripheral base address
u16Timeout – Number of clock cycles, plus one clock cycle that the watchdog timer counts before timing out

static inline void EQDC_EnableDMA(EQDC_Type *base, bool bEnable)#

Enable DMA for EQDC module.

Parameters:

base – EQDC peripheral base address
bEnable – Enables or disables the DMA

static inline void EQDC_SetBufferedRegisterLoadUpdateMode(EQDC_Type *base)#

Set Buffered Register Load (Update) Mode.

This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address

static inline void EQDC_ClearBufferedRegisterLoadUpdateMode(EQDC_Type *base)#

Clear Buffered Register Load (Update) Mode.

Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address

static inline void EQDC_SetEqdcLdok(EQDC_Type *base)#

Set load okay.

Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and take effect. When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically cleared after the values in outer-set is loaded into the inner-set.

Parameters:

base – EQDC peripheral base address.

static inline uint16_t EQDC_GetEqdcLdok(EQDC_Type *base)#

Get load okay.

Parameters:

base – EQDC peripheral base address.

static inline void EQDC_ClearEqdcLdok(EQDC_Type *base)#

Clear load okay.

Parameters:

base – EQDC peripheral base address.

static inline uint32_t EQDC_GetStatusFlags(EQDC_Type *base)#

Get the status flags.

Parameters:

base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the status flags, _eqdc_status_flags.

static inline void EQDC_ClearStatusFlags(EQDC_Type *base, uint32_t u32Flags)#

Clear the status flags.

Parameters:

base – EQDC peripheral base address.
u32Flags – Logical OR’ed value of the flags to clear, _eqdc_status_flags.

static inline uint16_t EQDC_GetSignalStatusFlags(EQDC_Type *base)#

Get the signals’ real-time status.

Parameters:

base – EQDC peripheral base address.

Returns:

Logical OR’ed value of the real-time signal status, _eqdc_signal_status.

static inline eqdc_count_direction_flag_t EQDC_GetLastCountDirection(EQDC_Type *base)#

Get the direction of the last count.

Parameters:

base – EQDC peripheral base address.

Returns:

Direction of the last count.

static inline void EQDC_EnableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)#

Enable the interrupts.

Parameters:

base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DisableInterrupts(EQDC_Type *base, uint32_t u32Interrupts)#

Disable the interrupts.

Parameters:

base – EQDC peripheral base address.
u32Interrupts – Logical OR’ed value of the interrupts, _eqdc_interrupt_enable.

static inline void EQDC_DoSoftwareLoadInitialPositionValue(EQDC_Type *base)#

Load the initial position value to position counter.

Software trigger to load the initial position value (UINIT and LINIT) contents to position counter (UPOS and LPOS), so that to provide the consistent operation the position counter registers.

Parameters:

base – EQDC peripheral base address.

static inline void EQDC_SetInitialPositionValue(EQDC_Type *base, uint32_t u32PositionInitValue)#

Set initial position value for EQDC module.

Set the position counter initial value (UINIT, LINIT). After writing values to the UINIT and LINIT registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionInitValue – Position initial value

static inline void EQDC_SetPositionCounterValue(EQDC_Type *base, uint32_t positionCounterValue)#

Set position counter value.

Set the position counter value (POS or UPOS, LPOS).

Parameters:

base – EQDC peripheral base address
positionCounterValue – Position counter value

static inline void EQDC_SetPositionModulusValue(EQDC_Type *base, uint32_t positionModulusValue)#

Set position counter modulus value.

Set the position counter modulus value (UMOD, LMOD). After writing values to the UMOD and LMOD registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
positionModulusValue – Position modulus value

static inline void EQDC_SetPositionCompare0Value(EQDC_Type *base, uint32_t u32PositionComp0Value)#

Set position counter compare 0 value.

Set the position counter compare 0 value (UCOMP0, LCOMP0). After writing values to the UCOMP0 and LCOMP0 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp0Value – Position modulus value

static inline void EQDC_SetPositionCompare1Value(EQDC_Type *base, uint32_t u32PositionComp1Value)#

Set position counter compare 1 value.

Set the position counter compare 1 value (UCOMP1, LCOMP1). After writing values to the UCOMP1 and LCOMP1 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp1Value – Position modulus value

static inline void EQDC_SetPositionCompare2Value(EQDC_Type *base, uint32_t u32PositionComp2Value)#

Set position counter compare 2 value.

Set the position counter compare 2 value (UCOMP2, LCOMP2). After writing values to the UCOMP2 and LCOMP2 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp2Value – Position modulus value

static inline void EQDC_SetPositionCompare3Value(EQDC_Type *base, uint32_t u32PositionComp3Value)#

Set position counter compare 3 value.

Set the position counter compare 3 value (UCOMP3, LCOMP3). After writing values to the UCOMP3 and LCOMP3 registers, the values are “buffered” into outer-set registers temporarily. Values will be loaded into inner-set registers and take effect using the following two methods:

If CTRL2[LDMODE] is 1, “buffered” values are loaded into inner-set and take effect at the next roll-over or roll-under if CTRL[LDOK] is set.
If CTRL2[LDMODE] is 0, “buffered” values are loaded into inner-set and take effect immediately when CTRL[LDOK] is set.

Parameters:

base – EQDC peripheral base address
u32PositionComp3Value – Position modulus value

static inline uint32_t EQDC_GetPosition(EQDC_Type *base)#

Get the current position counter’s value.

Parameters:

base – EQDC peripheral base address.

Returns:

Current position counter’s value.

static inline uint32_t EQDC_GetHoldPosition(EQDC_Type *base)#

Get the hold position counter’s value.

The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter’s value.

static inline uint32_t EQDC_GetHoldPosition1(EQDC_Type *base)#

Get the hold position counter1’s value.

The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. Position counter is captured into POSH1 on the rising edge of ICAP[1].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter1’s value.

static inline uint32_t EQDC_GetHoldPosition2(EQDC_Type *base)#

Get the hold position counter2’s value.

The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. Position counter is captured into POSH2 on the rising edge of ICAP[2].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter2’s value.

static inline uint32_t EQDC_GetHoldPosition3(EQDC_Type *base)#

Get the hold position counter3’s value.

The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. Position counter is captured into POSH3 on the rising edge of ICAP[3].

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position counter3’s value.

static inline uint16_t EQDC_GetPositionDifference(EQDC_Type *base)#

Get the position difference counter’s value.

Parameters:

base – EQDC peripheral base address.

Returns:

The position difference counter’s value.

static inline uint16_t EQDC_GetHoldPositionDifference(EQDC_Type *base)#

Get the hold position difference counter’s value.

The position difference (POSD) value is loaded to hold position difference (POSDH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), POSDH will only be udpated when reading POSD.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position difference counter’s value.

static inline uint16_t EQDC_GetRevolution(EQDC_Type *base)#

Get the revolution counter’s value.

Get the revolution counter (REV) value.

Parameters:

base – EQDC peripheral base address.

Returns:

The revolution counter’s value.

static inline uint16_t EQDC_GetHoldRevolution(EQDC_Type *base)#

Get the hold revolution counter’s value.

The revolution counter (REV) value is loaded to hold revolution (REVH) when:

Position register (POS or UPOS, LPOS), or position difference register (POSD), or revolution register (REV) is read.
TRIGGER happens and TRIGGER is enabled to update the hold registers.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold position revolution counter’s value.

static inline uint16_t EQDC_GetLastEdgeTime(EQDC_Type *base)#

Get the last edge time.

Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. The last edge time register counts up using the peripheral clock after prescaler. Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. If the last edge timer count reaches 0xffff, the counting will stop in order to prevent an overflow.Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The last edge time.

static inline uint16_t EQDC_GetHoldLastEdgeTime(EQDC_Type *base)#

Get the hold last edge time.

The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) when the position difference register register (POSD) is read.

Parameters:

base – EQDC peripheral base address.

Returns:

Hold of last edge time.

static inline uint16_t EQDC_GetPositionDifferencePeriod(EQDC_Type *base)#

Get the Position Difference Period counter value.

The Position Difference Period counter (POSDPER) counts up using the prescaled peripheral clock. When reading the position difference register(POSD), the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an overflow. Counting will continue when an edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The position difference period counter value.

static inline uint16_t EQDC_GetBufferedPositionDifferencePeriod(EQDC_Type *base)#

Get buffered Position Difference Period counter value.

The Bufferd Position Difference Period (POSDPERBFR) value is updated with the position difference period counter(POSDPER) when any edge occurs on PHASEA or PHASEB.

Parameters:

base – EQDC peripheral base address.

Returns:

The buffered position difference period counter value.

static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)#

Get Hold Position Difference Period counter value.

The hold position difference period(POSDPERH) is updated with the value of buffered position difference period(POSDPERBFR) when the position difference(POSD) register is read.

Parameters:

base – EQDC peripheral base address.

Returns:

The hold position difference period counter value.

enum _eqdc_status_flags#

EQDC status flags, these flags indicate the counter’s events. .

Values:

enumerator kEQDC_HomeEnableTransitionFlag#: HOME/ENABLE signal transition occured.

enumerator kEQDC_IndexPresetPulseFlag#: INDEX/PRESET pulse occured.

enumerator kEQDC_WatchdogTimeoutFlag#: Watchdog timeout occured.

enumerator kEQDC_SimultPhaseChangeFlag#: Simultaneous change of PHASEA and PHASEB occured.

enumerator kEQDC_CountDirectionChangeFlag#: Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverFlag#: Position counter rolls over from 0xFFFFFFFF to 0, or from MOD value to INIT value.

enumerator kEQDC_PositionRollUnderFlag#: Position register roll under from 0 to 0xFFFFFFFF, or from INIT value to MOD value.

enumerator kEQDC_PositionCompare0Flag#: Position counter match the COMP0 value.

enumerator kEQDC_PositionCompare1Flag#: Position counter match the COMP1 value.

enumerator kEQDC_PositionCompare2Flag#: Position counter match the COMP2 value.

enumerator kEQDC_PositionCompare3Flag#: Position counter match the COMP3 value.

enumerator kEQDC_StatusAllFlags#

enum _eqdc_signal_status#

Signal status, these flags indicate the raw and filtered input signal status. .

Values:

enumerator kEQDC_SignalStatusRawHomeEnable#: Raw HOME/ENABLE input.

enumerator kEQDC_SignalStatusRawIndexPreset#: Raw INDEX/PRESET input.

enumerator kEQDC_SignalStatusRawPhaseB#: Raw PHASEB input.

enumerator kEQDC_SignalStatusRawPhaseA#: Raw PHASEA input.

enumerator kEQDC_SignalStatusFilteredHomeEnable#: The filtered HOME/ENABLE input.

enumerator kEQDC_SignalStatusFilteredIndexPreset#: The filtered INDEX/PRESET input.

enumerator kEQDC_SignalStatusFilteredPhaseB#: The filtered PHASEB input.

enumerator kEQDC_SignalStatusFilteredPhaseA#: The filtered PHASEA input.

enumerator kEQDC_SignalStatusPositionCompare0Flag#: Position Compare 0 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare1Flag#: Position Compare 1 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare2Flag#: Position Compare 2 Flag Output.

enumerator kEQDC_SignalStatusPositionCompare3Flag#: Position Compare 3 Flag Output.

enumerator kEQDC_SignalStatusCountDirectionFlagHold#: Count Direction Flag Hold.

enumerator kEQDC_SignalStatusCountDirectionFlag#: Count Direction Flag Output.

enumerator kEQDC_SignalStatusAllFlags#

enum _eqdc_interrupt_enable#

Interrupt enable/disable mask. .

Values:

enumerator kEQDC_HomeEnableTransitionInterruptEnable#: HOME/ENABLE signal transition interrupt enable.

enumerator kEQDC_IndexPresetPulseInterruptEnable#: INDEX/PRESET pulse interrupt enable.

enumerator kEQDC_WatchdogTimeoutInterruptEnable#: Watchdog timeout interrupt enable.

enumerator kEQDC_SimultPhaseChangeInterruptEnable#: Simultaneous PHASEA and PHASEB change interrupt enable.

enumerator kEQDC_CountDirectionChangeInterruptEnable#: Count direction change interrupt enable.

enumerator kEQDC_PositionRollOverInterruptEnable#: Roll-over interrupt enable.

enumerator kEQDC_PositionRollUnderInterruptEnable#: Roll-under interrupt enable.

enumerator kEQDC_AllInterruptEnable#

enum _eqdc_home_enable_init_pos_counter_mode#

Define HOME/ENABLE signal’s trigger mode.

Values:

enumerator kEQDC_HomeInitPosCounterDisabled#: Don’t use HOME/ENABLE signal to initialize the position counter.

enumerator kEQDC_HomeInitPosCounterOnRisingEdge#: Use positive going edge to trigger initialization of position counters.

enumerator kEQDC_HomeInitPosCounterOnFallingEdge#: Use negative going edge to trigger initialization of position counters.

enum _eqdc_index_preset_init_pos_counter_mode#

Define INDEX/PRESET signal’s trigger mode.

Values:

enumerator kEQDC_IndexInitPosCounterDisabled#: INDEX/PRESET pulse does not initialize the position counter.

enumerator kEQDC_IndexInitPosCounterOnRisingEdge#: Use INDEX/PRESET pulse rising edge to initialize position counter.

enumerator kEQDC_IndexInitPosCounterOnFallingEdge#: Use INDEX/PRESET pulse falling edge to initialize position counter.

enum _eqdc_operate_mode#

Define type for decoder opertion mode.

The Quadrature Decoder operates in following 4 operation modes: 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor.

Values:

enumerator kEQDC_QuadratureDecodeOperationMode#: Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_QuadratureCountOperationMode#: Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE.

enumerator kEQDC_SinglePhaseDecodeOperationMode#: Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME.

enumerator kEQDC_SinglePhaseCountOperationMode#: Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE.

enum _eqdc_count_mode#

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

Values:

enumerator kEQDC_QuadratureX4#: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX2#: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_QuadratureX1#: Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode.

enumerator kEQDC_UpDownPulseCount#: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountDoubleEdge#: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enumerator kEQDC_SignedCountSingleEdge#: Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode.

enum _eqdc_output_pulse_mode#

Define type for the condition of POSMATCH pulses.

Values:

enumerator kEQDC_OutputPulseOnCounterEqualCompare#: POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3).

enumerator kEQDC_OutputPulseOnReadingPositionCounter#: POSMATCH pulses when reading position counter(POS and LPOS), revolution counter(REV), position difference counter(POSD).

enum _eqdc_revolution_count_condition#

Define type for determining how the revolution counter (REV) is incremented/decremented.

Values:

enumerator kEQDC_RevolutionCountOnIndexPulse#: Use INDEX pulse to increment/decrement revolution counter.

enumerator kEQDC_RevolutionCountOnRollOverModulus#: Use modulus counting roll-over/under to increment/decrement revolution counter.

enum _eqdc_filter_sample_count#

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

Values:

enumerator kEQDC_Filter3Samples#: 3 samples.

enumerator kEQDC_Filter4Samples#: 4 samples.

enumerator kEQDC_Filter5Samples#: 5 samples.

enumerator kEQDC_Filter6Samples#: 6 samples.

enumerator kEQDC_Filter7Samples#: 7 samples.

enumerator kEQDC_Filter8Samples#: 8 samples.

enumerator kEQDC_Filter9Samples#: 9 samples.

enumerator kEQDC_Filter10Samples#: 10 samples.

enum _eqdc_count_direction_flag#

Count direction.

Values:

enumerator kEQDC_CountDirectionDown#: Last count was in down direction.

enumerator kEQDC_CountDirectionUp#: Last count was in up direction.

enum _eqdc_prescaler#

Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

Values:

enumerator kEQDC_Prescaler1#: Prescaler value 1.

enumerator kEQDC_Prescaler2#: Prescaler value 2.

enumerator kEQDC_Prescaler4#: Prescaler value 4.

enumerator kEQDC_Prescaler8#: Prescaler value 8.

enumerator kEQDC_Prescaler16#: Prescaler value 16.

enumerator kEQDC_Prescaler32#: Prescaler value 32.

enumerator kEQDC_Prescaler64#: Prescaler value 64.

enumerator kEQDC_Prescaler128#: Prescaler value 128.

enumerator kEQDC_Prescaler256#: Prescaler value 256.

enumerator kEQDC_Prescaler512#: Prescaler value 512.

enumerator kEQDC_Prescaler1024#: Prescaler value 1024.

enumerator kEQDC_Prescaler2048#: Prescaler value 2048.

enumerator kEQDC_Prescaler4096#: Prescaler value 4096.

enumerator kEQDC_Prescaler8192#: Prescaler value 8192.

enumerator kEQDC_Prescaler16384#: Prescaler value 16384.

enumerator kEQDC_Prescaler32768#: Prescaler value 32768.

typedef enum _eqdc_home_enable_init_pos_counter_mode eqdc_home_enable_init_pos_counter_mode_t#: Define HOME/ENABLE signal’s trigger mode.

typedef enum _eqdc_index_preset_init_pos_counter_mode eqdc_index_preset_init_pos_counter_mode_t#: Define INDEX/PRESET signal’s trigger mode.

typedef enum _eqdc_operate_mode eqdc_operate_mode_t#

Define type for decoder opertion mode.

typedef enum _eqdc_count_mode eqdc_count_mode_t#

Define type for decoder count mode.

In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, PHASEA = 0 and PHASEB = 0 mean reverse direction.

If PHASEA leads PHASEB, then motion is in the positive direction.
If PHASEA trails PHASEB,then motion is in the negative direction. In single phase mode, there are three count modes:
In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction.
In Signed Count mode (double edge), both position counter (POS) and position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input PHASEB provides the selected position counter direction (up/down).
In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction.

typedef enum _eqdc_output_pulse_mode eqdc_output_pulse_mode_t#: Define type for the condition of POSMATCH pulses.

typedef enum _eqdc_revolution_count_condition eqdc_revolution_count_condition_t#: Define type for determining how the revolution counter (REV) is incremented/decremented.

typedef enum _eqdc_filter_sample_count eqdc_filter_sample_count_t#

Input Filter Sample Count.

The Input Filter Sample Count represents the number of consecutive samples that must agree, before the input filter accepts an input transition

typedef enum _eqdc_count_direction_flag eqdc_count_direction_flag_t#: Count direction.

typedef enum _eqdc_prescaler eqdc_prescaler_t#: Prescaler used by Last Edge Time (LASTEDGE) and Position Difference Period Counter (POSDPER).

typedef struct _eqdc_config eqdc_config_t#: Define user configuration structure for EQDC module.

FSL_EQDC_DRIVER_VERSION#

EQDC_CTRL_W1C_FLAGS#: W1C bits in EQDC CTRL registers.

EQDC_INTCTRL_W1C_FLAGS#: W1C bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_EN#: Interrupt enable bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_EN#: Interrupt enable bits in EQDC INTCTRL registers.

EQDC_CTRL_INT_FLAGS#: Interrupt flag bits in EQDC CTRL registers.

EQDC_INTCTRL_INT_FLAGS#: Interrupt flag bits in EQDC INTCTRL registers.

struct _eqdc_config#

#include <fsl_eqdc.h>

Define user configuration structure for EQDC module.

Public Members

bool enableReverseDirection#: Enable reverse direction counting.

bool countOnce#: Selects modulo loop or one shot counting mode.

bool enableDma#: Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3)

bool bufferedRegisterLoadMode#: selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD).

bool enableTriggerInitPositionCounter#: Initialize position counter with initial register(UINIT, LINIT) value on TRIGGER’s rising edge.

bool enableIndexInitPositionCounter#

Enables the feature that the position counter to be initialized by Index Event Edge Mark.

This option works together with _eqdc_index_preset_init_pos_counter_mode and enableReverseDirection; If enabled, the behavior is like this:

When PHA leads PHB (Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX rising edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX falling edge reset position counter. If enableReverseDirection is false, then Reset position counter to initial value. If enableReverseDirection is true, then reset position counter to modulus value.

When PHA lags PHB (Counter Clockwise): If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnRisingEdge, then INDEX falling edge reset position counter. If _eqdc_index_preset_init_pos_counter_mode is kEQDC_IndexInitPosCounterOnFallingEdge, then INDEX rising edge reset position counter. If enableReverseDirection is false, then Reset position counter to modulus value. If enableReverseDirection is true, then reset position counter to initial value.

bool enableTriggerClearPositionRegisters#: Clear position counter(POS), revolution counter(REV), position difference counter (POSD) on TRIGGER’s rising edge.

bool enableTriggerHoldPositionRegisters#: Load position counter(POS), revolution counter(REV), position difference counter (POSD) values to hold registers on TRIGGER’s rising edge.

bool filterPhaseA#: Filter operation on PHASEA input, when write 1, it means filter for PHASEA input is bypassed.

bool filterPhaseB#: Filter operation on PHASEB input, when write 1, it means filter for PHASEB input is bypassed.

bool filterIndPre#: Filter operation on INDEX/PRESET input, when write 1, it means filter for INDEX/PRESET input is bypassed.

bool filterHomEna#: Filter operation on HOME/ENABLE input, when write 1, it means filter for HOME/ENABLE input is bypassed.

bool enableWatchdog#: Enable the watchdog to detect if the target is moving or not.

uint16_t watchdogTimeoutValue#: Watchdog timeout count value. It stores the timeout count for the quadrature decoder module watchdog timer.

eqdc_prescaler_t prescaler#: Prescaler.

bool filterClockSourceselection#: Filter Clock Source selection.

eqdc_filter_sample_count_t filterSampleCount#: Input Filter Sample Count. This value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The value represent the number of consecutive samples that must agree prior to the input filter accepting an input transition.

uint8_t filterSamplePeriod#: Input Filter Sample Period. This value should be set such that the sampling period is larger than the period of the expected noise. This value represents the sampling period (in IPBus clock cycles) of the decoder input signals. The available range is 0 - 255.

eqdc_operate_mode_t operateMode#: Selects operation mode.

eqdc_count_mode_t countMode#: Selects count mode.

eqdc_home_enable_init_pos_counter_mode_t homeEnableInitPosCounterMode#: Select how HOME/Enable signal used to initialize position counters.

eqdc_index_preset_init_pos_counter_mode_t indexPresetInitPosCounterMode#: Select how INDEX/Preset signal used to initialize position counters.

eqdc_output_pulse_mode_t outputPulseMode#: The condition of POSMATCH pulses.

uint32_t positionCompareValue[4]#: Position compare 0 ~ 3 value. The available value is a 32-bit number.

eqdc_revolution_count_condition_t revolutionCountCondition#: Revolution Counter Modulus Enable.

uint32_t positionModulusValue#: Position modulus value. The available value is a 32-bit number.

uint32_t positionInitialValue#: Position initial value. The available value is a 32-bit number.

uint32_t positionCounterValue#: Position counter value. When Modulo mode enabled, the positionCounterValue should be in the range of positionInitialValue and positionModulusValue.

bool enablePeriodMeasurement#: Enable period measurement. When enabled, the position difference hold register (POSDH) is only updated when position difference register (POSD) is read.

uint16_t enabledInterruptsMask#: Mask of interrupts to be enabled, should be OR’ed value of _eqdc_interrupt_enable.

ERM: error recording module#

void ERM_Init(ERM_Type *base)#

ERM module initialization function.

Parameters:

base – ERM base address.

void ERM_Deinit(ERM_Type *base)#: De-initializes the ERM.

static inline void ERM_EnableInterrupts(ERM_Type *base, uint32_t channel, uint32_t mask)#

ERM enable interrupts.

Parameters:

base – ERM peripheral base address.
channel – memory channel.
mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline void ERM_DisableInterrupts(ERM_Type *base, uint32_t channel, uint32_t mask)#

ERM module disable interrupts.

Parameters:

base – ERM base address.
channel – memory channel.
mask – single correction interrupt or non-correction interrupt enable to disable for one specific memory region. Refer to “_erm_interrupt_enable” enumeration.

static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, uint32_t channel)#

Gets ERM interrupt flags.

Parameters:

base – ERM peripheral base address.

Returns:

ERM event flags.

static inline void ERM_ClearInterruptStatus(ERM_Type *base, uint32_t channel, uint32_t mask)#

ERM module clear interrupt status flag.

Parameters:

base – ERM base address.
mask – event flag to clear. Refer to “_erm_interrupt_flag” enumeration.

uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, uint32_t channel)#

ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n.

Parameters:

base – ERM base address.
channel – memory channel.

Return values:

memory – error absolute address.

FSL_ERM_DRIVER_VERSION#: Driver version.

ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.

This structure contains the settings for all of the ERM interrupt configurations.

Values:

enumerator kERM_SingleCorrectionIntEnable#: Single Correction Interrupt Notification enable.

enumerator kERM_NonCorrectableIntEnable#: Non-Correction Interrupt Notification enable.

enumerator kERM_AllInterruptsEnable#: All Interrupts enable

ERM interrupt status, _erm_interrupt_flag.

This provides constants for the ERM event status for use in the ERM functions.

Values:

enumerator kERM_SingleBitCorrectionIntFlag#: Single-Bit Correction Event.

enumerator kERM_NonCorrectableErrorIntFlag#: Non-Correctable Error Event.

enumerator kERM_AllIntsFlag#: All Events.

FGPIO Driver#

FlexCAN: Flex Controller Area Network Driver#

FlexCAN Driver#

bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base)#

Determine whether the FlexCAN instance support CAN FD mode at run time.

Note

Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.

uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx)#

Get Mailbox offset number by dword.

This function gets the offset number of the specified mailbox. Mailbox is not consecutive between memory regions when payload is not 8 bytes so need to calculate the specified mailbox address. For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword after the 0x4002_4080, which is actually the address of mailbox MB[1].CS.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – Mailbox index.

Returns:

Mailbox address offset in word.

status_t FLEXCAN_EnterFreezeMode(CAN_Type *base)#

Enter FlexCAN Freeze Mode.

This function makes the FlexCAN work under Freeze Mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

status_t FLEXCAN_ExitFreezeMode(CAN_Type *base)#

Exit FlexCAN Freeze Mode.

This function makes the FlexCAN leave Freeze Mode.

Parameters:

base – FlexCAN peripheral base address.

Returns:

kStatus_Success Enter Freeze Mode successful kStatus_Timeout Timeout when wait for Freeze Mode Acknowledge

uint32_t FLEXCAN_GetInstance(CAN_Type *base)#

Get the FlexCAN instance from peripheral base address.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN instance.

bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)#

Calculates the improved timing values by specific bit Rates for classical CAN.

This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 v4.2.0 and previous version document.

Parameters:

base – FlexCAN peripheral base address.
bitRate – The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration.

void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz)#

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_Init function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.

bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, uint32_t bitRate, uint32_t bitRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig)#

Calculates the improved timing values by specific bit rates for CANFD.

This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based on the recommendation of the CiA 1301 v1.0.0 document.

Parameters:

base – FlexCAN peripheral base address.
bitRate – The CANFD bus control speed in bps defined by user.
bitRateFD – The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate switching.
sourceClock_Hz – The Source clock frequency in Hz.
pTimingConfig – Pointer to the FlexCAN timing configuration structure.

Returns:

TRUE if timing configuration found, FALSE if failed to find configuration

void FLEXCAN_FDInit(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs)#

Initializes a FlexCAN instance.

This function initializes the FlexCAN module with user-defined settings. This example shows how to set up the flexcan_config_t parameters and how to call the FLEXCAN_FDInit function by passing in these parameters.

flexcan_config_t flexcanConfig;
flexcanConfig.clkSrc               = kFLEXCAN_ClkSrc0;
flexcanConfig.bitRate              = 1000000U;
flexcanConfig.bitRateFD            = 2000000U;
flexcanConfig.maxMbNum             = 16;
flexcanConfig.enableLoopBack       = false;
flexcanConfig.enableSelfWakeup     = false;
flexcanConfig.enableIndividMask    = false;
flexcanConfig.disableSelfReception = false;
flexcanConfig.enableListenOnlyMode = false;
flexcanConfig.enableDoze           = false;
flexcanConfig.timingConfig         = timingConfig;
FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the user-defined configuration structure.
sourceClock_Hz – FlexCAN Protocol Engine clock source frequency in Hz.
dataSize – FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs to be less than or equal to this value.
brs – True if bit rate switch is enabled in FD mode.

void FLEXCAN_Deinit(CAN_Type *base)#

De-initializes a FlexCAN instance.

This function disables the FlexCAN module clock and sets all register values to the reset value.

Parameters:

base – FlexCAN peripheral base address.

void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig)#

Gets the default configuration structure.

This function initializes the FlexCAN configuration structure to default values. The default values are as follows. flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; flexcanConfig->bitRate = 1000000U; flexcanConfig->bitRateFD = 2000000U; flexcanConfig->maxMbNum = 16; flexcanConfig->enableLoopBack = false; flexcanConfig->enableSelfWakeup = false; flexcanConfig->enableIndividMask = false; flexcanConfig->disableSelfReception = false; flexcanConfig->enableListenOnlyMode = false; flexcanConfig->enableDoze = false; flexcanConfig->enablePretendedeNetworking = false; flexcanConfig->enableMemoryErrorControl = true; flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; flexcanConfig->enableTransceiverDelayMeasure = true; flexcanConfig->enableRemoteRequestFrameStored = true; flexcanConfig->payloadEndianness = kFLEXCAN_bigEndian; flexcanConfig.timingConfig = timingConfig;

Parameters:

pConfig – Pointer to the FlexCAN configuration structure.

void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)#

Sets the FlexCAN classical CAN protocol timing characteristic.

This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.

Note

Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps)#

Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.

This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.

Note

Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().

Parameters:

base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRate_Bps – Bit rate in Bps.

Returns:

kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.

void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig)#

Sets the FlexCAN CANFD data phase timing characteristic.

This function gives user settings to CANFD data phase timing characteristic. The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() to set both Nominal/Data bit Rate instead.

Note

Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the timing configuration structure.

status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps)#

Set bit rate of FlexCAN FD frame.

This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing values.

Parameters:

base – FlexCAN peripheral base address.
sourceClock_Hz – Source Clock in Hz.
bitRateN_Bps – Nominal bit Rate in Bps.
bitRateD_Bps – Data bit Rate in Bps.

Returns:

kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.

void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)#

Sets the FlexCAN receive message buffer global mask.

This function sets the global mask for the FlexCAN message buffer in a matching process. The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().

Parameters:

base – FlexCAN peripheral base address.
mask – Rx Message Buffer Global Mask value.

void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)#

Sets the FlexCAN receive FIFO global mask.

This function sets the global mask for FlexCAN FIFO in a matching process.

Parameters:

base – FlexCAN peripheral base address.
mask – Rx Fifo Global Mask value.

void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)#

Sets the FlexCAN receive individual mask.

This function sets the individual mask for the FlexCAN matching process. The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to the Rx Filter with the same index. Note that only the first 32 individual masks can be used as the Rx FIFO filter mask.

Parameters:

base – FlexCAN peripheral base address.
maskIdx – The Index of individual Mask.
mask – Rx Individual Mask value.

void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)#

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
- true: Enable Tx Message Buffer.
- false: Disable Tx Message Buffer.

void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)#

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer. User should invoke this API when CTRL2[RRS]=1. When CTRL2[RRS]=1, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbEmpty, kFLEXCAN_RxMbFull or kFLEXCAN_RxMbOverrun. Message buffer will store the remote frame in the same fashion of a data frame. No automatic remote response frame will be generated. User need to setup another message buffer to respond remote request.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
- true: Enable Rx Message Buffer.
- false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)#

Configures a FlexCAN Message Buffer identifier.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)#

Configures a FlexCAN transmit message buffer.

This function aborts the previous transmission, cleans the Message Buffer, and configures it as a Transmit Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
enable – Enable/disable Tx Message Buffer.
- true: Enable Tx Message Buffer.
- false: Disable Tx Message Buffer.

void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable)#

Configures a FlexCAN Receive Message Buffer.

This function cleans a FlexCAN build-in Message Buffer and configures it as a Receive Message Buffer.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pRxMbConfig – Pointer to the FlexCAN Message Buffer configuration structure.
enable – Enable/disable Rx Message Buffer.
- true: Enable Rx Message Buffer.
- false: Disable Rx Message Buffer.

static inline void FLEXCAN_SetFDMbID(CAN_Type *base, uint8_t mbIdx, uint32_t id)#

Configures a FlexCAN Message Buffer identifier.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
id – CAN Message Buffer Identifier, should use FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

void FLEXCAN_SetRemoteResponseMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pFrame)#

Configures a FlexCAN Remote Response Message Buffer.

User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, frame’s ID is compared to the IDs of the receive mailboxes with the CODE field configured as kFLEXCAN_RxMbRanswer. If there is a matching ID, then this mailbox content will be transmitted as response. The received remote request frame is not stored in receive buffer. It is only used to trigger a transmission of a frame in response.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The Message Buffer index.
pFrame – Pointer to CAN message frame structure for response.

void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable)#

Configures the FlexCAN Legacy Rx FIFO.

This function configures the FlexCAN Rx FIFO with given configuration.

Note

Legacy Rx FIFO only can receive classic CAN message.

Parameters:

base – FlexCAN peripheral base address.
pRxFifoConfig – Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Legacy Rx FIFO.
- true: Enable Legacy Rx FIFO.
- false: Disable Legacy Rx FIFO.

void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable)#

Configures the FlexCAN Enhanced Rx FIFO.

This function configures the Enhanced Rx FIFO with given configuration.

Note

Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time.

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter is false.
enable – Enable/disable Enhanced Rx FIFO.
- true: Enable Enhanced Rx FIFO.
- false: Disable Enhanced Rx FIFO.

void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig)#

Configures the FlexCAN Pretended Networking mode.

This function configures the FlexCAN Pretended Networking mode with given configuration.

Parameters:

base – FlexCAN peripheral base address.
pConfig – Pointer to the FlexCAN Rx FIFO configuration structure.

static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)#

Gets the FlexCAN module interrupt flags.

This function gets all FlexCAN status flags. The flags are returned as the logical OR value of the enumerators _flexcan_flags. To check the specific status, compare the return value with enumerators in _flexcan_flags.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.

static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)#

Clears status flags with the provided mask.

This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag can’t be cleared by this function.

Parameters:

base – FlexCAN peripheral base address.
mask – The status flags to be cleared, it is logical OR value of _flexcan_flags.

static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)#

Gets the FlexCAN Bus Error Counter value.

This function gets the FlexCAN Bus Error Counter value for both Tx and Rx direction. These values may be needed in the upper layer error handling.

Parameters:

base – FlexCAN peripheral base address.
txErrBuf – Buffer to store Tx Error Counter value.
rxErrBuf – Buffer to store Rx Error Counter value.

static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)#

Gets the FlexCAN low 64 Message Buffer interrupt flags.

This function gets the interrupt flags of a given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)#

Gets the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

Returns:

The status of given Message Buffers.

static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)#

Clears the FlexCAN low 64 Message Buffer interrupt flags.

This function clears the interrupt flags of a given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)#

Clears the FlexCAN High 64 Message Buffer interrupt flags.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus)#

Gets the FlexCAN Memory Error Report registers status.

This function gets the FlexCAN Memory Error Report registers status.

Parameters:

base – FlexCAN peripheral base address.
errorStatus – Pointer to FlexCAN Memory Error Report registers status structure.

static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)#

Gets the FlexCAN Number of Matches when in Pretended Networking.

This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event.

Parameters:

base – FlexCAN peripheral base address.

Returns:

The number of received wake up msessages.

static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)#

Gets the number of FlexCAN Enhanced Rx FIFO available frames.

This function gets the number of CAN messages stored in the Enhanced Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.

Returns:

The number of available CAN messages stored in the Enhanced Rx FIFO.

static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)#

Enables FlexCAN interrupts according to the provided mask.

This function enables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

base – FlexCAN peripheral base address.
mask – The interrupts to enable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)#

Disables FlexCAN interrupts according to the provided mask.

This function disables the FlexCAN interrupts according to the provided mask. The mask is a logical OR of enumeration members, see _flexcan_interrupt_enable.

Parameters:

base – FlexCAN peripheral base address.
mask – The interrupts to disable. Logical OR of _flexcan_interrupt_enable.

static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)#

Enables FlexCAN low 64 Message Buffer interrupts.

This function enables the interrupts of given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)#

Enables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)#

Disables FlexCAN low 64 Message Buffer interrupts.

This function disables the interrupts of given Message Buffers.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)#

Disables FlexCAN high 64 Message Buffer interrupts.

Valid only if the number of available MBs exceeds 64.

Parameters:

base – FlexCAN peripheral base address.
mask – The ORed FlexCAN Message Buffer mask.

void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)#

Enables or disables the FlexCAN Rx FIFO DMA request.

This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
enable – true to enable, false to disable.

static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)#

Gets the Rx FIFO Head address.

This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.

Parameters:

base – FlexCAN peripheral base address.

Returns:

FlexCAN Rx FIFO Head address.

static inline status_t FLEXCAN_Enable(CAN_Type *base, bool enable)#

Enables or disables the FlexCAN module operation.

This function enables or disables the FlexCAN module.

Parameters:

base – FlexCAN base pointer.
enable – true to enable, false to disable.

Returns:

kStatus_Success Enable FlexCAN module successful kStatus_Timeout Timeout when wait for Low-Power Mode Acknowledge

status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame)#

Writes a FlexCAN Message to the Transmit Message Buffer.

This function writes a CAN Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN Message transmit. After that the function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)#

Reads a FlexCAN Message from Receive Message Buffer.

This function reads a CAN message from a specified Receive Message Buffer. The function fills a receive CAN message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty or inactive.
kStatus_Timeout – - Timeout when wait for Rx Message Buffer busy.

status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame)#

Writes a FlexCAN FD Message to the Transmit Message Buffer.

This function writes a CAN FD Message to the specified Transmit Message Buffer and changes the Message Buffer state to start CAN FD Message transmit. After that the function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.

status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)#

Reads a FlexCAN FD Message from Receive Message Buffer.

This function reads a CAN FD message from a specified Receive Message Buffer. The function fills a receive CAN FD message frame structure with just received data and activates the Message Buffer again. The function returns immediately.

Parameters:

base – FlexCAN peripheral base address.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty or inactive.
kStatus_Timeout – - Timeout when wait for Rx Message Buffer busy.

status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame)#

Reads a FlexCAN Message from Legacy Rx FIFO.

This function reads a CAN message from the FlexCAN Legacy Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)#

Reads a FlexCAN Message from Enhanced Rx FIFO.

This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.

status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)#

Reads a FlexCAN Message from Wake Up MB.

This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The last message is stored in WMB3.

Parameters:

base – FlexCAN peripheral base address.
pRxFrame – Pointer to CAN message frame structure for reception.
mbIdx – The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.

Return values:

kStatus_Success – - Read Message from Wake up Message Buffer successfully.
kStatus_Fail – - Wake up Message Buffer has no valid content.

status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame)#

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pTxFrame – Pointer to CAN FD message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame)#

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN FD Message Buffer index.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)#

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)#

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN FD Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)#

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.

void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)#

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN FD Message Buffer index.

status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame)#

Performs a polling send transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pTxFrame – Pointer to CAN message frame to be sent.

Return values:

kStatus_Success – - Write Tx Message Buffer Successfully.
kStatus_Fail – - Tx Message Buffer is currently in use.
kStatus_Timeout – - Failed to send frames within specific time.

status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame)#

Performs a polling receive transaction on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
mbIdx – The FlexCAN Message Buffer index.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Rx Message Buffer is full and has been read successfully.
kStatus_FLEXCAN_RxOverflow – - Rx Message Buffer is already overflowed and has been read successfully.
kStatus_Fail – - Rx Message Buffer is empty.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame)#

Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
kStatus_Timeout – - Failed to receive frames within specific time.

status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame)#

Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.

Note

A transfer handle does not need to be created before calling this API.

Parameters:

base – FlexCAN peripheral base pointer.
pRxFrame – Pointer to CAN FD message frame structure for reception.

Return values:

kStatus_Success – - Read Message from Rx FIFO successfully.
kStatus_Fail – - Rx FIFO is not enabled.
kStatus_Timeout – - Failed to receive frames within specific time.

void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData)#

Initializes the FlexCAN handle.

This function initializes the FlexCAN handle, which can be used for other FlexCAN transactional APIs. Usually, for a specified FlexCAN instance, call this API once to get the initialized handle.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
callback – The callback function.
userData – The parameter of the callback function.

status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)#

Sends a message using IRQ.

This function sends a message using IRQ. This is a non-blocking function, which returns right away. When messages have been sent out, the send callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx Message Buffer sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Tx Message Buffer is in use.

status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)#

Receives a message using IRQ.

This function receives a message using IRQ. This is non-blocking function, which returns right away. When the message has been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – - Start Rx Message Buffer receiving process successfully.
kStatus_FLEXCAN_RxBusy – - Rx Message Buffer is in use.

status_t FLEXCAN_TransferRemoteRequestNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)#

Sends a remote request frame using IRQ.

This function sends a remote request frame using IRQ. This is a non-blocking function, which returns right away. When the remote request frame has been sent out, the send callback function is called. User should invoke API FLEXCAN_TransferReceiveNonBlocking to receive the response frame. Receive message buffer index should less than send message buffer index.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Start Tx remote request frame sending process successfully.
kStatus_Fail – Write Tx Message Buffer failed.
kStatus_FLEXCAN_TxBusy – Message Buffer is transmitting remote request frame.

status_t FLEXCAN_TransferRemoteResponseNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer)#

Configures a FlexCAN Message Buffer for automatic remote response using IRQ.

This function configures a Message Buffer to automatically respond to remote request frames using IRQ. This is a non-blocking function, which returns right away. When a matching remote request frame is received, the configured response frame will be transmitted automatically, and the callback function will be called. User should invoke this API when CTRL2[RRS]=0. When CTRL2[RRS]=0, if a remote request frame is received and matches a mailbox configured with CODE=kFLEXCAN_RxMbRanswer, the mailbox content will be transmitted as a response frame automatically. The received remote request frame is not stored.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pMbXfer – FlexCAN Message Buffer transfer structure. See the flexcan_mb_transfer_t.

Return values:

kStatus_Success – Configure remote response Message Buffer successfully.
kStatus_Busy – Message Buffer is waiting for remote request frame or transmitting response frame.

status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)#

Receives a message from Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the flexcan_fifo_transfer_t.

Return values:

kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)#

Gets the Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)#

Receives a message from Enhanced Rx FIFO using IRQ.

This function receives a message using IRQ. This is a non-blocking function, which returns right away. When all messages have been received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
pFifoXfer – FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@

Return values:

kStatus_Success – - Start Rx FIFO receiving process successfully.
kStatus_FLEXCAN_RxFifoBusy – - Rx FIFO is currently in use.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count)#

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx)#

Gets the detail index of Mailbox’s Timestamp by handle.

Then function can only be used when calling non-blocking Data transfer (TX/RX) API, After TX/RX data transfer done (User can get the status by handler’s callback function), we can get the detail index of Mailbox’s timestamp by handle, Detail non-blocking data transfer API (TX/RX) contain. -FLEXCAN_TransferSendNonBlocking -FLEXCAN_TransferFDSendNonBlocking -FLEXCAN_TransferReceiveNonBlocking -FLEXCAN_TransferFDReceiveNonBlocking -FLEXCAN_TransferReceiveFifoNonBlocking

Parameters:

handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

Return values:

the – index of mailbox ‘s timestamp stored in the handle.

static inline uint32_t FLEXCAN_GetHighResolutionTimeStamp(CAN_Type *base, uint8_t mbIdx)#

void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)#

Aborts the interrupt driven message send process.

This function aborts the interrupt driven message send process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)#

Aborts the interrupt driven message receive process.

This function aborts the interrupt driven message receive process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
mbIdx – The FlexCAN Message Buffer index.

void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)#

Aborts the interrupt driven message receive from Rx FIFO process.

This function aborts the interrupt driven message receive from Rx FIFO process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle)#

Aborts the interrupt driven message receive from Enhanced Rx FIFO process.

This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)#

FlexCAN IRQ handle function.

This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_MbHandleIRQ(CAN_Type *base, flexcan_handle_t *handle, uint32_t startMbIdx, uint32_t endMbIdx)#

FlexCAN Message Buffer IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
startMbIdx – First Message Buffer to handle.
endMbIdx – Last Message Buffer to handle.

void FLEXCAN_EnhancedRxFifoHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)#

FlexCAN Enhanced Rx FIFO IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_BusoffErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)#

FlexCAN Bus Off, Error and Warning IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_PNWakeUpHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)#

FlexCAN Pretended Networking Wake-up IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

void FLEXCAN_MemoryErrorHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)#

FlexCAN Memory Error IRQ handle function.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.

FSL_FLEXCAN_DRIVER_VERSION#: FlexCAN driver version.

FlexCAN transfer status.

Values:

enumerator kStatus_FLEXCAN_TxBusy#: Tx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_TxIdle#: Tx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_TxSwitchToRx#: Remote Message is send out and Message buffer changed to Receive one.

enumerator kStatus_FLEXCAN_RxBusy#: Rx Message Buffer is Busy.

enumerator kStatus_FLEXCAN_RxIdle#: Rx Message Buffer is Idle.

enumerator kStatus_FLEXCAN_RxOverflow#: Rx Message Buffer is Overflowed.

enumerator kStatus_FLEXCAN_RxFifoBusy#: Rx Message FIFO is Busy.

enumerator kStatus_FLEXCAN_RxFifoIdle#: Rx Message FIFO is Idle.

enumerator kStatus_FLEXCAN_RxFifoOverflow#: Rx Message FIFO is overflowed.

enumerator kStatus_FLEXCAN_RxFifoWarning#: Rx Message FIFO is almost overflowed.

enumerator kStatus_FLEXCAN_RxFifoDisabled#: Rx Message FIFO is disabled during reading.

enumerator kStatus_FLEXCAN_ErrorStatus#: FlexCAN Module Error and Status.

enumerator kStatus_FLEXCAN_WakeUp#: FlexCAN is waken up from STOP mode.

enumerator kStatus_FLEXCAN_UnHandled#: UnHadled Interrupt asserted.

enumerator kStatus_FLEXCAN_RxRemote#: Rx Remote Message Received in Mail box.

enumerator kStatus_FLEXCAN_RxFifoUnderflow#: Enhanced Rx Message FIFO is underflow.

enumerator kStatus_FLEXCAN_MemoryError#: FlexCAN Memory Error.

enum _flexcan_frame_format#

FlexCAN frame format.

Values:

enumerator kFLEXCAN_FrameFormatStandard#: Standard frame format attribute.

enumerator kFLEXCAN_FrameFormatExtend#: Extend frame format attribute.

enum _flexcan_frame_type#

FlexCAN frame type.

Values:

enumerator kFLEXCAN_FrameTypeData#: Data frame type attribute.

enumerator kFLEXCAN_FrameTypeRemote#: Remote frame type attribute.

enum _flexcan_clock_source#

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

Values:

enumerator kFLEXCAN_ClkSrcOsc#: FlexCAN Protocol Engine clock from Oscillator.

enumerator kFLEXCAN_ClkSrcPeri#: FlexCAN Protocol Engine clock from Peripheral Clock.

enumerator kFLEXCAN_ClkSrc0#: FlexCAN Protocol Engine clock selected by user as SRC == 0.

enumerator kFLEXCAN_ClkSrc1#: FlexCAN Protocol Engine clock selected by user as SRC == 1.

enum _flexcan_wake_up_source#

FlexCAN wake up source.

Values:

enumerator kFLEXCAN_WakeupSrcUnfiltered#: FlexCAN uses unfiltered Rx input to detect edge.

enumerator kFLEXCAN_WakeupSrcFiltered#: FlexCAN uses filtered Rx input to detect edge.

enum _flexcan_endianness#

FlexCAN payload endianness.

Values:

enumerator kFLEXCAN_bigEndian#: Transmit frame with MSB first, receive frame with big-endian format.

enumerator kFLEXCAN_littleEndian#: Transmit frame with LSB first, receive frame with little-endian format.

enum _flexcan_MB_timestamp_base#

FlexCAN timebase used for capturing 16-bit TIME_STAMP field of message buffer.

Values:

enumerator kFLEXCAN_CANTimer#: FlexCAN free-running timer.

enumerator kFLEXCAN_Lower16bitsHRTimer#: Lower 16 bits of high-resolution on-chip timer.

enumerator kFLEXCAN_Upper16bitsHRTimer#: Upper 16 bits of high-resolution on-chip timer.

enum _flexcan_capture_point#

FlexCAN capture point of 32-bit high resolution timebase during a CAN frame.

Values:

enumerator kFLEXCAN_CANFrameID2ndBit#: Second bit of identifier field of any frame is on the CAN bus. HR_TIME_STAMPn register will not capture 32-bit counter value.

enumerator kFLEXCAN_CANFrameEnd#: End of the CAN frame.

enumerator kFLEXCAN_CANFrameStart#: Start of the CAN frame.

enumerator kFLEXCAN_CANFDFrameRes#: Start of frame for classical CAN frames; res bit for CAN FD frames.

enum _flexcan_rx_fifo_filter_type#

FlexCAN Rx Fifo Filter type.

Values:

enumerator kFLEXCAN_RxFifoFilterTypeA#: One full ID (standard and extended) per ID Filter element.

enumerator kFLEXCAN_RxFifoFilterTypeB#: Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeC#: Four partial 8-bit Standard or extended ID slices per ID Filter Table element.

enumerator kFLEXCAN_RxFifoFilterTypeD#: All frames rejected.

enum _flexcan_mb_size#

FlexCAN Message Buffer Payload size.

Values:

enumerator kFLEXCAN_8BperMB#: Selects 8 bytes per Message Buffer.

enumerator kFLEXCAN_16BperMB#: Selects 16 bytes per Message Buffer.

enumerator kFLEXCAN_32BperMB#: Selects 32 bytes per Message Buffer.

enumerator kFLEXCAN_64BperMB#: Selects 64 bytes per Message Buffer.

enum _flexcan_fd_frame_length#

FlexCAN CAN FD frame supporting data length (available DLC values).

For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, the high order bytes that do not fit the Payload size will lose.

Values:

enumerator kFLEXCAN_0BperFrame#: Frame contains 0 valid data bytes.

enumerator kFLEXCAN_1BperFrame#: Frame contains 1 valid data bytes.

enumerator kFLEXCAN_2BperFrame#: Frame contains 2 valid data bytes.

enumerator kFLEXCAN_3BperFrame#: Frame contains 3 valid data bytes.

enumerator kFLEXCAN_4BperFrame#: Frame contains 4 valid data bytes.

enumerator kFLEXCAN_5BperFrame#: Frame contains 5 valid data bytes.

enumerator kFLEXCAN_6BperFrame#: Frame contains 6 valid data bytes.

enumerator kFLEXCAN_7BperFrame#: Frame contains 7 valid data bytes.

enumerator kFLEXCAN_8BperFrame#: Frame contains 8 valid data bytes.

enumerator kFLEXCAN_12BperFrame#: Frame contains 12 valid data bytes.

enumerator kFLEXCAN_16BperFrame#: Frame contains 16 valid data bytes.

enumerator kFLEXCAN_20BperFrame#: Frame contains 20 valid data bytes.

enumerator kFLEXCAN_24BperFrame#: Frame contains 24 valid data bytes.

enumerator kFLEXCAN_32BperFrame#: Frame contains 32 valid data bytes.

enumerator kFLEXCAN_48BperFrame#: Frame contains 48 valid data bytes.

enumerator kFLEXCAN_64BperFrame#: Frame contains 64 valid data bytes.

enum _flexcan_efifo_dma_per_read_length#

FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

Values:

enumerator kFLEXCAN_1WordPerRead#: Transfer 1 32-bit words (CS).

enumerator kFLEXCAN_2WordPerRead#: Transfer 2 32-bit words (CS + ID).

enumerator kFLEXCAN_3WordPerRead#: Transfer 3 32-bit words (CS + ID + 1~4 bytes data).

enumerator kFLEXCAN_4WordPerRead#: Transfer 4 32-bit words (CS + ID + 5~8 bytes data).

enumerator kFLEXCAN_5WordPerRead#: Transfer 5 32-bit words (CS + ID + 9~12 bytes data).

enumerator kFLEXCAN_6WordPerRead#: Transfer 6 32-bit words (CS + ID + 13~16 bytes data).

enumerator kFLEXCAN_7WordPerRead#: Transfer 7 32-bit words (CS + ID + 17~20 bytes data).

enumerator kFLEXCAN_8WordPerRead#: Transfer 8 32-bit words (CS + ID + 21~24 bytes data).

enumerator kFLEXCAN_9WordPerRead#: Transfer 9 32-bit words (CS + ID + 25~28 bytes data).

enumerator kFLEXCAN_10WordPerRead#: Transfer 10 32-bit words (CS + ID + 29~32 bytes data).

enumerator kFLEXCAN_11WordPerRead#: Transfer 11 32-bit words (CS + ID + 33~36 bytes data).

enumerator kFLEXCAN_12WordPerRead#: Transfer 12 32-bit words (CS + ID + 37~40 bytes data).

enumerator kFLEXCAN_13WordPerRead#: Transfer 13 32-bit words (CS + ID + 41~44 bytes data).

enumerator kFLEXCAN_14WordPerRead#: Transfer 14 32-bit words (CS + ID + 45~48 bytes data).

enumerator kFLEXCAN_15WordPerRead#: Transfer 15 32-bit words (CS + ID + 49~52 bytes data).

enumerator kFLEXCAN_16WordPerRead#: Transfer 16 32-bit words (CS + ID + 53~56 bytes data).

enumerator kFLEXCAN_17WordPerRead#: Transfer 17 32-bit words (CS + ID + 57~60 bytes data).

enumerator kFLEXCAN_18WordPerRead#: Transfer 18 32-bit words (CS + ID + 61~64 bytes data).

enumerator kFLEXCAN_19WordPerRead#: Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).

enumerator kFLEXCAN_20WordPerRead#: Transfer 20 32-bit words (CS + ID + 64 bytes data + ID HIT + HR timestamp).

enum _flexcan_rx_fifo_priority#

FlexCAN Enhanced/Legacy Rx FIFO priority.

The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.

Values:

enumerator kFLEXCAN_RxFifoPrioLow#: Matching process start from Rx Message Buffer first.

enumerator kFLEXCAN_RxFifoPrioHigh#: Matching process start from Enhanced/Legacy Rx FIFO first.

enum _flexcan_interrupt_enable#

FlexCAN interrupt enable enumerations.

This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.

Note

FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.

Values:

enumerator kFLEXCAN_BusOffInterruptEnable#: Bus Off interrupt, use bit 15.

enumerator kFLEXCAN_ErrorInterruptEnable#: CAN Error interrupt, use bit 14.

enumerator kFLEXCAN_TxWarningInterruptEnable#: Tx Warning interrupt, use bit 11.

enumerator kFLEXCAN_RxWarningInterruptEnable#: Rx Warning interrupt, use bit 10.

enumerator kFLEXCAN_FDErrorInterruptEnable#: CAN FD Error interrupt, use bit 31.

enumerator kFLEXCAN_PNMatchWakeUpInterruptEnable#: PN Match Wake Up interrupt, use high word bit 17.

enumerator kFLEXCAN_PNTimeoutWakeUpInterruptEnable#: PN Timeout Wake Up interrupt, use high word bit 16. Enhanced Rx FIFO Underflow interrupt, use high word bit 31.

enumerator kFLEXCAN_ERxFifoUnderflowInterruptEnable#: Enhanced Rx FIFO Overflow interrupt, use high word bit 30.

enumerator kFLEXCAN_ERxFifoOverflowInterruptEnable#: Enhanced Rx FIFO Watermark interrupt, use high word bit 29.

enumerator kFLEXCAN_ERxFifoWatermarkInterruptEnable#: Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28.

enumerator kFLEXCAN_ERxFifoDataAvlInterruptEnable#

enumerator kFLEXCAN_HostAccessNCErrorInterruptEnable#: Host Access With Non-Correctable Errors interrupt, use high word bit 0.

enumerator kFLEXCAN_FlexCanAccessNCErrorInterruptEnable#: FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2.

enumerator kFLEXCAN_HostOrFlexCanCErrorInterruptEnable#: Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3.

enum _flexcan_flags#

FlexCAN status flags.

This provides constants for the FlexCAN status flags for use in the FlexCAN functions.

Note

The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to read status flags and distinguish which error is occur using _flexcan_error_flags enumerations.

Values:

enumerator kFLEXCAN_ErrorOverrunFlag#: Error Overrun Status.

enumerator kFLEXCAN_FDErrorIntFlag#: CAN FD Error Interrupt Flag.

enumerator kFLEXCAN_BusoffDoneIntFlag#: Bus Off process completed Interrupt Flag.

enumerator kFLEXCAN_SynchFlag#: CAN Synchronization Status.

enumerator kFLEXCAN_TxWarningIntFlag#: Tx Warning Interrupt Flag.

enumerator kFLEXCAN_RxWarningIntFlag#: Rx Warning Interrupt Flag.

enumerator kFLEXCAN_IdleFlag#: FlexCAN In IDLE Status.

enumerator kFLEXCAN_FaultConfinementFlag#: FlexCAN Fault Confinement State.

enumerator kFLEXCAN_TransmittingFlag#: FlexCAN In Transmission Status.

enumerator kFLEXCAN_ReceivingFlag#: FlexCAN In Reception Status.

enumerator kFLEXCAN_BusOffIntFlag#: Bus Off Interrupt Flag.

enumerator kFLEXCAN_ErrorIntFlag#: CAN Error Interrupt Flag.

enumerator kFLEXCAN_ErrorFlag#

enumerator kFLEXCAN_PNMatchIntFlag#: PN Matching Event Interrupt Flag.

enumerator kFLEXCAN_PNTimeoutIntFlag#: PN Timeout Event Interrupt Flag.

enumerator kFLEXCAN_ERxFifoUnderflowIntFlag#: Enhanced Rx FIFO underflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoOverflowIntFlag#: Enhanced Rx FIFO overflow Interrupt Flag.

enumerator kFLEXCAN_ERxFifoWatermarkIntFlag#: Enhanced Rx FIFO watermark Interrupt Flag.

enumerator kFLEXCAN_ERxFifoDataAvlIntFlag#: Enhanced Rx FIFO data available Interrupt Flag.

enumerator kFLEXCAN_ERxFifoEmptyFlag#: Enhanced Rx FIFO empty status.

enumerator kFLEXCAN_ERxFifoFullFlag#: Enhanced Rx FIFO full status.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorIntFlag#: Host Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag#: FlexCAN Access With Non-Correctable Error Interrupt Flag.

enumerator kFLEXCAN_CorrectableErrorIntFlag#: Correctable Error Interrupt Flag.

enumerator kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag#: Host Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag#: FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_CorrectableErrorOverrunFlag#: Correctable Error Interrupt Overrun Flag.

enumerator kFLEXCAN_AllMemoryErrorIntFlag#: All Memory Error Interrupt Flags.

enumerator kFLEXCAN_AllMemoryErrorFlag#: All Memory Error Flags.

enum _flexcan_error_flags#

FlexCAN error status flags.

The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. This enumerations should be used with KFLEXCAN_ErrorFlag in _flexcan_flags enumerations to ditermine which error is generated.

Values:

enumerator kFLEXCAN_FDStuffingError#: Stuffing Error.

enumerator kFLEXCAN_FDFormError#: Form Error.

enumerator kFLEXCAN_FDCrcError#: Cyclic Redundancy Check Error.

enumerator kFLEXCAN_FDBit0Error#: Unable to send dominant bit.

enumerator kFLEXCAN_FDBit1Error#: Unable to send recessive bit.

enumerator kFLEXCAN_TxErrorWarningFlag#: Tx Error Warning Status.

enumerator kFLEXCAN_RxErrorWarningFlag#: Rx Error Warning Status.

enumerator kFLEXCAN_StuffingError#: Stuffing Error.

enumerator kFLEXCAN_FormError#: Form Error.

enumerator kFLEXCAN_CrcError#: Cyclic Redundancy Check Error.

enumerator kFLEXCAN_AckError#: Received no ACK on transmission.

enumerator kFLEXCAN_Bit0Error#: Unable to send dominant bit.

enumerator kFLEXCAN_Bit1Error#: Unable to send recessive bit.

FlexCAN Legacy Rx FIFO status flags.

The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies more Message Buffer space), Rx FIFO status flags are mapped to the corresponding Message Buffer status flags.

Values:

enumerator kFLEXCAN_RxFifoOverflowFlag#: Rx FIFO overflow flag.

enumerator kFLEXCAN_RxFifoWarningFlag#: Rx FIFO almost full flag.

enumerator kFLEXCAN_RxFifoFrameAvlFlag#: Frames available in Rx FIFO flag.

enum _flexcan_memory_error_type#

FlexCAN Memory Error Type.

Values:

enumerator kFLEXCAN_CorrectableError#: The memory error is correctable which means on bit error.

enumerator kFLEXCAN_NonCorrectableError#: The memory error is non-correctable which means two bit errors.

enum _flexcan_memory_access_type#

FlexCAN Memory Access Type.

Values:

enumerator kFLEXCAN_MoveOutFlexCanAccess#: The memory error was detected during move-out FlexCAN access.

enumerator kFLEXCAN_MoveInAccess#: The memory error was detected during move-in FlexCAN access.

enumerator kFLEXCAN_TxArbitrationAccess#: The memory error was detected during Tx Arbitration FlexCAN access.

enumerator kFLEXCAN_RxMatchingAccess#: The memory error was detected during Rx Matching FlexCAN access.

enumerator kFLEXCAN_MoveOutHostAccess#: The memory error was detected during Rx Matching Host (CPU) access.

enum _flexcan_byte_error_syndrome#

FlexCAN Memory Error Byte Syndrome.

Values:

enumerator kFLEXCAN_NoError#: No bit error in this byte.

enumerator kFLEXCAN_ParityBits0Error#: Parity bit 0 error in this byte.

enumerator kFLEXCAN_ParityBits1Error#: Parity bit 1 error in this byte.

enumerator kFLEXCAN_ParityBits2Error#: Parity bit 2 error in this byte.

enumerator kFLEXCAN_ParityBits3Error#: Parity bit 3 error in this byte.

enumerator kFLEXCAN_ParityBits4Error#: Parity bit 4 error in this byte.

enumerator kFLEXCAN_DataBits0Error#: Data bit 0 error in this byte.

enumerator kFLEXCAN_DataBits1Error#: Data bit 1 error in this byte.

enumerator kFLEXCAN_DataBits2Error#: Data bit 2 error in this byte.

enumerator kFLEXCAN_DataBits3Error#: Data bit 3 error in this byte.

enumerator kFLEXCAN_DataBits4Error#: Data bit 4 error in this byte.

enumerator kFLEXCAN_DataBits5Error#: Data bit 5 error in this byte.

enumerator kFLEXCAN_DataBits6Error#: Data bit 6 error in this byte.

enumerator kFLEXCAN_DataBits7Error#: Data bit 7 error in this byte.

enumerator kFLEXCAN_AllZeroError#: All-zeros non-correctable error in this byte.

enumerator kFLEXCAN_AllOneError#: All-ones non-correctable error in this byte.

enumerator kFLEXCAN_NonCorrectableErrors#: Non-correctable error in this byte.

enum _flexcan_pn_match_source#

FlexCAN Pretended Networking match source selection.

Values:

enumerator kFLEXCAN_PNMatSrcID#: Message match with ID filtering.

enumerator kFLEXCAN_PNMatSrcIDAndData#: Message match with ID filtering and payload filtering.

enum _flexcan_pn_match_mode#

FlexCAN Pretended Networking mode match type.

Values:

enumerator kFLEXCAN_PNMatModeEqual#: Match upon ID/Payload contents against an exact target value.

enumerator kFLEXCAN_PNMatModeGreater#: Match upon an ID/Payload value greater than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeSmaller#: Match upon an ID/Payload value smaller than or equal to a specified target value.

enumerator kFLEXCAN_PNMatModeRange#: Match upon an ID/Payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit

typedef enum _flexcan_frame_format flexcan_frame_format_t#: FlexCAN frame format.

typedef enum _flexcan_frame_type flexcan_frame_type_t#: FlexCAN frame type.

typedef enum _flexcan_clock_source flexcan_clock_source_t#

FlexCAN clock source.

Deprecated:

Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0

Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1

typedef enum _flexcan_wake_up_source flexcan_wake_up_source_t#: FlexCAN wake up source.

typedef enum _flexcan_endianness flexcan_endianness_t#: FlexCAN payload endianness.

typedef enum _flexcan_MB_timestamp_base flexcan_MB_timestamp_base_t#: FlexCAN timebase used for capturing 16-bit TIME_STAMP field of message buffer.

typedef enum _flexcan_capture_point flexcan_capture_point_t#: FlexCAN capture point of 32-bit high resolution timebase during a CAN frame.

typedef enum _flexcan_rx_fifo_filter_type flexcan_rx_fifo_filter_type_t#: FlexCAN Rx Fifo Filter type.

typedef enum _flexcan_mb_size flexcan_mb_size_t#: FlexCAN Message Buffer Payload size.

typedef enum _flexcan_efifo_dma_per_read_length flexcan_efifo_dma_per_read_length_t#: FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations.

typedef enum _flexcan_rx_fifo_priority flexcan_rx_fifo_priority_t#

FlexCAN Enhanced/Legacy Rx FIFO priority.

typedef enum _flexcan_memory_error_type flexcan_memory_error_type_t#: FlexCAN Memory Error Type.

typedef enum _flexcan_memory_access_type flexcan_memory_access_type_t#: FlexCAN Memory Access Type.

typedef enum _flexcan_byte_error_syndrome flexcan_byte_error_syndrome_t#: FlexCAN Memory Error Byte Syndrome.

typedef struct _flexcan_memory_error_report_status flexcan_memory_error_report_status_t#

FlexCAN memory error register status structure.

This structure contains the memory access properties that caused a memory error access. It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.

typedef struct _flexcan_frame flexcan_frame_t#: FlexCAN message frame structure.

typedef struct _flexcan_fd_frame flexcan_fd_frame_t#

CAN FD message frame structure.

The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length selected for the message buffers. The length should be a enumeration member, see _flexcan_fd_frame_length.

typedef struct _flexcan_timing_config flexcan_timing_config_t#: FlexCAN protocol timing characteristic configuration structure.

typedef struct _flexcan_config flexcan_config_t#

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

typedef struct _flexcan_rx_mb_config flexcan_rx_mb_config_t#

FlexCAN Receive Message Buffer configuration structure.

This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive Message Buffer. The function abort previous receiving process, clean the Message Buffer and activate the Rx Message Buffer using given Message Buffer setting.

typedef enum _flexcan_pn_match_source flexcan_pn_match_source_t#: FlexCAN Pretended Networking match source selection.

typedef enum _flexcan_pn_match_mode flexcan_pn_match_mode_t#: FlexCAN Pretended Networking mode match type.

typedef struct _flexcan_pn_config flexcan_pn_config_t#

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

typedef struct _flexcan_rx_fifo_config flexcan_rx_fifo_config_t#: FlexCAN Legacy Rx FIFO configuration structure.

typedef struct _flexcan_enhanced_rx_fifo_std_id_filter flexcan_enhanced_rx_fifo_std_id_filter_t#: FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter flexcan_enhanced_rx_fifo_ext_id_filter_t#: FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

typedef struct _flexcan_enhanced_rx_fifo_config flexcan_enhanced_rx_fifo_config_t#: FlexCAN Enhanced Rx FIFO configuration structure.

typedef struct _flexcan_mb_transfer flexcan_mb_transfer_t#: FlexCAN Message Buffer transfer.

typedef struct _flexcan_fifo_transfer flexcan_fifo_transfer_t#: FlexCAN Rx FIFO transfer.

typedef struct _flexcan_handle flexcan_handle_t#: FlexCAN handle structure definition.

typedef void (*flexcan_transfer_callback_t)(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData)#

FLEXCAN_WAIT_TIMEOUT#

FLEXCAN_POLLING_TIMEOUT#: Max loops to wait for polling transfer.

FLEXCAN_MODULE_TIMEOUT#: Max loops to wait for FlexCAN register access complete.

FLEXCAN_MB_BUSY_TIMEOUT#: Max loops to wait for FlexCAN RX Message Buffer busy.

DLC_LENGTH_DECODE(dlc)#: FlexCAN frame length helper macro.

FLEXCAN_ID_STD(id)#

FlexCAN Frame ID helper macro.

Standard Frame ID helper macro.

FLEXCAN_ID_EXT(id)#: Extend Frame ID helper macro.

FLEXCAN_RX_MB_STD_MASK(id, rtr, ide)#

FlexCAN Rx Message Buffer Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide)#: Extend Rx Message Buffer Mask helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide)#

FlexCAN Legacy Rx FIFO Mask helper macro.

Standard Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)#: Standard Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)#: Standard Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id)#: Standard Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id)#: Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id)#: Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id)#: Standard Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)#: Extend Rx FIFO Mask helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)#: Extend Rx FIFO Mask helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)#: Extend Rx FIFO Mask helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id)#: Extend Rx FIFO Mask helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id)#: Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id)#: Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id)#: Extend Rx FIFO Mask helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide)#

FlexCAN Rx FIFO Filter helper macro.

Standard Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide)#: Standard Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide)#: Standard Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id)#: Standard Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id)#: Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id)#: Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)#: Standard Rx FIFO Filter helper macro Type C lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide)#: Extend Rx FIFO Filter helper macro Type A helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide)#: Extend Rx FIFO Filter helper macro Type B upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide)#: Extend Rx FIFO Filter helper macro Type B lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)#: Extend Rx FIFO Filter helper macro Type C upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id)#: Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id)#: Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro.

FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id)#: Extend Rx FIFO Filter helper macro Type C lower part helper macro.

ENHANCED_RX_FIFO_FSCH(x)#: FlexCAN Enhanced Rx FIFO Filter and Mask helper macro.

RTR_STD_HIGH(x)#

RTR_STD_LOW(x)#

RTR_EXT(x)#

ID_STD_LOW(id)#

ID_STD_HIGH(id)#

ID_EXT(id)#

FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask)#: Standard ID filter element with filter + mask scheme.

FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask)#: Standard ID filter element with filter range.

FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2)#: Standard ID filter element with two filters without masks.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr)#: Extended ID filter element with filter + mask scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask)#: Extended ID filter element with filter + mask scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr)#: Extended ID filter element with range scheme low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask)#: Extended ID filter element with range scheme high word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2)#: Extended ID filter element with two filters without masks low word.

FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1)#: Extended ID filter element with two filters without masks high word.

FLEXCAN_PN_STD_MASK(id, rtr)#

FlexCAN Pretended Networking ID Mask helper macro.

Standard Rx Message Buffer Mask helper macro.

FLEXCAN_PN_EXT_MASK(id, rtr)#: Extend Rx Message Buffer Mask helper macro.

FLEXCAN_PN_INT_MASK(x)#: FlexCAN interrupt/status flag helper macro.

FLEXCAN_PN_INT_UNMASK(x)#

FLEXCAN_PN_STATUS_MASK(x)#

FLEXCAN_PN_STATUS_UNMASK(x)#

FLEXCAN_EFIFO_INT_MASK(x)#

FLEXCAN_EFIFO_INT_UNMASK(x)#

FLEXCAN_EFIFO_STATUS_MASK(x)#

FLEXCAN_EFIFO_STATUS_UNMASK(x)#

FLEXCAN_MECR_INT_MASK(x)#

FLEXCAN_MECR_INT_UNMASK(x)#

FLEXCAN_MECR_STATUS_MASK(x)#

FLEXCAN_MECR_STATUS_UNMASK(x)#

FLEXCAN_ERROR_AND_STATUS_INT_FLAG#

FLEXCAN_PNWAKE_UP_FLAG#

FLEXCAN_WAKE_UP_FLAG#

FLEXCAN_MEMORY_ERROR_INT_FLAG#

FLEXCAN_ENHANCED_RX_FIFO_INT_FLAG#: FlexCAN Enhanced Rx FIFO base address helper macro.

E_RX_FIFO(base)#

FLEXCAN_CALLBACK(x)#

FlexCAN transfer callback function.

The FlexCAN transfer callback returns a value from the underlying layer. If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of Message Buffer that generate transfer event. If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be Ignored.

struct _flexcan_memory_error_report_status#

#include <fsl_flexcan.h>

FlexCAN memory error register status structure.

Public Members

flexcan_memory_error_type_t errorType#: The type of memory error that giving rise to the report.

flexcan_memory_access_type_t accessType#: The type of memory access that giving rise to the memory error.

uint16_t accessAddress#: The address where memory error detected.

uint32_t errorData#: The raw data word read from memory with error.

struct _flexcan_frame#: #include <fsl_flexcan.h>

FlexCAN message frame structure.

struct _flexcan_fd_frame#

#include <fsl_flexcan.h>

CAN FD message frame structure.

Public Members

uint32_t idhit#: Note

ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is correct. CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive mode).

uint32_t hrtimestamp#: Note

HR timestamp offset is changed dynamically according to data length code (DLC). External 32-bit on-chip timer high-resolution timestamp.

struct _flexcan_timing_config#

#include <fsl_flexcan.h>

FlexCAN protocol timing characteristic configuration structure.

Public Members

uint32_t preDivider#: Classic CAN or CAN FD nominal phase bit rate prescaler.

uint32_t rJumpwidth#: Classic CAN or CAN FD nominal phase Re-sync Jump Width.

uint32_t phaseSeg1#: Classic CAN or CAN FD nominal phase Segment 1.

uint32_t phaseSeg2#: Classic CAN or CAN FD nominal phase Segment 2.

uint32_t propSeg#: Classic CAN or CAN FD nominal phase Propagation Segment.

uint32_t fpreDivider#: CAN FD data phase bit rate prescaler.

uint32_t frJumpwidth#: CAN FD data phase Re-sync Jump Width.

uint32_t fphaseSeg1#: CAN FD data phase Phase Segment 1.

uint32_t fphaseSeg2#: CAN FD data phase Phase Segment 2.

uint32_t fpropSeg#: CAN FD data phase Propagation Segment.

struct _flexcan_config#

#include <fsl_flexcan.h>

FlexCAN module configuration structure.

Deprecated:

Do not use the baudRate. It has been superceded bitRate

Do not use the baudRateFD. It has been superceded bitRateFD

Public Members

flexcan_clock_source_t clkSrc#: Clock source for FlexCAN Protocol Engine.

flexcan_wake_up_source_t wakeupSrc#: Wake up source selection.

uint8_t maxMbNum#: The maximum number of Message Buffers used by user.

bool enableLoopBack#: Enable or Disable Loop Back Self Test Mode.

bool enableTimerSync#: Enable or Disable Timer Synchronization.

bool enableIndividMask#: Enable or Disable Rx Individual Mask and Queue feature.

bool disableSelfReception#: Enable or Disable Self Reflection.

bool enableListenOnlyMode#: Enable or Disable Listen Only Mode.

bool enableDoze#: Enable or Disable Doze Mode.

bool enablePretendedeNetworking#: Enable or Disable the Pretended Networking mode.

bool enableMemoryErrorControl#: Enable or Disable the memory errors detection and correction mechanism.

bool enableNonCorrectableErrorEnterFreeze#: Enable or Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode.

bool enableTransceiverDelayMeasure#: Enable or Disable the transceiver delay measurement, when it is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset.

bool enableRemoteRequestFrameStored#: true: Store Remote Request Frame in the same fashion of data frame. false: Generate an automatic Remote Response Frame.

bool enableThreeSamplingMode#: true: Three samples are used to determine the value of the received bit, providing noise immunity against fast transient changes. false: One sample is used to determine the value of the received bit.

bool disableBusOffAutoRecovery#: true: Automatic recovering from Bus-Off state is disabled. false: Automatic recovering from Bus-Off state is enabled according to CAN Specification.

uint8_t txArbitrationStartDelay#: Determines how many CAN bits the transmission arbitration process start point can be delayed from the first bit of CRC field on CAN bus, valid range 0-31.

bool enableEntireArbitrationCompare#: true: Enable Entire Frame Arbitration Field Comparison for Rx MB. The IDE and RTR fields of the RX MBs are compared to their corresponding bits within the incoming frame (mask bits apply). false: The IDE field of the RX MB filter is always compared and RTR is never compared despite mask bits.

flexcan_endianness_t payloadEndianness#: Selects the byte order for the payload of transmit and receive frames, see flexcan_endianness_t.

bool enableExternalTimeTick#: true: External time tick clocks the free-running timer. false: FlexCAN bit clock clocks the free-running timer.

flexcan_MB_timestamp_base_t captureTimeBase#: Timebase of message buffer 16-bit TIME_STAMP field.

flexcan_capture_point_t capturePoint#: Point in time when 32-bit timebase is captured during CAN frame.

struct _flexcan_rx_mb_config#

#include <fsl_flexcan.h>

FlexCAN Receive Message Buffer configuration structure.

Public Members

uint32_t id#: CAN Message Buffer Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

flexcan_frame_format_t format#: CAN Frame Identifier format(Standard of Extend).

flexcan_frame_type_t type#: CAN Frame Type(Data or Remote for classical CAN only).

struct _flexcan_pn_config#

#include <fsl_flexcan.h>

FlexCAN Pretended Networking configuration structure.

This structure is used as the parameter of FLEXCAN_SetPNConfig() function. The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.

Public Members

bool enableTimeout#: Enable or Disable timeout event trigger wakeup.

uint16_t timeoutValue#: The timeout value that generates a wakeup event, the counter timer is incremented based on 64 times the CAN Bit Time unit.

bool enableMatch#: Enable or Disable match event trigger wakeup.

flexcan_pn_match_source_t matchSrc#: Selects the match source (ID and/or data match) to trigger wakeup.

uint8_t matchNum#: The number of times a given message must match the predefined ID and/or data before generating a wakeup event, range in 0x1 ~ 0xFF.

flexcan_pn_match_mode_t idMatchMode#: The ID match type.

flexcan_pn_match_mode_t dataMatchMode#: The data match type.

uint32_t idLower#: The ID target values 1 which used either for ID match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in ID match “range detection”.

uint32_t idUpper#

The ID target values 2 which used only as the upper limit value in ID match “range

detection” or used to store the ID mask in “equal to”.

uint8_t lengthLower#

The lower limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

uint8_t lengthUpper#

The upper limit for length of data bytes which used only in data match “range

detection”. Range in 0x0 ~ 0x8.

struct _flexcan_rx_fifo_config#

#include <fsl_flexcan.h>

FlexCAN Legacy Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable#: Pointer to the FlexCAN Legacy Rx FIFO identifier filter table.

uint8_t idFilterNum#: The FlexCAN Legacy Rx FIFO Filter elements quantity.

flexcan_rx_fifo_filter_type_t idFilterType#: The FlexCAN Legacy Rx FIFO Filter type.

flexcan_rx_fifo_priority_t priority#: The FlexCAN Legacy Rx FIFO receive priority.

struct _flexcan_enhanced_rx_fifo_std_id_filter#

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Standard ID filter element structure.

Public Members

uint32_t filterType#: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1#: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1#: CAN Frame Type(DATA or REMOTE).

uint32_t rtr2#: CAN Frame Identifier(STD or EXT format).

uint32_t std2#: Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_ext_id_filter#

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO Extended ID filter element structure.

Public Members

uint32_t filterType#: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t rtr1#: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t std1#: CAN Frame Type(DATA or REMOTE).

uint32_t rtr2#: CAN Frame Identifier(STD or EXT format).

uint32_t std2#: Substitute Remote request.

struct _flexcan_enhanced_rx_fifo_config#

#include <fsl_flexcan.h>

FlexCAN Enhanced Rx FIFO configuration structure.

Public Members

uint32_t *idFilterTable#: Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member occupies 32 bit word, table size should be equal to idFilterNum. There are two types of Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table members), the extended-ID filter element needs to be placed in front of the table.

uint8_t idFilterPairNum#: idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two standard ID filter elements.

uint8_t extendIdFilterNum#: The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO identifier filter table, each extended-ID filter element occupies 2 words, extendIdFilterNum need less than or equal to idFilterPairNum.

uint8_t fifoWatermark#: (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO which can trigger FIFO watermark interrupt or a DMA request.

flexcan_efifo_dma_per_read_length_t dmaPerReadLength#: Define the length of each read of the Enhanced RX FIFO element by the DAM, see _flexcan_fd_frame_length.

flexcan_rx_fifo_priority_t priority#: The FlexCAN Enhanced Rx FIFO receive priority.

struct _flexcan_mb_transfer#

#include <fsl_flexcan.h>

FlexCAN Message Buffer transfer.

Public Members

flexcan_frame_t *frame#: The buffer of CAN Message to be transfer.

uint8_t mbIdx#: The index of Message buffer used to transfer Message.

struct _flexcan_fifo_transfer#

#include <fsl_flexcan.h>

FlexCAN Rx FIFO transfer.

Public Members

flexcan_fd_frame_t *framefd#: The buffer of CAN Message to be received from Enhanced Rx FIFO.

flexcan_frame_t *frame#: The buffer of CAN Message to be received from Legacy Rx FIFO.

size_t frameNum#: Depth of CAN Message receive array of Legacy or Enhanced Rx FIFO.

struct _flexcan_handle#

#include <fsl_flexcan.h>

FlexCAN handle structure.

Public Members

flexcan_transfer_callback_t callback#: Callback function.

void *userData#: FlexCAN callback function parameter.

flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]#: The buffer for received CAN data from Message Buffers.

flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]#: The buffer for received CAN FD data from Message Buffers.

flexcan_frame_t *volatile rxFifoFrameBuf#: The buffer for received CAN data from Legacy Rx FIFO.

flexcan_fd_frame_t *volatile rxFifoFDFrameBuf#: The buffer for received CAN FD data from Enhanced Rx FIFO.

size_t rxFifoFrameNum#: The number of CAN messages remaining to be received from Legacy or Enhanced Rx FIFO.

size_t rxFifoTransferTotalNum#: Total CAN Message number need to be received from Legacy or Enhanced Rx FIFO.

volatile uint8_t mbState[CAN_WORD1_COUNT]#: Message Buffer transfer state.

volatile uint8_t rxFifoState#: Rx FIFO transfer state.

volatile uint32_t timestamp[CAN_WORD1_COUNT]#: Mailbox transfer timestamp.

struct byteStatus#

Public Members

bool byteIsRead#: The byte n (0~3) was read or not. The type of error and which bit in byte (n) is affected by the error.

struct __unnamed22__#

Public Members

uint32_t timestamp#: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length#: CAN frame data length in bytes (Range: 0~8).

uint32_t type#: CAN Frame Type(DATA or REMOTE).

uint32_t format#: CAN Frame Identifier(STD or EXT format).

uint32_t __pad0__#: Reserved.

uint32_t idhit#: CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode).

struct __unnamed24__#

Public Members

uint32_t id#: CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__#: Reserved.

union __unnamed26__#

Public Members

struct _flexcan_frame

struct _flexcan_frame

struct __unnamed28__#

Public Members

uint32_t dataWord0#: CAN Frame payload word0.

uint32_t dataWord1#: CAN Frame payload word1.

struct __unnamed30__#

Public Members

uint8_t dataByte3#: CAN Frame payload byte3.

uint8_t dataByte2#: CAN Frame payload byte2.

uint8_t dataByte1#: CAN Frame payload byte1.

uint8_t dataByte0#: CAN Frame payload byte0.

uint8_t dataByte7#: CAN Frame payload byte7.

uint8_t dataByte6#: CAN Frame payload byte6.

uint8_t dataByte5#: CAN Frame payload byte5.

uint8_t dataByte4#: CAN Frame payload byte4.

struct __unnamed32__#

Public Members

uint32_t timestamp#: FlexCAN internal Free-Running Counter Time Stamp.

uint32_t length#: CAN FD frame data length code (DLC), range see _flexcan_fd_frame_length, When the length <= 8, it equal to the data length, otherwise the number of valid frame data is not equal to the length value. user can use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes.

uint32_t type#: CAN Frame Type(DATA only).

uint32_t format#: CAN Frame Identifier(STD or EXT format).

uint32_t srr#: Substitute Remote request.

uint32_t esi#: Error State Indicator.

uint32_t brs#: Bit Rate Switch.

uint32_t edl#: Extended Data Length.

struct __unnamed34__#

Public Members

uint32_t id#: CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro.

uint32_t __pad0__#: Reserved.

union __unnamed36__#

Public Members

struct _flexcan_fd_frame

struct _flexcan_fd_frame

struct __unnamed38__#

Public Members

uint32_t dataWord[16]#: CAN FD Frame payload, 16 double word maximum.

struct __unnamed40__#

Public Members

uint8_t dataByte3#: CAN Frame payload byte3.

uint8_t dataByte2#: CAN Frame payload byte2.

uint8_t dataByte1#: CAN Frame payload byte1.

uint8_t dataByte0#: CAN Frame payload byte0.

uint8_t dataByte7#: CAN Frame payload byte7.

uint8_t dataByte6#: CAN Frame payload byte6.

uint8_t dataByte5#: CAN Frame payload byte5.

uint8_t dataByte4#: CAN Frame payload byte4.

union __unnamed42__#

Public Members

struct _flexcan_config

struct _flexcan_config

struct __unnamed44__#

Public Members

uint32_t baudRate#: FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t baudRateFD#: FlexCAN FD bit rate in bps, for CANFD data phase.

struct __unnamed46__#

Public Members

uint32_t bitRate#: FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase.

uint32_t bitRateFD#: FlexCAN FD bit rate in bps, for CANFD data phase.

union __unnamed48__#

Public Members

struct _flexcan_pn_config

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

struct _flexcan_pn_config

struct __unnamed52__#

< The data target values 1 which used either for data match “equal to”, “smaller than”, “greater than” comparisons, or as the lower limit value in data match “range

detection”.

Public Members

uint32_t lowerWord0#: CAN Frame payload word0.

uint32_t lowerWord1#: CAN Frame payload word1.

struct __unnamed54__#

Public Members

uint8_t lowerByte3#: CAN Frame payload byte3.

uint8_t lowerByte2#: CAN Frame payload byte2.

uint8_t lowerByte1#: CAN Frame payload byte1.

uint8_t lowerByte0#: CAN Frame payload byte0.

uint8_t lowerByte7#: CAN Frame payload byte7.

uint8_t lowerByte6#: CAN Frame payload byte6.

uint8_t lowerByte5#: CAN Frame payload byte5.

uint8_t lowerByte4#: CAN Frame payload byte4.

union __unnamed50__#

Public Members

struct _flexcan_pn_config

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

struct _flexcan_pn_config

struct __unnamed56__#

< The data target values 2 which used only as the upper limit value in data match “range

detection” or used to store the data mask in “equal to”.

Public Members

uint32_t upperWord0#: CAN Frame payload word0.

uint32_t upperWord1#: CAN Frame payload word1.

struct __unnamed58__#

Public Members

uint8_t upperByte3#: CAN Frame payload byte3.

uint8_t upperByte2#: CAN Frame payload byte2.

uint8_t upperByte1#: CAN Frame payload byte1.

uint8_t upperByte0#: CAN Frame payload byte0.

uint8_t upperByte7#: CAN Frame payload byte7.

uint8_t upperByte6#: CAN Frame payload byte6.

uint8_t upperByte5#: CAN Frame payload byte5.

uint8_t upperByte4#: CAN Frame payload byte4.

FlexCAN eDMA Driver#

void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_edma_transfer_callback_t callback, void *userData, edma_handle_t *rxFifoEdmaHandle)#

Initializes the FlexCAN handle, which is used in transactional functions.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxFifoEdmaHandle – User-requested DMA handle for Rx FIFO DMA transfer.

void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, flexcan_fifo_transfer_t *pFifoXfer, edma_transfer_config_t *pEdmaConfig)#

Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.

This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.

Parameters:

base – FlexCAN peripheral base address.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.
pEdmaConfig – The user configuration structure of type edma_transfer_t.

status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, flexcan_edma_handle_t *handle, edma_transfer_config_t *pEdmaConfig)#

Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.

This function to Update edma transfer confiugration and Start eDMA transfer

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pEdmaConfig – The user configuration structure of type edma_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)#

Receives the CAN Message from the Legacy Rx FIFO using eDMA.

This function receives the CAN Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)#

Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)#

Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.

status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle, flexcan_fifo_transfer_t *pFifoXfer)#

Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.

This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns right away. After the CAN Message is received, the receive callback function is called.

Parameters:

base – FlexCAN peripheral base address.
handle – Pointer to flexcan_edma_handle_t structure.
pFifoXfer – FlexCAN Rx FIFO EDMA transfer structure, see flexcan_fifo_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXCAN_RxFifoBusy – Previous transfer ongoing.

static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)#

Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.

Parameters:

base – FlexCAN peripheral base address.
handle – FlexCAN handle pointer.
count – Number of CAN messages receive so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

FSL_FLEXCAN_EDMA_DRIVER_VERSION#: FlexCAN EDMA driver version.

typedef struct _flexcan_edma_handle flexcan_edma_handle_t#

typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData)#: FlexCAN transfer callback function.

struct _flexcan_edma_handle#

#include <fsl_flexcan_edma.h>

FlexCAN eDMA handle.

Public Members

flexcan_edma_transfer_callback_t callback#: Callback function.

void *userData#: FlexCAN callback function parameter.

edma_handle_t *rxFifoEdmaHandle#: The EDMA handler for Rx FIFO.

volatile uint8_t rxFifoState#: Rx FIFO transfer state.

size_t frameNum#: The number of messages that need to be received.

flexcan_fd_frame_t *framefd#: Point to the buffer of CAN Message to be received from Enhanced Rx FIFO.

FlexIO: FlexIO Driver#

Flexio_a-format#

Error codes for the A_Format driver.

Values:

enumerator kStatus_FLEXIO_A_FORMAT_TxBusy#: Transmitter is busy.

enumerator kStatus_FLEXIO_A_FORMAT_RxBusy#: Receiver is busy.

enumerator kStatus_FLEXIO_A_FORMAT_TxIdle#: Transmitter is idle.

enumerator kStatus_FLEXIO_A_FORMAT_RxIdle#: Receiver is idle.

enumerator kStatus_FLEXIO_A_FORMAT_NotSyncCMD#: This Command doesn’t support sync mode.

enumerator kStatus_FLEXIO_A_FORMAT_OutOfIDRange#: A-format encoder ID is out of range.

enumerator kStatus_FLEXIO_A_FORMAT_RxRingBufferOverrun#: A-format RX software ring buffer overrun.

enumerator kStatus_FLEXIO_A_FORMAT_RxHardwareOverrun#: A-format RX receiver overrun.

enumerator kStatus_FLEXIO_A_FORMAT_FrameErr#: Frame format error.

enumerator kStatus_FLEXIO_A_FORMAT_Timeout#: A-format times out.

enumerator kStatus_FLEXIO_A_FORMAT_BaudrateNotSupport#: Baudrate is not supported in current clock source

enum _flexio_a_format_encoder_status#

Values:

enumerator kFLEXIO_A_FORMAT_ES_NoErr#

enumerator kFLEXIO_A_FORMAT_ES_Busy_MemBusy#

enumerator kFLEXIO_A_FORMAT_ES_Batt#

enumerator kFLEXIO_A_FORMAT_ES_OvSpd_MemErr_OvTemp_OvFlow#

enumerator kFLEXIO_A_FORMAT_ES_STErr_PSErr_MTErr_INCErr#

enumerator kFLEXIO_A_FORMAT_ES_FrameErr#

enumerator kFLEXIO_A_FORMAT_ES_Anyone#

enum _flexio_a_format_baud_rate_bps#

FlexIO A_FORMAT baud rate.

Values:

enumerator kFLEXIO_A_FORMAT_2_5MHZ#: Baud rate is 2.5Mbps

enumerator kFLEXIO_A_FORMAT_4MHZ#: Baud rate is 4Mbps

enumerator kFLEXIO_A_FORMAT_6_67MHZ#: Baud rate is 6.67Mbps

enumerator kFLEXIO_A_FORMAT_8MHZ#: Baud rate is 8Mbps

enumerator kFLEXIO_A_FORMAT_16MHZ#: Baud rate is 16Mbps

enum _flexio_a_format_user_modes#

FlexIO A_FORMAT user modes.

Values:

enumerator kFLEXIO_A_FORMAT_USERMODE_ONESHOT#: User mode is oneshot

enumerator kFLEXIO_A_FORMAT_USERMODE_SYNC#: User mode is sync

enum _flexio_a_format_interrupt_enable#

Define FlexIO A-format interrupt mask.

Values:

enumerator kFLEXIO_A_FORMAT_TxDataRegEmptyInterruptEnable#: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_A_FORMAT_RxDataRegFullInterruptEnable#: Receive buffer full interrupt enable.

enum _flexio_a_format_status_flags#

Define FlexIO A-format status mask.

Values:

enumerator kFLEXIO_A_FORMAT_TxDataRegEmptyFlag#: Transmit buffer empty flag.

enumerator kFLEXIO_A_FORMAT_RxDataRegFullFlag#: Receive buffer full flag.

enumerator kFLEXIO_A_FORMAT_RxOverRunFlag#: Receive buffer over run flag.

typedef enum _flexio_a_format_encoder_status flexio_a_format_es_t#

typedef enum _flexio_a_format_baud_rate_bps flexio_a_format_baud_rate_bps_t#: FlexIO A_FORMAT baud rate.

typedef enum _flexio_a_format_user_modes flexio_a_format_user_modes_t#: FlexIO A_FORMAT user modes.

typedef struct _flexio_a_format_handle flexio_a_format_handle_t#

typedef struct _flexio_a_format_type FLEXIO_A_FORMAT_Type#: Define FlexIO A_FORMAT access structure typedef.

typedef struct _flexio_a_format_config flexio_a_format_config_t#: Define FlexIO A_FORMAT user configuration structure.

typedef struct _flexio_a_format_transfer flexio_a_format_transfer_t#: Define FlexIO A-format transfer structure.

typedef void (*flexio_a_format_transfer_callback_t)(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, status_t status, void *userData)#: FlexIO UART transfer callback function.

static inline void FLEXIO_A_Format_WriteHalfWord(FLEXIO_A_FORMAT_Type *base, const uint16_t *buffer)#

Writes one half word of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_A_Format_ReadHalfWord(FLEXIO_A_FORMAT_Type *base, uint16_t *buffer)#

Reads one half word of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
buffer – The buffer to store the received bytes.

void FLEXIO_A_Format_Config_DR_length(FLEXIO_A_FORMAT_Type *base, uint32_t nFrames)#

The duration of the high level of the RS485 DR Pin is set according to the number of frames.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure
nFrames – The number of frames (Each 16bit of data is one frame)

status_t FLEXIO_A_Format_Init(FLEXIO_A_FORMAT_Type *base, const flexio_a_format_config_t *userConfig, uint32_t srcClock_Hz)#

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO A-Format hardware, and configures the FlexIO A-Format with FlexIO A-Format configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_A_Format_GetDefaultConfig().

Example

FLEXIO_A_FORMAT_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_a_format_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_bps = 2500000
};
FLEXIO_A_Format_Init(&base, &config, srcClock_Hz);

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
userConfig – Pointer to the flexio_a_format_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Configuration success.
kStatus_FLEXIO_A_FORMAT_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_A_Format_Deinit(FLEXIO_A_FORMAT_Type *base)#

Resets the FlexIO A-Format shifter and timer config.

note After calling this API, call the FLEXIO_A_Format_Init to use the FlexIO A_format module.

Parameters:

base – Pointer to FLEXIO_A_FORMAT_Type structure

void FLEXIO_A_Format_GetDefaultConfig(flexio_a_format_config_t *userConfig)#

Gets the default configuration to configure the FlexIO A-format. The configuration can be used directly for calling the FLEXIO_A_Format_Init(). Example:

flexio_a_format_config_t config;
FLEXIO_A_Format_GetDefaultConfig(&userConfig);

param userConfig Pointer to the flexio_a_format_config_t structure.

void FLEXIO_A_Format_EnableInterrupts(FLEXIO_A_FORMAT_Type *base, uint32_t mask)#

Enables the FlexIO A-format interrupt.

This function enables the FlexIO A-format interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
mask – Interrupt source.

void FLEXIO_A_Format_DisableInterrupts(FLEXIO_A_FORMAT_Type *base, uint32_t mask)#

Disables the FlexIO A-format interrupt.

This function disables the FlexIO A-format interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
mask – Interrupt source.

uint32_t FLEXIO_A_Format_GetStatusFlags(FLEXIO_A_FORMAT_Type *base)#

Gets the FlexIO A-format status flags.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.

Returns:

FlexIO A-format status flags.

void FLEXIO_A_Format_ClearStatusFlags(FLEXIO_A_FORMAT_Type *base, uint32_t mask)#

Clears the FlexIO A-format status flags.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
mask – Status flag. The parameter can be any combination of the following values: arg kFLEXIO_A_FORMAT_TxDataRegEmptyFlag arg kFLEXIO_A_FORMAT_RxDataRegFullFlag arg kFLEXIO_A_FORMAT_RxOverRunFlag

status_t FLEXIO_A_Format_WriteBlocking(FLEXIO_A_FORMAT_Type *base, const uint16_t *txData, size_t txSize)#

Sends a buffer of data bytes.

note This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_A_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_A_Format_ReadBlocking(FLEXIO_A_FORMAT_Type *base, uint16_t *rxData, size_t rxSize)#

Receives a buffer of bytes.

note This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_A_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_A_Format_TransferCreateHandle(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, flexio_a_format_transfer_callback_t callback, void *userData)#

Initializes the A-format handle.

This function initializes the FlexIO A-format handle, which can be used for other FlexIO A-format transactional APIs. Call this API once to get the initialized handle.

The A-format driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_A_Format_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as p ringBuffer.

Parameters:

base – to FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_A_Format_TransferStartRingBuffer(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, uint16_t *ringBuffer, size_t ringBufferSize)#

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific A-format handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the A_Format_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

note When using the RX ring buffer, one byte is reserved for internal use. In other words, if p ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_A_Format_TransferStopRingBuffer(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle)#

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

status_t FLEXIO_A_Format_TransferSendNonBlocking(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, flexio_a_format_transfer_t *xfer)#

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO A-format driver calls the callback function and passes the ref kStatus_FLEXIO_A_FORMAT_TxIdle as status parameter.

note The kStatus_FLEXIO_A_FORMAT_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
xfer – FlexIO A-format transfer structure. See flexio_a_format_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_A_FORMAT_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_A_Format_TransferAbortSend(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle)#

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainHalfwords to find out how many half-words are still not sent out.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

status_t FLEXIO_A_Format_TransferGetSendCount(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, size_t *count)#

Gets the number of half-words sent.

This function gets the number of half-words sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
count – Number of half-words sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_A_Format_TransferReceiveNonBlocking(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, flexio_a_format_transfer_t *xfer, size_t *receivedHalfWords)#

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter p receivedHalfWords shows how many half-words are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the A-format driver. When new data arrives, the receive request is serviced first. When all data is received, the A-format driver notifies the upper layer through a callback function and passes the status parameter ref kStatus_A_FORMAT_RxIdle. For example, if the upper layer needs 10 half-words but there are only 5 half-words in the ring buffer, the 5 half-words are copied to xfer->data. This function returns with the parameter p receivedHalfWords set to 5. For the last 5 half-words, newly arrived data is saved from the xfer->data[5]. When 5 half-words are received, the A-format driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
xfer – A-format transfer structure. See flexio_a_format_transfer_t.
receivedHalfWords – Half-words received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_A_FORMAT_RxBusy – Previous receive request is not finished.

void FLEXIO_A_Format_TransferAbortReceive(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle)#

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

status_t FLEXIO_A_Format_TransferGetReceiveCount(FLEXIO_A_FORMAT_Type *base, flexio_a_format_handle_t *handle, size_t *count)#

Gets the number of half-words received.

This function gets the number of half-words received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_A_FORMAT_Type structure.
handle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.
count – Number of half-words received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_A_Format_TransferHandleIRQ(void *uartType, void *uartHandle)#

FlexIO A-format IRQ handler function.

This function processes the FlexIO A-format transmit and receives the IRQ request.

Parameters:

uartType – Pointer to the FLEXIO_A_FORMAT_Type structure.
uartHandle – Pointer to the flexio_a_format_handle_t structure to store the transfer state.

void FLEXIO_A_Format_FlushShifters(FLEXIO_A_FORMAT_Type *base)#

brief Flush tx/rx shifters.

param base Pointer to the FLEXIO_A_FORMAT_Type structure.

A_FORMAT_SYNC_CODE_CMD#: The command data frame sync code of A-format.

A_FORMAT_SYNC_CODE_IF#: The encoder information field sync code of A-format.

A_FORMAT_FRAME_CODE_CDF#: A-format CDF frame code.

A_FORMAT_FRAME_CODE_MDF0#: A-format MDF frame code.

A_FORMAT_FRAME_CODE_MDF1#

A_FORMAT_FRAME_CODE_MDF2#

A_FORMAT_CDF(x)#: A-format command code.

A_FORMAT_REQ_IT_ABS_FULL_40BIT#

brief Give the command code an alias

IT: Individual Transmission MT: Multiple Transmission

A_FORMAT_REQ_IT_ABS_LOWER_24BIT#

A_FORMAT_REQ_IT_ABS_UPPER_24BIT#

A_FORMAT_REQ_IT_ENCODER_STAT#

A_FORMAT_REQ_MT_ABS_FULL_40BIT#

A_FORMAT_REQ_MT_ABS_LOWER_24BIT#

A_FORMAT_REQ_MT_ABS_UPPER_24BIT#

A_FORMAT_REQ_MT_ENCODER_STAT#

A_FORMAT_REQ_IT_CLEAR_STAT_FLAG#

A_FORMAT_REQ_IT_CLEAR_MULTI_TURN#

A_FORMAT_REQ_IT_CLEAR_STAT_MULTI#

A_FORMAT_REQ_IT_SET_ENCODER_ADDR1#

A_FORMAT_REQ_IT_PRESET_SINGLE_TURN_0#

A_FORMAT_REQ_IT_MEMORY_READ#

A_FORMAT_REQ_IT_MEMORY_WRITE#

A_FORMAT_REQ_IT_TEMPERATURE_10BIT#

A_FORMAT_REQ_IT_ID_CODE_READ1#

A_FORMAT_REQ_IT_ID_CODE_READ2#

A_FORMAT_REQ_IT_ID_CODE_WRITE1#

A_FORMAT_REQ_IT_ID_CODE_WRITE2#

A_FORMAT_REQ_IT_SET_ENCODER_ADDR2#

A_FORMAT_REQ_IT_ABS_LOWER_17BIT#

A_FORMAT_REQ_MT_ABS_LOWER_17BIT#

A_FORMAT_REQ_IT_ABS_LOWER_24BIT_STAT#

A_FORMAT_REQ_MT_ABS_LOWER_24BIT_STAT#

A_FORMAT_REQ_IT_ABS_LOWER_24BIT_TEMP#

A_FORMAT_REQ_MT_ABS_LOWER_24BIT_TEMP#

A_FORMAT_CRC_POLY_COMMAND_DATA#: The command data CRC polynomial of A-format.

A_FORMAT_CRC_POLY_ENCODER_DATA#: The encoder data CRC polynomial of A-format.

A_FORMAT_CDF_MASK_SYNC_CODE#: The mask of the CDF sync code.

A_FORMAT_CDF_MASK_FRAME_CODE#: The mask of the CDF frame code.

A_FORMAT_CDF_MASK_ENCODER_ADDR#: The mask of the CDF encoder address.

A_FORMAT_CDF_MASK_COMMAND_CODE#: The mask of the CDF command code.

A_FORMAT_CDF_MASK_CRC_CODE#: The mask of the CDF CRC code.

A_FORMAT_MDF_MASK_SYNC_CODE#: The mask of the MDF sync code.

A_FORMAT_MDF_MASK_FRAME_CODE#: The mask of the MDF frame code.

A_FORMAT_MDF_MASK_DATA_BIT#: The mask of the MDF data bit.

A_FORMAT_MDF_MASK_CRC_CODE#: The mask of the MDF CRC code.

A_FORMAT_IF_MASK_ENCODER_ADDR#: The mask of the IF encoder address.

A_FORMAT_IF_MASK_COMMAND_CODE#: The mask of the IF command code.

A_FORMAT_IF_MASK_ENCODER_STAT#: The mask of the IF encoder status.

A_FORMAT_CDF_SHIFT_SYNC_CODE(x)#: Shift the sync code for command data frame.

A_FORMAT_CDF_SHIFT_FRAME_CODE(x)#: Shift the frame code for command data frame.

A_FORMAT_CDF_SHIFT_ENCODER_ADDR(x)#: Shift the encoder address for command data frame.

A_FORMAT_CDF_SHIFT_COMMAND_CODE(x)#: Shift the command code for command data frame.

A_FORMAT_CDF_SHIFT_CRC_CODE(x)#: Shift the CRC code for command data frame.

A_FORMAT_MDF_SHIFT_SYNC_CODE(x)#: Shift the sync code for memory data frame.

A_FORMAT_MDF_SHIFT_FRAME_CODE(x)#: Shift the frame code for memory data frame.

A_FORMAT_MDF_SHIFT_DATA_BIT(x)#: Shift the data bit for memory data frame.

A_FORMAT_MDF_SHIFT_CRC_CODE(x)#: Shift the CRC code for memory data frame.

A_FORMAT_PACK_CDF(EA, CC, CRC)#: Pack the command data frame.

A_FORMAT_PACK_MDF(FC, DA, CRC)#: Pack the memory data frame.

A_FORMAT_GET_ENC_ADDR_CDF(x)#: Get encoder address from the CDF frame.

A_FORMAT_GET_CMD_CODE_CDF(x)#: Get command code from the CDF frame.

A_FORMAT_CRC_RANGE_IN_CDF#: The mask of CRC-applied range in CDF frame.

A_FORMAT_GET_CRC_DATA_CDF(x)#: Get CRC data from the CDF frame.

A_FORMAT_GET_CRC_CODE_CDF(x)#: Get CRC code from the CDF frame.

A_FORMAT_SET_CRC_CODE_CDF(cdf, crc)#: Set CRC code to the CDF frame.

A_FORMAT_CRC_RANGE_IN_MDF#: The mask of CRC-applied range in MDF frame.

A_FORMAT_GET_CRC_DATA_MDF(x)#: Get CRC data from the MDF frame.

A_FORMAT_SET_CRC_CODE_MDF(mdf, crc)#: Set CRC code to the MDF frame.

A_FORMAT_GET_ENC_ADDR_IF(x)#: Get encoder address from the IF frame.

A_FORMAT_GET_CMD_CODE_IF(x)#: Get command code from the IF frame.

A_FORMAT_GET_ENC_STAT_IF(x)#: Get encoder status from the IF frame.

ENCODER_ADDRESS_IT(x)#

ENCODER_ADDRESS_MT(x)#

ENCODER_ADDRESS_IS_MT(x)#

ENCODER_ADDRESS(x)#

HALFWORD_NUM(x)#

GET_TEMPERATURE_IS_BELOW_ZERO(x)#

GET_TEMPERATURE_DATA(x)#

GET_TEMPERATURE_VALUE(x)#

GET_ENCODER_ID(x)#

A_FORMAT_TIMER_TX_INDEX#

A_FORMAT_TIMER_TX_CLOCK_INDEX#

A_FORMAT_TIMER_RX_INDEX#

A_FORMAT_TIMER_RX_CLOCK_INDEX#

A_FORMAT_TIMER_DR_INDEX#

FSL_FLEXIO_A_FORMAT_DRIVER_VERSION#: FlexIO A_Format driver version.

A_FORMAT_RETRY_TIMES#: Retry times for waiting flag.

A_FORMAT_ENCODER_MAX_NUM#: Maximum number of encoders on an A-format bus.

A_FORMAT_BITS_PER_FRAME_DATA#: The number of bits per frame without start and stop bits.

A_FORMAT_BITS_PER_FRAME_WHOLE#: The number of bits per frame with start and stop bits.

A_FORMAT_TIMER_COMPARE_VALUE(cmp)#: Calculate the value of the FlexIO timer compare register.

FLEXIO_Type *flexioBase#: FlexIO base pointer.

flexio_a_format_handle_t *hanlde#

uint16_t timerDiv#: srcClock_Hz / baudRate_bps

uint16_t TxDR_Offset#: The offset between Tx and DR pins

uint16_t interval#: Interval between frames

uint8_t TxPinIndex#: Pin select for A_FORMAT_Tx.

uint8_t RxPinIndex#: Pin select for A_FORMAT_Rx.

uint8_t DRPinIndex#: Pin select for A_FORMAT_DR.

uint8_t shifterIndex[2]#: Shifter index used in FlexIO A_FORMAT.

uint8_t timerIndex[5]#: Timer index used in FlexIO A_FORMAT.

uint8_t triggerIn#: Trigger signal for sync mode.

bool enableA_Format#: Enable/disable FlexIO A_FORMAT TX & RX.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode

bool enableInDebug#: Enable/disable FlexIO operation in debug mode

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_a_format_baud_rate_bps_t baudRate_bps#: Baud rate in bps.

uint8_t userMode#

uint16_t *data#: The buffer of data to be transfer.

uint16_t *rxData#: The buffer to receive data.

const uint16_t *txData#: The buffer of data to be sent.

union _flexio_a_format_transfer

size_t dataSize#: Transfer size

const uint16_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize#: Size of the remaining data to send.

uint16_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize#: Size of the remaining data to receive.

size_t txDataSizeAll#: Total bytes to be sent.

size_t rxDataSizeAll#: Total bytes to be received.

uint16_t *rxRingBuffer#: Start address of the receiver ring buffer.

size_t rxRingBufferSize#: Size of the ring buffer.

volatile uint16_t rxRingBufferHead#: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail#: Index for the user to get data from the ring buffer.

flexio_a_format_transfer_callback_t callback#: Callback function.

void *userData#: A-format callback function parameter.

volatile uint8_t txState#: TX transfer state.

volatile uint8_t rxState#: RX transfer state

struct _flexio_a_format_type#: #include <fsl_flexio_a-format.h>

Define FlexIO A_FORMAT access structure typedef.

struct _flexio_a_format_config#: #include <fsl_flexio_a-format.h>

Define FlexIO A_FORMAT user configuration structure.

struct _flexio_a_format_transfer#: #include <fsl_flexio_a-format.h>

Define FlexIO A-format transfer structure.

struct _flexio_a_format_handle#: #include <fsl_flexio_a-format.h>

Define FLEXIO A-format handle structure.

union __unnamed84__#

Public Members

uint16_t *data#: The buffer of data to be transfer.

uint16_t *rxData#: The buffer to receive data.

const uint16_t *txData#: The buffer of data to be sent.

FlexIO Camera Driver#

void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config)#

Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera.

Parameters:

base – Pointer to FLEXIO_CAMERA_Type structure
config – Pointer to flexio_camera_config_t structure

void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base)#

Resets the FLEXIO_CAMERA shifer and timer config.

Note

After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module.

Parameters:

base – Pointer to FLEXIO_CAMERA_Type structure

void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config)#

Gets the default configuration to configure the FlexIO Camera. The configuration can be used directly for calling the FLEXIO_CAMERA_Init(). Example:

flexio_camera_config_t config;
FLEXIO_CAMERA_GetDefaultConfig(&userConfig);

Parameters:

config – Pointer to the flexio_camera_config_t structure

static inline void FLEXIO_CAMERA_Enable(FLEXIO_CAMERA_Type *base, bool enable)#

Enables/disables the FlexIO Camera module operation.

Parameters:

base – Pointer to the FLEXIO_CAMERA_Type
enable – True to enable, false does not have any effect.

uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base)#

Gets the FlexIO Camera status flags.

Parameters:

base – Pointer to FLEXIO_CAMERA_Type structure

Returns:

FlexIO shifter status flags

FLEXIO_SHIFTSTAT_SSF_MASK
0

void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask)#

Clears the receive buffer full flag manually.

Parameters:

base – Pointer to the device.
mask – status flag The parameter can be any combination of the following values:
- kFLEXIO_CAMERA_RxDataRegFullFlag
- kFLEXIO_CAMERA_RxErrorFlag

void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base)#

Switches on the interrupt for receive buffer full event.

Parameters:

base – Pointer to the device.

void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base)#

Switches off the interrupt for receive buffer full event.

Parameters:

base – Pointer to the device.

static inline void FLEXIO_CAMERA_EnableRxDMA(FLEXIO_CAMERA_Type *base, bool enable)#

Enables/disables the FlexIO Camera receive DMA.

The FlexIO Camera mode can’t work without the DMA or eDMA support, Usually, it needs at least two DMA or eDMA channels, one for transferring data from Camera, such as 0V7670 to FlexIO buffer, another is for transferring data from FlexIO buffer to LCD.

Parameters:

base – Pointer to FLEXIO_CAMERA_Type structure
enable – True to enable, false to disable.

static inline uint32_t FLEXIO_CAMERA_GetRxBufferAddress(FLEXIO_CAMERA_Type *base)#

Gets the data from the receive buffer.

Parameters:

base – Pointer to the device.

Returns:

data Pointer to the buffer that keeps the data with count of base->shifterCount .

FSL_FLEXIO_CAMERA_DRIVER_VERSION#: FlexIO Camera driver version.

Error codes for the Camera driver.

Values:

enumerator kStatus_FLEXIO_CAMERA_RxBusy#: Receiver is busy.

enumerator kStatus_FLEXIO_CAMERA_RxIdle#: Camera receiver is idle.

enum _flexio_camera_status_flags#

Define FlexIO Camera status mask.

Values:

enumerator kFLEXIO_CAMERA_RxDataRegFullFlag#: Receive buffer full flag.

enumerator kFLEXIO_CAMERA_RxErrorFlag#: Receive buffer error flag.

typedef struct _flexio_camera_type FLEXIO_CAMERA_Type#: Define structure of configuring the FlexIO Camera device.

typedef struct _flexio_camera_config flexio_camera_config_t#: Define FlexIO Camera user configuration structure.

typedef struct _flexio_camera_transfer flexio_camera_transfer_t#: Define FlexIO Camera transfer structure.

FLEXIO_CAMERA_PARALLEL_DATA_WIDTH#: Define the Camera CPI interface is constantly 8-bit width.

struct _flexio_camera_type#

#include <fsl_flexio_camera.h>

Define structure of configuring the FlexIO Camera device.

Public Members

FLEXIO_Type *flexioBase#: FlexIO module base address.

uint32_t datPinStartIdx#: First data pin (D0) index for flexio_camera. Then the successive following FLEXIO_CAMERA_DATA_WIDTH-1 pins are used as D1-D7.

uint32_t pclkPinIdx#: Pixel clock pin (PCLK) index for flexio_camera.

uint32_t hrefPinIdx#: Horizontal sync pin (HREF) index for flexio_camera.

uint8_t shifterStartIdx#: First shifter index used for flexio_camera data FIFO.

uint32_t shifterCount#: The count of shifters that are used as flexio_camera data FIFO.

uint32_t timerIdx#: Timer index used for flexio_camera in FlexIO.

struct _flexio_camera_config#

#include <fsl_flexio_camera.h>

Define FlexIO Camera user configuration structure.

Public Members

bool enablecamera#: Enable/disable FlexIO Camera TX & RX.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode

bool enableInDebug#: Enable/disable FlexIO operation in debug mode

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

struct _flexio_camera_transfer#

#include <fsl_flexio_camera.h>

Define FlexIO Camera transfer structure.

Public Members

uint32_t dataAddress#: Transfer buffer

uint32_t dataNum#: Transfer num

FlexIO Driver#

void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig)#

Gets the default configuration to configure the FlexIO module. The configuration can used directly to call the FLEXIO_Configure().

Example:

flexio_config_t config;
FLEXIO_GetDefaultConfig(&config);

Parameters:

userConfig – pointer to flexio_config_t structure

void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)#

Configures the FlexIO with a FlexIO configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig().

Example

flexio_config_t config = {
.enableFlexio = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false
};
FLEXIO_Configure(base, &config);

Parameters:

base – FlexIO peripheral base address
userConfig – pointer to flexio_config_t structure

void FLEXIO_Deinit(FLEXIO_Type *base)#

Gates the FlexIO clock. Call this API to stop the FlexIO clock.

Note

After calling this API, call the FLEXO_Init to use the FlexIO module.

Parameters:

base – FlexIO peripheral base address

uint32_t FLEXIO_GetInstance(FLEXIO_Type *base)#

Get instance number for FLEXIO module.

Parameters:

base – FLEXIO peripheral base address.

void FLEXIO_Reset(FLEXIO_Type *base)#

Resets the FlexIO module.

Parameters:

base – FlexIO peripheral base address

static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable)#

Enables the FlexIO module operation.

Parameters:

base – FlexIO peripheral base address
enable – true to enable, false to disable.

static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base)#

Reads the input data on each of the FlexIO pins.

Parameters:

base – FlexIO peripheral base address

Returns:

FlexIO pin input data

static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base)#

Gets the current state pointer for state mode use.

Parameters:

base – FlexIO peripheral base address

Returns:

current State pointer

void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)#

Configures the shifter with the shifter configuration. The configuration structure covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper mode, select which timer controls the shifter to shift, whether to generate start bit/stop bit, and the polarity of start bit and stop bit.

Example

flexio_shifter_config_t config = {
.timerSelect = 0,
.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinPolarity = kFLEXIO_PinActiveLow,
.shifterMode = kFLEXIO_ShifterModeTransmit,
.inputSource = kFLEXIO_ShifterInputFromPin,
.shifterStop = kFLEXIO_ShifterStopBitHigh,
.shifterStart = kFLEXIO_ShifterStartBitLow
};
FLEXIO_SetShifterConfig(base, &config);

Parameters:

base – FlexIO peripheral base address
index – Shifter index
shifterConfig – Pointer to flexio_shifter_config_t structure

void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig)#

Configures the timer with the timer configuration. The configuration structure covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper mode, select trigger source for timer and the timer pin output and the timing for timer.

Example

flexio_timer_config_t config = {
.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0),
.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow,
.triggerSource = kFLEXIO_TimerTriggerSourceInternal,
.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection,
.pinSelect = 0,
.pinPolarity = kFLEXIO_PinActiveHigh,
.timerMode = kFLEXIO_TimerModeDual8BitBaudBit,
.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset,
.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput,
.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput,
.timerDisable = kFLEXIO_TimerDisableOnTimerCompare,
.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh,
.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable,
.timerStart = kFLEXIO_TimerStartBitEnabled
};
FLEXIO_SetTimerConfig(base, &config);

Parameters:

base – FlexIO peripheral base address
index – Timer index
timerConfig – Pointer to the flexio_timer_config_t structure

static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)#

This function set the value of the prescaler on flexio channels.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.
index – Timer index
clocksource – Set clock value

static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)#

Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask)#

Disables the shifter status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)#

Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask)#

Disables the shifter error interrupt. The interrupt won’t generate when the corresponding SEF is set.

Note

For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)#

Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask)#

Disables the timer status interrupt. The interrupt won’t generate when the corresponding SSF is set.

Note

For multiple timer status interrupt enable, for example, two timer status enable, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base)#

Gets the shifter status flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Shifter status flags

static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask)#

Clears the shifter status flags.

Note

For clearing multiple shifter status flags, for example, two shifter status flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base)#

Gets the shifter error flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Shifter error flags

static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask)#

Clears the shifter error flags.

Note

For clearing multiple shifter error flags, for example, two shifter error flags, can calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter error mask which can be calculated by (1 << shifter index)

static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base)#

Gets the timer status flags.

Parameters:

base – FlexIO peripheral base address

Returns:

Timer status flags

static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask)#

Clears the timer status flags.

Note

For clearing multiple timer status flags, for example, two timer status flags, can calculate the mask by using ((1 << timer index0) | (1 << timer index1))

Parameters:

base – FlexIO peripheral base address
mask – The timer status mask which can be calculated by (1 << timer index)

static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable)#

Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set.

Note

For multiple shifter status DMA enables, for example, calculate the mask by using ((1 << shifter index0) | (1 << shifter index1))

Parameters:

base – FlexIO peripheral base address
mask – The shifter status mask which can be calculated by (1 << shifter index)
enable – True to enable, false to disable.

uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index)#

Gets the shifter buffer address for the DMA transfer usage.

Parameters:

base – FlexIO peripheral base address
type – Shifter type of flexio_shifter_buffer_type_t
index – Shifter index

Returns:

Corresponding shifter buffer index

status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr)#

Registers the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.
handle – Pointer to the handler for FlexIO simulated peripheral.
isr – FlexIO simulated peripheral interrupt handler.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_UnregisterHandleIRQ(void *base)#

Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral.

Parameters:

base – Pointer to the FlexIO simulated peripheral type.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)#

Sets the output level of the multiple FLEXIO pins to the logic 0.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)#

Sets the output level of the multiple FLEXIO pins to the logic 1.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)#

Reverses the current output logic of the multiple FLEXIO pins.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)#

Sets the output level of the FLEXIO pins to the logic 1 or 0.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.
output – FLEXIO pin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)#

Enables the FLEXIO output pin function.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)#

Reads the current input value of the FLEXIO pin.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

Return values:

FLEXIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.

static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)#

Gets the FLEXIO input pin status.

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.

Return values:

FLEXIO – port input status

0: corresponding pin input capture no status.
1: corresponding pin input capture rising or falling edge.

static inline void FLEXIO_SetPinLevel(FLEXIO_Type *base, uint8_t pin, bool level)#

Sets the FLEXIO output pin level.

Parameters:

base – FlexIO peripheral base address
pin – FlexIO pin number.
level – FlexIO output pin level to set, can be either 0 or 1.

static inline bool FLEXIO_GetPinOverride(const FLEXIO_Type *const base, uint8_t pin)#

Gets the enabled status of a FLEXIO output pin.

Parameters:

base – FlexIO peripheral base address
pin – FlexIO pin number.

Return values:

FlexIO – port enabled status

0: corresponding output pin is in disabled state.
1: corresponding output pin is in enabled state.

static inline void FLEXIO_ConfigPinOverride(FLEXIO_Type *base, uint8_t pin, bool enabled)#

Enables or disables a FLEXIO output pin.

Parameters:

base – FlexIO peripheral base address
pin – Flexio pin number.
enabled – Enable or disable the FlexIO pin.

static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)#

Clears the multiple FLEXIO input pins status.

Parameters:

base – FlexIO peripheral base address
mask – FLEXIO pin number mask

FSL_FLEXIO_DRIVER_VERSION#: FlexIO driver version.

enum _flexio_timer_trigger_polarity#

Define time of timer trigger polarity.

Values:

enumerator kFLEXIO_TimerTriggerPolarityActiveHigh#: Active high.

enumerator kFLEXIO_TimerTriggerPolarityActiveLow#: Active low.

enum _flexio_timer_trigger_source#

Define type of timer trigger source.

Values:

enumerator kFLEXIO_TimerTriggerSourceExternal#: External trigger selected.

enumerator kFLEXIO_TimerTriggerSourceInternal#: Internal trigger selected.

enum _flexio_pin_config#

Define type of timer/shifter pin configuration.

Values:

enumerator kFLEXIO_PinConfigOutputDisabled#: Pin output disabled.

enumerator kFLEXIO_PinConfigOpenDrainOrBidirection#: Pin open drain or bidirectional output enable.

enumerator kFLEXIO_PinConfigBidirectionOutputData#: Pin bidirectional output data.

enumerator kFLEXIO_PinConfigOutput#: Pin output.

enum _flexio_pin_polarity#

Definition of pin polarity.

Values:

enumerator kFLEXIO_PinActiveHigh#: Active high.

enumerator kFLEXIO_PinActiveLow#: Active low.

enum _flexio_timer_mode#

Define type of timer work mode.

Values:

enumerator kFLEXIO_TimerModeDisabled#: Timer Disabled.

enumerator kFLEXIO_TimerModeDual8BitBaudBit#: Dual 8-bit counters baud/bit mode.

enumerator kFLEXIO_TimerModeDual8BitPWM#: Dual 8-bit counters PWM mode.

enumerator kFLEXIO_TimerModeSingle16Bit#: Single 16-bit counter mode.

enumerator kFLEXIO_TimerModeDual8BitPWMLow#: Dual 8-bit counters PWM Low mode.

enum _flexio_timer_output#

Define type of timer initial output or timer reset condition.

Values:

enumerator kFLEXIO_TimerOutputOneNotAffectedByReset#: Logic one when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputZeroNotAffectedByReset#: Logic zero when enabled and is not affected by timer reset.

enumerator kFLEXIO_TimerOutputOneAffectedByReset#: Logic one when enabled and on timer reset.

enumerator kFLEXIO_TimerOutputZeroAffectedByReset#: Logic zero when enabled and on timer reset.

enum _flexio_timer_decrement_source#

Define type of timer decrement.

Values:

enumerator kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput#: Decrement counter on FlexIO clock, Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput#: Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

enumerator kFLEXIO_TimerDecSrcOnPinInputShiftPinInput#: Decrement counter on Pin input (both edges), Shift clock equals Pin input.

enumerator kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput#: Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

enum _flexio_timer_reset_condition#

Define type of timer reset condition.

Values:

enumerator kFLEXIO_TimerResetNever#: Timer never reset.

enumerator kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput#: Timer reset on Timer Pin equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput#: Timer reset on Timer Trigger equal to Timer Output.

enumerator kFLEXIO_TimerResetOnTimerPinRisingEdge#: Timer reset on Timer Pin rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerRisingEdge#: Timer reset on Trigger rising edge.

enumerator kFLEXIO_TimerResetOnTimerTriggerBothEdge#: Timer reset on Trigger rising or falling edge.

enum _flexio_timer_disable_condition#

Define type of timer disable condition.

Values:

enumerator kFLEXIO_TimerDisableNever#: Timer never disabled.

enumerator kFLEXIO_TimerDisableOnPreTimerDisable#: Timer disabled on Timer N-1 disable.

enumerator kFLEXIO_TimerDisableOnTimerCompare#: Timer disabled on Timer compare.

enumerator kFLEXIO_TimerDisableOnTimerCompareTriggerLow#: Timer disabled on Timer compare and Trigger Low.

enumerator kFLEXIO_TimerDisableOnPinBothEdge#: Timer disabled on Pin rising or falling edge.

enumerator kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh#: Timer disabled on Pin rising or falling edge provided Trigger is high.

enumerator kFLEXIO_TimerDisableOnTriggerFallingEdge#: Timer disabled on Trigger falling edge.

enum _flexio_timer_enable_condition#

Define type of timer enable condition.

Values:

enumerator kFLEXIO_TimerEnabledAlways#: Timer always enabled.

enumerator kFLEXIO_TimerEnableOnPrevTimerEnable#: Timer enabled on Timer N-1 enable.

enumerator kFLEXIO_TimerEnableOnTriggerHigh#: Timer enabled on Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerHighPinHigh#: Timer enabled on Trigger high and Pin high.

enumerator kFLEXIO_TimerEnableOnPinRisingEdge#: Timer enabled on Pin rising edge.

enumerator kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh#: Timer enabled on Pin rising edge and Trigger high.

enumerator kFLEXIO_TimerEnableOnTriggerRisingEdge#: Timer enabled on Trigger rising edge.

enumerator kFLEXIO_TimerEnableOnTriggerBothEdge#: Timer enabled on Trigger rising or falling edge.

enum _flexio_timer_stop_bit_condition#

Define type of timer stop bit generate condition.

Values:

enumerator kFLEXIO_TimerStopBitDisabled#: Stop bit disabled.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompare#: Stop bit is enabled on timer compare.

enumerator kFLEXIO_TimerStopBitEnableOnTimerDisable#: Stop bit is enabled on timer disable.

enumerator kFLEXIO_TimerStopBitEnableOnTimerCompareDisable#: Stop bit is enabled on timer compare and timer disable.

enum _flexio_timer_start_bit_condition#

Define type of timer start bit generate condition.

Values:

enumerator kFLEXIO_TimerStartBitDisabled#: Start bit disabled.

enumerator kFLEXIO_TimerStartBitEnabled#: Start bit enabled.

enum _flexio_timer_output_state#

FlexIO as PWM channel output state.

Values:

enumerator kFLEXIO_PwmLow#: The output state of PWM channel is low

enumerator kFLEXIO_PwmHigh#: The output state of PWM channel is high

enum _flexio_shifter_timer_polarity#

Define type of timer polarity for shifter control.

Values:

enumerator kFLEXIO_ShifterTimerPolarityOnPositive#: Shift on positive edge of shift clock.

enumerator kFLEXIO_ShifterTimerPolarityOnNegitive#: Shift on negative edge of shift clock.

enum _flexio_shifter_mode#

Define type of shifter working mode.

Values:

enumerator kFLEXIO_ShifterDisabled#: Shifter is disabled.

enumerator kFLEXIO_ShifterModeReceive#: Receive mode.

enumerator kFLEXIO_ShifterModeTransmit#: Transmit mode.

enumerator kFLEXIO_ShifterModeMatchStore#: Match store mode.

enumerator kFLEXIO_ShifterModeMatchContinuous#: Match continuous mode.

enumerator kFLEXIO_ShifterModeState#: SHIFTBUF contents are used for storing programmable state attributes.

enumerator kFLEXIO_ShifterModeLogic#: SHIFTBUF contents are used for implementing programmable logic look up table.

enum _flexio_shifter_input_source#

Define type of shifter input source.

Values:

enumerator kFLEXIO_ShifterInputFromPin#: Shifter input from pin.

enumerator kFLEXIO_ShifterInputFromNextShifterOutput#: Shifter input from Shifter N+1.

enum _flexio_shifter_stop_bit#

Define of STOP bit configuration.

Values:

enumerator kFLEXIO_ShifterStopBitDisable#: Disable shifter stop bit.

enumerator kFLEXIO_ShifterStopBitLow#: Set shifter stop bit to logic low level.

enumerator kFLEXIO_ShifterStopBitHigh#: Set shifter stop bit to logic high level.

enum _flexio_shifter_start_bit#

Define type of START bit configuration.

Values:

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable#: Disable shifter start bit, transmitter loads data on enable.

enumerator kFLEXIO_ShifterStartBitDisabledLoadDataOnShift#: Disable shifter start bit, transmitter loads data on first shift.

enumerator kFLEXIO_ShifterStartBitLow#: Set shifter start bit to logic low level.

enumerator kFLEXIO_ShifterStartBitHigh#: Set shifter start bit to logic high level.

enum _flexio_shifter_buffer_type#

Define FlexIO shifter buffer type.

Values:

enumerator kFLEXIO_ShifterBuffer#: Shifter Buffer N Register.

enumerator kFLEXIO_ShifterBufferBitSwapped#: Shifter Buffer N Bit Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferByteSwapped#: Shifter Buffer N Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferBitByteSwapped#: Shifter Buffer N Bit Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleByteSwapped#: Shifter Buffer N Nibble Byte Swapped Register.

enumerator kFLEXIO_ShifterBufferHalfWordSwapped#: Shifter Buffer N Half Word Swapped Register.

enumerator kFLEXIO_ShifterBufferNibbleSwapped#: Shifter Buffer N Nibble Swapped Register.

enum _flexio_gpio_direction#

FLEXIO gpio direction definition.

Values:

enumerator kFLEXIO_DigitalInput#: Set current pin as digital input

enumerator kFLEXIO_DigitalOutput#: Set current pin as digital output

enum _flexio_pin_input_config#

FLEXIO gpio input config.

Values:

enumerator kFLEXIO_InputInterruptDisabled#: Interrupt request is disabled.

enumerator kFLEXIO_InputInterruptEnable#: Interrupt request is enable.

enumerator kFLEXIO_FlagRisingEdgeEnable#: Input pin flag on rising edge.

enumerator kFLEXIO_FlagFallingEdgeEnable#: Input pin flag on falling edge.

typedef enum _flexio_timer_trigger_polarity flexio_timer_trigger_polarity_t#: Define time of timer trigger polarity.

typedef enum _flexio_timer_trigger_source flexio_timer_trigger_source_t#: Define type of timer trigger source.

typedef enum _flexio_pin_config flexio_pin_config_t#: Define type of timer/shifter pin configuration.

typedef enum _flexio_pin_polarity flexio_pin_polarity_t#: Definition of pin polarity.

typedef enum _flexio_timer_mode flexio_timer_mode_t#: Define type of timer work mode.

typedef enum _flexio_timer_output flexio_timer_output_t#: Define type of timer initial output or timer reset condition.

typedef enum _flexio_timer_decrement_source flexio_timer_decrement_source_t#: Define type of timer decrement.

typedef enum _flexio_timer_reset_condition flexio_timer_reset_condition_t#: Define type of timer reset condition.

typedef enum _flexio_timer_disable_condition flexio_timer_disable_condition_t#: Define type of timer disable condition.

typedef enum _flexio_timer_enable_condition flexio_timer_enable_condition_t#: Define type of timer enable condition.

typedef enum _flexio_timer_stop_bit_condition flexio_timer_stop_bit_condition_t#: Define type of timer stop bit generate condition.

typedef enum _flexio_timer_start_bit_condition flexio_timer_start_bit_condition_t#: Define type of timer start bit generate condition.

typedef enum _flexio_timer_output_state flexio_timer_output_state_t#: FlexIO as PWM channel output state.

typedef enum _flexio_shifter_timer_polarity flexio_shifter_timer_polarity_t#: Define type of timer polarity for shifter control.

typedef enum _flexio_shifter_mode flexio_shifter_mode_t#: Define type of shifter working mode.

typedef enum _flexio_shifter_input_source flexio_shifter_input_source_t#: Define type of shifter input source.

typedef enum _flexio_shifter_stop_bit flexio_shifter_stop_bit_t#: Define of STOP bit configuration.

typedef enum _flexio_shifter_start_bit flexio_shifter_start_bit_t#: Define type of START bit configuration.

typedef enum _flexio_shifter_buffer_type flexio_shifter_buffer_type_t#: Define FlexIO shifter buffer type.

typedef struct _flexio_config_ flexio_config_t#: Define FlexIO user configuration structure.

typedef struct _flexio_timer_config flexio_timer_config_t#: Define FlexIO timer configuration structure.

typedef struct _flexio_shifter_config flexio_shifter_config_t#: Define FlexIO shifter configuration structure.

typedef enum _flexio_gpio_direction flexio_gpio_direction_t#: FLEXIO gpio direction definition.

typedef enum _flexio_pin_input_config flexio_pin_input_config_t#: FLEXIO gpio input config.

typedef struct _flexio_gpio_config flexio_gpio_config_t#

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

typedef void (*flexio_isr_t)(void *base, void *handle)#: typedef for FlexIO simulated driver interrupt handler.

FLEXIO_Type *const s_flexioBases[]#: Pointers to flexio bases for each instance.

const clock_ip_name_t s_flexioClocks[]#: Pointers to flexio clocks for each instance.

void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)#

Configure a FLEXIO pin used by the board.

To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. Then, call the FLEXIO_SetPinConfig() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalInput,
  0U,
  kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
}
Define a digital output pin configuration,
flexio_gpio_config_t config =
{
  kFLEXIO_DigitalOutput,
  0U,
  0U
}

Parameters:

base – FlexIO peripheral base address
pin – FLEXIO pin number.
config – FLEXIO pin configuration pointer.

FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x)#: Calculate FlexIO timer trigger.

FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x)#

FLEXIO_TIMER_TRIGGER_SEL_TIMn(x)#

struct _flexio_config_#

#include <fsl_flexio.h>

Define FlexIO user configuration structure.

Public Members

bool enableFlexio#: Enable/disable FlexIO module

bool enableInDoze#: Enable/disable FlexIO operation in doze mode

bool enableInDebug#: Enable/disable FlexIO operation in debug mode

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

struct _flexio_timer_config#

#include <fsl_flexio.h>

Define FlexIO timer configuration structure.

Public Members

uint32_t triggerSelect#: The internal trigger selection number using MACROs.

flexio_timer_trigger_polarity_t triggerPolarity#: Trigger Polarity.

flexio_timer_trigger_source_t triggerSource#: Trigger Source, internal (see ‘trgsel’) or external.

flexio_pin_config_t pinConfig#: Timer Pin Configuration.

uint32_t pinSelect#: Timer Pin number Select.

flexio_pin_polarity_t pinPolarity#: Timer Pin Polarity.

flexio_timer_mode_t timerMode#: Timer work Mode.

flexio_timer_output_t timerOutput#: Configures the initial state of the Timer Output and whether it is affected by the Timer reset.

flexio_timer_decrement_source_t timerDecrement#: Configures the source of the Timer decrement and the source of the Shift clock.

flexio_timer_reset_condition_t timerReset#: Configures the condition that causes the timer counter (and optionally the timer output) to be reset.

flexio_timer_disable_condition_t timerDisable#: Configures the condition that causes the Timer to be disabled and stop decrementing.

flexio_timer_enable_condition_t timerEnable#: Configures the condition that causes the Timer to be enabled and start decrementing.

flexio_timer_stop_bit_condition_t timerStop#: Timer STOP Bit generation.

flexio_timer_start_bit_condition_t timerStart#: Timer STRAT Bit generation.

uint32_t timerCompare#: Value for Timer Compare N Register.

struct _flexio_shifter_config#

#include <fsl_flexio.h>

Define FlexIO shifter configuration structure.

Public Members

uint32_t timerSelect#: Selects which Timer is used for controlling the logic/shift register and generating the Shift clock.

flexio_shifter_timer_polarity_t timerPolarity#: Timer Polarity.

flexio_pin_config_t pinConfig#: Shifter Pin Configuration.

uint32_t pinSelect#: Shifter Pin number Select.

flexio_pin_polarity_t pinPolarity#: Shifter Pin Polarity.

flexio_shifter_mode_t shifterMode#: Configures the mode of the Shifter.

uint32_t parallelWidth#: Configures the parallel width when using parallel mode.

flexio_shifter_input_source_t inputSource#: Selects the input source for the shifter.

flexio_shifter_stop_bit_t shifterStop#: Shifter STOP bit.

flexio_shifter_start_bit_t shifterStart#: Shifter START bit.

struct _flexio_gpio_config#

#include <fsl_flexio.h>

The FLEXIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, use inputConfig param. If configured as an output pin, use outputLogic.

Public Members

flexio_gpio_direction_t pinDirection#: FLEXIO pin direction, input or output

uint8_t outputLogic#: Set a default output logic, which has no use in input

uint8_t inputConfig#: Set an input config

FlexIO eDMA I2S Driver#

void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)#

Initializes the FlexIO I2S eDMA handle.

This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle)#

Initializes the FlexIO I2S Rx eDMA handle.

This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional APIs. Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer.
callback – FlexIO I2S eDMA callback function called while finished a block.
userData – User parameter for callback.
dmaHandle – eDMA handle for FlexIO I2S. This handle is a static value allocated by users.

void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)#

Configures the FlexIO I2S Tx audio format.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred. This function also sets the eDMA parameter according to format.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S eDMA handle pointer
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode.

status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)#

Performs a non-blocking FlexIO I2S transfer using DMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.

Return values:

kStatus_Success – Start a FlexIO I2S eDMA send successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_TxBusy – FlexIO I2S is busy sending data.

status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, flexio_i2s_transfer_t *xfer)#

Performs a non-blocking FlexIO I2S receive using eDMA.

Note

This interface returned immediately after transfer initiates. Users should call FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
xfer – Pointer to DMA transfer structure.

Return values:

kStatus_Success – Start a FlexIO I2S eDMA receive successfully.
kStatus_InvalidArgument – The input arguments is invalid.
kStatus_RxBusy – FlexIO I2S is busy receiving data.

void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)#

Aborts a FlexIO I2S transfer using eDMA.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.

void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle)#

Aborts a FlexIO I2S receive using eDMA.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.

status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)#

Gets the remaining bytes to be sent.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count)#

Get the remaining bytes to be received.

Parameters:

base – FlexIO I2S peripheral base address.
handle – FlexIO I2S DMA handle pointer.
count – Bytes received.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION#: FlexIO I2S EDMA driver version 2.1.9.

typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t#

typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, status_t status, void *userData)#: FlexIO I2S eDMA transfer callback function for finish and error.

struct _flexio_i2s_edma_handle#

#include <fsl_flexio_i2s_edma.h>

FlexIO I2S DMA transfer handle, users should not touch the content of the handle.

Public Members

edma_handle_t *dmaHandle#: DMA handler for FlexIO I2S send

uint8_t bytesPerFrame#: Bytes in a frame

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

uint32_t state#: Internal state for FlexIO I2S eDMA transfer

flexio_i2s_edma_callback_t callback#: Callback for users while transfer finish or error occurred

void *userData#: User callback parameter

edma_tcd_t tcd[(4U) + 1U]#: TCD pool for eDMA transfer.

flexio_i2s_transfer_t queue[(4U)]#: Transfer queue storing queued transfer.

size_t transferSize[(4U)]#: Data bytes need to transfer

volatile uint8_t queueUser#: Index for user to queue transfer.

volatile uint8_t queueDriver#: Index for driver to get the transfer data and size

FlexIO eDMA MCU Interface LCD Driver#

status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle, flexio_mculcd_edma_transfer_callback_t callback, void *userData, edma_handle_t *txDmaHandle, edma_handle_t *rxDmaHandle)#

Initializes the FLEXO MCULCD master eDMA handle.

This function initializes the FLEXO MCULCD master eDMA handle which can be used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD instance, call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_MCULCD_Type structure.
handle – Pointer to flexio_mculcd_edma_handle_t structure to store the transfer state.
callback – MCULCD transfer complete callback, NULL means no callback.
userData – callback function parameter.
txDmaHandle – User requested eDMA handle for FlexIO MCULCD eDMA TX, the DMA request source of this handle should be the first of TX shifters.
rxDmaHandle – User requested eDMA handle for FlexIO MCULCD eDMA RX, the DMA request source of this handle should be the last of RX shifters.

Return values:

kStatus_Success – Successfully create the handle.

status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle, flexio_mculcd_transfer_t *xfer)#

Performs a non-blocking FlexIO MCULCD transfer using eDMA.

This function returns immediately after transfer initiates. To check whether the transfer is completed, user could:

Use the transfer completed callback;
Polling function FLEXIO_MCULCD_GetTransferCountEDMA

Parameters:

base – pointer to FLEXIO_MCULCD_Type structure.
handle – pointer to flexio_mculcd_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO MCULCD transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_MCULCD_Busy – FlexIO MCULCD is not idle, it is running another transfer.

void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle)#

Aborts a FlexIO MCULCD transfer using eDMA.

Parameters:

base – pointer to FLEXIO_MCULCD_Type structure.
handle – FlexIO MCULCD eDMA handle pointer.

status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle, size_t *count)#

Gets the remaining bytes for FlexIO MCULCD eDMA transfer.

Parameters:

base – pointer to FLEXIO_MCULCD_Type structure.
handle – FlexIO MCULCD eDMA handle pointer.
count – Number of count transferred so far by the eDMA transaction.

Return values:

kStatus_Success – Get the transferred count Successfully.
kStatus_NoTransferInProgress – No transfer in process.

typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t#: typedef for flexio_mculcd_edma_handle_t in advance.

typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle, status_t status, void *userData)#

FlexIO MCULCD master callback for transfer complete.

When transfer finished, the callback function is called and returns the status as kStatus_FLEXIO_MCULCD_Idle.

FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION#: FlexIO MCULCD EDMA driver version.

struct _flexio_mculcd_edma_handle#

#include <fsl_flexio_mculcd_edma.h>

FlexIO MCULCD eDMA transfer handle, users should not touch the content of the handle.

Public Members

FLEXIO_MCULCD_Type *base#: Pointer to the FLEXIO_MCULCD_Type.

uint8_t txShifterNum#: Number of shifters used for TX.

uint8_t rxShifterNum#: Number of shifters used for RX.

uint32_t minorLoopBytes#: eDMA transfer minor loop bytes.

edma_modulo_t txEdmaModulo#: Modulo value for the FlexIO shifter buffer access.

edma_modulo_t rxEdmaModulo#: Modulo value for the FlexIO shifter buffer access.

uint32_t dataAddrOrSameValue#: When sending the same value for many times, this is the value to send. When writing or reading array, this is the address of the data array.

size_t dataCount#: Total count to be transferred.

volatile size_t remainingCount#: Remaining count still not transfered.

volatile uint32_t state#: FlexIO MCULCD driver internal state.

edma_handle_t *txDmaHandle#: DMA handle for MCULCD TX

edma_handle_t *rxDmaHandle#: DMA handle for MCULCD RX

flexio_mculcd_edma_transfer_callback_t completionCallback#: Callback for MCULCD DMA transfer

void *userData#: User Data for MCULCD DMA callback

FlexIO eDMA SPI Driver#

status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_master_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)#

Initializes the FlexIO SPI master eDMA handle.

This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional APIs. For a specified FlexIO SPI instance, call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, flexio_spi_transfer_t *xfer)#

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)#

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.

status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, size_t *count)#

Gets the number of bytes transferred so far using FlexIO SPI master eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.

static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_slave_edma_transfer_callback_t callback, void *userData, edma_handle_t *txHandle, edma_handle_t *rxHandle)#

Initializes the FlexIO SPI slave eDMA handle.

This function initializes the FlexIO SPI slave eDMA handle.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
callback – SPI callback, NULL means no callback.
userData – callback function parameter.
txHandle – User requested eDMA handle for FlexIO SPI TX eDMA transfer.
rxHandle – User requested eDMA handle for FlexIO SPI RX eDMA transfer.

status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, flexio_spi_transfer_t *xfer)#

Performs a non-blocking FlexIO SPI transfer using eDMA.

Note

This interface returns immediately after transfer initiates. Call FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and check whether the FlexIO SPI transfer is finished.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
xfer – Pointer to FlexIO SPI transfer structure.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – FlexIO SPI is not idle, is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle)#

Aborts a FlexIO SPI transfer using eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, size_t *count)#

Gets the number of bytes transferred so far using FlexIO SPI slave eDMA.

Parameters:

base – Pointer to FLEXIO_SPI_Type structure.
handle – FlexIO SPI eDMA handle pointer.
count – Number of bytes transferred so far by the non-blocking transaction.

FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION#: FlexIO SPI EDMA driver version.

typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t#: typedef for flexio_spi_master_edma_handle_t in advance.

typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t#: Slave handle is the same with master handle.

typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle, status_t status, void *userData)#: FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle, status_t status, void *userData)#: FlexIO SPI slave callback for finished transmit.

struct _flexio_spi_master_edma_handle#

#include <fsl_flexio_spi_edma.h>

FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.

Public Members

size_t transferSize#: Total bytes to be transferred.

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

bool txInProgress#: Send transfer in progress

bool rxInProgress#: Receive transfer in progress

edma_handle_t *txHandle#: DMA handler for SPI send

edma_handle_t *rxHandle#: DMA handler for SPI receive

flexio_spi_master_edma_transfer_callback_t callback#: Callback for SPI DMA transfer

void *userData#: User Data for SPI DMA callback

FlexIO eDMA UART Driver#

status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_edma_transfer_callback_t callback, void *userData, edma_handle_t *txEdmaHandle, edma_handle_t *rxEdmaHandle)#

Initializes the UART handle which is used in transactional functions.

Parameters:

base – Pointer to FLEXIO_UART_Type.
handle – Pointer to flexio_uart_edma_handle_t structure.
callback – The callback function.
userData – The parameter of the callback function.
rxEdmaHandle – User requested DMA handle for RX DMA transfer.
txEdmaHandle – User requested DMA handle for TX DMA transfer.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO SPI eDMA type/handle table out of range.

status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)#

Sends data using eDMA.

This function sends data using eDMA. This is a non-blocking function, which returns right away. When all data is sent out, the send callback function is called.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – UART handle pointer.
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_FLEXIO_UART_TxBusy – Previous transfer on going.

status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, flexio_uart_transfer_t *xfer)#

Receives data using eDMA.

This function receives data using eDMA. This is a non-blocking function, which returns right away. When all data is received, the receive callback function is called.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
xfer – UART eDMA transfer structure, see flexio_uart_transfer_t.

Return values:

kStatus_Success – if succeed, others failed.
kStatus_UART_RxBusy – Previous transfer on going.

void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)#

Aborts the sent data which using eDMA.

This function aborts sent data which using eDMA.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure

void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle)#

Aborts the receive data which using eDMA.

This function aborts the receive data which using eDMA.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure

status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)#

Gets the number of bytes sent out.

This function gets the number of bytes sent out.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count)#

Gets the number of bytes received.

This function gets the number of bytes received.

Parameters:

base – Pointer to FLEXIO_UART_Type
handle – Pointer to flexio_uart_edma_handle_t structure
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

FSL_FLEXIO_UART_EDMA_DRIVER_VERSION#: FlexIO UART EDMA driver version.

typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t#

typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, status_t status, void *userData)#: UART transfer callback function.

struct _flexio_uart_edma_handle#

#include <fsl_flexio_uart_edma.h>

UART eDMA handle.

Public Members

flexio_uart_edma_transfer_callback_t callback#: Callback function.

void *userData#: UART callback function parameter.

size_t txDataSizeAll#: Total bytes to be sent.

size_t rxDataSizeAll#: Total bytes to be received.

edma_handle_t *txEdmaHandle#: The eDMA TX channel used.

edma_handle_t *rxEdmaHandle#: The eDMA RX channel used.

uint8_t nbytes#: eDMA minor byte transfer count initially configured.

volatile uint8_t txState#: TX transfer state.

volatile uint8_t rxState#: RX transfer state

FlexIO I2C Master Driver#

status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base)#

Make sure the bus isn’t already pulled down.

Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure..

Return values:

kStatus_Success –
kStatus_FLEXIO_I2C_Busy –

status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)#

Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C hardware configuration.

Example

FLEXIO_I2C_Type base = {
.flexioBase = FLEXIO,
.SDAPinIndex = 0,
.SCLPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_i2c_master_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 100000
};
FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz);

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
masterConfig – Pointer to flexio_i2c_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Initialization successful
kStatus_InvalidArgument – The source clock exceed upper range limitation

void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)#

De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master shifer and timer config, module can’t work unless the FLEXIO_I2C_MasterInit is called.

Parameters:

base – pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)#

Gets the default configuration to configure the FlexIO module. The configuration can be used directly for calling the FLEXIO_I2C_MasterInit().

Example:

flexio_i2c_master_config_t config;
FLEXIO_I2C_MasterGetDefaultConfig(&config);

Parameters:

masterConfig – Pointer to flexio_i2c_master_config_t structure.

static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)#

Enables/disables the FlexIO module operation.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
enable – Pass true to enable module, false does not have any effect.

uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)#

Gets the FlexIO I2C master status flags.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure

Returns:

Status flag, use status flag to AND _flexio_i2c_master_status_flags can get the related status.

void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)#

Clears the FlexIO I2C master status flags.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
- kFLEXIO_I2C_RxFullFlag
- kFLEXIO_I2C_ReceiveNakFlag

void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)#

Enables the FlexIO i2c master interrupt requests.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source. Currently only one interrupt request source:
- kFLEXIO_I2C_TransferCompleteInterruptEnable

void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)#

Disables the FlexIO I2C master interrupt requests.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
mask – Interrupt source.

void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)#

Sets the FlexIO I2C master transfer baudrate.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
baudRate_Bps – the baud rate value in HZ
srcClock_Hz – source clock in HZ

void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)#

Sends START + 7-bit address to the bus.

Note

This API should be called when the transfer configuration is ready to send a START signal and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address is put into the data register but the address transfer is not finished on the bus. Ensure that the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
address – 7-bit address.
direction – transfer direction. This parameter is one of the values in flexio_i2c_direction_t:
- kFLEXIO_I2C_Write: Transmit
- kFLEXIO_I2C_Read: Receive

void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)#

Sends the stop signal on the bus.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)#

Sends the repeated start signal on the bus.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)#

Sends the stop signal when transfer is still on-going.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)#

Configures the sent ACK/NAK for the following byte.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
enable – True to configure send ACK, false configure to send NAK.

status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count)#

Sets the number of bytes to be transferred from a start signal to a stop signal.

Note

Call this API before a transfer begins because the timer generates a number of clocks according to the number of bytes that need to be transferred.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
count – Number of bytes need to be transferred from a start signal to a re-start/stop signal

Return values:

kStatus_Success – Successfully configured the count.
kStatus_InvalidArgument – Input argument is invalid.

static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data)#

Writes one byte of data to the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is put into the data register but the data transfer is not finished on the bus. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
data – a byte of data.

static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base)#

Reads one byte of data from the I2C bus.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the data is ready in the register.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.

Returns:

data byte read.

status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)#

Sends a buffer of data in bytes.

Note

This function blocks via polling until all bytes have been sent.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
txBuff – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Nak – Receive NAK during writing data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)#

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
rxBuff – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)#

Performs a master polling transfer on the I2C bus.

Note

The API does not return until the transfer succeeds or fails due to receiving NAK.

Parameters:

base – pointer to FLEXIO_I2C_Type structure.
xfer – pointer to flexio_i2c_master_transfer_t structure.

Returns:

status of status_t.

status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_callback_t callback, void *userData)#

Initializes the I2C handle which is used in transactional functions.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure to store the transfer state.
callback – Pointer to user callback function.
userData – User param passed to the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/isr table out of range.

status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, flexio_i2c_master_transfer_t *xfer)#

Performs a master interrupt non-blocking transfer on the I2C bus.

Note

The API returns immediately after the transfer initiates. Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state
xfer – pointer to flexio_i2c_master_transfer_t structure

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_FLEXIO_I2C_Busy – FlexIO I2C is not idle, is running another transfer.

status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)#

Gets the master transfer status during a interrupt non-blocking transfer.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure.
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)#

Aborts an interrupt non-blocking transfer early.

Note

This API can be called at any time when an interrupt non-blocking transfer initiates to abort the transfer early.

Parameters:

base – Pointer to FLEXIO_I2C_Type structure
handle – Pointer to flexio_i2c_master_handle_t structure which stores the transfer state

void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)#

Master interrupt handler.

Parameters:

i2cType – Pointer to FLEXIO_I2C_Type structure
i2cHandle – Pointer to flexio_i2c_master_transfer_t structure

FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION#

FlexIO I2C transfer status.

Values:

enumerator kStatus_FLEXIO_I2C_Busy#: I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Idle#: I2C is busy doing transfer.

enumerator kStatus_FLEXIO_I2C_Nak#: NAK received during transfer.

enumerator kStatus_FLEXIO_I2C_Timeout#: Timeout polling status flags.

enum _flexio_i2c_master_interrupt#

Define FlexIO I2C master interrupt mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyInterruptEnable#: Tx buffer empty interrupt enable.

enumerator kFLEXIO_I2C_RxFullInterruptEnable#: Rx buffer full interrupt enable.

enum _flexio_i2c_master_status_flags#

Define FlexIO I2C master status mask.

Values:

enumerator kFLEXIO_I2C_TxEmptyFlag#: Tx shifter empty flag.

enumerator kFLEXIO_I2C_RxFullFlag#: Rx shifter full/Transfer complete flag.

enumerator kFLEXIO_I2C_ReceiveNakFlag#: Receive NAK flag.

enum _flexio_i2c_direction#

Direction of master transfer.

Values:

enumerator kFLEXIO_I2C_Write#: Master send to slave.

enumerator kFLEXIO_I2C_Read#: Master receive from slave.

typedef enum _flexio_i2c_direction flexio_i2c_direction_t#: Direction of master transfer.

typedef struct _flexio_i2c_type FLEXIO_I2C_Type#: Define FlexIO I2C master access structure typedef.

typedef struct _flexio_i2c_master_config flexio_i2c_master_config_t#: Define FlexIO I2C master user configuration structure.

typedef struct _flexio_i2c_master_transfer flexio_i2c_master_transfer_t#: Define FlexIO I2C master transfer structure.

typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t#: FlexIO I2C master handle typedef.

typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, status_t status, void *userData)#: FlexIO I2C master transfer callback typedef.

I2C_RETRY_TIMES#: Retry times for waiting flag.

struct _flexio_i2c_type#

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master access structure typedef.

Public Members

FLEXIO_Type *flexioBase#: FlexIO base pointer.

uint8_t SDAPinIndex#: Pin select for I2C SDA.

uint8_t SCLPinIndex#: Pin select for I2C SCL.

uint8_t shifterIndex[2]#: Shifter index used in FlexIO I2C.

uint8_t timerIndex[3]#: Timer index used in FlexIO I2C.

uint32_t baudrate#: Master transfer baudrate, used to calculate delay time.

struct _flexio_i2c_master_config#

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master user configuration structure.

Public Members

bool enableMaster#: Enables the FlexIO I2C peripheral at initialization time.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode.

bool enableInDebug#: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps#: Baud rate in Bps.

struct _flexio_i2c_master_transfer#

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master transfer structure.

Public Members

uint32_t flags#: Transfer flag which controls the transfer, reserved for FlexIO I2C.

uint8_t slaveAddress#: 7-bit slave address.

flexio_i2c_direction_t direction#: Transfer direction, read or write.

uint32_t subaddress#: Sub address. Transferred MSB first.

uint8_t subaddressSize#: Size of sub address.

uint8_t volatile *data#: Transfer buffer.

volatile size_t dataSize#: Transfer size.

struct _flexio_i2c_master_handle#

#include <fsl_flexio_i2c_master.h>

Define FlexIO I2C master handle structure.

Public Members

flexio_i2c_master_transfer_t transfer#: FlexIO I2C master transfer copy.

size_t transferSize#: Total bytes to be transferred.

uint8_t state#: Transfer state maintained during transfer.

flexio_i2c_master_transfer_callback_t completionCallback#: Callback function called at transfer event. Callback function called at transfer event.

void *userData#: Callback parameter passed to callback function.

bool needRestart#: Whether master needs to send re-start signal.

FlexIO I2S Driver#

void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)#

Initializes the FlexIO I2S.

This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. The configuration structure can be filled by the user, or be set with default values by FLEXIO_I2S_GetDefaultConfig().

Note

This API should be called at the beginning of the application to use the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault because the clock is not enabled.

Parameters:

base – FlexIO I2S base pointer
config – FlexIO I2S configure structure.

void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)#

Sets the FlexIO I2S configuration structure to default values.

The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify some fields of the structure before calling FLEXIO_I2S_Init().

Parameters:

config – pointer to master configuration structure

void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)#

De-initializes the FlexIO I2S.

Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, call the FLEXO_I2S_Init to use the FlexIO I2S module.

Parameters:

base – FlexIO I2S base pointer

static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable)#

Enables/disables the FlexIO I2S module operation.

Parameters:

base – Pointer to FLEXIO_I2S_Type
enable – True to enable, false dose not have any effect.

uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)#

Gets the FlexIO I2S status flags.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags.

void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)#

Enables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
mask – interrupt source

void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)#

Disables the FlexIO I2S interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – pointer to FLEXIO_I2S_Type structure
mask – interrupt source

static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable)#

Enables/disables the FlexIO I2S Tx DMA requests.

Parameters:

base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.

static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable)#

Enables/disables the FlexIO I2S Rx DMA requests.

Parameters:

base – FlexIO I2S base pointer
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base)#

Gets the FlexIO I2S send data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s send data register address.

static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base)#

Gets the FlexIO I2S receive data register address.

This function returns the I2S data register address, mainly used by DMA/eDMA.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure

Returns:

FlexIO i2s receive data register address.

void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)#

Configures the FlexIO I2S audio format in master mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.
srcClock_Hz – I2S master clock source frequency in Hz.

void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)#

Configures the FlexIO I2S audio format in slave mode.

Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
format – Pointer to FlexIO I2S audio data format structure.

status_t FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)#

Sends data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
txData – Pointer to the data to be written.
size – Bytes to be written.

Return values:

kStatus_Success – Successfully write data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data)#

Writes data into a data register.

Parameters:

base – FlexIO I2S base pointer.
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
data – Data to be written.

status_t FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)#

Receives a piece of data using a blocking method.

Note

This function blocks via polling until data is ready to be sent.

Parameters:

base – FlexIO I2S base pointer
bitWidth – How many bits in a audio word, usually 8/16/24/32 bits.
rxData – Pointer to the data to be read.
size – Bytes to be read.

Return values:

kStatus_Success – Successfully read data.
kStatus_FLEXIO_I2C_Timeout – Timeout polling status flags.

static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base)#

Reads a data from the data register.

Parameters:

base – FlexIO I2S base pointer

Returns:

Data read from data register.

void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)#

Initializes the FlexIO I2S handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.

void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_format_t *format, uint32_t srcClock_Hz)#

Configures the FlexIO I2S audio format.

Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data format to be transferred.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – FlexIO I2S handle pointer.
format – Pointer to audio data format structure.
srcClock_Hz – FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode.

void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_callback_t callback, void *userData)#

Initializes the FlexIO I2S receive handle.

This function initializes the FlexIO I2S handle which can be used for other FlexIO I2S transactional APIs. Call this API once to get the initialized handle.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure to store the transfer state.
callback – FlexIO I2S callback function, which is called while finished a block.
userData – User parameter for the FlexIO I2S callback.

status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)#

Performs an interrupt non-blocking send transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

kStatus_Success – Successfully start the data transmission.
kStatus_FLEXIO_I2S_TxBusy – Previous transmission still not finished, data not all written to TX register yet.
kStatus_InvalidArgument – The input parameter is invalid.

status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, flexio_i2s_transfer_t *xfer)#

Performs an interrupt non-blocking receive transfer on FlexIO I2S.

Note

The API returns immediately after transfer initiates. Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether the transfer is finished. If the return status is 0, the transfer is finished.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
xfer – Pointer to flexio_i2s_transfer_t structure

Return values:

kStatus_Success – Successfully start the data receive.
kStatus_FLEXIO_I2S_RxBusy – Previous receive still not finished.
kStatus_InvalidArgument – The input parameter is invalid.

void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)#

Aborts the current send.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)#

Aborts the current receive.

Note

This API can be called at any time when interrupt non-blocking transfer initiates to abort the transfer in a early time.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state

status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)#

Gets the remaining bytes to be sent.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes sent.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)#

Gets the remaining bytes to be received.

Parameters:

base – Pointer to FLEXIO_I2S_Type structure.
handle – Pointer to flexio_i2s_handle_t structure which stores the transfer state
count – Bytes recieved.

Return values:

kStatus_Success – Succeed get the transfer count.
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress.

Returns:

count Bytes received.

void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)#

Tx interrupt handler.

Parameters:

i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure

void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)#

Rx interrupt handler.

Parameters:

i2sBase – Pointer to FLEXIO_I2S_Type structure.
i2sHandle – Pointer to flexio_i2s_handle_t structure.

FSL_FLEXIO_I2S_DRIVER_VERSION#: FlexIO I2S driver version 2.2.2.

FlexIO I2S transfer status.

Values:

enumerator kStatus_FLEXIO_I2S_Idle#: FlexIO I2S is in idle state

enumerator kStatus_FLEXIO_I2S_TxBusy#: FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_RxBusy#: FlexIO I2S Tx is busy

enumerator kStatus_FLEXIO_I2S_Error#: FlexIO I2S error occurred

enumerator kStatus_FLEXIO_I2S_QueueFull#: FlexIO I2S transfer queue is full.

enumerator kStatus_FLEXIO_I2S_Timeout#: FlexIO I2S timeout polling status flags.

enum _flexio_i2s_master_slave#

Master or slave mode.

Values:

enumerator kFLEXIO_I2S_Master#: Master mode

enumerator kFLEXIO_I2S_Slave#: Slave mode

_flexio_i2s_interrupt_enable Define FlexIO FlexIO I2S interrupt mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyInterruptEnable#: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_I2S_RxDataRegFullInterruptEnable#: Receive buffer full interrupt enable.

_flexio_i2s_status_flags Define FlexIO FlexIO I2S status mask.

Values:

enumerator kFLEXIO_I2S_TxDataRegEmptyFlag#: Transmit buffer empty flag.

enumerator kFLEXIO_I2S_RxDataRegFullFlag#: Receive buffer full flag.

enum _flexio_i2s_sample_rate#

Audio sample rate.

Values:

enumerator kFLEXIO_I2S_SampleRate8KHz#: Sample rate 8000Hz

enumerator kFLEXIO_I2S_SampleRate11025Hz#: Sample rate 11025Hz

enumerator kFLEXIO_I2S_SampleRate12KHz#: Sample rate 12000Hz

enumerator kFLEXIO_I2S_SampleRate16KHz#: Sample rate 16000Hz

enumerator kFLEXIO_I2S_SampleRate22050Hz#: Sample rate 22050Hz

enumerator kFLEXIO_I2S_SampleRate24KHz#: Sample rate 24000Hz

enumerator kFLEXIO_I2S_SampleRate32KHz#: Sample rate 32000Hz

enumerator kFLEXIO_I2S_SampleRate44100Hz#: Sample rate 44100Hz

enumerator kFLEXIO_I2S_SampleRate48KHz#: Sample rate 48000Hz

enumerator kFLEXIO_I2S_SampleRate96KHz#: Sample rate 96000Hz

enum _flexio_i2s_word_width#

Audio word width.

Values:

enumerator kFLEXIO_I2S_WordWidth8bits#: Audio data width 8 bits

enumerator kFLEXIO_I2S_WordWidth16bits#: Audio data width 16 bits

enumerator kFLEXIO_I2S_WordWidth24bits#: Audio data width 24 bits

enumerator kFLEXIO_I2S_WordWidth32bits#: Audio data width 32 bits

typedef struct _flexio_i2s_type FLEXIO_I2S_Type#: Define FlexIO I2S access structure typedef.

typedef enum _flexio_i2s_master_slave flexio_i2s_master_slave_t#: Master or slave mode.

typedef struct _flexio_i2s_config flexio_i2s_config_t#: FlexIO I2S configure structure.

typedef struct _flexio_i2s_format flexio_i2s_format_t#: FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

typedef enum _flexio_i2s_sample_rate flexio_i2s_sample_rate_t#: Audio sample rate.

typedef enum _flexio_i2s_word_width flexio_i2s_word_width_t#: Audio word width.

typedef struct _flexio_i2s_transfer flexio_i2s_transfer_t#: Define FlexIO I2S transfer structure.

typedef struct _flexio_i2s_handle flexio_i2s_handle_t#

typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, status_t status, void *userData)#: FlexIO I2S xfer callback prototype.

I2S_RETRY_TIMES#: Retry times for waiting flag.

FLEXIO_I2S_XFER_QUEUE_SIZE#: FlexIO I2S transfer queue size, user can refine it according to use case.

struct _flexio_i2s_type#

#include <fsl_flexio_i2s.h>

Define FlexIO I2S access structure typedef.

Public Members

FLEXIO_Type *flexioBase#: FlexIO base pointer

uint8_t txPinIndex#: Tx data pin index in FlexIO pins

uint8_t rxPinIndex#: Rx data pin index

uint8_t bclkPinIndex#: Bit clock pin index

uint8_t fsPinIndex#: Frame sync pin index

uint8_t txShifterIndex#: Tx data shifter index

uint8_t rxShifterIndex#: Rx data shifter index

uint8_t bclkTimerIndex#: Bit clock timer index

uint8_t fsTimerIndex#: Frame sync timer index

struct _flexio_i2s_config#

#include <fsl_flexio_i2s.h>

FlexIO I2S configure structure.

Public Members

bool enableI2S#: Enable FlexIO I2S

flexio_i2s_master_slave_t masterSlave#: Master or slave

flexio_pin_polarity_t txPinPolarity#: Tx data pin polarity, active high or low

flexio_pin_polarity_t rxPinPolarity#: Rx data pin polarity

flexio_pin_polarity_t bclkPinPolarity#: Bit clock pin polarity

flexio_pin_polarity_t fsPinPolarity#: Frame sync pin polarity

flexio_shifter_timer_polarity_t txTimerPolarity#: Tx data valid on bclk rising or falling edge

flexio_shifter_timer_polarity_t rxTimerPolarity#: Rx data valid on bclk rising or falling edge

struct _flexio_i2s_format#

#include <fsl_flexio_i2s.h>

FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx.

Public Members

uint8_t bitWidth#: Bit width of audio data, always 8/16/24/32 bits

uint32_t sampleRate_Hz#: Sample rate of the audio data

struct _flexio_i2s_transfer#

#include <fsl_flexio_i2s.h>

Define FlexIO I2S transfer structure.

Public Members

uint8_t *data#: Data buffer start pointer

size_t dataSize#: Bytes to be transferred.

struct _flexio_i2s_handle#

#include <fsl_flexio_i2s.h>

Define FlexIO I2S handle structure.

Public Members

uint32_t state#: Internal state

flexio_i2s_callback_t callback#: Callback function called at transfer event

void *userData#: Callback parameter passed to callback function

uint8_t bitWidth#: Bit width for transfer, 8/16/24/32bits

flexio_i2s_transfer_t queue[(4U)]#: Transfer queue storing queued transfer

size_t transferSize[(4U)]#: Data bytes need to transfer

volatile uint8_t queueUser#: Index for user to queue transfer

volatile uint8_t queueDriver#: Index for driver to get the transfer data and size

FlexIO MCU Interface LCD Driver#

status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz)#

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_MCULCD_GetDefaultConfig.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
config – Pointer to the flexio_mculcd_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Initialization success.
kStatus_InvalidArgument – Initialization failed because of invalid argument.

void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base)#

Resets the FLEXIO_MCULCD timer and shifter configuration.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config)#

Gets the default configuration to configure the FlexIO MCULCD.

The default configuration value is:

config->enable = true;
config->enableInDoze = false;
config->enableInDebug = true;
config->enableFastAccess = true;
config->baudRate_Bps = 96000000U;

Parameters:

config – Pointer to the flexio_mculcd_config_t structure.

uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base)#

Gets FlexIO MCULCD status flags.

Note

Don’t use this function with DMA APIs.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.

Returns:

status flag; OR’ed value or the _flexio_mculcd_status_flags.

void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask)#

Clears FlexIO MCULCD status flags.

Note

Don’t use this function with DMA APIs.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
mask – Status to clear, it is the OR’ed value of _flexio_mculcd_status_flags.

void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask)#

Enables the FlexIO MCULCD interrupt.

This function enables the FlexIO MCULCD interrupt.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
mask – Interrupts to enable, it is the OR’ed value of _flexio_mculcd_interrupt_enable.

void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask)#

Disables the FlexIO MCULCD interrupt.

This function disables the FlexIO MCULCD interrupt.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
mask – Interrupts to disable, it is the OR’ed value of _flexio_mculcd_interrupt_enable.

static inline void FLEXIO_MCULCD_EnableTxDMA(FLEXIO_MCULCD_Type *base, bool enable)#

Enables/disables the FlexIO MCULCD transmit DMA.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
enable – True means enable DMA, false means disable DMA.

static inline void FLEXIO_MCULCD_EnableRxDMA(FLEXIO_MCULCD_Type *base, bool enable)#

Enables/disables the FlexIO MCULCD receive DMA.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_MCULCD_GetTxDataRegisterAddress(FLEXIO_MCULCD_Type *base)#

Gets the FlexIO MCULCD transmit data register address.

This function returns the MCULCD data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.

Returns:

FlexIO MCULCD transmit data register address.

static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type *base)#

Gets the FlexIO MCULCD receive data register address.

This function returns the MCULCD data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.

Returns:

FlexIO MCULCD receive data register address.

status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)#

Set desired baud rate.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
baudRate_Bps – Desired baud rate in bit-per-second for all data lines combined.
srcClock_Hz – FLEXIO clock frequency in Hz.

Return values:

kStatus_Success – Set successfully.
kStatus_InvalidArgument – Could not set the baud rate.

void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)#

Configures the FLEXIO MCULCD to multiple beats write mode.

At the begining multiple beats write operation, the FLEXIO MCULCD is configured to multiple beats write mode using this function. After write operation, the configuration is cleared by FLEXIO_MCULCD_ClearSingleBeatWriteConfig.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)#

Clear the FLEXIO MCULCD multiple beats write mode configuration.

Clear the write configuration set by FLEXIO_MCULCD_SetSingleBeatWriteConfig.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)#

Configures the FLEXIO MCULCD to multiple beats read mode.

At the begining or multiple beats read operation, the FLEXIO MCULCD is configured to multiple beats read mode using this function. After read operation, the configuration is cleared by FLEXIO_MCULCD_ClearSingleBeatReadConfig.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)#

Clear the FLEXIO MCULCD multiple beats read mode configuration.

Clear the read configuration set by FLEXIO_MCULCD_SetSingleBeatReadConfig.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)#

Configures the FLEXIO MCULCD to multiple beats write mode.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)#

Clear the FLEXIO MCULCD multiple beats write mode configuration.

Clear the write configuration set by FLEXIO_MCULCD_SetMultBeatsWriteConfig.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base)#

Configures the FLEXIO MCULCD to multiple beats read mode.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base)#

Clear the FLEXIO MCULCD multiple beats read mode configuration.

Clear the read configuration set by FLEXIO_MCULCD_SetMultBeatsReadConfig.

Note

This is an internal used function, upper layer should not use.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.

static inline void FLEXIO_MCULCD_Enable(FLEXIO_MCULCD_Type *base, bool enable)#

Enables/disables the FlexIO MCULCD module operation.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type.
enable – True to enable, false does not have any effect.

uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base)#

Read data from the FLEXIO MCULCD RX shifter buffer.

Read data from the RX shift buffer directly, it does no check whether the buffer is empty or not.

If the data bus width is 8-bit:

uint8_t value;
value = (uint8_t)FLEXIO_MCULCD_ReadData(base);

If the data bus width is 16-bit:

uint16_t value;
value = (uint16_t)FLEXIO_MCULCD_ReadData(base);

Note

This function returns the RX shifter buffer value (32-bit) directly. The return value should be converted according to data bus width.

Note

Don’t use this function with DMA APIs.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.

Returns:

The data read out.

static inline void FLEXIO_MCULCD_WriteData(FLEXIO_MCULCD_Type *base, uint32_t data)#

Write data into the FLEXIO MCULCD TX shifter buffer.

Write data into the TX shift buffer directly, it does no check whether the buffer is full or not.

Note

Don’t use this function with DMA APIs.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
data – The data to write.

static inline void FLEXIO_MCULCD_StartTransfer(FLEXIO_MCULCD_Type *base)#

Assert the nCS to start transfer.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.

static inline void FLEXIO_MCULCD_StopTransfer(FLEXIO_MCULCD_Type *base)#

De-assert the nCS to stop transfer.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.

void FLEXIO_MCULCD_WaitTransmitComplete(void)#

Wait for transmit data send out finished.

Currently there is no effective method to wait for the data send out from the shiter, so here use a while loop to wait.

Note

This is an internal used function.

void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command)#

Send command in blocking way.

This function sends the command and returns when the command has been sent out.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
command – The command to send.

void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, const void *data, size_t size)#

Send data array in blocking way.

This function sends the data array and returns when the data sent out.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
data – The data array to send.
size – How many bytes to write.

void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size)#

Read data into array in blocking way.

This function reads the data into array and returns when the data read finished.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
data – The array to save the data.
size – How many bytes to read.

void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size)#

Send the same value many times in blocking way.

This function sends the same value many times. It could be used to clear the LCD screen. If the data bus width is 8, this function will send LSB 8 bits of sameValue for size times. If the data bus is 16, this function will send LSB 16 bits of sameValue for size / 2 times.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
sameValue – The same value to send.
size – How many bytes to send.

void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer)#

Performs a polling transfer.

Note

The API does not return until the transfer finished.

Parameters:

base – pointer to FLEXIO_MCULCD_Type structure.
xfer – pointer to flexio_mculcd_transfer_t structure.

status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, flexio_mculcd_transfer_callback_t callback, void *userData)#

Initializes the FlexIO MCULCD handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
handle – Pointer to the flexio_mculcd_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, flexio_mculcd_transfer_t *xfer)#

Transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
handle – Pointer to the flexio_mculcd_handle_t structure to store the transfer state.
xfer – FlexIO MCULCD transfer structure. See flexio_mculcd_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_MCULCD_Busy – MCULCD is busy with another transfer.

void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle)#

Aborts the data transfer, which used IRQ.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
handle – Pointer to the flexio_mculcd_handle_t structure to store the transfer state.

status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count)#

Gets the data transfer status which used IRQ.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
handle – Pointer to the flexio_mculcd_handle_t structure to store the transfer state.
count – How many bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_Success – Get the transferred count Successfully.
kStatus_NoTransferInProgress – No transfer in process.

void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle)#

FlexIO MCULCD IRQ handler function.

Parameters:

base – Pointer to the FLEXIO_MCULCD_Type structure.
handle – Pointer to the flexio_mculcd_handle_t structure to store the transfer state.

FSL_FLEXIO_MCULCD_DRIVER_VERSION#: FlexIO MCULCD driver version.

FlexIO LCD transfer status.

Values:

enumerator kStatus_FLEXIO_MCULCD_Idle#: FlexIO LCD is idle.

enumerator kStatus_FLEXIO_MCULCD_Busy#: FlexIO LCD is busy

enumerator kStatus_FLEXIO_MCULCD_Error#: FlexIO LCD error occurred

enum _flexio_mculcd_pixel_format#

Define FlexIO MCULCD pixel format.

Values:

enumerator kFLEXIO_MCULCD_RGB565#: RGB565, 16-bit.

enumerator kFLEXIO_MCULCD_BGR565#: BGR565, 16-bit.

enumerator kFLEXIO_MCULCD_RGB888#: RGB888, 24-bit.

enumerator kFLEXIO_MCULCD_BGR888#: BGR888, 24-bit.

enum _flexio_mculcd_bus#

Define FlexIO MCULCD bus type.

Values:

enumerator kFLEXIO_MCULCD_8080#: Using Intel 8080 bus.

enumerator kFLEXIO_MCULCD_6800#: Using Motorola 6800 bus.

enum _flexio_mculcd_interrupt_enable#

Define FlexIO MCULCD interrupt mask.

Values:

enumerator kFLEXIO_MCULCD_TxEmptyInterruptEnable#: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_MCULCD_RxFullInterruptEnable#: Receive buffer full interrupt enable.

enum _flexio_mculcd_status_flags#

Define FlexIO MCULCD status mask.

Values:

enumerator kFLEXIO_MCULCD_TxEmptyFlag#: Transmit buffer empty flag.

enumerator kFLEXIO_MCULCD_RxFullFlag#: Receive buffer full flag.

enum _flexio_mculcd_dma_enable#

Define FlexIO MCULCD DMA mask.

Values:

enumerator kFLEXIO_MCULCD_TxDmaEnable#: Tx DMA request source

enumerator kFLEXIO_MCULCD_RxDmaEnable#: Rx DMA request source

enum _flexio_mculcd_transfer_mode#

Transfer mode.

Values:

enumerator kFLEXIO_MCULCD_ReadArray#: Read data into an array.

enumerator kFLEXIO_MCULCD_WriteArray#: Write data from an array.

enumerator kFLEXIO_MCULCD_WriteSameValue#: Write the same value many times.

typedef enum _flexio_mculcd_pixel_format flexio_mculcd_pixel_format_t#: Define FlexIO MCULCD pixel format.

typedef enum _flexio_mculcd_bus flexio_mculcd_bus_t#: Define FlexIO MCULCD bus type.

typedef void (*flexio_mculcd_pin_func_t)(bool set)#: Function to set or clear the CS and RS pin.

typedef struct _flexio_mculcd_type FLEXIO_MCULCD_Type#: Define FlexIO MCULCD access structure typedef.

typedef struct _flexio_mculcd_config flexio_mculcd_config_t#: Define FlexIO MCULCD configuration structure.

typedef enum _flexio_mculcd_transfer_mode flexio_mculcd_transfer_mode_t#: Transfer mode.

typedef struct _flexio_mculcd_transfer flexio_mculcd_transfer_t#: Define FlexIO MCULCD transfer structure.

typedef struct _flexio_mculcd_handle flexio_mculcd_handle_t#: typedef for flexio_mculcd_handle_t in advance.

typedef void (*flexio_mculcd_transfer_callback_t)(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, status_t status, void *userData)#

FlexIO MCULCD callback for finished transfer.

When transfer finished, the callback function is called and returns the status as kStatus_FLEXIO_MCULCD_Idle.

FLEXIO_MCULCD_WAIT_COMPLETE_TIME#

The delay time to wait for FLEXIO transmit complete.

Currently there is no method to detect whether the data has been sent out from the shifter, so the driver use a software delay for this. When the data is written to shifter buffer, the driver call the delay function to wait for the data shift out. If this value is too small, then the last few bytes might be lost when writing data using interrupt method or DMA method.

FLEXIO_MCULCD_DATA_BUS_WIDTH#: The data bus width, must be 8 or 16.

FLEXIO_MCULCD_LEGACY_GPIO_FUNC#

Whether to use legacy GPIO functions to control the CS/RS/RDWR pin signal.

If using the legacy pin functions, there is no user defined argument passed to the function.

struct _flexio_mculcd_type#

#include <fsl_flexio_mculcd.h>

Define FlexIO MCULCD access structure typedef.

Public Members

FLEXIO_Type *flexioBase#: FlexIO base pointer.

flexio_mculcd_bus_t busType#: The bus type, 8080 or 6800.

uint8_t dataPinStartIndex#: Start index of the data pin, the FlexIO pin dataPinStartIndex to (dataPinStartIndex + FLEXIO_MCULCD_DATA_BUS_WIDTH -1) will be used for data transfer. Only support data bus width 8 and 16.

uint8_t ENWRPinIndex#: Pin select for WR(8080 mode), EN(6800 mode).

uint8_t RDPinIndex#: Pin select for RD(8080 mode), not used in 6800 mode.

uint8_t txShifterStartIndex#: Start index of shifters used for data write, it must be 0 or 4.

uint8_t txShifterEndIndex#: End index of shifters used for data write.

uint8_t rxShifterStartIndex#: Start index of shifters used for data read.

uint8_t rxShifterEndIndex#: End index of shifters used for data read, it must be 3 or 7.

uint8_t timerIndex#: Timer index used in FlexIO MCULCD.

flexio_mculcd_pin_func_t setCSPin#: Function to set or clear the CS pin.

flexio_mculcd_pin_func_t setRSPin#: Function to set or clear the RS pin.

flexio_mculcd_pin_func_t setRDWRPin#: Function to set or clear the RD/WR pin, only used in 6800 mode.

struct _flexio_mculcd_config#

#include <fsl_flexio_mculcd.h>

Define FlexIO MCULCD configuration structure.

Public Members

bool enable#: Enable/disable FlexIO MCULCD after configuration.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode.

bool enableInDebug#: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps#: Baud rate in bit-per-second for all data lines combined.

struct _flexio_mculcd_transfer#

#include <fsl_flexio_mculcd.h>

Define FlexIO MCULCD transfer structure.

Public Members

uint32_t command#: Command to send.

uint32_t dataAddrOrSameValue#: When sending the same value for many times, this is the value to send. When writing or reading array, this is the address of the data array.

size_t dataSize#: How many bytes to transfer.

flexio_mculcd_transfer_mode_t mode#: Transfer mode.

bool dataOnly#: Send data only when tx without the command.

struct _flexio_mculcd_handle#

#include <fsl_flexio_mculcd.h>

Define FlexIO MCULCD handle structure.

Public Members

uint32_t dataAddrOrSameValue#: When sending the same value for many times, this is the value to send. When writing or reading array, this is the address of the data array.

size_t dataCount#: Total count to be transferred.

volatile size_t remainingCount#: Remaining count to transfer.

volatile uint32_t state#: FlexIO MCULCD internal state.

flexio_mculcd_transfer_callback_t completionCallback#: FlexIO MCULCD transfer completed callback.

void *userData#: Callback parameter.

FlexIO SPI Driver#

void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)#

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, and configures the FlexIO SPI with FlexIO SPI master configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_MasterGetDefaultConfig().

Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_spi_master_config_t config = {
.enableMaster = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 500000,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);

Note

1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
masterConfig – Pointer to the flexio_spi_master_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)#

Resets the FlexIO SPI timer and shifter config.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)#

Gets the default configuration to configure the FlexIO SPI master. The configuration can be used directly by calling the FLEXIO_SPI_MasterConfigure(). Example:

flexio_spi_master_config_t masterConfig;
FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);

Parameters:

masterConfig – Pointer to the flexio_spi_master_config_t structure.

void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)#

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_SPI_SlaveGetDefaultConfig().

Note

1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. Example

FLEXIO_SPI_Type spiDev = {
.flexioBase = FLEXIO,
.SDOPinIndex = 0,
.SDIPinIndex = 1,
.SCKPinIndex = 2,
.CSnPinIndex = 3,
.shifterIndex = {0,1},
.timerIndex = {0}
};
flexio_spi_slave_config_t config = {
.enableSlave = true,
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
.direction = kFLEXIO_SPI_MsbFirst,
.dataMode = kFLEXIO_SPI_8BitMode
};
FLEXIO_SPI_SlaveInit(&spiDev, &config);

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)#

Gates the FlexIO clock.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.

void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)#

Gets the default configuration to configure the FlexIO SPI slave. The configuration can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). Example:

flexio_spi_slave_config_t slaveConfig;
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);

Parameters:

slaveConfig – Pointer to the flexio_spi_slave_config_t structure.

uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)#

Gets FlexIO SPI status flags.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.

Returns:

status flag; Use the status flag to AND the following flag mask and get the status.

kFLEXIO_SPI_TxEmptyFlag
kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)#

Clears FlexIO SPI status flags.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – status flag The parameter can be any combination of the following values:
- kFLEXIO_SPI_TxEmptyFlag
- kFLEXIO_SPI_RxEmptyFlag

void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)#

Enables the FlexIO SPI interrupt.

This function enables the FlexIO SPI interrupt.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source. The parameter can be any combination of the following values:
- kFLEXIO_SPI_RxFullInterruptEnable
- kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)#

Disables the FlexIO SPI interrupt.

This function disables the FlexIO SPI interrupt.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – interrupt source The parameter can be any combination of the following values:
- kFLEXIO_SPI_RxFullInterruptEnable
- kFLEXIO_SPI_TxEmptyInterruptEnable

void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)#

Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
mask – SPI DMA source.
enable – True means enable DMA, false means disable DMA.

static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)#

Gets the FlexIO SPI transmit data register address for MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI transmit data register address.

static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)#

Gets the FlexIO SPI receive data register address for the MSB first transfer.

This function returns the SPI data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

FlexIO SPI receive data register address.

static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable)#

Enables/disables the FlexIO SPI module operation.

Parameters:

base – Pointer to the FLEXIO_SPI_Type.
enable – True to enable, false does not have any effect.

void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)#

Sets baud rate for the FlexIO SPI transfer, which is only used for the master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
baudRate_Bps – Baud Rate needed in Hz.
srcClockHz – SPI source clock frequency in Hz.

static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)#

Writes one byte of data, which is sent using the MSB method.

Note

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
data – 8/16/32 bit data.

static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)#

Reads 8 bit/16 bit data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.

Returns:

8 bit/16 bit data received.

status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, const uint8_t *buffer, size_t size)#

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The data bytes to send.
size – The number of data bytes to send.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint8_t *buffer, size_t size)#

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
direction – Shift direction of MSB first or LSB first.
buffer – The buffer to store the received bytes.
size – The number of data bytes to be received.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)#

Receives a buffer of bytes.

Note

This function blocks via polling until all bytes have been received.

Parameters:

base – pointer to FLEXIO_SPI_Type structure
xfer – FlexIO SPI transfer structure, see flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_FLEXIO_SPI_Timeout – The transfer timed out and was aborted.

void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)#

Flush tx/rx shifters.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.

status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_master_transfer_callback_t callback, void *userData)#

Initializes the FlexIO SPI Master handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, flexio_spi_transfer_t *xfer)#

Master transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle, is running another transfer.

void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)#

Aborts the master data transfer, which used IRQ.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)#

Gets the data transfer status which used IRQ.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)#

FlexIO SPI master IRQ handler function.

Parameters:

spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_master_handle_t structure to store the transfer state.

status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_slave_transfer_callback_t callback, void *userData)#

Initializes the FlexIO SPI Slave handle, which is used in transactional functions.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, flexio_spi_transfer_t *xfer)#

Slave transfer data using IRQ.

This function sends data using IRQ. This is a non-blocking function, which returns right away. When all data is sent out/received, the callback function is called.

Parameters:

handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
base – Pointer to the FLEXIO_SPI_Type structure.
xfer – FlexIO SPI transfer structure. See flexio_spi_transfer_t.

Return values:

kStatus_Success – Successfully start a transfer.
kStatus_InvalidArgument – Input argument is invalid.
kStatus_FLEXIO_SPI_Busy – SPI is not idle; it is running another transfer.

static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle)#

Aborts the slave data transfer which used IRQ, share same API with master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, size_t *count)#

Gets the data transfer status which used IRQ, share same API with master.

Parameters:

base – Pointer to the FLEXIO_SPI_Type structure.
handle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
count – Number of bytes transferred so far by the non-blocking transaction.

Return values:

kStatus_InvalidArgument – count is Invalid.
kStatus_Success – Successfully return the count.

void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)#

FlexIO SPI slave IRQ handler function.

Parameters:

spiType – Pointer to the FLEXIO_SPI_Type structure.
spiHandle – Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.

FSL_FLEXIO_SPI_DRIVER_VERSION#: FlexIO SPI driver version.

Error codes for the FlexIO SPI driver.

Values:

enumerator kStatus_FLEXIO_SPI_Busy#: FlexIO SPI is busy.

enumerator kStatus_FLEXIO_SPI_Idle#: SPI is idle

enumerator kStatus_FLEXIO_SPI_Error#: FlexIO SPI error.

enumerator kStatus_FLEXIO_SPI_Timeout#: FlexIO SPI timeout polling status flags.

enum _flexio_spi_clock_phase#

FlexIO SPI clock phase configuration.

Values:

enumerator kFLEXIO_SPI_ClockPhaseFirstEdge#: First edge on SPSCK occurs at the middle of the first cycle of a data transfer.

enumerator kFLEXIO_SPI_ClockPhaseSecondEdge#: First edge on SPSCK occurs at the start of the first cycle of a data transfer.

enum _flexio_spi_shift_direction#

FlexIO SPI data shifter direction options.

Values:

enumerator kFLEXIO_SPI_MsbFirst#: Data transfers start with most significant bit.

enumerator kFLEXIO_SPI_LsbFirst#: Data transfers start with least significant bit.

enum _flexio_spi_data_bitcount_mode#

FlexIO SPI data length mode options.

Values:

enumerator kFLEXIO_SPI_8BitMode#: 8-bit data transmission mode.

enumerator kFLEXIO_SPI_16BitMode#: 16-bit data transmission mode.

enumerator kFLEXIO_SPI_32BitMode#: 32-bit data transmission mode.

enum _flexio_spi_interrupt_enable#

Define FlexIO SPI interrupt mask.

Values:

enumerator kFLEXIO_SPI_TxEmptyInterruptEnable#: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_SPI_RxFullInterruptEnable#: Receive buffer full interrupt enable.

enum _flexio_spi_status_flags#

Define FlexIO SPI status mask.

Values:

enumerator kFLEXIO_SPI_TxBufferEmptyFlag#: Transmit buffer empty flag.

enumerator kFLEXIO_SPI_RxBufferFullFlag#: Receive buffer full flag.

enum _flexio_spi_dma_enable#

Define FlexIO SPI DMA mask.

Values:

enumerator kFLEXIO_SPI_TxDmaEnable#: Tx DMA request source

enumerator kFLEXIO_SPI_RxDmaEnable#: Rx DMA request source

enumerator kFLEXIO_SPI_DmaAllEnable#: All DMA request source

enum _flexio_spi_transfer_flags#

Define FlexIO SPI transfer flags.

Note

Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag.

Values:

enumerator kFLEXIO_SPI_8bitMsb#: FlexIO SPI 8-bit MSB first

enumerator kFLEXIO_SPI_8bitLsb#: FlexIO SPI 8-bit LSB first

enumerator kFLEXIO_SPI_16bitMsb#: FlexIO SPI 16-bit MSB first

enumerator kFLEXIO_SPI_16bitLsb#: FlexIO SPI 16-bit LSB first

enumerator kFLEXIO_SPI_32bitMsb#: FlexIO SPI 32-bit MSB first

enumerator kFLEXIO_SPI_32bitLsb#: FlexIO SPI 32-bit LSB first

enumerator kFLEXIO_SPI_csContinuous#: Enable the CS signal continuous mode

typedef enum _flexio_spi_clock_phase flexio_spi_clock_phase_t#: FlexIO SPI clock phase configuration.

typedef enum _flexio_spi_shift_direction flexio_spi_shift_direction_t#: FlexIO SPI data shifter direction options.

typedef enum _flexio_spi_data_bitcount_mode flexio_spi_data_bitcount_mode_t#: FlexIO SPI data length mode options.

typedef struct _flexio_spi_type FLEXIO_SPI_Type#: Define FlexIO SPI access structure typedef.

typedef struct _flexio_spi_master_config flexio_spi_master_config_t#: Define FlexIO SPI master configuration structure.

typedef struct _flexio_spi_slave_config flexio_spi_slave_config_t#: Define FlexIO SPI slave configuration structure.

typedef struct _flexio_spi_transfer flexio_spi_transfer_t#: Define FlexIO SPI transfer structure.

typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t#: typedef for flexio_spi_master_handle_t in advance.

typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t#: Slave handle is the same with master handle.

typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, status_t status, void *userData)#: FlexIO SPI master callback for finished transmit.

typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle, status_t status, void *userData)#: FlexIO SPI slave callback for finished transmit.

FLEXIO_SPI_DUMMYDATA#: FlexIO SPI dummy transfer data, the data is sent while txData is NULL.

SPI_RETRY_TIMES#: Retry times for waiting flag.

FLEXIO_SPI_XFER_DATA_FORMAT(flag)#: Get the transfer data format of width and bit order.

struct _flexio_spi_type#

#include <fsl_flexio_spi.h>

Define FlexIO SPI access structure typedef.

Public Members

FLEXIO_Type *flexioBase#: FlexIO base pointer.

uint8_t SDOPinIndex#: Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as GPIO input and disable all pull up/down in application.

uint8_t SDIPinIndex#: Pin select for data input.

uint8_t SCKPinIndex#: Pin select for clock.

uint8_t CSnPinIndex#: Pin select for enable.

uint8_t shifterIndex[2]#: Shifter index used in FlexIO SPI.

uint8_t timerIndex[2]#: Timer index used in FlexIO SPI.

struct _flexio_spi_master_config#

#include <fsl_flexio_spi.h>

Define FlexIO SPI master configuration structure.

Public Members

bool enableMaster#: Enable/disable FlexIO SPI master after configuration.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode.

bool enableInDebug#: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps#: Baud rate in Bps.

flexio_spi_clock_phase_t phase#: Clock phase.

flexio_spi_data_bitcount_mode_t dataMode#: 8bit or 16bit mode.

struct _flexio_spi_slave_config#

#include <fsl_flexio_spi.h>

Define FlexIO SPI slave configuration structure.

Public Members

bool enableSlave#: Enable/disable FlexIO SPI slave after configuration.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode.

bool enableInDebug#: Enable/disable FlexIO operation in debug mode.

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

flexio_spi_clock_phase_t phase#: Clock phase.

flexio_spi_data_bitcount_mode_t dataMode#: 8bit or 16bit mode.

struct _flexio_spi_transfer#

#include <fsl_flexio_spi.h>

Define FlexIO SPI transfer structure.

Public Members

const uint8_t *txData#: Send buffer.

uint8_t *rxData#: Receive buffer.

size_t dataSize#: Transfer bytes.

uint8_t flags#: FlexIO SPI control flag, MSB first or LSB first.

struct _flexio_spi_master_handle#

#include <fsl_flexio_spi.h>

Define FlexIO SPI handle structure.

Public Members

const uint8_t *txData#: Transfer buffer.

uint8_t *rxData#: Receive buffer.

size_t transferSize#: Total bytes to be transferred.

volatile size_t txRemainingBytes#: Send data remaining in bytes.

volatile size_t rxRemainingBytes#: Receive data remaining in bytes.

volatile uint32_t state#: FlexIO SPI internal state.

uint8_t bytePerFrame#: SPI mode, 2bytes or 1byte in a frame

flexio_spi_shift_direction_t direction#: Shift direction.

flexio_spi_master_transfer_callback_t callback#: FlexIO SPI callback.

void *userData#: Callback parameter.

bool isCsContinuous#: Is current transfer using CS continuous mode.

uint32_t timer1Cfg#: TIMER1 TIMCFG regiser value backup.

Flexio_t-format#

Error codes for the T_Format driver.

Values:

enumerator kStatus_FLEXIO_T_FORMAT_EncErr0_CountingErr#: Transmitter is busy.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr1_LogicOR#: Encoder error: Logic-OR of Over-heat, Multi-turn error, Battery error and Battery alarm.

enumerator kStatus_FLEXIO_T_FORMAT_ComAlr0_ParityErr#: Communication alarm: Parity error.

enumerator kStatus_FLEXIO_T_FORMAT_ComAlr1_DelimiterErr#: Communication alarm: Delimiter error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_OS#: Over speed.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_FS#: Full absolute status.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_CE#: Countering error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_OF#: Countering overflow.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_OH#: Over heat.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_ME#: Multi-turn error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_BE#: Battery error.

enumerator kStatus_FLEXIO_T_FORMAT_EncErr_BA#: Battery alarm.

enumerator kStatus_FLEXIO_T_FORMAT_FrameErr#: Frame format error.

enumerator kStatus_FLEXIO_T_FORMAT_BaudrateNotSupport#

enumerator kStatus_FLEXIO_T_FORMAT_Timeout#: T_FORMAT times out.

enumerator kStatus_FLEXIO_T_FORMAT_TxBusy#: Transmitter is busy.

enumerator kStatus_FLEXIO_T_FORMAT_RxBusy#: Receiver is busy.

enumerator kStatus_FLEXIO_T_FORMAT_TxIdle#: Transmitter is idle.

enumerator kStatus_FLEXIO_T_FORMAT_RxIdle#: Receiver is idle.

enumerator kStatus_FLEXIO_T_FORMAT_RxRingBufferOverrun#: A-format RX software ring buffer overrun.

enumerator kStatus_FLEXIO_T_FORMAT_RxHardwareOverrun#: A-format RX receiver overrun.

enum _flexio_t_format_interrupt_enable#

Define FlexIO T-format interrupt mask.

Values:

enumerator kFLEXIO_T_FORMAT_TxDataRegEmptyInterruptEnable#: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_T_FORMAT_RxDataRegFullInterruptEnable#: Receive buffer full interrupt enable.

enum _flexio_t_format_flags#

Values:

enumerator kFLEXIO_T_FORMAT_TxDataRegEmptyFlag#: Transmit buffer empty flag.

enumerator kFLEXIO_T_FORMAT_RxDataRegFullFlag#: Receive buffer full flag.

enumerator kFLEXIO_T_FORMAT_RxOverRunFlag#: Receive buffer over run flag.

enum _flexio_t_format_user_modes#

FlexIO T_FORMAT user modes.

Values:

enumerator kFLEXIO_T_FORMAT_USERMODE_ONESHOT#: User mode is oneshot

enumerator kFLEXIO_T_FORMAT_USERMODE_SYNC#: User mode is sync

typedef enum _flexio_t_format_user_modes flexio_t_format_user_modes_t#: FlexIO T_FORMAT user modes.

typedef struct _flexio_t_format_handle flexio_t_format_handle_t#

typedef struct _flexio_t_format_type FLEXIO_T_FORMAT_Type#: Define FlexIO T_FORMAT access structure typedef.

typedef struct _flexio_t_format_config flexio_t_format_config_t#: Define FlexIO T_FORMAT user configuration structure.

typedef struct _flexio_t_format_transfer flexio_t_format_transfer_t#: Define FlexIO T-format transfer structure.

typedef void (*flexio_t_format_transfer_callback_t)(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, status_t status, void *userData)#: FlexIO T-format transfer callback function.

static inline void FLEXIO_T_Format_WriteByte(FLEXIO_T_FORMAT_Type *base, const uint8_t *buffer)#

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_T_Format_ReadByte(FLEXIO_T_FORMAT_Type *base, uint8_t *buffer)#

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
buffer – The buffer to store the received bytes.

void FLEXIO_T_Format_Config_DR_length(FLEXIO_T_FORMAT_Type *base, uint32_t nFrames)#

The duration of the high level of the RS485 DR Pin is set according to the number of frames.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure
nFrames – The number of frames (Each 8bit of data is one frame)

status_t FLEXIO_T_Format_Init(FLEXIO_T_FORMAT_Type *base, flexio_t_format_config_t *userConfig, uint32_t srcClock_Hz)#

Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO T-Format hardware, and configures the FlexIO T-Format with FlexIO T-Format configuration. The configuration structure can be filled by the user, or be set with default values by the FLEXIO_T_FORMAT_GetDefaultConfig().

Example

FLEXIO_T_FORMAT_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_t_format_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_bps = 2500000
};
FLEXIO_T_Format_Init(&base, &config);

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
userConfig – Pointer to the flexio_t_format_config_t structure.

Return values:

kStatus_Success – Configuration success.

void FLEXIO_T_Format_Deinit(FLEXIO_T_FORMAT_Type *base)#

Resets the FlexIO T-Format shifter and timer config.

note After calling this API, call the FLEXIO_T_Format_Init to use the FlexIO T_format module.

Parameters:

base – Pointer to FLEXIO_T_FORMAT_Type structure

void FLEXIO_T_Format_GetDefaultConfig(flexio_t_format_config_t *userConfig)#

Gets the default configuration to configure the FlexIO T-format. The configuration can be used directly for calling the FLEXIO_T_Format_Init(). Example:

flexio_t_format_config_t config;
FLEXIO_T_Format_GetDefaultConfig(&userConfig);

Parameters:

userConfig – Pointer to the flexio_t_format_config_t structure.

void FLEXIO_T_Format_EnableInterrupts(FLEXIO_T_FORMAT_Type *base, uint32_t mask)#

Enables the FlexIO T-format interrupt.

This function enables the FlexIO T-format interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
mask – Interrupt source.

void FLEXIO_T_Format_DisableInterrupts(FLEXIO_T_FORMAT_Type *base, uint32_t mask)#

Disables the FlexIO T-format interrupt.

This function disables the FlexIO T-format interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
mask – Interrupt source.

uint32_t FLEXIO_T_Format_GetStatusFlags(FLEXIO_T_FORMAT_Type *base)#

Gets the FlexIO T-format status flags.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.

Returns:

FlexIO T-format status flags.

void FLEXIO_T_Format_ClearStatusFlags(FLEXIO_T_FORMAT_Type *base, uint32_t mask)#

Clears the FlexIO T-format status flags.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
mask – Status flag. The parameter can be any combination of the following values: arg kFLEXIO_T_FORMAT_TxDataRegEmptyFlag arg kFLEXIO_T_FORMAT_RxDataRegFullFlag arg kFLEXIO_T_FORMAT_RxOverRunFlag

status_t FLEXIO_T_Format_WriteBlocking(FLEXIO_T_FORMAT_Type *base, const uint8_t *txData, size_t txSize)#

Sends a buffer of data bytes.

note This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_T_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_T_Format_ReadBlocking(FLEXIO_T_FORMAT_Type *base, uint8_t *rxData, size_t rxSize)#

Receives a buffer of bytes.

note This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_T_FORMAT_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_T_Format_TransferCreateHandle(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, flexio_t_format_transfer_callback_t callback, void *userData)#

Initializes the T-format handle.

This function initializes the FlexIO T-format handle, which can be used for other FlexIO T-format transactional APIs. Call this API once to get the initialized handle.

The T-format driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_T_Format_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as p ringBuffer.

Parameters:

base – to FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_T_Format_TransferStartRingBuffer(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)#

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific T-format handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the T_Format_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

note When using the RX ring buffer, one byte is reserved for internal use. In other words, if p ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_T_Format_TransferStopRingBuffer(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle)#

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.

status_t FLEXIO_T_Format_TransferSendNonBlocking(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, flexio_t_format_transfer_t *xfer)#

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO T-format driver calls the callback function and passes the ref kStatus_FLEXIO_T_FORMAT_TxIdle as status parameter.

note The kStatus_FLEXIO_T_FORMAT_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
xfer – FlexIO T-format transfer structure. See flexio_t_format_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_T_FORMAT_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_T_Format_TransferAbortSend(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle)#

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainHalfwords to find out how many half-words are still not sent out.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.

status_t FLEXIO_T_Format_TransferGetSendCount(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, size_t *count)#

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_T_Format_TransferReceiveNonBlocking(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, flexio_t_format_transfer_t *xfer, size_t *receivedBytes)#

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter p receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the T-format driver. When new data arrives, the receive request is serviced first. When all data is received, the T-format driver notifies the upper layer through a callback function and passes the status parameter ref kStatus_T_FORMAT_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the T-format driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
xfer – T-format transfer structure. See flexio_t_format_transfer_t.
receivedBytes – bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_T_FORMAT_RxBusy – Previous receive request is not finished.

void FLEXIO_T_Format_TransferAbortReceive(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle)#

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.

status_t FLEXIO_T_Format_TransferGetReceiveCount(FLEXIO_T_FORMAT_Type *base, flexio_t_format_handle_t *handle, size_t *count)#

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
handle – Pointer to the flexio_t_format_handle_t structure to store the transfer state.
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_T_Format_SendSyncReq(FLEXIO_T_FORMAT_Type *base, const uint8_t cf)#

FlexIO T-format IRQ handler function.

Parameters:

base – Pointer to the FLEXIO_T_FORMAT_Type structure.
cf – Sets commands to be sent in synchronous mode.

Returns:

kStatus_Success

T_FORMAT_SINK_CODE_CF#: The Sink code of the control field of T-format.

T_FORMAT_CF_MASK_SINK_CODE#: The mask of the CF sink code.

T_FORMAT_CF_MASK_DATA_ID_CODE#: The mask of the CF data ID code.

T_FORMAT_CF_MASK_ID_PARITY#: The mask of the CF ID parity.

T_FORMAT_CF_DATA_ID_CODE(x)#: Data ID code for the control field.

T_FORMAT_CF_ID_PARITY(x)#: ID parity for the control field.

T_FORMAT_DATA_ID(code, parity)#: The DATA ID Code of the T-format.

T_FORMAT_CF(DataID)#: The control field of T-format.

T_FORMAT_CF_GET_ABS#: List of the control field value.

T_FORMAT_CF_GET_ABM#

T_FORMAT_CF_GET_ENCID#

T_FORMAT_CF_GET_ALL#

T_FORMAT_CF_RESET_ALL_ERROR#

T_FORMAT_CF_RESET_ABS#

T_FORMAT_CF_RESET_ABM_ERROR#

T_FORMAT_CF_EEPROM_WRITE#

T_FORMAT_CF_EEPROM_READOUT#

T_FORMAT_ALMC_MASK_OVER_SPEED#: The mask bit of ALMC(Encoder error)

T_FORMAT_ALMC_MASK_FULL_ABSOLUTE_STATUS#

T_FORMAT_ALMC_MASK_COUNTING_ERROR#

T_FORMAT_ALMC_MASK_COUNTER_OVERFLOW#

T_FORMAT_ALMC_MASK_OVERHEAT#

T_FORMAT_ALMC_MASK_MULTITURN_ERROR#

T_FORMAT_ALMC_MASK_BATTERY_ERROR#

T_FORMAT_ALMC_MASK_BATTERY_ALARM#

T_FORMAT_SF_MASK_ENCODER_ERROR#: The mask of the SF encoder error.

T_FORMAT_SF_MASK_COMMUNICATION_ALARM#: The mask of the SF communication alarm.

T_FORMAT_SF_GET_ENCODER_ERROR(x)#: Get the SF encoder error.

T_FORMAT_SF_GET_COMMUNICATION_ALARM(x)#: Get the SF communication alarm.

T_FORMAT_ADF_MASK_ADDRESS#: The mask of the ADF address.

T_FORMAT_SF_MASK_BUSY_STATUS#: The mask of the ADF busy status.

T_FORMAT_CRC_POLYNOMIAL#: The CRC polynomial.

T_FORMAT_ABS_BYTE#: The number of the byte in the received data.

T_FORMAT_ABM_BYTE#

T_FORMAT_ENCODER_ID_BYTE#

T_FORMAT_ALL_INFO_BYTE#

T_FORMAT_EEPROM_BYTE#

T_FORMAT_OVER_HEAT_NOT_CAUSE#: Do not cause Over-heat.

T_FORMAT_OVER_HEAT_TEMPERATURE(x)#

T_FORMAT_TIMER_TX_INDEX#

T_FORMAT_TIMER_RX_INDEX#

T_FORMAT_TIMER_DR_INDEX#

FSL_FLEXIO_T_FORMAT_DRIVER_VERSION#: FlexIO T_Format driver version.

T_FORMAT_RETRY_TIMES#: Retry times for waiting flag.

T_FORMAT_ENCODER_MAX_NUM#: Maximum number of encoders on an T-format bus.

T_FORMAT_BITS_PER_FRAME_DATA#: The number of bits per frame without start and stop bits.

T_FORMAT_BITS_PER_FRAME_WHOLE#: The number of bits per frame with start and stop bits.

T_FORMAT_TIMER_COMPARE_VALUE(cmp)#: Calculate the value of the FlexIO timer compare register.

FLEXIO_Type *flexioBase: FlexIO base pointer.

flexio_t_format_handle_t *hanlde

uint16_t timerDiv: srcClock_Hz / baudRate_bps

uint16_t TxDR_Offset: The offset between Tx and DR pins

uint16_t interval: Interval between frames

uint8_t TxPinIndex: Pin select for T_FORMAT_Tx.

uint8_t RxPinIndex: Pin select for T_FORMAT_Rx.

uint8_t DRPinIndex: Pin select for T_FORMAT_DR.

uint8_t shifterIndex[2]: Shifter index used in FlexIO T_FORMAT.

uint8_t timerIndex[3]: Timer index used in FlexIO T_FORMAT.

uint8_t triggerIn: Trigger signal for sync mode.

bool enableT_Format#: Enable/disable FlexIO T_FORMAT TX & RX.

bool enableInDoze: Enable/disable FlexIO operation in doze mode

bool enableInDebug: Enable/disable FlexIO operation in debug mode

bool enableFastAccess: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint8_t userMode

uint8_t *data: The buffer of data to be transfer.

uint8_t *rxData: The buffer to receive data.

const uint8_t *txData: The buffer of data to be sent.

union _flexio_t_format_transfer

size_t dataSize: Transfer size

const uint8_t *volatile txData: Address of remaining data to send.

volatile size_t txDataSize: Size of the remaining data to send.

uint8_t *volatile rxData: Address of remaining data to receive.

volatile size_t rxDataSize: Size of the remaining data to receive.

size_t txDataSizeAll: Total bytes to be sent.

size_t rxDataSizeAll: Total bytes to be received.

uint8_t *rxRingBuffer: Start address of the receiver ring buffer.

size_t rxRingBufferSize: Size of the ring buffer.

volatile uint16_t rxRingBufferHead: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail: Index for the user to get data from the ring buffer.

flexio_t_format_transfer_callback_t callback: Callback function.

void *userData: A-format callback function parameter.

volatile uint8_t txState: TX transfer state.

volatile uint8_t rxState: RX transfer state

struct _flexio_t_format_type#: #include <fsl_flexio_t-format.h>

Define FlexIO T_FORMAT access structure typedef.

struct _flexio_t_format_config#: #include <fsl_flexio_t-format.h>

Define FlexIO T_FORMAT user configuration structure.

struct _flexio_t_format_transfer#: #include <fsl_flexio_t-format.h>

Define FlexIO T-format transfer structure.

struct _flexio_t_format_handle#: #include <fsl_flexio_t-format.h>

Define FLEXIO T-format handle structure.

union __unnamed94__#

Public Members

uint8_t *data#: The buffer of data to be transfer.

uint8_t *rxData#: The buffer to receive data.

const uint8_t *txData#: The buffer of data to be sent.

FlexIO UART Driver#

status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz)#

Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART hardware, and configures the FlexIO UART with FlexIO UART configuration. The configuration structure can be filled by the user or be set with default values by FLEXIO_UART_GetDefaultConfig().

Example

FLEXIO_UART_Type base = {
.flexioBase = FLEXIO,
.TxPinIndex = 0,
.RxPinIndex = 1,
.shifterIndex = {0,1},
.timerIndex = {0,1}
};
flexio_uart_config_t config = {
.enableInDoze = false,
.enableInDebug = true,
.enableFastAccess = false,
.baudRate_Bps = 115200U,
.bitCountPerChar = 8
};
FLEXIO_UART_Init(base, &config, srcClock_Hz);

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
userConfig – Pointer to the flexio_uart_config_t structure.
srcClock_Hz – FlexIO source clock in Hz.

Return values:

kStatus_Success – Configuration success.
kStatus_FLEXIO_UART_BaudrateNotSupport – Baudrate is not supported for current clock source frequency.

void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base)#

Resets the FlexIO UART shifter and timer config.

Note

After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module.

Parameters:

base – Pointer to FLEXIO_UART_Type structure

void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig)#

Gets the default configuration to configure the FlexIO UART. The configuration can be used directly for calling the FLEXIO_UART_Init(). Example:

flexio_uart_config_t config;
FLEXIO_UART_GetDefaultConfig(&userConfig);

Parameters:

userConfig – Pointer to the flexio_uart_config_t structure.

uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base)#

Gets the FlexIO UART status flags.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART status flags.

void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask)#

Gets the FlexIO UART status flags.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Status flag. The parameter can be any combination of the following values:
- kFLEXIO_UART_TxDataRegEmptyFlag
- kFLEXIO_UART_RxEmptyFlag
- kFLEXIO_UART_RxOverRunFlag

void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)#

Enables the FlexIO UART interrupt.

This function enables the FlexIO UART interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.

void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask)#

Disables the FlexIO UART interrupt.

This function disables the FlexIO UART interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
mask – Interrupt source.

static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base)#

Gets the FlexIO UARt transmit data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART transmit data register address.

static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base)#

Gets the FlexIO UART receive data register address.

This function returns the UART data register address, which is mainly used by DMA/eDMA.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

Returns:

FlexIO UART receive data register address.

static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable)#

Enables/disables the FlexIO UART transmit DMA. This function enables/disables the FlexIO UART Tx DMA, which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.

static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)#

Enables/disables the FlexIO UART receive DMA. This function enables/disables the FlexIO UART Rx DMA, which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn’t trigger the DMA request.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
enable – True to enable, false to disable.

static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable)#

Enables/disables the FlexIO UART module operation.

Parameters:

base – Pointer to the FLEXIO_UART_Type.
enable – True to enable, false does not have any effect.

static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer)#

Writes one byte of data.

Note

This is a non-blocking API, which returns directly after the data is put into the data register. Ensure that the TxEmptyFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
buffer – The data bytes to send.

static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer)#

Reads one byte of data.

Note

This is a non-blocking API, which returns directly after the data is read from the data register. Ensure that the RxFullFlag is asserted before calling this API.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
buffer – The buffer to store the received bytes.

status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize)#

Sends a buffer of data bytes.

Note

This function blocks using the polling method until all bytes have been sent.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
txData – The data bytes to send.
txSize – The number of data bytes to send.

Return values:

kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully wrote all data.

status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize)#

Receives a buffer of bytes.

Note

This function blocks using the polling method until all bytes have been received.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
rxData – The buffer to store the received bytes.
rxSize – The number of data bytes to be received.

Return values:

kStatus_FLEXIO_UART_Timeout – Transmission timed out and was aborted.
kStatus_Success – Successfully received all data.

status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_callback_t callback, void *userData)#

Initializes the UART handle.

This function initializes the FlexIO UART handle, which can be used for other FlexIO UART transactional APIs. Call this API once to get the initialized handle.

The UART driver supports the “background” receiving, which means that users can set up a RX ring buffer optionally. Data received is stored into the ring buffer even when the user doesn’t call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly. The ring buffer is disabled if passing NULL as ringBuffer.

Parameters:

base – to FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
callback – The callback function.
userData – The parameter of the callback function.

Return values:

kStatus_Success – Successfully create the handle.
kStatus_OutOfRange – The FlexIO type/handle/ISR table out of range.

void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)#

Sets up the RX ring buffer.

This function sets up the RX ring buffer to a specific UART handle.

When the RX ring buffer is used, data received is stored into the ring buffer even when the user doesn’t call the UART_ReceiveNonBlocking() API. If there is already data received in the ring buffer, users can get the received data from the ring buffer directly.

Note

When using the RX ring buffer, one byte is reserved for internal use. In other words, if ringBufferSize is 32, only 31 bytes are used for saving data.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
ringBuffer – Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
ringBufferSize – Size of the ring buffer.

void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)#

Aborts the background transfer and uninstalls the ring buffer.

This function aborts the background transfer and uninstalls the ring buffer.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer)#

Transmits a buffer of data using the interrupt method.

This function sends data using an interrupt method. This is a non-blocking function, which returns directly without waiting for all data to be written to the TX register. When all data is written to the TX register in ISR, the FlexIO UART driver calls the callback function and passes the kStatus_FLEXIO_UART_TxIdle as status parameter.

Note

The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written to the TX register. However, it does not ensure that all data is sent out.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – FlexIO UART transfer structure. See flexio_uart_transfer_t.

Return values:

kStatus_Success – Successfully starts the data transmission.
kStatus_UART_TxBusy – Previous transmission still not finished, data not written to the TX register.

void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)#

Aborts the interrupt-driven data transmit.

This function aborts the interrupt-driven data sending. Get the remainBytes to find out how many bytes are still not sent out.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)#

Gets the number of bytes sent.

This function gets the number of bytes sent driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes sent so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, flexio_uart_transfer_t *xfer, size_t *receivedBytes)#

Receives a buffer of data using the interrupt method.

This function receives data using the interrupt method. This is a non-blocking function, which returns without waiting for all data to be received. If the RX ring buffer is used and not empty, the data in ring buffer is copied and the parameter receivedBytes shows how many bytes are copied from the ring buffer. After copying, if the data in ring buffer is not enough to read, the receive request is saved by the UART driver. When new data arrives, the receive request is serviced first. When all data is received, the UART driver notifies the upper layer through a callback function and passes the status parameter kStatus_UART_RxIdle. For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, the 5 bytes are copied to xfer->data. This function returns with the parameter receivedBytes set to 5. For the last 5 bytes, newly arrived data is saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. If the RX ring buffer is not enabled, this function enables the RX and RX interrupt to receive data to xfer->data. When all data is received, the upper layer is notified.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
xfer – UART transfer structure. See flexio_uart_transfer_t.
receivedBytes – Bytes received from the ring buffer directly.

Return values:

kStatus_Success – Successfully queue the transfer into the transmit queue.
kStatus_FLEXIO_UART_RxBusy – Previous receive request is not finished.

void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle)#

Aborts the receive data which was using IRQ.

This function aborts the receive data which was using IRQ.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count)#

Gets the number of bytes received.

This function gets the number of bytes received driven by interrupt.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.
handle – Pointer to the flexio_uart_handle_t structure to store the transfer state.
count – Number of bytes received so far by the non-blocking transaction.

Return values:

kStatus_NoTransferInProgress – transfer has finished or no transfer in progress.
kStatus_Success – Successfully return the count.

void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)#

FlexIO UART IRQ handler function.

This function processes the FlexIO UART transmit and receives the IRQ request.

Parameters:

uartType – Pointer to the FLEXIO_UART_Type structure.
uartHandle – Pointer to the flexio_uart_handle_t structure to store the transfer state.

void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)#

Flush tx/rx shifters.

Parameters:

base – Pointer to the FLEXIO_UART_Type structure.

FSL_FLEXIO_UART_DRIVER_VERSION#: FlexIO UART driver version.

Error codes for the UART driver.

Values:

enumerator kStatus_FLEXIO_UART_TxBusy#: Transmitter is busy.

enumerator kStatus_FLEXIO_UART_RxBusy#: Receiver is busy.

enumerator kStatus_FLEXIO_UART_TxIdle#: UART transmitter is idle.

enumerator kStatus_FLEXIO_UART_RxIdle#: UART receiver is idle.

enumerator kStatus_FLEXIO_UART_ERROR#: ERROR happens on UART.

enumerator kStatus_FLEXIO_UART_RxRingBufferOverrun#: UART RX software ring buffer overrun.

enumerator kStatus_FLEXIO_UART_RxHardwareOverrun#: UART RX receiver overrun.

enumerator kStatus_FLEXIO_UART_Timeout#: UART times out.

enumerator kStatus_FLEXIO_UART_BaudrateNotSupport#: Baudrate is not supported in current clock source

enum _flexio_uart_bit_count_per_char#

FlexIO UART bit count per char.

Values:

enumerator kFLEXIO_UART_7BitsPerChar#: 7-bit data characters

enumerator kFLEXIO_UART_8BitsPerChar#: 8-bit data characters

enumerator kFLEXIO_UART_9BitsPerChar#: 9-bit data characters

enum _flexio_uart_interrupt_enable#

Define FlexIO UART interrupt mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyInterruptEnable#: Transmit buffer empty interrupt enable.

enumerator kFLEXIO_UART_RxDataRegFullInterruptEnable#: Receive buffer full interrupt enable.

enum _flexio_uart_status_flags#

Define FlexIO UART status mask.

Values:

enumerator kFLEXIO_UART_TxDataRegEmptyFlag#: Transmit buffer empty flag.

enumerator kFLEXIO_UART_RxDataRegFullFlag#: Receive buffer full flag.

enumerator kFLEXIO_UART_RxOverRunFlag#: Receive buffer over run flag.

typedef enum _flexio_uart_bit_count_per_char flexio_uart_bit_count_per_char_t#: FlexIO UART bit count per char.

typedef struct _flexio_uart_type FLEXIO_UART_Type#: Define FlexIO UART access structure typedef.

typedef struct _flexio_uart_config flexio_uart_config_t#: Define FlexIO UART user configuration structure.

typedef struct _flexio_uart_transfer flexio_uart_transfer_t#: Define FlexIO UART transfer structure.

typedef struct _flexio_uart_handle flexio_uart_handle_t#

typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, status_t status, void *userData)#: FlexIO UART transfer callback function.

UART_RETRY_TIMES#: Retry times for waiting flag.

struct _flexio_uart_type#

#include <fsl_flexio_uart.h>

Define FlexIO UART access structure typedef.

Public Members

FLEXIO_Type *flexioBase#: FlexIO base pointer.

uint8_t TxPinIndex#: Pin select for UART_Tx.

uint8_t RxPinIndex#: Pin select for UART_Rx.

uint8_t shifterIndex[2]#: Shifter index used in FlexIO UART.

uint8_t timerIndex[2]#: Timer index used in FlexIO UART.

struct _flexio_uart_config#

#include <fsl_flexio_uart.h>

Define FlexIO UART user configuration structure.

Public Members

bool enableUart#: Enable/disable FlexIO UART TX & RX.

bool enableInDoze#: Enable/disable FlexIO operation in doze mode

bool enableInDebug#: Enable/disable FlexIO operation in debug mode

bool enableFastAccess#: Enable/disable fast access to FlexIO registers, fast access requires the FlexIO clock to be at least twice the frequency of the bus clock.

uint32_t baudRate_Bps#: Baud rate in Bps.

flexio_uart_bit_count_per_char_t bitCountPerChar#: number of bits, 7/8/9 -bit

struct _flexio_uart_transfer#

#include <fsl_flexio_uart.h>

Define FlexIO UART transfer structure.

Public Members

size_t dataSize#: Transfer size

struct _flexio_uart_handle#

#include <fsl_flexio_uart.h>

Define FLEXIO UART handle structure.

Public Members

const uint8_t *volatile txData#: Address of remaining data to send.

volatile size_t txDataSize#: Size of the remaining data to send.

uint8_t *volatile rxData#: Address of remaining data to receive.

volatile size_t rxDataSize#: Size of the remaining data to receive.

size_t txDataSizeAll#: Total bytes to be sent.

size_t rxDataSizeAll#: Total bytes to be received.

uint8_t *rxRingBuffer#: Start address of the receiver ring buffer.

size_t rxRingBufferSize#: Size of the ring buffer.

volatile uint16_t rxRingBufferHead#: Index for the driver to store received data into ring buffer.

volatile uint16_t rxRingBufferTail#: Index for the user to get data from the ring buffer.

flexio_uart_transfer_callback_t callback#: Callback function.

void *userData#: UART callback function parameter.

volatile uint8_t txState#: TX transfer state.

volatile uint8_t rxState#: RX transfer state

union __unnamed97__#

Public Members

uint8_t *data#: The buffer of data to be transfer.

uint8_t *rxData#: The buffer to receive data.

const uint8_t *txData#: The buffer of data to be sent.

FlexPWM: Enhanced Flex Pulse Width Modulator#

void FLEXPWM_GetDefaultSubmoduleConfig(flexpwm_submodule_config_t *config)#

Get default configuration for FlexPWM submodule.

This function initializes the FlexPWM submodule configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigSubmodule().

Default values:

Clock source: IPBus clock (kFLEXPWM_ClockSource_IPBusClock)
Prescaler: Divide by 1 (no prescaling)
Counter initial value: 0
Counter modulo value: 0xFFFF (maximum range)
Initialization source: Local sync
Load mode: Opportunity (load at PWM reload opportunity)
Load frequency: 0 (every PWM cycle)
Half-cycle reload: Disabled
Full-cycle reload: Enabled
Reload source: Local reload
Half-cycle value: 0
Debug mode: Disabled (PWM stops in Debug mode)
Wait mode: Disabled (PWM stops in Wait mode)

Parameters:

config – Pointer to the submodule configuration structure.

void FLEXPWM_ConfigSubmodule(PWM_Type *base, uint8_t submodule, const flexpwm_submodule_config_t *config)#

Configure a FlexPWM submodule.

This function configures the basic parameters of a FlexPWM submodule, including:

Clock source and prescaler (CTRL2[CLK_SEL], CTRL[PRSC])
Counter initialization and modulo values (INIT, VAL1)
Counter initialization source (CTRL2[INIT_SEL])
Register reload mode, frequency, and timing (CTRL[LDMOD, LDFQ, HALF, FULL], CTRL2[RELOAD_SEL])
Half-cycle reload point (VAL0)
Debug and Wait mode behavior (CTRL2[DBGEN, WAITEN])

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration write behavior:

This function writes configuration values to buffered registers.
The configuration does NOT take effect immediately.
After calling this function, you must set MCTRL[LDOK] bit using a separate function to transfer buffered register values to active registers.
The actual transfer timing depends on the configured reload mode and reload opportunities.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Start the PWM counter (use a separate start API)
Configure PWM waveform parameters (VAL2-VAL5, deadtime, polarity, etc.)
Configure fault protection or capture functionality
Configure FORCE_OUT behavior (use FLEXPWM_ConfigForceOut)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the submodule configuration structure.

void FLEXPWM_ConfigPWM(PWM_Type *base, uint8_t submodule, const flexpwm_pwm_config_t *config)#

Configure PWM output for a FlexPWM submodule.

This function configures the PWM output parameters for a FlexPWM submodule, including:

Compare values (VAL2, VAL3, VAL4, VAL5)
Output polarity (POLA, POLB)
Initial values (PWM23_INIT, PWM45_INIT)
Operating mode: independent or complementary (INDEP)
Complementary mode source selection (MCTRL[IPOL]) - only in complementary mode

Note

For complementary mode (complementary = true):

Only the selected channel compare values (pwma if ipolSource=kFLEXPWM_IPOL_PWM23, or pwmb if ipolSource=kFLEXPWM_IPOL_PWM45) needs to be configured.
But polarity still needs to be set for the complementary output to work correctly.
The unselected channel will be ignored by the hardware.
MCTRL[IPOL] will be set according to ipolSource parameter.

Note

For independent mode (complementary = false):

Both pwma and pwmb must be fully configured.
INDEP bit will be set to 1 in SMxCTRL2.
MCTRL[IPOL] is ignored by the hardware in this mode.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Trigger FORCE_OUT events (in complementary mode, MCTRL[IPOL] requires FORCE_OUT to take effect)
Enable PWM_A Output or PWM_B Output (use a separate API to enable outputs)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the PWM configuration structure.

void FLEXPWM_ConfigPWMChannelX(PWM_Type *base, uint8_t submodule, const flexpwm_pwm_channel_config_t *pwmx)#

Configure PWM_X output for a FlexPWM submodule.

This function configures the PWM_X output parameters for a FlexPWM submodule, including:

Compare values (VAL0, VAL1)
Output polarity (POLX)
Initial values (PWMX_INIT)

Note

When submodule works in local sync mode, PWM_X polarity is inverted, because VAL1 determines both counter modulo and PWM_X turn-off edge. VAL0 determines PWM_X turn-on edge. Recommend setting submodule counter works in master sync mode if you want to use the PWM_X output, then both VAL0 and VAL1 can be used to control PWM_X waveform shape and polarity is normal.

Note

This function does NOT:

Set the MCTRL[LDOK] bit (you must call a separate LDOK function)
Enable PWM_X Output (use a separate API to enable outputs)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
pwmx – Pointer to the PWM_X configuration structure.

void FLEXPWM_GetDefaultForceOutConfig(flexpwm_force_out_config_t *config)#

Get default configuration for force output.

This function initializes the force output configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigForceOut().

Default values:

FORCE_OUT trigger source: Local software force (kFLEXPWM_ForceOutputSource_LocalForce)
Counter initialization on FORCE_OUT: Disabled (false)
PWM_A source: Generated PWM signal (kFLEXPWM_ForcePwmSource_Generated)
PWM_A software value: Logic 0 (false)
PWM_B source: Generated PWM signal (kFLEXPWM_ForcePwmSource_Generated)
PWM_B software value: Logic 0 (false)

Parameters:

config – Pointer to the force output configuration structure.

void FLEXPWM_ConfigForceOut(PWM_Type *base, uint8_t submodule, const flexpwm_force_out_config_t *config)#

Configure FORCE_OUT for a FlexPWM submodule.

This function configures the FORCE_OUT event parameters for a FlexPWM submodule, including:

FORCE_OUT trigger source (CTRL2[FORCE_SEL]): software, master, external, sync signals, etc.
Counter initialization triggered by FORCE_OUT (CTRL2[FRCEN])
PWM source selection for deadtime logic (DTSRCSEL[SMxSEL23/45]): generated, inverted, software-controlled, or external signals
Software-controlled output values (SWCOUT[SMxOUT23/45]) when source is software-controlled

Note

Configuration write behavior:

This function performs read-modify-write operations on global registers (DTSRCSEL, SWCOUT) to protect other submodules’ configurations.
Register writes are immediate and take effect when the corresponding FORCE_OUT event occurs.
SWCOUT and DTSRCSEL are NOT affected by MCTRL[LDOK]; they are independent double-buffered registers that update on FORCE_OUT events.

Note

FORCE_OUT event effects: When a FORCE_OUT event occurs, the following updated values take effect simultaneously:

PWM source routing from DTSRCSEL
Software-controlled output values from SWCOUT
Counter may be reinitialized if FRCEN is enabled

Note

This function does NOT:

Trigger FORCE_OUT events (DTSRCSEL and SWCOUT settings require FORCE_OUT event to take effect)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the force output configuration structure.

void FLEXPWM_GetDefaultFaultConfig(flexpwm_fault_config_t *config)#

Get default configuration for fault protection.

This function initializes the fault protection configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigFaultProtection().

Default values:

Fault Input Active Level (faultInputActiveLevel): Active high (true)
Fault Clearing Mode (faultClearingMode): Automatic fault clearing
Safety Mode (enableSafetyMode): Enabled (safe mode)
Full Cycle Recovery (enableFullCycleRecovery): Enabled
Half Cycle Recovery (enableHalfCycleRecovery): Disabled
Combinational Path (enableCombinatorialPath): Enabled (allow combinational path for fastest response)

Parameters:

config – Pointer to the fault protection configuration structure.

void FLEXPWM_GetDefaultFaultSubmoduleConfig(flexpwm_fault_submodule_config_t *config)#

Get default configuration for fault submodule protection.

This function initializes the fault submodule configuration structure with safe default values. The default configuration can be used directly or modified before calling FLEXPWM_ConfigFaultSubmodule().

Default values:

Disable Mask: All faults (0x0F) affect each output
Output Behavior: High-Z (high impedance) for all outputs

For single-channel platforms: disableMask_ch0 = 0x0F For dual-channel platforms: disableMask_ch0 = 0x0F, disableMask_ch1 = 0x0F

Parameters:

config – Pointer to the fault submodule configuration structure.

void FLEXPWM_GetDefaultFaultFilterConfig(flexpwm_fault_filter_config_t *config)#

Get default configuration for fault filter.

This function initializes the fault filter configuration structure with safe default values. The default configuration provides moderate debouncing suitable for typical applications.

Default values:

Filter Period (FILT_PER): 0x08 (8 IPBus clock cycles)
Filter Count (FILT_CNT): 0x04 (7 consecutive samples = 4+3)
Glitch Stretching (GSTR): Enabled

Effective debounce window: ~56 IPBus clock cycles

Parameters:

config – Pointer to the fault filter configuration structure.

void FLEXPWM_ConfigFaultProtection(PWM_Type *base, uint8_t faultChannel, const flexpwm_fault_config_t *config, uint16_t faultMask)#

Configure fault protection for a FlexPWM fault channel.

This function configures global fault protection parameters for one fault channel, including fault input active level, clearing mode, safety mode, and fault recovery timing.

Configuration details:

Fault input active level (faultInputActiveLevel): Selects whether fault is triggered by high or low
Fault clearing mode (faultClearingMode): Controls how and when PWM outputs are re-enabled
Safety mode (enableSafetyMode): Adds extra requirement that fault input be de-asserted before re-enable
Fault recovery timing (enableFullCycleRecovery, enableHalfCycleRecovery): Specifies during which PWM cycle phase outputs re-enable
Combinational path (enableCombinatorialPath): Trades off response speed vs. latency

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration applies to the entire fault channel (all submodules that reference it). For platforms with dual fault channels, call this function separately for each channel.

Note

For platforms with dual fault channels:

faultChannel 0: Configures FAULT0-3 (FCTRL/FSTS/FFILT at offset 0x18C)
faultChannel 1: Configures FAULT4-7 (FCTRL/FSTS/FFILT at offset 0x198)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number (0 or 1 for dual-channel platforms).
config – Pointer to the fault protection configuration structure.
faultMask – Fault input selection mask for the channel. Each bit corresponds to one fault input:
- bit[0] = FAULT0 (or FAULT4 for channel 1)
- bit[1] = FAULT1 (or FAULT5 for channel 1)
- bit[2] = FAULT2 (or FAULT6 for channel 1)
- bit[3] = FAULT3 (or FAULT7 for channel 1) Example: 0x05 = configure FAULT0 and FAULT2 with the same settings. Can use flexpwm_fault_mask_t enum values (kFLEXPWM_FaultMask_0/1/2/3) and OR them together for multiple faults: (kFLEXPWM_FaultMask_0 | kFLEXPWM_FaultMask_2) = 0x05.

void FLEXPWM_ConfigFaultSubmodule(PWM_Type *base, uint8_t submodule, const flexpwm_fault_submodule_config_t *config)#

Configure fault submodule protection for a FlexPWM submodule.

This function configures fault-to-PWM-output mapping and output behavior for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a single submodule. Each output can independently select which faults affect it and how it responds during a fault.

Configuration per output:

Disable Mask: Selects which fault inputs can disable this output
- disableMask_ch0: Bits [0-3] for FAULT0-3
- disableMask_ch1: Bits [0-3] for FAULT4-7 (dual-channel platforms only)
Output Behavior: Specifies pin state during fault (Force 0, Force 1, or High-Z)

Note

Configuration applies to SMxDISMAP and SMxOCTRL registers. These registers are not affected by LDOK or FORCE_OUT; configuration takes effect immediately upon register write.

Note

For dual-channel platforms, specify disableMask_ch0 and disableMask_ch1 to control which faults (from either channel) can disable each output.

Note

For single-channel platforms, only disableMask_ch0 is used; disableMask_ch1 is conditionally compiled out.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the fault submodule configuration structure.

void FLEXPWM_ConfigFaultFilter(PWM_Type *base, uint8_t faultChannel, const flexpwm_fault_filter_config_t *config)#

Configure fault filter for a FlexPWM fault channel.

This function configures the input filter for fault protection pins, including sampling period, sample count requirement, and glitch stretching logic.

The filter helps reject electrical noise and false fault triggers by requiring the FAULTx signal to be stable for N consecutive samples before a fault is reported. With GSTR enabled, narrow fault glitches (< 2 IPBus cycles) are automatically stretched.

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Note

Configuration applies to the entire fault channel (FFILT register). For platforms with dual fault channels, call this function separately for each channel.

Note

Filter delay calculation:

Without GSTR: delay = FILT_PER * (FILT_CNT + 3) IPBus cycles
With GSTR: may be reduced due to glitch stretching logic

Note

To disable filtering:

Set filterPeriod = 0 (sampling disabled, filter bypassed)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number (0 or 1 for dual-channel platforms).
config – Pointer to the fault filter configuration structure.

void FLEXPWM_GetDefaultOutputTriggerConfig(flexpwm_output_trigger_config_t *config)#

Get default configuration for output trigger.

This function initializes the output trigger configuration structure with safe default values:

outTriggerEnable: 0 (all triggers disabled)
triggerFrequency: kFLEXPWM_TriggerFrequency_EveryCycle (trigger every PWM cycle)
muxTrig0Source: kFLEXPWM_TriggerMuxSource_GeneratedTrigger (use PWM_OUT_TRIG0)
muxTrig1Source: kFLEXPWM_TriggerMuxSource_GeneratedTrigger (use PWM_OUT_TRIG1)
stretchPrescaler: kFLEXPWM_StretchPrescaler_None (no prescaling, if supported)

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigOutputTrigger().

void FLEXPWM_ConfigOutputTrigger(PWM_Type *base, uint8_t submodule, const flexpwm_output_trigger_config_t *config)#

Configure output trigger for a FlexPWM submodule.

This function configures the output trigger parameters for a FlexPWM submodule, including:

Trigger source mapping from VAL0-5 register matches (SMxTCTRL[OUT_TRIG_EN])
Trigger output frequency control (SMxTCTRL[TRGFRQ])
PWM_MUX_TRIG0 port source selection (SMxTCTRL[PWAOT0])
PWM_MUX_TRIG1 port source selection (SMxTCTRL[PWBOT1])

The output trigger mechanism allows PWM events (counter matches with VAL registers) to trigger external modules such as ADC, DMA, or other peripherals for synchronized operation.

Note

Trigger source mapping:

VAL0, VAL2, VAL4 matches generate PWM_OUT_TRIG0
VAL1, VAL3, VAL5 matches generate PWM_OUT_TRIG1 Multiple sources can be enabled simultaneously (OR logic).

Note

Trigger frequency control (TRGFRQ): This setting only takes effect when CTRL[LDFQ] is non-zero (reload frequency divider active).

false: Trigger outputs every PWM cycle regardless of reload occurrence
true: Trigger outputs only on the last PWM cycle before a reload opportunity

Note

Port routing: PWM_MUX_TRIG0/1 ports can be routed to either:

Generated trigger signals (PWM_OUT_TRIG0/1) from VAL register matches
Direct PWM outputs (PWM_A/PWM_B) for waveform monitoring Both ports are independently configurable.

Note

Configuration takes effect immediately upon register write. This function does NOT require setting MCTRL[LDOK].

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the output trigger configuration structure.

void FLEXPWM_GetDefaultInputCaptureConfig(flexpwm_input_capture_config_t *config)#

Get default configuration for input capture.

This function initializes the input capture configuration structure with safe default values. The default values are:

All channels (A/B/X):
- edge0 = kFLEXPWM_CaptureEdge_Disabled
- edge1 = kFLEXPWM_CaptureEdge_Disabled
- oneshot = false (free running mode)
- inputSelect = kFLEXPWM_CaptureInput_RawSignal
- edgeCompareValue = 0
- fifoWatermark = kFLEXPWM_CaptureFifoWatermark_1

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigInputCapture().

Parameters:

config – Pointer to the input capture configuration structure.

void FLEXPWM_GetDefaultCaptureFilterConfig(flexpwm_capture_filter_config_t *config)#

Get default configuration for capture filter.

This function initializes the capture filter configuration structure with safe default values. The default values are:

All channels (A/B/X):
- filterPeriod = 0 (filter bypassed, sampling disabled)
- filterCount = 0 (requires 3 consecutive samples)

After calling this function, the user should modify the fields as needed before calling FLEXPWM_ConfigInputCaptureFilter().

Parameters:

config – Pointer to the capture filter configuration structure.

void FLEXPWM_ConfigInputCapture(PWM_Type *base, uint8_t submodule, const flexpwm_input_capture_config_t *config)#

Configure input capture for a FlexPWM submodule.

This function configures the input capture parameters for up to three capture channels (Capture_A, Capture_B, Capture_X) of a FlexPWM submodule, including:

Edge detection configuration for two edge detectors per channel (SMxCAPTCTRLA/B/X[EDGx0/1])
One-shot or free-running mode (SMxCAPTCTRLA/B/X[ONESHOTx])
Input source selection: raw signal or edge counter output (SMxCAPTCTRLA/B/X[INP_SELx])
Edge counter compare value (SMxCAPTCOMPA/B/X[EDGCMPx])
FIFO watermark level (SMxCAPTCTRLA/B/X[CFxWM])

Note

Edge counter behavior:

When inputSelect = kFLEXPWM_CaptureInput_EdgeCounter, the edge counter is automatically enabled (EDGCNTx_EN = 1) by this function.
When inputSelect = kFLEXPWM_CaptureInput_RawSignal, the edge counter remains disabled.

Note

Capture enable control:

This function does NOT control the capture enable bits (ARMA/ARMB/ARMX).
After calling this function, use a separate enable API to start capture operation.

Note

CVAL register mapping (NON-INTUITIVE):

Capture_X: Edge0 -> CVAL0, Edge1 -> CVAL1
Capture_A: Edge0 -> CVAL2, Edge1 -> CVAL3
Capture_B: Edge0 -> CVAL4, Edge1 -> CVAL5

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the input capture configuration structure.

void FLEXPWM_ConfigInputCaptureFilter(PWM_Type *base, uint8_t submodule, const flexpwm_capture_filter_config_t *config)#

Configure input capture filter for a FlexPWM submodule.

This function configures the digital filter parameters for the three capture channels (Capture_A, Capture_B, Capture_X) of a FlexPWM submodule. The filter settings include:

Filter sampling period (SMxCAPTFILTA/B/X[CAPTx_FILT_PER])
Number of consecutive samples required (SMxCAPTFILTA/B/X[CAPTx_FILT_CNT])

The digital filter can eliminate glitches and noise on the capture input signals.

Note

Filter bypassing:

Set filterPeriod = 0 to bypass the filter (no sampling, filter disabled).

Note

Filter delay calculation:

Delay = filterPeriod * (filterCount + 3) IPBus clock cycles
Example: filterPeriod=5, filterCount=2 -> delay = 5*(2+3) = 25 cycles

Note

Hardware behavior:

This function always writes 0 to the filter register first, then writes the configuration value. This ensures correct behavior per hardware requirements.

Note

Prerequisites:

Call FLEXPWM_Init() before this function to enable the peripheral clock.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
config – Pointer to the capture filter configuration structure.

uint16_t FLEXPWM_GetInputCaptureValue(PWM_Type *base, uint8_t submodule, flexpwm_capture_index_t captureIndex)#

Read captured value from a FlexPWM capture channel.

This function reads the captured counter value from one of the six capture value registers (CVAL0-5) for the specified capture channel and edge detector.

Note

CVAL register mapping (NON-INTUITIVE):

kFLEXPWM_Capture_X_Edge0 -> CVAL0
kFLEXPWM_Capture_X_Edge1 -> CVAL1
kFLEXPWM_Capture_A_Edge0 -> CVAL2
kFLEXPWM_Capture_A_Edge1 -> CVAL3
kFLEXPWM_Capture_B_Edge0 -> CVAL4
kFLEXPWM_Capture_B_Edge1 -> CVAL5

Warning

Destructive read:

Reading a CVAL register decrements the FIFO count by 1.
If the FIFO is empty, the read value is undefined.
Check the FIFO empty flag (CFx) before reading to avoid invalid data.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
captureIndex – Capture channel and edge detector index (use flexpwm_capture_index_t enum).

Returns:

The captured counter value (16-bit).

uint16_t FLEXPWM_GetInputCaptureCycle(PWM_Type *base, uint8_t submodule, flexpwm_capture_index_t captureIndex)#

Read captured cycle counter value from a FlexPWM capture channel.

This function reads the captured cycle counter value from one of the six capture cycle registers (CCYC0-5) for the specified capture channel and edge detector. The cycle counter value represents the upper part of the extended timestamp when a capture event occurs.

Note

CCYC register mapping (matches CVAL mapping):

kFLEXPWM_Capture_X_Edge0 -> CCYC0
kFLEXPWM_Capture_X_Edge1 -> CCYC1
kFLEXPWM_Capture_A_Edge0 -> CCYC2
kFLEXPWM_Capture_A_Edge1 -> CCYC3
kFLEXPWM_Capture_B_Edge0 -> CCYC4
kFLEXPWM_Capture_B_Edge1 -> CCYC5

Note

Combined timestamp:

The full timestamp is {CCYC, CVAL} (cycle counter as upper 16 bits, capture value as lower 16 bits), forming a 32-bit extended timestamp.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
captureIndex – Capture channel and edge detector index (use flexpwm_capture_index_t enum).

Returns:

The captured cycle counter value (16-bit).

void FLEXPWM_EnableInputCapture(PWM_Type *base, uint8_t submodule, flexpwm_capture_channel_t channel)#

Enable input capture for a FlexPWM capture channel.

This function enables input capture operation for the specified capture channel by setting the corresponding ARM bit (ARMA/ARMB/ARMX) in the capture control register.

Note

ARM bit behavior in one-shot mode: When the capture channel is configured for one-shot mode (ONESHOT = 1), the ARM bit automatically clears after two capture events complete.

Note

Prerequisites: Before enabling capture, ensure:

Capture channel is configured (FLEXPWM_ConfigInputCapture)
Edge detectors are configured (EDGA0/EDGA1, EDGB0/EDGB1, or EDGX0/EDGX1)
Counter is running (FLEXPWM_EnableSubmoduleCounter)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
channel – Capture channel selection (use flexpwm_capture_channel_t enum).

void FLEXPWM_DisableInputCapture(PWM_Type *base, uint8_t submodule, flexpwm_capture_channel_t channel)#

Disable input capture for a FlexPWM capture channel.

This function disables input capture operation for the specified capture channel by clearing the corresponding ARM bit (ARMA/ARMB/ARMX) in the capture control register.

Note

FIFO handling: Disabling capture does not flush the FIFO. Any previously captured values remain readable. Clear the capture flags (CFx0/CFx1) separately if needed.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
channel – Capture channel selection (use flexpwm_capture_channel_t enum).

static inline void FLEXPWM_SetINIT(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the INIT register value for a FlexPWM submodule.

This function directly writes a value to the INIT register (initial count register). The INIT register defines the starting value of the counter when it is initialized.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM parameters. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for:

Ensuring LDOK is clear before calling this function
Setting LDOK after updating registers to trigger reload
Managing reload timing and synchronization

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the INIT register (16-bit).

static inline void FLEXPWM_SetVAL0(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL0 register value for a FlexPWM submodule.

This function directly writes a value to the VAL0 register. VAL0 defines the half-cycle reload point for the PWM counter.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL0 register (16-bit).

static inline void FLEXPWM_SetVAL1(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL1 register value for a FlexPWM submodule.

This function directly writes a value to the VAL1 register. VAL1 defines the modulo (period) value for the PWM counter.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM period. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL1 register (16-bit).

static inline void FLEXPWM_SetVAL2(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL2 register value for a FlexPWM submodule.

This function directly writes a value to the VAL2 register. VAL2 defines the count value at which PWM23 (PWM_A) is set high, controlling the turn-on edge of PWM_A output.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM_A duty cycle. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL2 register (16-bit).

static inline void FLEXPWM_SetVAL3(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL3 register value for a FlexPWM submodule.

This function directly writes a value to the VAL3 register. VAL3 defines the count value at which PWM23 (PWM_A) is set low, controlling the turn-off edge of PWM_A output.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL3 register (16-bit).

static inline void FLEXPWM_SetVAL4(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL4 register value for a FlexPWM submodule.

This function directly writes a value to the VAL4 register. VAL4 defines the count value at which PWM45 (PWM_B) is set high, controlling the turn-on edge of PWM_B output.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust PWM_B duty cycle. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL4 register (16-bit).

static inline void FLEXPWM_SetVAL5(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the VAL5 register value for a FlexPWM submodule.

This function directly writes a value to the VAL5 register. VAL5 defines the count value at which PWM45 (PWM_B) is set low, controlling the turn-off edge of PWM_B output.

Note

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the VAL5 register (16-bit).

static inline void FLEXPWM_SetDTCNT0(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the DTCNT0 register value for a FlexPWM submodule.

This function directly writes a value to the DTCNT0 register (deadtime count register 0). DTCNT0 specifies the number of IPBus clock cycles for deadtime delay insertion, independent of the PWM clock prescaler settings (CTRL[PRSC] and CTRL2[CLK_SEL]). DTCNT0 inserts software-selectable activation delays at PWM_A turn-on edge.

Note

DTCNT0 is an 11-bit register with valid range 0-0x7FF. Values exceeding this range will be masked to 11 bits.

Note

This function applies only to complementary PWM mode.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the DTCNT0 register (11-bit, range: 0-0x7FF).

static inline void FLEXPWM_SetDTCNT1(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the DTCNT1 register value for a FlexPWM submodule.

This function directly writes a value to the DTCNT1 register (deadtime count register 1). DTCNT1 specifies the number of IPBus clock cycles for deadtime delay insertion, independent of the PWM clock prescaler settings (CTRL[PRSC] and CTRL2[CLK_SEL]). DTCNT1 inserts software-selectable activation delays at PWM_B turn-on edge.

Note

DTCNT1 is an 11-bit register with valid range 0-0x7FF. Values exceeding this range will be masked to 11 bits.

Note

This function applies only to complementary PWM mode.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
value – The value to write to the DTCNT1 register (11-bit, range: 0-0x7FF).

static inline void FLEXPWM_SetPhaseDelay(PWM_Type *base, uint8_t submodule, uint16_t value)#

Set the Phase Delay register value for a FlexPWM submodule.

This function directly writes a value to the PHASEDLY register (phase delay register). PHASEDLY defines the time delay from the master sync signal (from submodule 0) to when this submodule recognizes the master sync, specified in PWM clock cycles.

Setting this register to a non-zero value and using the master sync signal as the initialization source allows this submodule’s output to be delayed by a fixed number of cycles relative to submodule 0, enabling phase-shifted PWM outputs.

Note

PHASEDLY is only valid for submodules 1-3. Submodule 0 is the master sync source and cannot have a phase delay relative to itself.

Note

This function is intended for use in runtime scenarios such as interrupt handlers to dynamically adjust phase delay. It performs a direct register write without checking or managing MCTRL[LDOK]. Users are responsible for reload timing.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (1-3, must NOT be 0).
value – The value to write to the PHASEDLY register (16-bit).

static inline void FLEXPWM_SetCompareMode(PWM_Type *base, uint8_t submodule, flexpwm_compare_mode_t compareMode)#

Set Compare Mode for a FlexPWM submodule.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
compareMode – The compare mode to set for the submodule.

static inline void FLEXPWM_MaskPWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Mask PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function sets the MASK register bits to mask (disable) PWM outputs by forcing them to logic 0 before output polarity is applied. The mask takes effect when a FORCE_OUT event occurs on the corresponding submodule, unless immediate update is enabled.

Note

MASK register characteristics:

Double-buffered register: writes take effect on next FORCE_OUT event
Use FLEXPWM_EnableUpdateMaskImmediately() to bypass FORCE_OUT requirement
Masking forces output to logic 0 before polarity inversion

Note

This function performs read-modify-write to preserve:

Mask settings for other submodules not specified in parameters
UPDATE_MASK bits (on platforms with FSL_FEATURE_PWM_MASK_HAS_UPDATE_MASK_BITFIELD)

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_UnMaskPWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Unmask PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function clears the MASK register bits to unmask (enable) PWM outputs. The unmask takes effect when a FORCE_OUT event occurs on the corresponding submodule, unless immediate update is enabled.

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_EnableUpdateMaskImmediately(PWM_Type *base, uint16_t submoduleMask)#

Enable immediate MASK register update for specified submodules.

This function configures the specified submodules to update their MASK register values immediately, bypassing the FORCE_OUT event requirement. This is useful for emergency stop or fault protection scenarios where immediate output masking is required.

Note

MASK[UPDATE_MASK] register characteristics:

Setting a bit to 1 enables immediate MASK update for that submodule
Once enabled, MASK updates take effect immediately without waiting for FORCE_OUT

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetPWMSource23(PWM_Type *base, uint8_t submodule, uint16_t source)#

Set PWM source for PWM23 (PWM_A) of a submodule.

This function selects the signal source that feeds into the deadtime insertion logic for PWM23 (PWM_A) output by configuring the DTSRCSEL register. The setting takes effect when a FORCE_OUT event occurs on the submodule.

Available sources:

Generated PWM: Normal PWM signal from PWM generator
Inverted PWM: Inverted version of generated PWM
Software: Software-controlled value from SWCOUT register
External: External input signal

Note

DTSRCSEL register characteristics:

Double-buffered: Changes take effect on next FORCE_OUT event
NOT affected by MCTRL[LDOK]: Independent of reload mechanism
Global register: This function performs read-modify-write to protect other submodules

Note

When source is set to kFLEXPWM_ForcePwmSource_Software, use FLEXPWM_SetSoftwareControlOutput23() to set the output value.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
source – PWM source selection (use flexpwm_force_pwm_source_t enum).

static inline void FLEXPWM_SetPWMSource45(PWM_Type *base, uint8_t submodule, uint16_t source)#

Set PWM source for PWM45 (PWM_B) of a submodule.

This function selects the signal source that feeds into the deadtime insertion logic for PWM45 (PWM_B) output by configuring the DTSRCSEL register. The setting takes effect when a FORCE_OUT event occurs on the submodule.

Note

See FLEXPWM_SetPWMSource23() documentation for detailed information about source selection, register characteristics, and usage notes.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
source – PWM source selection (use flexpwm_force_pwm_source_t enum).

static inline void FLEXPWM_SetSoftwareControlOutput23(PWM_Type *base, uint8_t submodule, uint16_t softwareValue)#

Set software-controlled output value for PWM23 (PWM_A) of a submodule.

This function sets the software-controlled PWM output value in the SWCOUT register. This value is used as the PWM source when DTSRCSEL is configured to select software control (kFLEXPWM_ForcePwmSource_Software). The setting takes effect when a FORCE_OUT event occurs on the submodule.

Note

SWCOUT register characteristics:

Double-buffered: Changes take effect on next FORCE_OUT event
NOT affected by MCTRL[LDOK]: Independent of reload mechanism
Global register: This function performs read-modify-write to protect other submodules

Note

Typical usage sequence:

Call FLEXPWM_SetPWMSource23(base, kFLEXPWM_ForcePwmSource_Software, submodule)
Call FLEXPWM_SetSoftwareControlOutput23(base, value, submodule)
Trigger FORCE_OUT event to make both settings take effect

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
softwareValue – Software control output value (0 or 1).
- 0: Logic 0 provided to deadtime logic instead of PWM23
- 1: Logic 1 provided to deadtime logic instead of PWM23

static inline void FLEXPWM_SetSoftwareControlOutput45(PWM_Type *base, uint8_t submodule, uint16_t softwareValue)#

Set software-controlled output value for PWM45 (PWM_B) of a submodule.

Note

See FLEXPWM_SetSoftwareControlOutput23() documentation for detailed information about register characteristics, usage sequence, and notes.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
softwareValue – Software control output value (0 or 1).
- 0: Logic 0 provided to deadtime logic instead of PWM45
- 1: Logic 1 provided to deadtime logic instead of PWM45

static inline void FLEXPWM_SetComplementaryPWMSource23(PWM_Type *base, uint16_t submoduleMask)#

Select PWM23 (PWM_A) as complementary PWM source for specified submodules.

This function configures the MCTRL[IPOL] register to select PWM23 (PWM_A) as the source for generating complementary PWM pair outputs in complementary mode. The setting takes effect when a FORCE_OUT event occurs on the submodule.

In complementary mode:

PWM_A output: PWM23 signal (non-inverted)
PWM_B output: ~PWM23 signal (inverted complement)

Note

MCTRL[IPOL] register characteristics:

Takes effect on FORCE_OUT event (double-buffered behavior)
Only applies when submodule is in complementary mode (INDEP = 0)
Ignored in independent mode (INDEP = 1)

Note

This function clears IPOL bits for specified submodules (IPOL = 0 selects PWM23).

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetComplementaryPWMSource45(PWM_Type *base, uint16_t submoduleMask)#

Select PWM45 (PWM_B) as complementary PWM source for specified submodules.

This function configures the MCTRL[IPOL] register to select PWM45 (PWM_B) as the source for generating complementary PWM pair outputs in complementary mode. The setting takes effect when a FORCE_OUT event occurs on the submodule.

In complementary mode:

PWM_A output: ~PWM45 signal (inverted complement)
PWM_B output: PWM45 signal (non-inverted)

Note

See FLEXPWM_SetComplementaryPWMSource23() documentation for detailed information about MCTRL[IPOL] characteristics and complementary mode operation.

Note

This function sets IPOL bits for specified submodules (IPOL = 1 selects PWM45).

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetLoadOkay(PWM_Type *base, uint16_t submoduleMask)#

Set Load Okay (LDOK) for specified submodules.

This function sets the MCTRL[LDOK] bits to enable register reload for the specified submodules. When LDOK is set, buffered register values will be transferred to active registers according to the reload mode and timing configured in CTRL[LDMOD, LDFQ, HALF, FULL].

Note

LDOK behavior:

Can only be set when the corresponding LDOK bit is currently 0
Automatically cleared by hardware after reload completes
Can be manually cleared using FLEXPWM_ClearLoadOkay()
While LDOK=1, writes to buffered registers are blocked

Note

Typical usage flow:

Modify buffered registers (VAL0-5, INIT, etc.) using FLEXPWM_SetVALx() or similar
Call FLEXPWM_SetLoadOkay() to trigger reload
Hardware transfers buffered values at the configured reload opportunity
LDOK automatically clears after reload completes

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_ClearLoadOkay(PWM_Type *base, uint16_t submoduleMask)#

Clear Load Okay (LDOK) for specified submodules.

This function clears the MCTRL[LDOK] bits by writing to MCTRL[CLDOK] bits. This cancels a pending reload operation for the specified submodules.

Note

MCTRL[CLDOK] (Clear LDOK) mechanism:

Writing 1 to CLDOK[x] clears the corresponding LDOK[x] bit
CLDOK is write-only; reading always returns 0
Use this when you need to cancel a pending reload

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline uint16_t FLEXPWM_GetLoadOkay(PWM_Type *base)#

Get Load Okay (LDOK) status.

This function reads the MCTRL[LDOK] bits to check which submodules have pending reload operations.

Note

Return value format:

Bit[0]: Submodule 0 LDOK status
Bit[1]: Submodule 1 LDOK status
Bit[2]: Submodule 2 LDOK status
Bit[3]: Submodule 3 LDOK status

Note

Usage example:

uint16_t ldokStatus = FLEXPWM_GetLoadOkay(PWM0);
if (ldokStatus & kFLEXPWM_SubmoduleMask_0) {
}

Parameters:

base – FlexPWM peripheral base address.

Returns:

LDOK status bits (bit[3:0] correspond to submodules 3-0). Use flexpwm_submodule_mask_t enum values to check specific submodules.

static inline void FLEXPWM_SetLocalForceOut(PWM_Type *base, uint8_t submodule)#

Set local FORCE_OUT event for a submodule.

This function sets the SMxCTRL2[FORCE] bit to trigger a local FORCE_OUT event. When a FORCE_OUT event occurs, several double-buffered registers immediately update:

DTSRCSEL (PWM source selection)
SWCOUT (software-controlled output values)
MASK (output masking)
MCTRL[IPOL] (complementary PWM source selection)

Additionally, if CTRL2[FRCEN] is enabled and the counter is running, the counter will be initialized to the INIT register value.

Note

FORCE_OUT trigger source: This function triggers a local FORCE_OUT event by setting CTRL2[FORCE]. The FORCE_OUT event only occurs if CTRL2[FORCE_SEL] = 0 (local force selected). If FORCE_SEL selects a different source, setting FORCE has no effect.

Note

Counter initialization: The counter is reinitialized only if:

CTRL2[FRCEN] = 1 (force initialization enabled), AND
MCTRL[RUN] = 1 (counter running) OR CTRL2[CLK_SEL] = 2 (submodule 0 aux clock)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).

static inline void FLEXPWM_SetCounterForceInitialization(PWM_Type *base, uint8_t submodule, bool enable)#

Enable or disable counter initialization on FORCE_OUT event.

This function controls whether FORCE_OUT events can trigger counter initialization by configuring the CTRL2[FRCEN] bit. When enabled, the counter will be reset to the INIT register value when local software forced event occurs.

Note

Counter initialization conditions: The counter is reinitialized only when ALL of the following conditions are met:

CTRL2[FRCEN] = 1 (enabled via this function), AND
A local FORCE_OUT event occurs (CTRL2[FORCE_SEL] = 0, CTRL2[FORCE] = 1)

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
enable – Enable or disable counter force initialization:
- true: FORCE_OUT events can trigger counter initialization (FRCEN = 1)
- false: FORCE_OUT events do not affect counter initialization (FRCEN = 0)

static inline void FLEXPWM_EnableSubmoduleCounter(PWM_Type *base, uint16_t submoduleMask)#

Enable PWM counter for specified submodules.

This function enables the PWM counters for the specified submodules by setting MCTRL[RUN] bits. When enabled, the counters start running and generating PWM waveforms.

Note

Effects of enabling counter (RUN=1):

Counter begins incrementing/decrementing according to configuration
PWM generation starts (if outputs are also enabled)
Reload events can occur at configured opportunities
FORCE_OUT can trigger counter initialization (if FRCEN enabled)

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_DisableSubmoduleCounter(PWM_Type *base, uint16_t submoduleMask)#

Disable PWM counter for specified submodules.

This function disables the PWM counters for the specified submodules by clearing MCTRL[RUN] bits. When disabled, the counters stop running but retain their configuration.

Note

Effects of disabling counter (RUN=0):

Counter stops incrementing/decrementing
PWM generation ceases (outputs hold last state or go to fault state)
Configuration registers remain intact
Fault clearing behavior changes (see fault protection documentation)

Parameters:

base – FlexPWM peripheral base address.
submoduleMask – Submodule selection mask (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_EnablePWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Enable PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function enables PWM outputs by setting the corresponding bits in the OUTEN register. Each output (PWM_A, PWM_B, PWM_X) can be independently enabled for each submodule.

Note

OUTEN register layout (same as MASK register):

bit[11:8]: PWMA_EN - PWM_A output enable for submodules 3-0
bit[7:4]: PWMB_EN - PWM_B output enable for submodules 3-0
bit[3:0]: PWMX_EN - PWM_X output enable for submodules 3-0

Note

Prerequisites: Before enabling outputs, ensure:

PWM waveform is configured (FLEXPWM_ConfigPWM)
Counter is running (FLEXPWM_EnableSubmoduleCounter)
Outputs are not masked (check MASK register)

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_DisablePWMOutput(PWM_Type *base, uint16_t aMask, uint16_t bMask, uint16_t xMask)#

Disable PWM_A, PWM_B, PWM_X outputs for specified submodules.

This function disables PWM outputs by clearing the corresponding bits in the OUTEN register. When an output is disabled, the pin is released from FlexPWM control and may be controlled by other peripherals or GPIO.

Note

Output disable effects:

Pin is tri-stated or controlled by GPIO/other peripherals
PWM waveform generation continues internally
Re-enabling the output will resume PWM operation seamlessly

Parameters:

base – FlexPWM peripheral base address.
aMask – Submodule mask for PWM_A outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
bMask – Submodule mask for PWM_B outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.
xMask – Submodule mask for PWM_X outputs (OR’ed combination of flexpwm_submodule_mask_t). bit[0]=SM0, bit[1]=SM1, bit[2]=SM2, bit[3]=SM3.

static inline void FLEXPWM_SetWriteProtection(PWM_Type *base, flexpwm_write_protect_t config)#

Set FlexPWM write protection mode.

This function configures the write protection for FlexPWM registers by setting MCTRL2[WRPROT]. Write protection prevents accidental modification of critical PWM configuration registers.

Note

Write protection modes:

kFLEXPWM_WriteProtect_Off: Write protection is disabled (default after reset)
kFLEXPWM_WriteProtect_On: Write protection is enabled but can be disabled
kFLEXPWM_WriteProtect_OffLocked: Write protection is disabled and locked until chip reset
kFLEXPWM_WriteProtect_OnLocked: Write protection is enabled and locked until chip reset

Note

Once a locked mode is set (OffLocked or OnLocked), the write protection state cannot be changed until the next chip reset. Use locked modes for safety-critical applications.

Parameters:

base – FlexPWM peripheral base address.
config – Write protection mode selection.

static inline void FLEXPWM_EnableSubmoduleInterrupts(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Enable FlexPWM submodule interrupts.

This function enables the specified interrupt sources for a FlexPWM submodule by setting the corresponding bits in the SMxINTEN register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Interrupt enable mask (OR’ed combination of _flexpwm_submodule_interrupt_enable flags).

static inline void FLEXPWM_DisableSubmoduleInterrupts(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Disable FlexPWM submodule interrupts.

This function disables the specified interrupt sources for a FlexPWM submodule by clearing the corresponding bits in the SMxINTEN register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Interrupt disable mask (OR’ed combination of _flexpwm_submodule_interrupt_enable flags).

static inline uint16_t FLEXPWM_GetSubmoduleStatusFlags(PWM_Type *base, uint8_t submodule)#

Get FlexPWM submodule status flags.

This function returns the current status flags from the SMxSTS register.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).

Returns:

Current status flags (combination of _flexpwm_submodule_status_flag values).

static inline void FLEXPWM_ClearSubmoduleStatusFlags(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Clear FlexPWM submodule status flags.

This function clears the specified status flags in the SMxSTS register using the write-1-to-clear (W1C) mechanism.

Note

Do not attempt to clear kFLEXPWM_RegisterUpdatedFlag (RUF) as it is read-only.

Parameters:

base – FlexPWM peripheral base address.
submodule – Submodule number (0-3).
mask – Status flag clear mask (OR’ed combination of _flexpwm_submodule_status_flag values). To clear a flag, set the corresponding bit to 1 in the mask.

static inline void FLEXPWM_EnableFaultInterrupts(PWM_Type *base, uint8_t faultChannel, uint16_t mask)#

Enable FlexPWM fault interrupts.

This function enables the specified fault interrupt sources by setting the corresponding bits in the FCTRL[FIE] field.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1): The same mask bit values are used for both fault channels. The faultChannel parameter determines which set of fault inputs is controlled:

faultChannel = 0: Controls FAULT0-3 interrupts
faultChannel = 1: Controls FAULT4-7 interrupts

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault interrupt enable mask (OR’ed combination of _flexpwm_fault_interrupt_enable flags).

static inline void FLEXPWM_DisableFaultInterrupts(PWM_Type *base, uint8_t faultChannel, uint16_t mask)#

Disable FlexPWM fault interrupts.

This function disables the specified fault interrupt sources by clearing the corresponding bits in the FCTRL[FIE] field.

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault interrupt disable mask (OR’ed combination of _flexpwm_fault_interrupt_enable flags).

static inline uint16_t FLEXPWM_GetFaultStatusFlags(PWM_Type *base, uint8_t faultChannel)#

Get FlexPWM fault status flags.

This function returns the current fault status flags (FFLAG bits) from the FSTS register. These are latched flags that indicate a fault event has occurred.

Note

To check real-time hardware pin status (rather than latched flags), use FLEXPWM_GetFaultFilteredPinStatusFlags() instead.

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)

Returns:

Current fault flags (combination of _flexpwm_fault_status_flag values).

static inline void FLEXPWM_ClearFaultStatusFlags(PWM_Type *base, uint8_t faultChannel, uint16_t mask)#

Clear FlexPWM fault status flags.

This function clears the specified fault status flags (FFLAG bits) in the FSTS register using the write-1-to-clear (W1C) mechanism.

Note

Clearing FFLAG does not automatically re-enable PWM outputs. The re-enable timing depends on fault clearing mode (FAUTO), safety mode (FSAFE), recovery timing (FHALF/FFULL), and the state of FFPIN (filtered pin status).

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3)
- 1: Fault channel 1 (FAULT4-7, if supported)
mask – Fault flag clear mask (OR’ed combination of _flexpwm_fault_status_flag values). To clear a flag, set the corresponding bit to 1 in the mask.

static inline uint16_t FLEXPWM_GetFaultFilteredPinStatusFlags(PWM_Type *base, uint8_t faultChannel)#

Get FlexPWM filtered fault pin status.

This function returns the real-time status of fault pins after filtering (FFPIN bits) from the FSTS register. These are read-only hardware status bits that reflect the current state of external fault signals.

Note

Key differences:

FFLAG: Software-clearable latched flag (historical event - “a fault occurred”)
FFPIN: Read-only real-time status (current state - “fault is active now”)

Parameters:

base – FlexPWM peripheral base address.
faultChannel – Fault channel number:
- 0: Fault channel 0 (FAULT0-3 pins)
- 1: Fault channel 1 (FAULT4-7 pins, if supported)

Returns:

Current filtered fault pin status (combination of _flexpwm_fault_pin_status values).

void FLEXPWM_ConfigDMA(PWM_Type *base, uint8_t submodule, const flexpwm_dma_config_t *config)#

Configures the DMA control strategy for a FlexPWM submodule.

This function configures the DMA trigger source and FIFO watermark logic. These settings define the DMA request generation strategy and should typically be configured once during initialization.

Note

This function only configures CAPTDE[7:6] and FAND bits in SMxDMAEN register. To enable/disable individual DMA channels at runtime, use FLEXPWM_EnableDMA() and FLEXPWM_DisableDMA().

Note

Prerequisites: Before calling this function, ensure:

FIFO watermark levels are configured in FLEXPWM_ConfigInputCapture()
Capture channels are properly configured if using capture DMA

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
config – Pointer to DMA configuration structure

static inline void FLEXPWM_EnableDMA(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Enable FlexPWM submodule DMA requests.

This function enables DMA request generation for the specified channels. It controls the VALDE bit (VALx/FRACVALx write) and capture channel enables (CX0DE, CX1DE, CB0DE, CB1DE, CA0DE, CA1DE).

Note

Before calling this function, ensure FLEXPWM_ConfigDMA() has been called to set up the DMA trigger strategy.

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
mask – Bit mask of DMA enable flags (OR’ed combination of _flexpwm_dma_enable)

static inline void FLEXPWM_DisableDMA(PWM_Type *base, uint8_t submodule, uint16_t mask)#

Disable FlexPWM submodule DMA requests.

This function disables DMA request generation for the specified channels.

Parameters:

base – FlexPWM peripheral base address
submodule – FlexPWM submodule number (0-3)
mask – Bit mask of DMA enable flags (OR’ed combination of _flexpwm_dma_enable)

FSL_FLEXPWM_DRIVER_VERSION#: Version 2.0.0

enum _flexpwm_clock_source#

FlexPWM clock source selection.

Values:

enumerator kFLEXPWM_ClockSource_IPBusClock#: IPBus clock

enumerator kFLEXPWM_ClockSource_ExtClock#: External clock (EXT_CLK)

enumerator kFLEXPWM_ClockSource_Submodule0Clock#: Submodule 0 auxiliary clock

enum _flexpwm_prescaler#

FlexPWM clock prescaler selection.

Values:

enumerator kFLEXPWM_Prescale_Divide_1#: Divide by 1

enumerator kFLEXPWM_Prescale_Divide_2#: Divide by 2

enumerator kFLEXPWM_Prescale_Divide_4#: Divide by 4

enumerator kFLEXPWM_Prescale_Divide_8#: Divide by 8

enumerator kFLEXPWM_Prescale_Divide_16#: Divide by 16

enumerator kFLEXPWM_Prescale_Divide_32#: Divide by 32

enumerator kFLEXPWM_Prescale_Divide_64#: Divide by 64

enumerator kFLEXPWM_Prescale_Divide_128#: Divide by 128

enum _flexpwm_load_mode#

FlexPWM load mode selection.

Values:

enumerator kFLEXPWM_LoadMode_Opportunity#: Load at PWM reload opportunity

enumerator kFLEXPWM_LoadMode_Immediate#: Load immediately after LDOK is set

enum _flexpwm_reload_source#

FlexPWM reload source selection.

Values:

enumerator kFLEXPWM_ReloadSource_LocalReload#: Local reload signal

enumerator kFLEXPWM_ReloadSource_MasterReload#: Master reload signal from submodule 0

enum _flexpwm_init_source#

FlexPWM counter initialization source selection.

Values:

enumerator kFLEXPWM_InitSource_LocalSync#: Local sync signal

enumerator kFLEXPWM_InitSource_MasterReload#: Master reload signal from submodule 0

enumerator kFLEXPWM_InitSource_MasterSync#: Master sync signal from submodule 0

enumerator kFLEXPWM_InitSource_ExtSync#: External sync signal (EXT_SYNC)

enum _flexpwm_compare_mode#

FlexPWM PWM compare mode selection.

Values:

enumerator kFLEXPWM_CompareMode_Equal#: Compare when counter equals compare value

enumerator kFLEXPWM_CompareMode_EqualGreater#: Compare when counter is equal or greater than compare value

enum _flexpwm_submodule_mask#

FlexPWM submodule mask for multi-submodule operations.

These flags can be OR’ed together to specify multiple submodules simultaneously. Used with functions that operate on multiple submodules at once.

Values:

enumerator kFLEXPWM_SubmoduleMask_0#: Submodule 0

enumerator kFLEXPWM_SubmoduleMask_1#: Submodule 1

enumerator kFLEXPWM_SubmoduleMask_2#: Submodule 2

enum _flexpwm_pwm_polarity#

FlexPWM PWM output polarity selection.

Values:

enumerator kFLEXPWM_Polarity_ActiveHigh#: PWM signal is normal (active high)

enumerator kFLEXPWM_Polarity_ActiveLow#: PWM signal is inverted (active low)

enum _flexpwm_ipol_source#

FlexPWM PWM output source selection for complementary mode.

Values:

enumerator kFLEXPWM_IPOL_PWM23#: Use PWM23 (PWM_A) as complementary PWM source

enumerator kFLEXPWM_IPOL_PWM45#: Use PWM45 (PWM_B) as complementary PWM source

enum _flexpwm_force_output_source#

FlexPWM FORCE_OUT event source selection.

Values:

enumerator kFLEXPWM_ForceOutputSource_LocalForce#: Local software forced event

enumerator kFLEXPWM_ForceOutputSource_MasterForce#: Master force signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_LocalReload#: Local reload signal

enumerator kFLEXPWM_ForceOutputSource_MasterReload#: Master reload signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_LocalSync#: Local sync signal

enumerator kFLEXPWM_ForceOutputSource_MasterSync#: Master sync signal from submodule 0

enumerator kFLEXPWM_ForceOutputSource_ExtForce#: External force signal (EXT_FORCE)

enumerator kFLEXPWM_ForceOutputSource_ExtSync#: External sync signal (EXT_SYNC)

enum _flexpwm_force_pwm_source#

FlexPWM PWM source selection for deadtime logic (DTSRCSEL)

Values:

enumerator kFLEXPWM_ForcePwmSource_Generated#: Generated PWM signal

enumerator kFLEXPWM_ForcePwmSource_Inverted#: Inverted PWM signal

enumerator kFLEXPWM_ForcePwmSource_Software#: Software controlled output (SWCOUT)

enumerator kFLEXPWM_ForcePwmSource_External#: External signal

enum _flexpwm_fault_output_behavior#

FlexPWM fault output behavior during fault condition.

Defines how PWM outputs respond when a fault is detected. Values map directly to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS] bitfields.

Values:

enumerator kFLEXPWM_FaultOutput_Force0#: 0b00 - Force output to logic 0

enumerator kFLEXPWM_FaultOutput_Force1#: 0b01 - Force output to logic 1

enumerator kFLEXPWM_FaultOutput_HighZ#: 0b10/0b11 - High impedance (3-state) output

enum _flexpwm_fault_mask#

FlexPWM fault input mask for fault protection configuration.

These flags can be OR’ed together to configure multiple fault inputs simultaneously with the same protection parameters. Used with FLEXPWM_ConfigFaultProtection() function.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1):

When faultChannel = 0: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT0-3
When faultChannel = 1: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT4-7 The enum values are the same, but the channel parameter determines which physical fault inputs are configured.

Values:

enumerator kFLEXPWM_FaultMask_0#: FAULT0 (ch0) or FAULT4 (ch1)

enumerator kFLEXPWM_FaultMask_1#: FAULT1 (ch0) or FAULT5 (ch1)

enumerator kFLEXPWM_FaultMask_2#: FAULT2 (ch0) or FAULT6 (ch1)

enumerator kFLEXPWM_FaultMask_3#: FAULT3 (ch0) or FAULT7 (ch1)

enum _flexpwm_fault_clearing_mode#

FlexPWM fault clearing mode selection.

Defines how fault conditions are cleared after a fault event.

Values:

enumerator kFLEXPWM_FaultClearingMode_Manual#: Manual clearing - software must clear FSTS[FFLAGx]

enumerator kFLEXPWM_FaultClearingMode_Automatic#: Automatic clearing when FAULTx de-asserts

enum _flexpwm_write_protect#

FlexPWM write protection mode selection.

Values:

enumerator kFLEXPWM_WriteProtect_Off#: Write protection off (default)

enumerator kFLEXPWM_WriteProtect_On#: Write protection on

enumerator kFLEXPWM_WriteProtect_OffLocked#: Write protection off and locked until chip reset

enumerator kFLEXPWM_WriteProtect_OnLocked#: Write protection on and locked until chip reset

enum _flexpwm_stretch_prescaler#

FlexPWM trigger signal stretch prescaler selection.

Stretch IPBus clock count prescaler for trigger signals including: mux0_trig, mux1_trig, out0_trig, out1_trig, pwma_trig, pwmb_trig

Values:

enumerator kFLEXPWM_StretchPrescaler_None#: No stretch

enumerator kFLEXPWM_StretchPrescaler_2Clocks#: Stretch for 2 IPBus clock periods

enumerator kFLEXPWM_StretchPrescaler_4Clocks#: Stretch for 4 IPBus clock periods

enumerator kFLEXPWM_StretchPrescaler_8Clocks#: Stretch for 8 IPBus clock periods

enum _flexpwm_trigger_mux_source#

FlexPWM output trigger source selection for PWM_MUX_TRIG0/1 ports.

Selects which signal is routed to the PWM_MUX_TRIG0/1 output ports.

Values:

enumerator kFLEXPWM_TriggerMuxSource_GeneratedTrigger#: Use PWM_OUT_TRIG0/1 (generated trigger signal)

enumerator kFLEXPWM_TriggerMuxSource_PWMOutput#: Use PWM_A/PWM_B output directly

enum _flexpwm_trigger_frequency#

FlexPWM output trigger frequency selection.

Controls the trigger output frequency when CTRL[LDFQ] is non-zero. Only takes effect when reload frequency divider is active (LDFQ > 0).

Values:

enumerator kFLEXPWM_TriggerFrequency_EveryCycle#: Trigger every PWM cycle even if reload doesn’t occur

enumerator kFLEXPWM_TriggerFrequency_OnReload#: Trigger only on last cycle before reload opportunity

enum _flexpwm_output_trigger_mask#

FlexPWM output trigger enable mask.

These flags can be OR’ed together to enable multiple trigger sources simultaneously. Used with outTriggerEnable field in flexpwm_output_trigger_config_t structure.

Values:

enumerator kFLEXPWM_OutputTriggerMask_VAL0#: VAL0 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL1#: VAL1 match triggers PWM_OUT_TRIG1

enumerator kFLEXPWM_OutputTriggerMask_VAL2#: VAL2 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL3#: VAL3 match triggers PWM_OUT_TRIG1

enumerator kFLEXPWM_OutputTriggerMask_VAL4#: VAL4 match triggers PWM_OUT_TRIG0

enumerator kFLEXPWM_OutputTriggerMask_VAL5#: VAL5 match triggers PWM_OUT_TRIG1

enum _flexpwm_capture_edge#

FlexPWM input capture edge selection.

This enumeration defines the edge detection modes for input capture. The enum values directly map to hardware register bit values.

Values:

enumerator kFLEXPWM_CaptureEdge_Disabled#: Disable capture (register bit value: 00b)

enumerator kFLEXPWM_CaptureEdge_Falling#: Capture on falling edge (register bit value: 01b)

enumerator kFLEXPWM_CaptureEdge_Rising#: Capture on rising edge (register bit value: 10b)

enumerator kFLEXPWM_CaptureEdge_Both#: Capture on any edge (register bit value: 11b)

enum _flexpwm_capture_fifo_watermark#

FlexPWM capture FIFO watermark selection.

This enumeration defines the FIFO watermark levels that determine when a watermark interrupt is triggered based on the number of valid samples in the FIFO.

Values:

enumerator kFLEXPWM_CaptureFifoWatermark_1#: Trigger when FIFO has 1 or more samples (00b)

enumerator kFLEXPWM_CaptureFifoWatermark_2#: Trigger when FIFO has 2 or more samples (01b)

enumerator kFLEXPWM_CaptureFifoWatermark_3#: Trigger when FIFO has 3 or more samples (10b)

enumerator kFLEXPWM_CaptureFifoWatermark_4#: Trigger when FIFO is full with 4 samples (11b)

enum _flexpwm_capture_input_select#

FlexPWM capture input source selection.

This enumeration selects the source signal for input capture.

Values:

enumerator kFLEXPWM_CaptureInput_RawSignal#: Use raw PWM input signal (register bit value: 0)

enumerator kFLEXPWM_CaptureInput_EdgeCounter#: Use edge counter output (register bit value: 1). Used to reduce capture frequency by counting N edges

enum _flexpwm_capture_index#

FlexPWM capture value index.

This enumeration defines the index for accessing capture value registers (CVAL0-5).

Note

Capture channel to CVAL register mapping (non-intuitive hardware mapping):

Capture_X Edge0/Edge1 -> CVAL0/CVAL1 (and CVAL0CYC/CVAL1CYC)
Capture_A Edge0/Edge1 -> CVAL2/CVAL3 (and CVAL2CYC/CVAL3CYC)
Capture_B Edge0/Edge1 -> CVAL4/CVAL5 (and CVAL4CYC/CVAL5CYC)

Values:

enumerator kFLEXPWM_Capture_X_Edge0#: CVAL0 - Capture_X Edge0

enumerator kFLEXPWM_Capture_X_Edge1#: CVAL1 - Capture_X Edge1

enumerator kFLEXPWM_Capture_A_Edge0#: CVAL2 - Capture_A Edge0

enumerator kFLEXPWM_Capture_A_Edge1#: CVAL3 - Capture_A Edge1

enumerator kFLEXPWM_Capture_B_Edge0#: CVAL4 - Capture_B Edge0

enumerator kFLEXPWM_Capture_B_Edge1#: CVAL5 - Capture_B Edge1

enum _flexpwm_capture_channel#

FlexPWM capture channel selection.

This enumeration defines the capture channel for enable/disable operations.

Values:

enumerator kFLEXPWM_Capture_A#: Capture channel A (PWM_A)

enumerator kFLEXPWM_Capture_B#: Capture channel B (PWM_B)

enumerator kFLEXPWM_Capture_X#: Capture channel X (PWM_X)

enum _flexpwm_submodule_interrupt_enable#

FlexPWM submodule interrupt enable flags.

These flags can be OR’ed together to enable multiple interrupt sources simultaneously. Use with FLEXPWM_EnableSubmoduleInterrupts() and FLEXPWM_DisableSubmoduleInterrupts().

Values:

enumerator kFLEXPWM_Compare0InterruptEnable#: VAL0 compare interrupt

enumerator kFLEXPWM_Compare1InterruptEnable#: VAL1 compare interrupt

enumerator kFLEXPWM_Compare2InterruptEnable#: VAL2 compare interrupt

enumerator kFLEXPWM_Compare3InterruptEnable#: VAL3 compare interrupt

enumerator kFLEXPWM_Compare4InterruptEnable#: VAL4 compare interrupt

enumerator kFLEXPWM_Compare5InterruptEnable#: VAL5 compare interrupt

enumerator kFLEXPWM_CaptureX0InterruptEnable#: Capture X0 interrupt

enumerator kFLEXPWM_CaptureX1InterruptEnable#: Capture X1 interrupt

enumerator kFLEXPWM_CaptureB0InterruptEnable#: Capture B0 interrupt

enumerator kFLEXPWM_CaptureB1InterruptEnable#: Capture B1 interrupt

enumerator kFLEXPWM_CaptureA0InterruptEnable#: Capture A0 interrupt

enumerator kFLEXPWM_CaptureA1InterruptEnable#: Capture A1 interrupt

enumerator kFLEXPWM_ReloadInterruptEnable#: Reload interrupt

enumerator kFLEXPWM_ReloadErrorInterruptEnable#: Reload error interrupt

enum _flexpwm_submodule_status_flag#

FlexPWM submodule status flags.

These flags represent the status of various events in a FlexPWM submodule. Use with FLEXPWM_GetSubmoduleStatusFlags() and FLEXPWM_ClearSubmoduleStatusFlags().

Note

kFLEXPWM_RegisterUpdatedFlag is read-only and cannot be cleared by software.

Values:

enumerator kFLEXPWM_Compare0Flag#: VAL0 compare flag

enumerator kFLEXPWM_Compare1Flag#: VAL1 compare flag

enumerator kFLEXPWM_Compare2Flag#: VAL2 compare flag

enumerator kFLEXPWM_Compare3Flag#: VAL3 compare flag

enumerator kFLEXPWM_Compare4Flag#: VAL4 compare flag

enumerator kFLEXPWM_Compare5Flag#: VAL5 compare flag

enumerator kFLEXPWM_CaptureX0Flag#: Capture X0 flag

enumerator kFLEXPWM_CaptureX1Flag#: Capture X1 flag

enumerator kFLEXPWM_CaptureB0Flag#: Capture B0 flag

enumerator kFLEXPWM_CaptureB1Flag#: Capture B1 flag

enumerator kFLEXPWM_CaptureA0Flag#: Capture A0 flag

enumerator kFLEXPWM_CaptureA1Flag#: Capture A1 flag

enumerator kFLEXPWM_ReloadFlag#: Reload flag

enumerator kFLEXPWM_ReloadErrorFlag#: Reload error flag

enumerator kFLEXPWM_RegisterUpdatedFlag#: Register updated flag (read-only)

enum _flexpwm_fault_interrupt_enable#

FlexPWM fault interrupt enable flags.

These flags can be OR’ed together to enable multiple fault interrupt sources. Use with FLEXPWM_EnableFaultInterrupts() and FLEXPWM_DisableFaultInterrupts().

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1): The same bit mask values are used for both fault channels:

faultChannel = 0: Controls FAULT0-3
faultChannel = 1: Controls FAULT4-7 The bit positions are the same, but the function parameter determines which fault channel is configured.

Values:

enumerator kFLEXPWM_Fault0InterruptEnable#: FAULT0 (ch0) or FAULT4 (ch1) interrupt

enumerator kFLEXPWM_Fault1InterruptEnable#: FAULT1 (ch0) or FAULT5 (ch1) interrupt

enumerator kFLEXPWM_Fault2InterruptEnable#: FAULT2 (ch0) or FAULT6 (ch1) interrupt

enumerator kFLEXPWM_Fault3InterruptEnable#: FAULT3 (ch0) or FAULT7 (ch1) interrupt

enum _flexpwm_fault_status_flag#

FlexPWM fault status flags (FFLAG)

These flags represent the latched fault status (FFLAG bits in FSTS register). Use with FLEXPWM_GetFaultStatusFlags() and FLEXPWM_ClearFaultStatusFlags().

Note

FFLAG characteristics:

Write-1-to-clear: Software must write 1 to clear each flag
Latched event: Set within 2 CPU cycles after FAULTx pin transitions to active state
Historical record: Indicates a fault event has occurred (not current pin state)
Interrupt capable: Can generate CPU interrupt requests when enabled
Manual clearing: Does not auto-clear; requires explicit software action

Note

To check the real-time, filtered hardware pin status (not the latched event), use FLEXPWM_GetFaultFilteredPinStatusFlags() to read FFPIN instead.

Note

For dual-channel platforms: The same bit mask values apply to both channels.

faultChannel = 0: FAULT0-3 flags
faultChannel = 1: FAULT4-7 flags

Values:

enumerator kFLEXPWM_Fault0Flag#: FAULT0 (ch0) or FAULT4 (ch1) flag

enumerator kFLEXPWM_Fault1Flag#: FAULT1 (ch0) or FAULT5 (ch1) flag

enumerator kFLEXPWM_Fault2Flag#: FAULT2 (ch0) or FAULT6 (ch1) flag

enumerator kFLEXPWM_Fault3Flag#: FAULT3 (ch0) or FAULT7 (ch1) flag

enum _flexpwm_fault_pin_status#

FlexPWM filtered fault pin status (FFPIN - read-only)

These flags represent the real-time status of fault pins after filtering (FFPIN bits in FSTS register). Use with FLEXPWM_GetFaultFilteredPinStatusFlags() to check if external fault signals are currently active.

Note

FFPIN characteristics:

Read-only: Cannot be written or cleared by software
Real-time status: Reflects current state of filtered FAULTx pin (not historical)
Polarity converted: Always shows active-high logic (1 = fault present)
Filter output: Shows fault filter output, not raw pin state
No interrupt: Does not directly generate interrupts (use FFLAG for interrupts)
Filter delay: May remain high briefly after raw pin clears due to filter latency

Note

Key differences from FFLAG:

FFLAG: Software-clearable latched flag (historical event - “a fault occurred”)
FFPIN: Read-only real-time status (current state - “fault is active now”)

Note

For dual-channel platforms: The same bit positions apply to both channels.

faultChannel = 0: FAULT0-3 pin status
faultChannel = 1: FAULT4-7 pin status

Values:

enumerator kFLEXPWM_Fault0PinActive#: FAULT0/4 pin active (filtered)

enumerator kFLEXPWM_Fault1PinActive#: FAULT1/5 pin active (filtered)

enumerator kFLEXPWM_Fault2PinActive#: FAULT2/6 pin active (filtered)

enumerator kFLEXPWM_Fault3PinActive#: FAULT3/7 pin active (filtered)

enum _flexpwm_dma_capture_source#

FlexPWM DMA capture source selection.

This enumeration defines the trigger source for DMA read requests from capture FIFOs.

Values:

enumerator kFLEXPWM_DMADisable#: Read DMA requests disabled

enumerator kFLEXPWM_DMAFIFOWatermark#: Exceeding FIFO watermark sets read DMA request

enumerator kFLEXPWM_DMALocalSync#: Local sync sets read DMA request

enumerator kFLEXPWM_DMALocalReload#: Local reload sets read DMA request

enum _flexpwm_dma_enable#

FlexPWM DMA enable flags.

These flags are used with FLEXPWM_EnableDMA() and FLEXPWM_DisableDMA() to control individual DMA channel enables. Multiple flags can be ORed together.

Values:

enumerator kFLEXPWM_DMA_CaptureX0Enable#: Capture X0 FIFO DMA enable (CX0DE)

enumerator kFLEXPWM_DMA_CaptureX1Enable#: Capture X1 FIFO DMA enable (CX1DE)

enumerator kFLEXPWM_DMA_CaptureB0Enable#: Capture B0 FIFO DMA enable (CB0DE)

enumerator kFLEXPWM_DMA_CaptureB1Enable#: Capture B1 FIFO DMA enable (CB1DE)

enumerator kFLEXPWM_DMA_CaptureA0Enable#: Capture A0 FIFO DMA enable (CA0DE)

enumerator kFLEXPWM_DMA_CaptureA1Enable#: Capture A1 FIFO DMA enable (CA1DE)

enumerator kFLEXPWM_DMA_ValueWriteEnable#: Value registers DMA write enable (VALDE)

typedef enum _flexpwm_clock_source flexpwm_clock_source_t#: FlexPWM clock source selection.

typedef enum _flexpwm_prescaler flexpwm_prescaler_t#: FlexPWM clock prescaler selection.

typedef enum _flexpwm_load_mode flexpwm_load_mode_t#: FlexPWM load mode selection.

typedef enum _flexpwm_reload_source flexpwm_reload_source_t#: FlexPWM reload source selection.

typedef enum _flexpwm_init_source flexpwm_init_source_t#: FlexPWM counter initialization source selection.

typedef enum _flexpwm_compare_mode flexpwm_compare_mode_t#: FlexPWM PWM compare mode selection.

typedef enum _flexpwm_submodule_mask flexpwm_submodule_mask_t#

FlexPWM submodule mask for multi-submodule operations.

These flags can be OR’ed together to specify multiple submodules simultaneously. Used with functions that operate on multiple submodules at once.

typedef struct _flexpwm_counter_config flexpwm_counter_config_t#: FlexPWM counter configuration structure.

typedef struct _flexpwm_reload_config flexpwm_reload_config_t#: FlexPWM reload configuration structure.

typedef struct _flexpwm_submodule_config flexpwm_submodule_config_t#

FlexPWM submodule configuration structure.

This structure defines the basic configuration parameters for a FlexPWM submodule, including clock source, prescaler, counter behavior, reload mechanism, and operating modes.

Note

This configuration writes to buffered registers. After calling FLEXPWM_ConfigSubmodule(), you must set MCTRL[LDOK] using a separate function to transfer the configuration to active registers.

Note

This function does not start the PWM counter. Use a separate API to enable the counter.

typedef enum _flexpwm_pwm_polarity flexpwm_pwm_polarity_t#: FlexPWM PWM output polarity selection.

typedef enum _flexpwm_ipol_source flexpwm_ipol_source_t#: FlexPWM PWM output source selection for complementary mode.

typedef struct _flexpwm_pwm_channel_config flexpwm_pwm_channel_config_t#

FlexPWM PWM channel configuration structure.

This structure defines the configuration for a PWM channel pair (PWM_A or PWM_B), including compare values, output polarity, and initial value.

typedef struct _flexpwm_pwm_config flexpwm_pwm_config_t#

FlexPWM PWM configuration structure.

This structure defines the PWM output configuration for a FlexPWM submodule, including compare values, polarity, and operating mode (independent or complementary).

Note

For complementary mode: Only the selected channel (specified by ipolSource) needs to be configured. The other channel will be ignored by the hardware. For example, if ipolSource = kFLEXPWM_IPOL_PWM23, only pwma will be used.

Note

For independent mode: Both pwma and pwmb must be configured separately. The ipolSource field is ignored when complementary = false.

typedef enum _flexpwm_force_output_source flexpwm_force_output_source_t#: FlexPWM FORCE_OUT event source selection.

typedef enum _flexpwm_force_pwm_source flexpwm_force_pwm_source_t#: FlexPWM PWM source selection for deadtime logic (DTSRCSEL)

typedef struct _flexpwm_force_out_channel_config flexpwm_force_out_channel_config_t#

FlexPWM PWM channel force output configuration structure.

This structure defines the force output configuration for a PWM channel (PWM_A or PWM_B), including the source selection and software-controlled output value.

typedef struct _flexpwm_force_out_config flexpwm_force_out_config_t#

FlexPWM force output configuration structure.

This structure defines the force output (FORCE_OUT event) configuration for a FlexPWM submodule, including the trigger source, PWM logical initial value, and PWM source selection.

typedef enum _flexpwm_fault_output_behavior flexpwm_fault_output_behavior_t#

FlexPWM fault output behavior during fault condition.

Defines how PWM outputs respond when a fault is detected. Values map directly to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS] bitfields.

typedef enum _flexpwm_fault_mask flexpwm_fault_mask_t#

FlexPWM fault input mask for fault protection configuration.

These flags can be OR’ed together to configure multiple fault inputs simultaneously with the same protection parameters. Used with FLEXPWM_ConfigFaultProtection() function.

Note

For dual-channel platforms (FSL_FEATURE_PWM_FAULT_CH_COUNT > 1):

When faultChannel = 0: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT0-3
When faultChannel = 1: Use kFLEXPWM_FaultMask_0/1/2/3 for FAULT4-7 The enum values are the same, but the channel parameter determines which physical fault inputs are configured.

typedef struct _flexpwm_fault_output_config flexpwm_fault_output_config_t#

FlexPWM fault output configuration structure.

Configures fault protection for a single PWM output (PWM_A, PWM_B, or PWM_X). Supports both single-channel (FAULT0-3 only) and dual-channel (FAULT0-3 and FAULT4-7) platforms via conditional compilation. Can use flexpwm_fault_mask_t enum values (kFLEXPWM_FaultMask_0/1/2/3) and OR them together for multiple faults.

typedef struct _flexpwm_fault_submodule_config flexpwm_fault_submodule_config_t#

FlexPWM fault submodule configuration structure.

Configures fault protection for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a FlexPWM submodule. Includes fault disable mapping and output behavior for each output.

typedef enum _flexpwm_fault_clearing_mode flexpwm_fault_clearing_mode_t#

FlexPWM fault clearing mode selection.

Defines how fault conditions are cleared after a fault event.

typedef struct _flexpwm_fault_config flexpwm_fault_config_t#

FlexPWM fault protection configuration structure.

Configures global fault protection parameters for one fault channel. These settings apply to all submodules and their outputs that reference this channel. For platforms with dual fault channels (FAULT0-3 and FAULT4-7), configure each channel separately using FLEXPWM_ConfigFaultProtection().

typedef struct _flexpwm_fault_filter_config flexpwm_fault_filter_config_t#

FlexPWM fault filter configuration structure.

Configures input filter for fault protection pins to debounce electrical noise. The filter requires the input signal to be stable for N consecutive samples (where each sample is taken every T IPBus clock cycles) before reporting a fault. Helps avoid false fault triggers from noise on FAULTx pins.

typedef enum _flexpwm_write_protect flexpwm_write_protect_t#: FlexPWM write protection mode selection.

typedef enum _flexpwm_stretch_prescaler flexpwm_stretch_prescaler_t#

FlexPWM trigger signal stretch prescaler selection.

Stretch IPBus clock count prescaler for trigger signals including: mux0_trig, mux1_trig, out0_trig, out1_trig, pwma_trig, pwmb_trig

typedef enum _flexpwm_trigger_mux_source flexpwm_trigger_mux_source_t#

FlexPWM output trigger source selection for PWM_MUX_TRIG0/1 ports.

Selects which signal is routed to the PWM_MUX_TRIG0/1 output ports.

typedef enum _flexpwm_trigger_frequency flexpwm_trigger_frequency_t#

FlexPWM output trigger frequency selection.

Controls the trigger output frequency when CTRL[LDFQ] is non-zero. Only takes effect when reload frequency divider is active (LDFQ > 0).

typedef enum _flexpwm_output_trigger_mask flexpwm_output_trigger_mask_t#

FlexPWM output trigger enable mask.

These flags can be OR’ed together to enable multiple trigger sources simultaneously. Used with outTriggerEnable field in flexpwm_output_trigger_config_t structure.

typedef struct _flexpwm_output_trigger_config flexpwm_output_trigger_config_t#

FlexPWM output trigger configuration structure.

This structure defines the output trigger configuration for a FlexPWM submodule, including trigger source mapping from VAL registers, trigger frequency control, and output port routing.

Note

outTriggerEnable is a 6-bit mask corresponding to OUT_TRIG_EN[5:0], where each bit enables a trigger source from VAL0-5 register matches:

bit[0]: VAL0 match triggers PWM_OUT_TRIG0
bit[1]: VAL1 match triggers PWM_OUT_TRIG1
bit[2]: VAL2 match triggers PWM_OUT_TRIG0
bit[3]: VAL3 match triggers PWM_OUT_TRIG1
bit[4]: VAL4 match triggers PWM_OUT_TRIG0
bit[5]: VAL5 match triggers PWM_OUT_TRIG1 Multiple bits can be set to combine trigger sources (OR logic).

Note

triggerFrequency only takes effect when CTRL[LDFQ] is non-zero.

false: Triggers output every PWM cycle even if reload doesn’t occur
true: Triggers output only on the last PWM cycle before a reload opportunity

typedef enum _flexpwm_capture_edge flexpwm_capture_edge_t#

FlexPWM input capture edge selection.

This enumeration defines the edge detection modes for input capture. The enum values directly map to hardware register bit values.

typedef enum _flexpwm_capture_fifo_watermark flexpwm_capture_fifo_watermark_t#

FlexPWM capture FIFO watermark selection.

This enumeration defines the FIFO watermark levels that determine when a watermark interrupt is triggered based on the number of valid samples in the FIFO.

typedef enum _flexpwm_capture_input_select flexpwm_capture_input_select_t#

FlexPWM capture input source selection.

This enumeration selects the source signal for input capture.

typedef enum _flexpwm_capture_index flexpwm_capture_index_t#

FlexPWM capture value index.

This enumeration defines the index for accessing capture value registers (CVAL0-5).

Note

Capture channel to CVAL register mapping (non-intuitive hardware mapping):

Capture_X Edge0/Edge1 -> CVAL0/CVAL1 (and CVAL0CYC/CVAL1CYC)
Capture_A Edge0/Edge1 -> CVAL2/CVAL3 (and CVAL2CYC/CVAL3CYC)
Capture_B Edge0/Edge1 -> CVAL4/CVAL5 (and CVAL4CYC/CVAL5CYC)

typedef enum _flexpwm_capture_channel flexpwm_capture_channel_t#

FlexPWM capture channel selection.

This enumeration defines the capture channel for enable/disable operations.

typedef struct _flexpwm_capture_channel_config flexpwm_capture_channel_config_t#

FlexPWM single capture channel configuration structure.

This structure defines the configuration parameters for a single input capture channel.

typedef struct _flexpwm_input_capture_config flexpwm_input_capture_config_t#

FlexPWM input capture configuration structure.

This structure contains the configuration for three independent input capture channels. Users can configure only the channels they need; unused channels should be left at default values.

Note

Capture channel to CVAL/CVALxCYC register mapping (important for reading capture values):

captureA -> CVAL2/CVAL3 (CVAL2CYC/CVAL3CYC)
captureB -> CVAL4/CVAL5 (CVAL4CYC/CVAL5CYC)
captureX -> CVAL0/CVAL1 (CVAL0CYC/CVAL1CYC)

typedef struct _flexpwm_capture_filter_channel_config flexpwm_capture_filter_channel_config_t#

FlexPWM capture filter channel configuration structure.

This structure defines the digital filter parameters for a single capture input pin.

typedef struct _flexpwm_capture_filter_config flexpwm_capture_filter_config_t#

FlexPWM input capture filter configuration structure.

This structure contains the filter configuration for three independent capture input pins.

Note

Capture filter to register mapping:

captureA -> SMxCAPTFILTA register
captureB -> SMxCAPTFILTB register
captureX -> SMxCAPTFILTX register

typedef enum _flexpwm_dma_capture_source flexpwm_dma_capture_source_t#

FlexPWM DMA capture source selection.

This enumeration defines the trigger source for DMA read requests from capture FIFOs.

typedef struct _flexpwm_dma_config flexpwm_dma_config_t#

FlexPWM DMA configuration structure.

This structure holds the DMA control strategy configuration. These settings should be configured during initialization and typically do not need to be modified at runtime.

uint32_t FLEXPWM_GetInstance(PWM_Type *base)#

Get the instance for FlexPWM module.

Parameters:

base – FlexPWM base address

Returns:

Instance number if valid base address is provided, otherwise returns ARRAY_SIZE(s_flexpwmBases)

status_t FLEXPWM_Init(PWM_Type *base)#

Initialize the FlexPWM module.

This function initializes the FlexPWM peripheral by:

Enabling clocks for all submodules (SM0-SM3)
Releasing peripheral reset (if supported by platform)

After calling this function, the FlexPWM module is ready for configuration. Additional configuration functions (FLEXPWM_ConfigSubmodule, FLEXPWM_ConfigPWM, etc.) should be called to set up the desired PWM behavior.

Note

This function does not configure any PWM parameters. It only enables the peripheral.

Note

This function does not start PWM generation. Use FLEXPWM_EnableSubmoduleCounter() and FLEXPWM_EnablePWMOutput() to start PWM output.

Parameters:

base – FlexPWM peripheral base address.

Returns:

kStatus_Success if initialization is successful. kStatus_InvalidArgument if the base address is invalid.

status_t FLEXPWM_DeInit(PWM_Type *base)#

Deinitialize the FlexPWM module.

This function deinitializes the FlexPWM peripheral by:

Disabling clocks for all submodules (SM0-SM3)
Asserting peripheral reset (if supported by platform)

After calling this function, all FlexPWM registers are reset.

Note

To re-enable PWM operation, call FLEXPWM_Init() again.

Parameters:

base – FlexPWM peripheral base address.

Returns:

kStatus_Success if deinitialization is successful. kStatus_InvalidArgument if the base address is invalid.

FLEXPWM_GET_FCTRL_REG(base, ch)#

FLEXPWM_GET_FSTS_REG(base, ch)#

FLEXPWM_GET_FFILT_REG(base, ch)#

FLEXPWM_GET_FCTRL2_REG(base, ch)#

struct _flexpwm_counter_config#

#include <fsl_flexpwm.h>

FlexPWM counter configuration structure.

Public Members

uint16_t initValue#: Counter initial value (INIT register).

uint16_t modValue#: Counter modulo value (VAL1 register). Defines the PWM period upper limit.

flexpwm_init_source_t initSource#: Counter initialization source selection. Determines when the counter resets to initValue.

struct _flexpwm_reload_config#

#include <fsl_flexpwm.h>

FlexPWM reload configuration structure.

Public Members

flexpwm_load_mode_t loadMode#

kFLEXPWM_LoadMode_Opportunity: Load at next reload opportunity (PWM cycle)
kFLEXPWM_LoadMode_Immediate: Load immediately after LDOK is set

uint8_t loadFrequency#

Load frequency divider (LDFQ field, 0-15). Buffered registers reload every (loadFrequency + 1) PWM cycles.

0: Every PWM cycle
1: Every 2 PWM cycles
15: Every 16 PWM cycles

bool enableHalfCycleReload#

Enable reload at half-cycle point (VAL0 match).

true: Reload can occur at VAL0 match
false: No reload at half-cycle

bool enableFullCycleReload#

Enable reload at full-cycle point (VAL1 match).

true: Reload can occur at VAL1 match
false: No reload at full-cycle

flexpwm_reload_source_t reloadSource#

Reload signal source selection.

kFLEXPWM_ReloadSource_LocalReload: Use local reload signal
kFLEXPWM_ReloadSource_MasterReload: Use master reload from submodule 0

uint16_t halfCycleValue#: Half-cycle reload point (VAL0 register). This value determines when half-cycle reload occurs. Note: Does not need to be exactly half the PWM period.

struct _flexpwm_submodule_config#

#include <fsl_flexpwm.h>

FlexPWM submodule configuration structure.

This structure defines the basic configuration parameters for a FlexPWM submodule, including clock source, prescaler, counter behavior, reload mechanism, and operating modes.

Note

This configuration writes to buffered registers. After calling FLEXPWM_ConfigSubmodule(), you must set MCTRL[LDOK] using a separate function to transfer the configuration to active registers.

Note

This function does not start the PWM counter. Use a separate API to enable the counter.

Public Members

flexpwm_clock_source_t clockSource#: Clock source for the submodule PWM counter.

flexpwm_prescaler_t prescaler#: Clock prescaler divider.

flexpwm_counter_config_t counterConfig#: Counter initialization and behavior configuration.

flexpwm_reload_config_t reloadConfig#: Register reload mechanism configuration.

bool enableDebugMode#

PWM behavior in Debug mode.

true: PWM continues running when MCU enters Debug mode
false: PWM stops when MCU enters Debug mode

struct _flexpwm_pwm_channel_config#

#include <fsl_flexpwm.h>

FlexPWM PWM channel configuration structure.

This structure defines the configuration for a PWM channel pair (PWM_A or PWM_B), including compare values, output polarity, and initial value.

Public Members

uint16_t compareValue_ON#

Compare value that defines the PWM turn-on edge (in normal polarity). Mapping per channel:

PWM_A: written to VAL2
PWM_B: written to VAL4
PWM_X: written to VAL0

uint16_t compareValue_OFF#

Compare value that defines the PWM turn-off edge (in normal polarity). Mapping per channel:

PWM_A: written to VAL3
PWM_B: written to VAL5
PWM_X: written to VAL1

flexpwm_pwm_polarity_t polarity#

Output polarity.

kFLEXPWM_Polarity_ActiveLow: PWM signal is inverted (active low)
kFLEXPWM_Polarity_ActiveHigh: PWM signal is normal (active high)

struct _flexpwm_pwm_config#

#include <fsl_flexpwm.h>

FlexPWM PWM configuration structure.

This structure defines the PWM output configuration for a FlexPWM submodule, including compare values, polarity, and operating mode (independent or complementary).

Note

For independent mode: Both pwma and pwmb must be configured separately. The ipolSource field is ignored when complementary = false.

Public Members

flexpwm_pwm_channel_config_t pwma#: PWM_A (PWM23) channel configuration

flexpwm_pwm_channel_config_t pwmb#: PWM_B (PWM45) channel configuration

bool complementary#

Operating mode.

true: Complementary mode (PWM_A and PWM_B form a complementary pair)
false: Independent mode (PWM_A and PWM_B are independent channels)

flexpwm_ipol_source_t ipolSource#

MCTRL[IPOL] - Select which channel pair as complementary source. Only used when complementary = true.

kFLEXPWM_IPOL_PWM23: Use PWM23 as source
kFLEXPWM_IPOL_PWM45: Use PWM45 as source

struct _flexpwm_force_out_channel_config#

#include <fsl_flexpwm.h>

FlexPWM PWM channel force output configuration structure.

This structure defines the force output configuration for a PWM channel (PWM_A or PWM_B), including the source selection and software-controlled output value.

Public Members

flexpwm_force_pwm_source_t source#: PWM source selection for this channel (DTSRCSEL).

bool softwareValue#: When source=kFLEXPWM_ForcePwmSource_Software, this value (0 or 1) is output to deadtime logic (SWCOUT).

struct _flexpwm_force_out_config#

#include <fsl_flexpwm.h>

FlexPWM force output configuration structure.

This structure defines the force output (FORCE_OUT event) configuration for a FlexPWM submodule, including the trigger source, PWM logical initial value, and PWM source selection.

Public Members

flexpwm_force_output_source_t forceSource#: FORCE_OUT trigger source (CTRL2[FORCE_SEL]).

flexpwm_force_out_channel_config_t pwma#: PWM_A (PWM23) force output configuration.

flexpwm_force_out_channel_config_t pwmb#: PWM_B (PWM45) force output configuration.

bool pwma_initialValue#

PWM_A (PWM23) logical initial value in normal polarity.

true: PWM_A output starts at logic 1
false: PWM_A output starts at logic 0

bool pwmb_initialValue#

PWM_B (PWM45) logical initial value in normal polarity.

true: PWM_B output starts at logic 1
false: PWM_B output starts at logic 0

bool pwmx_initialValue#

PWM_X logical initial value in normal polarity.

true: PWM_X output starts at logic 1
false: PWM_X output starts at logic 0

struct _flexpwm_fault_output_config#

#include <fsl_flexpwm.h>

FlexPWM fault output configuration structure.

Public Members

uint16_t disableMask_ch0#

Fault disable mask for channel 0 (FAULT0-3). Each bit selects one fault input:

bit[0] = FAULT0
bit[1] = FAULT1
bit[2] = FAULT2
bit[3] = FAULT3 Maps to SMxDISMAP[0] register.

flexpwm_fault_output_behavior_t outputBehavior#: Output behavior when fault is detected Maps to SMxOCTRL[PWMAFS/PWMBFS/PWMXFS].

struct _flexpwm_fault_submodule_config#

#include <fsl_flexpwm.h>

FlexPWM fault submodule configuration structure.

Configures fault protection for all three PWM outputs (PWM_A, PWM_B, PWM_X) of a FlexPWM submodule. Includes fault disable mapping and output behavior for each output.

Public Members

flexpwm_fault_output_config_t pwma#: PWM_A (PWM23) fault configuration. Controls which faults disable PWM_A output and how PWM_A behaves during fault.

flexpwm_fault_output_config_t pwmb#: PWM_B (PWM45) fault configuration. Controls which faults disable PWM_B output and how PWM_B behaves during fault.

flexpwm_fault_output_config_t pwmx#: PWM_X fault configuration. Controls which faults disable PWM_X output and how PWM_X behaves during fault.

struct _flexpwm_fault_config#

#include <fsl_flexpwm.h>

FlexPWM fault protection configuration structure.

Public Members

bool faultInputActiveLevel#

FAULTx input active level (FCTRL[FLVL])

false: Logic 0 on FAULTx indicates fault (active low)
true: Logic 1 on FAULTx indicates fault (active high)

flexpwm_fault_clearing_mode_t faultClearingMode#: Fault clearing mode (FCTRL[FAUTO])

bool enableSafetyMode#

Safety Mode (FCTRL[FSAFE]) Only useful for Manual fault clearing mode

false: Normal mode (PWM outputs enabled when FFLAG clears)
true: Safe mode (PWM outputs enabled only when both FFLAG and FFPIN are clear)

bool enableFullCycleRecovery#

Full Cycle Recovery (FSTS[FFULL])

true: PWM outputs can be re-enabled at PWM full cycle start
false: No re-enable at full cycle

bool enableHalfCycleRecovery#

Half Cycle Recovery (FSTS[FHALF])

true: PWM outputs can be re-enabled at PWM half cycle start
false: No re-enable at half cycle

bool enableCombinatorialPath#

Combinational Path Control (FCTRL2[NOCOMB])

true: Combinational path active - fault input directly disables PWM outputs (fastest response)
false: Combinational path disabled - only latched fault signal disables PWM outputs (adds latency)

struct _flexpwm_fault_filter_config#

#include <fsl_flexpwm.h>

FlexPWM fault filter configuration structure.

Public Members

uint8_t filterPeriod#

Fault Filter Period (FFILT[FILT_PER]) Sampling period in IPBus clock cycles. Range: 0-255

0: Input filter bypassed
N: FAULTx sampled every N IPBus cycles

uint8_t filterCount#

Fault Filter Count (FFILT[FILT_CNT]) Number of consecutive stable samples required to accept input transition. Range: 0-7 (actual samples = value + 3)

0: 3 samples
1: 4 samples
7: 10 samples

bool enableGlitchStretch#

Fault Glitch Stretching (FFILT[GSTR])

false: Glitch stretching disabled
true: Input fault signals stretched to min 2 IPBus cycles Prevents false triggers from narrow glitches

struct _flexpwm_output_trigger_config#

#include <fsl_flexpwm.h>

FlexPWM output trigger configuration structure.

This structure defines the output trigger configuration for a FlexPWM submodule, including trigger source mapping from VAL registers, trigger frequency control, and output port routing.

Note

outTriggerEnable is a 6-bit mask corresponding to OUT_TRIG_EN[5:0], where each bit enables a trigger source from VAL0-5 register matches:

bit[0]: VAL0 match triggers PWM_OUT_TRIG0
bit[1]: VAL1 match triggers PWM_OUT_TRIG1
bit[2]: VAL2 match triggers PWM_OUT_TRIG0
bit[3]: VAL3 match triggers PWM_OUT_TRIG1
bit[4]: VAL4 match triggers PWM_OUT_TRIG0
bit[5]: VAL5 match triggers PWM_OUT_TRIG1 Multiple bits can be set to combine trigger sources (OR logic).

Note

triggerFrequency only takes effect when CTRL[LDFQ] is non-zero.

false: Triggers output every PWM cycle even if reload doesn’t occur
true: Triggers output only on the last PWM cycle before a reload opportunity

Public Members

uint16_t outTriggerEnable#: Output trigger enable mask (OUT_TRIG_EN[5:0]). Bit mask for VAL0-5 trigger sources. OR’ed combination of flexpwm_output_trigger_mask_t Example: 0x05 enables VAL0 and VAL2 for TRIG0.

flexpwm_trigger_mux_source_t muxTrig0Source#

PWM_MUX_TRIG0 port source selection (PWAOT0).

kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Route PWM_OUT_TRIG0 signal
kFLEXPWM_TriggerMuxSource_PWMOutput: Route PWM_A output directly

flexpwm_trigger_mux_source_t muxTrig1Source#

PWM_MUX_TRIG1 port source selection (PWBOT1).

kFLEXPWM_TriggerMuxSource_GeneratedTrigger: Route PWM_OUT_TRIG1 signal
kFLEXPWM_TriggerMuxSource_PWMOutput: Route PWM_B output directly

flexpwm_trigger_frequency_t triggerFrequency#

Trigger frequency control (TRGFRQ). Controls trigger output frequency when CTRL[LDFQ] > 0.

kFLEXPWM_TriggerFrequency_EveryCycle: Trigger every PWM cycle
kFLEXPWM_TriggerFrequency_OnReload: Trigger only on last cycle before reload

flexpwm_stretch_prescaler_t stretchPrescaler#: Trigger signal stretch prescaler (MCTRL2[STRETCH_CNT_PRSC]). Stretches trigger signal pulse width by specified IPBus clock cycles.

struct _flexpwm_capture_channel_config#

#include <fsl_flexpwm.h>

FlexPWM single capture channel configuration structure.

This structure defines the configuration parameters for a single input capture channel.

Public Members

flexpwm_capture_edge_t edge0#: Edge0 capture edge selection

flexpwm_capture_edge_t edge1#: Edge1 capture edge selection

bool oneshot#

Capture mode.

true: One-shot mode
false: Free-running mode

flexpwm_capture_input_select_t inputSelect#

Input signal source selection.

kFLEXPWM_CaptureInput_RawSignal: Raw PWM input
kFLEXPWM_CaptureInput_EdgeCounter: Edge counter output

bool enableEdgeCounter#

Edge counter enable control.

true: Enable edge counter (EDGCNT_EN = 1)
false: Disable edge counter (EDGCNT_EN = 0)

uint8_t edgeCompareValue#: Edge counter compare value (0-255). Capture occurs when edge count reaches this value. Only valid when enableEdgeCounter = true

flexpwm_capture_fifo_watermark_t fifoWatermark#: FIFO watermark level

struct _flexpwm_input_capture_config#

#include <fsl_flexpwm.h>

FlexPWM input capture configuration structure.

This structure contains the configuration for three independent input capture channels. Users can configure only the channels they need; unused channels should be left at default values.

Note

Capture channel to CVAL/CVALxCYC register mapping (important for reading capture values):

captureA -> CVAL2/CVAL3 (CVAL2CYC/CVAL3CYC)
captureB -> CVAL4/CVAL5 (CVAL4CYC/CVAL5CYC)
captureX -> CVAL0/CVAL1 (CVAL0CYC/CVAL1CYC)

Public Members

flexpwm_capture_channel_config_t captureA#: Capture_A (PWM_A) channel configuration

flexpwm_capture_channel_config_t captureB#: Capture_B (PWM_B) channel configuration

flexpwm_capture_channel_config_t captureX#: Capture_X (PWM_X) channel configuration

struct _flexpwm_capture_filter_channel_config#

#include <fsl_flexpwm.h>

FlexPWM capture filter channel configuration structure.

This structure defines the digital filter parameters for a single capture input pin.

Public Members

uint8_t filterPeriod#

Filter sampling period in IPBus clock cycles (0-255).

0: Bypass filter (default)
Non-zero: Enable filter with specified sampling period

uint8_t filterCount#: Number of consecutive consistent samples required (0-7). Actual sample count = filterCount + 3 (i.e., 3-10 samples)

struct _flexpwm_capture_filter_config#

#include <fsl_flexpwm.h>

FlexPWM input capture filter configuration structure.

This structure contains the filter configuration for three independent capture input pins.

Note

Capture filter to register mapping:

captureA -> SMxCAPTFILTA register
captureB -> SMxCAPTFILTB register
captureX -> SMxCAPTFILTX register

Public Members

flexpwm_capture_filter_channel_config_t captureA#: Capture_A filter configuration

flexpwm_capture_filter_channel_config_t captureB#: Capture_B filter configuration

flexpwm_capture_filter_channel_config_t captureX#: Capture_X filter configuration

struct _flexpwm_dma_config#

#include <fsl_flexpwm.h>

FlexPWM DMA configuration structure.

This structure holds the DMA control strategy configuration. These settings should be configured during initialization and typically do not need to be modified at runtime.

Public Members

flexpwm_dma_capture_source_t captureSource#: Capture DMA enable source selection (CAPTDE[7:6])

bool fifoWatermarkAND#

FIFO watermark AND/OR control (FAND).

true: Selected FIFO watermarks are ANDed
false: Selected FIFO watermarks are ORed

FREQME: Frequency Measurement#

GLIKEY#

Values:

enumerator kStatus_GLIKEY_LockedError#: GLIKEY status for locked SFR registers (unexpected) .

enumerator kStatus_GLIKEY_NotLocked#: GLIKEY status for unlocked SFR registers.

enumerator kStatus_GLIKEY_Locked#: GLIKEY status for locked SFR registers.

enumerator kStatus_GLIKEY_DisabledError#: GLIKEY status for disabled error.

FSL_GLIKEY_DRIVER_VERSION#

Defines GLIKEY driver version 2.0.1.

Change log:

Version 2.0.1
- Implement INIT state recovery from the LOCKED state after a reset when the previous index was locked.
Version 2.0.0
- Initial version

GLIKEY_CODEWORD_STEP1#

GLIKEY_CODEWORD_STEP2#

GLIKEY_CODEWORD_STEP3#

GLIKEY_CODEWORD_STEP4#

GLIKEY_CODEWORD_STEP5#

GLIKEY_CODEWORD_STEP6#

GLIKEY_CODEWORD_STEP7#

GLIKEY_CODEWORD_STEP_EN#

GLIKEY_FSM_WR_DIS#

GLIKEY_FSM_INIT#

GLIKEY_FSM_STEP1#

GLIKEY_FSM_STEP2#

GLIKEY_FSM_STEP3#

GLIKEY_FSM_STEP4#

GLIKEY_FSM_LOCKED#

GLIKEY_FSM_WR_EN#

GLIKEY_FSM_SSR_RESET#

uint32_t GLIKEY_GetStatus(GLIKEY_Type *base)#

Retreives the current status of Glikey.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Glikey status information

status_t GLIKEY_IsLocked(GLIKEY_Type *base)#

Get if Glikey is locked.

This operation returns the locking status of Glikey.

Return values:

kStatus_GLIKEY_Locked – if locked
kStatus_GLIKEY_NotLocked – if unlocked

Returns:

Status

status_t GLIKEY_CheckLock(GLIKEY_Type *base)#

Check if Glikey is locked.

This operation returns the locking status of Glikey.

Return values:

kStatus_GLIKEY_LockedError – if locked
kStatus_GLIKEY_NotLocked – if unlocked

Returns:

Status kStatus_Success if success

status_t GLIKEY_SyncReset(GLIKEY_Type *base)#

Perform a synchronous reset of Glikey.

This function performs a synchrounous reset of the Glikey. This results in:

Glikey will return to the INIT state, unless it is in the LOCK state

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value)#

Set interrupt enable flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance
value – [in] Value to set the interrupt enable flag to, see #[TODO: add reference to constants]

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value)#

Get interrupt enable flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance
value – [out] Pointer which will be filled with the interrupt enable status, see #[TODO: add reference to constants]

Returns:

Status kStatus_Success if success

status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)#

Clear the interrupt status flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)#

Set the interrupt status flag of Glikey.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError

status_t GLIKEY_Lock(GLIKEY_Type *base)#

Lock Glikey SFR (Special Function Registers) interface.

This operation locks the Glikey SFR interface if it is not locked yet.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success

status_t GLIKEY_LockIndex(GLIKEY_Type *base)#

Lock Glikey index.

This operation is used to lock a Glikey index. It can only be executed from the WR_EN state, executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index)#

Check if Glikey index is locked.

This operation returns the locking status of Glikey index.

Parameters:

base – [in] The base address of the Glikey instance
index – [in] The index of the Glikey instance

Returns:

kStatus_GLIKEY_Locked if locked, kStatus_GLIKEY_NotLocked if unlocked Possible errors: kStatus_Fail

status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)#

Start Glikey enable.

This operation is used to set a new index and start a the sequence to enable it. It needs to be started from the INIT state. If the new index is already locked Glikey will go to LOCKED state, otherwise it will go to STEP1 state. If this operation is used when Glikey is in any state other than INIT Glikey will go to WR_DIS state. It can only recover from this state through a reset (synchrounous or asyncrhonous). If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance
index – [in] The index of the Glikey instance

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail

status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)#

Continue Glikey enable.

This operation is used to progress through the different states of the state machine, starting from STEP1 until the state WR_EN is reached. Each next state of the state machine can only be reached by providing the right codeword to this function. If anything goes wrong the state machine will go to WR_DIS state and can only recover from it through a reset (synchrous or asynchronous). If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance
codeword – [in] Encoded word for progressing to next FSM state (see GLIKEY_CODEWORD_STEPx/EN)

Returns:

Status kStatus_Success if success Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail, kStatus_GLIKEY_DisabledError

status_t GLIKEY_EndOperation(GLIKEY_Type *base)#

End Glikey operation.

This operation is used to end a Glikey operation. It can only be executed from the WR_EN, LOCKED and RESET states. Executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. After this operation Glikey will go to INIT state or stay in LOCKED state when the index was locked. If the Glikey SFR lock is active this operation will return an error.

Parameters:

base – [in] The base address of the Glikey instance

Returns:

A code-flow protected error code (see nxpCsslFlowProtection)

Returns:

Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index)#

Reset Glikey index.

This operation is used to reset a Glikey index. It can only be executed from the INIT state, executing it from any other state will result in Glikey entering WR_DIS state. When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. If the Glikey SFR lock is active or the index is locked this operation will return an error.

Returns:: A code-flow protected error code (see nxpCsslFlowProtection)
Returns:: Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError

GLIKEY#

GPIO: General-Purpose Input/Output Driver#

FSL_GPIO_DRIVER_VERSION#: GPIO driver version.

enum _gpio_pin_direction#

GPIO direction definition.

Values:

enumerator kGPIO_DigitalInput#: Set current pin as digital input

enumerator kGPIO_DigitalOutput#: Set current pin as digital output

enum _gpio_checker_attribute#

GPIO checker attribute.

Values:

enumerator kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW#: User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW#: User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW#: User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW#: User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW#: User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW#: User nonsecure:None; User Secure:None; Privileged Secure:Read+Write

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR#: User nonsecure:None; User Secure:None; Privileged Secure:Read

enumerator kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN#: User nonsecure:None; User Secure:None; Privileged Secure:None

enumerator kGPIO_IgnoreAttributeCheck#: Ignores the attribute check

enum _gpio_interrupt_config#

Configures the interrupt generation condition.

Values:

enumerator kGPIO_InterruptStatusFlagDisabled#: Interrupt status flag is disabled.

enumerator kGPIO_DMARisingEdge#: ISF flag and DMA request on rising edge.

enumerator kGPIO_DMAFallingEdge#: ISF flag and DMA request on falling edge.

enumerator kGPIO_DMAEitherEdge#: ISF flag and DMA request on either edge.

enumerator kGPIO_FlagRisingEdge#: Flag sets on rising edge.

enumerator kGPIO_FlagFallingEdge#: Flag sets on falling edge.

enumerator kGPIO_FlagEitherEdge#: Flag sets on either edge.

enumerator kGPIO_InterruptLogicZero#: Interrupt when logic zero.

enumerator kGPIO_InterruptRisingEdge#: Interrupt on rising edge.

enumerator kGPIO_InterruptFallingEdge#: Interrupt on falling edge.

enumerator kGPIO_InterruptEitherEdge#: Interrupt on either edge.

enumerator kGPIO_InterruptLogicOne#: Interrupt when logic one.

enumerator kGPIO_ActiveHighTriggerOutputEnable#: Enable active high-trigger output.

enumerator kGPIO_ActiveLowTriggerOutputEnable#: Enable active low-trigger output.

enum _gpio_interrupt_selection#

Configures the selection of interrupt/DMA request/trigger output.

Values:

enumerator kGPIO_InterruptOutput0#: Interrupt/DMA request/trigger output 0.

enumerator kGPIO_InterruptOutput1#: Interrupt/DMA request/trigger output 1.

enum gpio_pin_interrupt_control_t#

GPIO pin and interrupt control.

Values:

enumerator kGPIO_PinControlNonSecure#: Pin Control Non-Secure.

enumerator kGPIO_InterruptControlNonSecure#: Interrupt Control Non-Secure.

enumerator kGPIO_PinControlNonPrivilege#: Pin Control Non-Privilege.

enumerator kGPIO_InterruptControlNonPrivilege#: Interrupt Control Non-Privilege.

typedef enum _gpio_pin_direction gpio_pin_direction_t#: GPIO direction definition.

typedef enum _gpio_checker_attribute gpio_checker_attribute_t#: GPIO checker attribute.

typedef struct _gpio_pin_config gpio_pin_config_t#

The GPIO pin configuration structure.

Each pin can only be configured as either an output pin or an input pin at a time. If configured as an input pin, leave the outputConfig unused. Note that in some use cases, the corresponding port property should be configured in advance with the PORT_SetPinConfig().

typedef enum _gpio_interrupt_config gpio_interrupt_config_t#: Configures the interrupt generation condition.

typedef enum _gpio_interrupt_selection gpio_interrupt_selection_t#: Configures the selection of interrupt/DMA request/trigger output.

typedef struct _gpio_version_info gpio_version_info_t#: GPIO version information.

GPIO_FIT_REG(value)#

struct _gpio_pin_config#

#include <fsl_gpio.h>

The GPIO pin configuration structure.

Public Members

gpio_pin_direction_t pinDirection#: GPIO direction, input or output

uint8_t outputLogic#: Set a default output logic, which has no use in input

struct _gpio_version_info#

#include <fsl_gpio.h>

GPIO version information.

Public Members

uint16_t feature#: Feature Specification Number.

uint8_t minor#: Minor Version Number.

uint8_t major#: Major Version Number.

GPIO Driver#

void GPIO_PortInit(GPIO_Type *base)#

Initializes the GPIO peripheral.

This function ungates the GPIO clock.

Parameters:

base – GPIO peripheral base pointer.

void GPIO_PortDenit(GPIO_Type *base)#

Denitializes the GPIO peripheral.

Parameters:

base – GPIO peripheral base pointer.

void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)#

Initializes a GPIO pin used by the board.

To initialize the GPIO, define a pin configuration, as either input or output, in the user file. Then, call the GPIO_PinInit() function.

This is an example to define an input pin or an output pin configuration.

Define a digital input pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalInput,
  0,
}
Define a digital output pin configuration,
gpio_pin_config_t config =
{
  kGPIO_DigitalOutput,
  0,
}

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO port pin number
config – GPIO pin configuration pointer

void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *verInfo)#

Get GPIO version information.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
verInfo – GPIO version information

static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask)#

lock or unlock secure privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – pin or interrupt macro

static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask)#

Enable Pin Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask)#

Disable Pin Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Enable Pin Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Disable Pin Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)#

Enable Interrupt Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask)#

Disable Interrupt Control Non-Secure.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Enable Interrupt Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask)#

Disable Interrupt Control Non-Privilege.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask)#

Enable port input.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)#

Disable port input.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)#

Sets the output level of the multiple GPIO pins to the logic 1 or 0.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO pin number
output – GPIO pin output logic level.
- 0: corresponding pin output low-logic level.
- 1: corresponding pin output high-logic level.

static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)#

Sets the output level of the multiple GPIO pins to the logic 1.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)#

Sets the output level of the multiple GPIO pins to the logic 0.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)#

Reverses the current output logic of the multiple GPIO pins.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)#

Reads the current input value of the GPIO port.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
pin – GPIO pin number

Return values:

GPIO – port input value

0: corresponding pin input low-logic level.
1: corresponding pin input high-logic level.

static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)#

Configures the gpio pin interrupt/DMA request.

Parameters:

base – GPIO peripheral base pointer.
pin – GPIO pin number.
config – GPIO pin interrupt configuration.
- kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled.
- kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- kGPIO_InterruptLogicZero : Interrupt when logic zero.
- kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- kGPIO_InterruptEitherEdge : Interrupt on either edge.
- kGPIO_InterruptLogicOne : Interrupt when logic one.
- kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).

static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection)#

Configures the gpio pin interrupt/DMA request/trigger output channel selection.

Parameters:

base – GPIO peripheral base pointer.
pin – GPIO pin number.
selection – GPIO pin interrupt output selection.
- kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0.
- kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1.

uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base)#

Read the GPIO interrupt status flags.

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)

Returns:

The current GPIO’s interrupt status flag. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel)#

Read the GPIO interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.)
channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

Returns:

The current GPIO’s interrupt status flag based on the selected interrupt channel. ‘1’ means the related pin’s flag is set, ‘0’ means the related pin’s flag not set. For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending.

uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)#

Read individual pin’s interrupt status flag.

Parameters:

base – GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on)
pin – GPIO specific pin number.

Returns:

The current selected pin’s interrupt status flag.

void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask)#

Clears GPIO pin interrupt status flags.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro

void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel)#

Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS).

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
mask – GPIO pin number macro
channel – ‘0’ means selete interrupt channel 0, ‘1’ means selete interrupt channel 1.

void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin)#

Clear GPIO individual pin’s interrupt status flag.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on).
pin – GPIO specific pin number.

static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config)#

Sets the GPIO interrupt configuration in PCR register for multiple pins.

Parameters:

base – GPIO peripheral base pointer.
mask – GPIO pin number macro.
config – GPIO pin interrupt configuration.
- kGPIO_InterruptStatusFlagDisabled: Interrupt disabled.
- kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
- kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
- kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
- kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
- kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
- kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
- kGPIO_InterruptLogicZero : Interrupt when logic zero.
- kGPIO_InterruptRisingEdge : Interrupt on rising edge.
- kGPIO_InterruptFallingEdge: Interrupt on falling edge.
- kGPIO_InterruptEitherEdge : Interrupt on either edge.
- kGPIO_InterruptLogicOne : Interrupt when logic one.
- kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
- kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..

void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)#

brief The GPIO module supports a device-specific number of data ports, organized as 32-bit words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level attributes required for a successful access to the GPIO programming model. If the GPIO module’s GACR register organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little endian data convention.

Parameters:

base – GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
attribute – GPIO checker attribute

GPIO_PortGetInterruptFlags(base)#

GPIO_PortClearInterruptFlags(base, mask)#

I3C: I3C Driver#

FSL_I3C_DRIVER_VERSION#: I3C driver version.

I3C status return codes.

Values:

enumerator kStatus_I3C_Busy#: The master is already performing a transfer.

enumerator kStatus_I3C_Idle#: The slave driver is idle.

enumerator kStatus_I3C_Nak#: The slave device sent a NAK in response to an address.

enumerator kStatus_I3C_WriteAbort#: The slave device sent a NAK in response to a write.

enumerator kStatus_I3C_Term#: The master terminates slave read.

enumerator kStatus_I3C_HdrParityError#: Parity error from DDR read.

enumerator kStatus_I3C_CrcError#: CRC error from DDR read.

enumerator kStatus_I3C_ReadFifoError#: Read from M/SRDATAB register when FIFO empty.

enumerator kStatus_I3C_WriteFifoError#: Write to M/SWDATAB register when FIFO full.

enumerator kStatus_I3C_MsgError#: Message SDR/DDR mismatch or read/write message in wrong state

enumerator kStatus_I3C_InvalidReq#: Invalid use of request.

enumerator kStatus_I3C_Timeout#: The module has stalled too long in a frame.

enumerator kStatus_I3C_SlaveCountExceed#: The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

enumerator kStatus_I3C_IBIWon#: The I3C slave event IBI or MR or HJ won the arbitration on a header address.

enumerator kStatus_I3C_OverrunError#: Slave internal from-bus buffer/FIFO overrun.

enumerator kStatus_I3C_UnderrunError#: Slave internal to-bus buffer/FIFO underrun

enumerator kStatus_I3C_UnderrunNak#: Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kStatus_I3C_InvalidStart#: Slave invalid start flag

enumerator kStatus_I3C_SdrParityError#: SDR parity error

enumerator kStatus_I3C_S0S1Error#: S0 or S1 error

enum _i3c_hdr_mode#

I3C HDR modes.

Values:

enumerator kI3C_HDRModeNone#

enumerator kI3C_HDRModeDDR#

enumerator kI3C_HDRModeTSP#

enumerator kI3C_HDRModeTSL#

typedef enum _i3c_hdr_mode i3c_hdr_mode_t#: I3C HDR modes.

typedef struct _i3c_device_info i3c_device_info_t#: I3C device information.

I3C_RETRY_TIMES#

Max loops to wait for I3C operation status complete.

This is the maximum number of loops to wait for I3C operation status complete. If set to 0, it will wait indefinitely.

I3C_MAX_DEVCNT#

I3C_IBI_BUFF_SIZE#

struct _i3c_device_info#

#include <fsl_i3c.h>

I3C device information.

Public Members

uint8_t dynamicAddr#: Device dynamic address.

uint8_t staticAddr#: Static address.

uint8_t dcr#: Device characteristics register information.

uint8_t bcr#: Bus characteristics register information.

uint16_t vendorID#: Device vendor ID(manufacture ID).

uint32_t partNumber#: Device part number info

uint16_t maxReadLength#: Maximum read length.

uint16_t maxWriteLength#: Maximum write length.

uint8_t hdrMode#: Support hdr mode, could be OR logic in i3c_hdr_mode.

I3C Common Driver#

typedef struct _i3c_config i3c_config_t#

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

uint32_t I3C_GetInstance(I3C_Type *base)#

Get which instance current I3C is used.

Parameters:

base – The I3C peripheral base address.

void I3C_GetDefaultConfig(i3c_config_t *config)#

Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.

This function provides the following default configuration for I3C:

config->disableTimeout config->hKeep config->enableOpenDrainStop config->enableOpenDrainHigh config->baudRate_Hzconfig->baudRate_Hzconfig->baudRate_Hzconfig->masterDynamicAddress config->slowClock_Hz config->enableSlave config->vendorID config->enableRandomPart config->partNumber config->dcr config->bcr config->hdrMode config->nakAllRequest config->ignoreS0S1Error config->offline config->matchSlaveStartStop 

notranslate">

config->enableMaster                 = kI3C_MasterCapable; = false; = kI3C_MasterHighKeeperNone; = true; = true; class="o">.i2cBaud          = 400000U; class="o">.i3cPushPullBaud  = 12500000U; class="o">.i3cOpenDrainBaud = 2500000U; = 0x0AU; = 1000000U; = true; = 0x11BU; = false; = 0; = 0; = 0; = (uint8_t)kI3C_HDRModeDDR; = false; = false; = false; = false;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().

Parameters:

config – [out] User provided configuration structure for default values. Refer to i3c_config_t. 







void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)#

Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration. 

Parameters:

base – The I3C peripheral base address. 
config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







struct _i3c_config#


#include <fsl_i3c.h>
Structure with settings to initialize the I3C module, could both initialize master and slave functionality. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster#

Enable master mode. 




bool disableTimeout#

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep#

High keeper mode setting. 




bool enableOpenDrainStop#

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh#

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz#

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay#

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay#

I3C SCL delay after Repeated START. 




uint8_t masterDynamicAddress#

Main master dynamic address configuration. 




uint32_t maxWriteLength#

Maximum write length. 




uint32_t maxReadLength#

Maximum read length. 




bool enableSlave#

Whether to enable slave. 




uint8_t staticAddr#

Static address. 




uint16_t vendorID#

Device vendor ID(manufacture ID). 




uint32_t partNumber#

Device part number info 




uint8_t dcr#

Device characteristics register information. 




uint8_t bcr#

Bus characteristics register information. 




uint8_t hdrMode#

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest#

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error#

Whether to ignore S0/S1 error in SDR mode. 




bool offline#

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop#

Whether to assert start/stop status only the time slave is addressed. 







I3C Master Driver#


void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)#

Provides a default configuration for the I3C master peripheral. 
This function provides the following default configuration for the I3C master peripheral: 
masterConfig->enableMaster            = kI3C_MasterOn;
masterConfig->disableTimeout          = false;
masterConfig->hKeep                   = kI3C_MasterHighKeeperNone;
masterConfig->enableOpenDrainStop     = true;
masterConfig->enableOpenDrainHigh     = true;
masterConfig->baudRate_Hz             = 100000U;
masterConfig->busType                 = kI3C_TypeI2C;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with I3C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to i3c_master_config_t. 







void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)#

Initializes the I3C master peripheral. 
This function enables the peripheral clock and initializes the I3C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The I3C peripheral base address. 
masterConfig – User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







void I3C_MasterDeinit(I3C_Type *base)#

Deinitializes the I3C master peripheral. 
This function disables the I3C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)#

Set I3C module master mode. 

Parameters:

base – The I3C peripheral base address. 
enable – Enable master mode. 







status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)#





status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)#





status_t I3C_CheckForBusyBus(I3C_Type *base)#





void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)#

Provides a default configuration for the I3C slave peripheral. 
This function provides the following default configuration for the I3C slave peripheral: 
slaveConfig->enableslave             = true;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t. 







void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)#

Initializes the I3C slave peripheral. 
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

base – The I3C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. 







void I3C_SlaveDeinit(I3C_Type *base)#

Deinitializes the I3C slave peripheral. 
This function disables the I3C slave peripheral and gates the clock.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)#

Enable/Disable Slave. 

Parameters:

base – The I3C peripheral base address. 
isEnable – Enable or disable. 







static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)#

Gets the I3C master status flags. 
A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_master_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)#

Clears the I3C master status flag state. 
The following status register flags can be cleared:

kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag


Attempts to clear other flags has no effect.

See also
_i3c_master_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_master_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags(). 







static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)#

Gets the I3C master error status flags. 
A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_master_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)#

Clears the I3C master error status flag state. 

See also
_i3c_master_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_master_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_MasterGetStatusFlags(). 







i3c_master_state_t I3C_MasterGetState(I3C_Type *base)#

Gets the I3C master state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C master state. 






static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)#

Gets the I3C slave status flags. 
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)#

Clears the I3C slave status flag state. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Attempts to clear other flags has no effect.

See also
_i3c_slave_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags(). 







static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)#

Gets the I3C slave error status flags. 
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)#

Clears the I3C slave error status flag state. 

See also
_i3c_slave_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags(). 







i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)#

Gets the I3C slave state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C slave activity state, refer i3c_slave_activity_state_t. 






status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status)#





static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)#

Enables the I3C master interrupt requests. 
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)#

Disables the I3C master interrupt requests. 
All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_master_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)#

Returns the set of currently enabled I3C master interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)#

Returns the set of pending I3C master interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_master_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)#

Enables the I3C slave interrupt requests. 
Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)#

Disables the I3C slave interrupt requests. 
Only below flags can be disabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)#

Returns the set of currently enabled I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)#

Returns the set of pending I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)#

Enables or disables I3C master DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)#

Gets I3C master transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Master Transmit Data Register address. 






static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)#

Gets I3C master receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Master Receive Data Register address. 






static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)#

Enables or disables I3C slave DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)#

Gets I3C slave transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Transmit Data Register address. 






static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)#

Gets I3C slave receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Receive Data Register address. 






static inline void I3C_MasterSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)#

Sets the watermarks for I3C master FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_MasterTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_MasterRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)#

Gets the current number of bytes in the I3C master FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)#

Sets the watermarks for I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)#

Gets the current number of bytes in the I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz)#

Sets the I3C bus frequency for master transactions. 
The I3C master is automatically disabled and re-enabled as necessary to configure the baud rate. Do not call this function during a transfer, or the transfer is aborted.

Note
On devices affected by I3C errata ERR053429, an SDR read with PPBAUD < 2 can lose the last received byte when the RxFIFO fills before the CPU/DMA services it. For safe SDR reads, request a push-pull baud that yields PPBAUD > 1, or guarantee the CPU/DMA drains the RxFIFO fast enough to avoid a Full event.


Parameters:

base – The I3C peripheral base address. 
baudRate_Hz – Pointer to structure of requested bus frequency in Hertz. 
sourceClock_Hz – I3C functional clock frequency in Hertz. 







status_t I3C_MasterGetI2CPresetTiming(i3c_legacy_i2c_speed_mode_t speed, i3c_master_src_clk_t srcClk, i3c_timing_t *timing)#

Get prevalidated timing values for supported I2C speed. 

Parameters:

speed – [in] I2C Speed mode. 
srcClk – [in] FCLK source clock. 
timing – [out] Prevalidated timing values. Valid when kStatus_Success is returned. 


Returns:
kStatus_Success A supported preset timing is found. kStatus_Fail The requested timing is not supported. 






status_t I3C_MasterCalcTiming(const i3c_master_baudrate_config_t *baudRate, uint32_t sourceClock_Hz, i3c_timing_t *timing)#

Calculate timing from desired baud rates. 

Parameters:

baudRate – [in] Desired baud rates and bus configuration. 
sourceClock_Hz – [in] Master peripheral clock (FCLK) frequency in Hz. 
timing – [out] I3C timing register field values. Valid only when kStatus_Success is returned. 


Returns:
kStatus_Success Target rate is achieved. kStatus_Fail Target rate isn’t achieved. 






void I3C_MasterSetTiming(I3C_Type *base, const i3c_timing_t *timing)#

Set I3C timing parameters. 

Parameters:

base – I3C peripheral base address. 
timing – Pre-calculated timing values. 







static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)#

Returns whether the bus is idle. 
Requires the master mode to be enabled. 

Parameters:

base – The I3C peripheral base address. 


Return values:

true – Bus is busy. 
false – Bus is idle. 







status_t I3C_MasterStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)#

Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified in the call. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the a address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 







status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)#

Sends a START signal and slave address on the I2C/I3C bus. 
This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure that another master is not occupying the bus. Then a START signal is transmitted, followed by the 7-bit address specified in the address parameter. Note that this function does not actually wait until the START and address are successfully sent on the bus before returning.

Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:

kStatus_Success – START signal and address were successfully enqueued in the transmit FIFO. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 







status_t I3C_MasterRepeatedStartWithRxSize(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)#

Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified in the call. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize configuration.

Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 
rxSize – Read terminate size for the followed read transfer, limit to 255 bytes. 


Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 






static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)#

Sends a repeated START signal and slave address on the I2C/I3C bus. 
This function is used to send a Repeated START signal when a transfer is already in progress. Like I3C_MasterStart(), it also sends the specified 7-bit address.

Note
This function exists primarily to maintain compatible APIs between I3C and I2C drivers, as well as to better document the intent of code that uses these APIs.


Parameters:

base – The I3C peripheral base address. 
type – The bus type to use in this transaction. 
address – 7-bit slave device address, in bits [6:0]. 
dir – Master transfer direction, either kI3C_Read or kI3C_Write. This parameter is used to set the R/w bit (bit 0) in the transmitted slave address. 


Return values:
kStatus_Success – Repeated START signal and address were successfully enqueued in the transmit FIFO. 






status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)#

Performs a polling send transfer on the I2C/I3C bus. 
Sends up to txSize number of bytes to the previously addressed slave device. The slave may reply with a NAK to any byte in order to terminate the transfer early. If this happens, this function returns kStatus_I3C_Nak.

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. 


Return values:

kStatus_Success – Data was sent successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Nak – The slave device sent a NAK in response to an address. 
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)#

Performs a polling receive transfer on the I2C/I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 
flags – Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Term – The master terminates slave read. 
kStatus_I3C_HdrParityError – Parity error from DDR read. 
kStatus_I3C_CrcError – CRC error from DDR read. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_MasterStop(I3C_Type *base)#

Sends a STOP signal on the I2C/I3C bus. 
This function does not return until the STOP signal is seen on the bus, or an error occurs.

Parameters:

base – The I3C peripheral base address. 


Return values:

kStatus_Success – The STOP signal was successfully sent on the bus and the transaction terminated. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_InvalidReq – Invalid use of request. 







void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq)#

I3C master emit request. 

Parameters:

base – The I3C peripheral base address. 
masterReq – I3C master request of type i3c_bus_request_t







static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)#

I3C master emit request. 

Parameters:

base – The I3C peripheral base address. 
ibiResponse – I3C master emit IBI response of type i3c_ibi_response_t







void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)#

I3C master register IBI rule. 

Parameters:

base – The I3C peripheral base address. 
ibiRule – Pointer to ibi rule description of type i3c_register_ibi_addr_t







void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)#

I3C master get IBI rule. 

Parameters:

base – The I3C peripheral base address. 
ibiRule – Pointer to store the read out ibi rule description. 







i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base)#

I3C master get IBI Type. 

Parameters:

base – The I3C peripheral base address. 


Return values:
i3c_ibi_type_t – Type of i3c_ibi_type_t. 






static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)#

I3C master get IBI Address. 

Parameters:

base – The I3C peripheral base address. 


Return values:
The – 8-bit IBI address. 






status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, uint8_t *addressList, uint32_t count, i3c_master_daa_baudrate_t *daaBaudRate)#

Performs a DAA in the i3c bus with specified temporary baud rate. 

Parameters:

base – The I3C peripheral base address. 
addressList – The pointer for address list which is used to do DAA. 
count – The address count in the address list. 
daaBaudRate – The temporary baud rate in DAA process, NULL for using initial setting. The initial setting is set back between the completion of the DAA and the return of this function. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. 







static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)#

Performs a DAA in the i3c bus. 

Parameters:

base – The I3C peripheral base address. 
addressList – The pointer for address list which is used to do DAA. 
count – The address count in the address list. The initial setting is set back between the completion of the DAA and the return of this function. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 
kStatus_I3C_SlaveCountExceed – The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. 







i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count)#

Get device information list after DAA process is done. 

Parameters:

base – The I3C peripheral base address. 
count – [out] The pointer to store the available device count. 


Returns:
Pointer to the i3c_device_info_t array. 






void I3C_MasterClearDeviceCount(I3C_Type *base)#

Clear the global device count which represents current devices number on the bus. When user resets all dynamic addresses on the bus, should call this API. 

Parameters:

base – The I3C peripheral base address. 







status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer)#

Performs a master polling transfer on the I2C/I3C bus. 

Note
The API does not return until the transfer succeeds or fails due to error happens during transfer.


Parameters:

base – The I3C peripheral base address. 
transfer – Pointer to the transfer structure. 


Return values:

kStatus_Success – Data was received successfully. 
kStatus_I3C_Busy – Another master is currently utilizing the bus. 
kStatus_I3C_IBIWon – The I3C slave event IBI or MR or HJ won the arbitration on a header address. 
kStatus_I3C_Timeout – The module has stalled too long in a frame. 
kStatus_I3C_Nak – The slave device sent a NAK in response to an address. 
kStatus_I3C_WriteAbort – The slave device sent a NAK in response to a write. 
kStatus_I3C_Term – The master terminates slave read. 
kStatus_I3C_HdrParityError – Parity error from DDR read. 
kStatus_I3C_CrcError – CRC error from DDR read. 
kStatus_I3C_MsgError – Message SDR/DDR mismatch or read/write message in wrong state. 
kStatus_I3C_ReadFifoError – Read from M/SRDATAB register when FIFO empty. 
kStatus_I3C_WriteFifoError – Write to M/SWDATAB register when FIFO full. 
kStatus_I3C_InvalidReq – Invalid use of request. 







status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)#

Performs a polling send transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)#

Performs a polling receive transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






void I3C_MasterTransferCreateHandle(I3C_Type *base, i3c_master_handle_t *handle, const i3c_master_transfer_callback_t *callback, void *userData)#

Creates a new handle for the I3C master non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The I3C peripheral base address. 
handle – [out] Pointer to the I3C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer)#

Performs a non-blocking transaction on the I2C/I3C bus. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or a non-blocking transaction is already in progress. 







status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count)#

Returns number of bytes transferred so far. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a non-blocking transaction currently in progress. 







void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)#

Terminates a non-blocking I3C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the I3C peripheral’s IRQ priority.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 







void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)#

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
intHandle – Pointer to the I3C master driver handle. 







void I3C_DriverIRQHandler(uint32_t instance)#

Common IRQ handler entry for all I3C instances. 
This function dispatches the IRQ to the correct instance handler using the instance index.

Parameters:

instance – I3C instance number. 







enum _i3c_master_flags#

I3C master peripheral flags. 
The following status register flags can be cleared:

kI3C_MasterSlaveStartFlag
kI3C_MasterControlDoneFlag
kI3C_MasterCompleteFlag
kI3C_MasterArbitrationWonFlag
kI3C_MasterSlave2MasterFlag


All flags except kI3C_MasterBetweenFlag and kI3C_MasterNackDetectFlag can be enabled as interrupts.

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_MasterBetweenFlag#

Between messages/DAAs flag 




enumerator kI3C_MasterNackDetectFlag#

NACK detected flag 




enumerator kI3C_MasterSlaveStartFlag#

Slave request start flag 




enumerator kI3C_MasterControlDoneFlag#

Master request complete flag 




enumerator kI3C_MasterCompleteFlag#

Transfer complete flag 




enumerator kI3C_MasterRxReadyFlag#

Rx data ready in Rx buffer flag 




enumerator kI3C_MasterTxReadyFlag#

Tx buffer ready for Tx data flag 




enumerator kI3C_MasterArbitrationWonFlag#

Header address won arbitration flag 




enumerator kI3C_MasterErrorFlag#

Error occurred flag 




enumerator kI3C_MasterSlave2MasterFlag#

Switch from slave to master flag 




enumerator kI3C_MasterClearFlags#







enum _i3c_master_error_flags#

I3C master error flags to indicate the causes. 

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_MasterErrorNackFlag#

Slave NACKed the last address 




enumerator kI3C_MasterErrorWriteAbortFlag#

Slave NACKed the write data 




enumerator kI3C_MasterErrorParityFlag#

Parity error from DDR read 




enumerator kI3C_MasterErrorCrcFlag#

CRC error from DDR read 




enumerator kI3C_MasterErrorReadFlag#

Read from MRDATAB register when FIFO empty 




enumerator kI3C_MasterErrorWriteFlag#

Write to MWDATAB register when FIFO full 




enumerator kI3C_MasterErrorMsgFlag#

Message SDR/DDR mismatch or read/write message in wrong state 




enumerator kI3C_MasterErrorInvalidReqFlag#

Invalid use of request 




enumerator kI3C_MasterErrorTimeoutFlag#

The module has stalled too long in a frame 




enumerator kI3C_MasterAllErrorFlags#

All error flags 






enum _i3c_master_state#

I3C working master state. 
Values:


enumerator kI3C_MasterStateIdle#

Bus stopped. 




enumerator kI3C_MasterStateSlvReq#

Bus stopped but slave holding SDA low. 




enumerator kI3C_MasterStateMsgSdr#

In SDR Message mode from using MWMSG_SDR. 




enumerator kI3C_MasterStateNormAct#

In normal active SDR mode. 




enumerator kI3C_MasterStateDdr#

In DDR Message mode. 




enumerator kI3C_MasterStateDaa#

In ENTDAA mode. 




enumerator kI3C_MasterStateIbiAck#

Waiting on IBI ACK/NACK decision. 




enumerator kI3C_MasterStateIbiRcv#

Receiving IBI. 






enum _i3c_master_enable#

I3C master enable configuration. 
Values:


enumerator kI3C_MasterOff#

Master off. 




enumerator kI3C_MasterOn#

Master on. 




enumerator kI3C_MasterCapable#

Master capable. 






enum _i3c_master_hkeep#

I3C high keeper configuration. 
Values:


enumerator kI3C_MasterHighKeeperNone#

Use PUR to hold SCL high. 




enumerator kI3C_MasterHighKeeperWiredIn#

Use pin_HK controls. 




enumerator kI3C_MasterPassiveSDA#

Hi-Z for Bus Free and hold SDA. 




enumerator kI3C_MasterPassiveSDASCL#

Hi-Z both for Bus Free, and can Hi-Z SDA for hold. 






enum _i3c_bus_request#

Emits the requested operation when doing in pieces vs. by message. 
Values:


enumerator kI3C_RequestNone#

No request. 




enumerator kI3C_RequestEmitStartAddr#

Request to emit start and address on bus. 




enumerator kI3C_RequestEmitStop#

Request to emit stop on bus. 




enumerator kI3C_RequestIbiAckNack#

Manual IBI ACK or NACK. 




enumerator kI3C_RequestProcessDAA#

Process DAA. 




enumerator kI3C_RequestForceExit#

Request to force exit. 




enumerator kI3C_RequestAutoIbi#

Hold in stopped state, but Auto-emit START,7E. 






enum _i3c_bus_type#

Bus type with EmitStartAddr. 
Values:


enumerator kI3C_TypeI3CSdr#

SDR mode of I3C. 




enumerator kI3C_TypeI2C#

Standard i2c protocol. 




enumerator kI3C_TypeI3CDdr#

HDR-DDR mode of I3C. 






enum _i3c_ibi_response#

IBI response. 
Values:


enumerator kI3C_IbiRespAck#

ACK with no mandatory byte. 




enumerator kI3C_IbiRespNack#

NACK. 




enumerator kI3C_IbiRespAckMandatory#

ACK with mandatory byte. 




enumerator kI3C_IbiRespManual#

Reserved. 






enum _i3c_ibi_type#

IBI type. 
Values:


enumerator kI3C_IbiNormal#

In-band interrupt. 




enumerator kI3C_IbiHotJoin#

slave hot join. 




enumerator kI3C_IbiMasterRequest#

slave master ship request. 






enum _i3c_ibi_state#

IBI state. 
Values:


enumerator kI3C_IbiReady#

In-band interrupt ready state, ready for user to handle. 




enumerator kI3C_IbiDataBuffNeed#

In-band interrupt need data buffer for data receive. 




enumerator kI3C_IbiAckNackPending#

In-band interrupt Ack/Nack pending for decision. 






enum _i3c_direction#

Direction of master and slave transfers. 
Values:


enumerator kI3C_Write#

Master transmit. 




enumerator kI3C_Read#

Master receive. 






enum _i3c_tx_trigger_level#

Watermark of TX int/dma trigger level. 
Values:


enumerator kI3C_TxTriggerOnEmpty#

Trigger on empty. 




enumerator kI3C_TxTriggerUntilOneQuarterOrLess#

Trigger on 1/4 full or less. 




enumerator kI3C_TxTriggerUntilOneHalfOrLess#

Trigger on 1/2 full or less. 




enumerator kI3C_TxTriggerUntilOneLessThanFull#

Trigger on 1 less than full or less. 






enum _i3c_rx_trigger_level#

Watermark of RX int/dma trigger level. 
Values:


enumerator kI3C_RxTriggerOnNotEmpty#

Trigger on not empty. 




enumerator kI3C_RxTriggerUntilOneQuarterOrMore#

Trigger on 1/4 full or more. 




enumerator kI3C_RxTriggerUntilOneHalfOrMore#

Trigger on 1/2 full or more. 




enumerator kI3C_RxTriggerUntilThreeQuarterOrMore#

Trigger on 3/4 full or more. 






enum _i3c_rx_term_ops#

I3C master read termination operations. 
Values:


enumerator kI3C_RxTermDisable#

Master doesn’t terminate read, used for CCC transfer. 




enumerator kI3C_RxAutoTerm#

Master auto terminate read after receiving specified bytes(<=255). 




enumerator kI3C_RxTermLastByte#

Master terminates read at any time after START, no length limitation. 






enum _i3c_start_scl_delay#

I3C start SCL delay options. 
Values:


enumerator kI3C_NoDelay#

No delay. 




enumerator kI3C_IncreaseSclHalfPeriod#

Increases SCL clock period by 1/2. 




enumerator kI3C_IncreaseSclOnePeriod#

Increases SCL clock period by 1. 




enumerator kI3C_IncreaseSclOneAndHalfPeriod#

Increases SCL clock period by 1 1/2 






enum _i3c_master_bus_mode#

I3C bus topology. Selects how the baud rate is calculated for the bus. 
Values:


enumerator kI3C_PureBus#

Only I3C devices on the bus. 




enumerator kI3C_MixedFastBus#

I3C and legacy I2C Fm/Fm+ devices share the bus. 




enumerator kI3C_LimitedBus#

I3C controller on a legacy I2C bus. 






enum _i3c_legacy_i2c_speed_mode#

Legacy I2C preset selector. 
Values:


enumerator kI3C_LegacyI2CStandardMode#

Reserved for future Standard-mode support. 




enumerator kI3C_LegacyI2CFastMode#

Legacy I2C Fast-mode preset. 




enumerator kI3C_LegacyI2CFastModePlus#

Legacy I2C Fast-mode Plus preset. 






enum _i3c_master_src_clk#

Validated source clock selector for I2C timing presets. 
Values:


enumerator kI3C_MasterSrcClk24M#

Use the validated 24 MHz timing table. 




enumerator kI3C_MasterSrcClk25M#

Use the validated 25 MHz timing table. 






enum _i3c_master_transfer_flags#

Transfer option flags. 

Note
These enumerations are intended to be OR’d together to form a bit mask of options for the _i3c_master_transfer::flags field. 

Values:


enumerator kI3C_TransferDefaultFlag#

Transfer starts with a start signal, stops with a stop signal. 




enumerator kI3C_TransferNoStartFlag#

Don’t send a start condition, address, and sub address 




enumerator kI3C_TransferRepeatedStartFlag#

Send a repeated start condition 




enumerator kI3C_TransferNoStopFlag#

Don’t send a stop condition. 




enumerator kI3C_TransferWordsFlag#

Transfer in words, else transfer in bytes. 




enumerator kI3C_TransferDisableRxTermFlag#

Disable Rx termination. Note: It’s for I3C CCC transfer. 




enumerator kI3C_TransferRxAutoTermFlag#

Set Rx auto-termination. Note: It’s adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. 




enumerator kI3C_TransferStartWithBroadcastAddr#

Start transfer with 0x7E, then read/write data with device address. 






typedef enum _i3c_master_state i3c_master_state_t#

I3C working master state. 




typedef enum _i3c_master_enable i3c_master_enable_t#

I3C master enable configuration. 




typedef enum _i3c_master_hkeep i3c_master_hkeep_t#

I3C high keeper configuration. 




typedef enum _i3c_bus_request i3c_bus_request_t#

Emits the requested operation when doing in pieces vs. by message. 




typedef enum _i3c_bus_type i3c_bus_type_t#

Bus type with EmitStartAddr. 




typedef enum _i3c_ibi_response i3c_ibi_response_t#

IBI response. 




typedef enum _i3c_ibi_type i3c_ibi_type_t#

IBI type. 




typedef enum _i3c_ibi_state i3c_ibi_state_t#

IBI state. 




typedef enum _i3c_direction i3c_direction_t#

Direction of master and slave transfers. 




typedef enum _i3c_tx_trigger_level i3c_tx_trigger_level_t#

Watermark of TX int/dma trigger level. 




typedef enum _i3c_rx_trigger_level i3c_rx_trigger_level_t#

Watermark of RX int/dma trigger level. 




typedef enum _i3c_rx_term_ops i3c_rx_term_ops_t#

I3C master read termination operations. 




typedef enum _i3c_start_scl_delay i3c_start_scl_delay_t#

I3C start SCL delay options. 




typedef struct _i3c_register_ibi_addr i3c_register_ibi_addr_t#

Structure with setting master IBI rules and slave registry. 




typedef struct _i3c_baudrate i3c_baudrate_hz_t#

Structure with I3C baudrate settings. 




typedef struct _i3c_master_daa_baudrate i3c_master_daa_baudrate_t#

I3C DAA baud rate configuration. 




typedef enum _i3c_master_bus_mode i3c_master_bus_mode_t#

I3C bus topology. Selects how the baud rate is calculated for the bus. 




typedef enum _i3c_legacy_i2c_speed_mode i3c_legacy_i2c_speed_mode_t#

Legacy I2C preset selector. 




typedef enum _i3c_master_src_clk i3c_master_src_clk_t#

Validated source clock selector for I2C timing presets. 




typedef struct _i3c_master_baudrate_config i3c_master_baudrate_config_t#

I3C master baud rate configuration. 




typedef struct _i3c_timing i3c_timing_t#

Pre-calculated I3C MCONFIG timing fields. 
Pre-compute the timing at init, then switch with I3C_MasterSetTiming(). The actualXxxBaud fields report the rates the hardware achieves. 




typedef struct _i3c_master_config i3c_master_config_t#

Structure with settings to initialize the I3C master module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef struct _i3c_master_transfer i3c_master_transfer_t#





typedef struct _i3c_master_handle i3c_master_handle_t#





typedef struct _i3c_master_transfer_callback i3c_master_transfer_callback_t#

i3c master callback functions. 




typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle)#

Typedef for master interrupt handler. 




struct _i3c_register_ibi_addr#


#include <fsl_i3c.h>
Structure with setting master IBI rules and slave registry. 

Public Members


uint8_t address[5]#

Address array for registry. 




bool i3cFastStart#

Allow the START header to run as push-pull speed if all dynamic addresses take MSB 0. 




bool ibiHasPayload#

Whether the address array has mandatory IBI byte. 







struct _i3c_baudrate#


#include <fsl_i3c.h>
Structure with I3C baudrate settings. 

Public Members


uint32_t i2cBaud#

Desired I2C baud rate in Hertz. 




uint32_t i3cPushPullBaud#

Desired I3C push-pull baud rate in Hertz. 




uint32_t i3cOpenDrainBaud#

Desired I3C open-drain baud rate in Hertz. 







struct _i3c_master_daa_baudrate#


#include <fsl_i3c.h>
I3C DAA baud rate configuration. 

Public Members


uint32_t sourceClock_Hz#

FCLK, function clock in Hertz. 




uint32_t i3cPushPullBaud#

Desired I3C push-pull baud rate in Hertz. 




uint32_t i3cOpenDrainBaud#

Desired I3C open-drain baud rate in Hertz. 







struct _i3c_master_baudrate_config#


#include <fsl_i3c.h>
I3C master baud rate configuration. 

Public Members


i3c_master_bus_mode_t busMode#

Bus topology. 




uint32_t i2cBaud#

Desired legacy I2C baud rate in Hz; 0 = do not program I2CBAUD. 




uint32_t i3cPushPullBaud#

Desired I3C push-pull SCL frequency in Hz. 




uint32_t i3cOpenDrainBaud#

Desired I3C open-drain SCL frequency in Hz. 




bool enableODHPP#

Open-drain HIGH shape: true = narrow (normal I3C frames), false = symmetric (required for the first-7Eh broadcast). 







struct _i3c_timing#


#include <fsl_i3c.h>
Pre-calculated I3C MCONFIG timing fields. 
Pre-compute the timing at init, then switch with I3C_MasterSetTiming(). The actualXxxBaud fields report the rates the hardware achieves. 

Public Members


uint8_t ppBaud#

MCONFIG[PPBAUD] field. 




uint8_t ppLow#

MCONFIG[PPLOW] field. 




uint8_t odBaud#

MCONFIG[ODBAUD] field (0 is forbidden). 




bool odHighPP#

MCONFIG[ODHPP] field. 




uint8_t i2cBaud#

MCONFIG[I2CBAUD] field. 




uint32_t actualPpBaud#

Achieved PP SCL frequency in Hz. 




uint32_t actualOdBaud#

Achieved OD SCL frequency in Hz. 




uint32_t actualI2cBaud#

Achieved I2C SCL frequency in Hz (0 if no I2C is configured). 







struct _i3c_master_config#


#include <fsl_i3c.h>
Structure with settings to initialize the I3C master module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster#

Enable master mode. 




bool disableTimeout#

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep#

High keeper mode setting. 




bool enableOpenDrainStop#

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh#

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz#

Desired baud rate settings. 




i3c_start_scl_delay_t startSclDelay#

I3C SCL delay after START. 




i3c_start_scl_delay_t restartSclDelay#

I3C SCL delay after Repeated START. 







struct _i3c_master_transfer_callback#


#include <fsl_i3c.h>
i3c master callback functions. 

Public Members


void (*slave2Master)(I3C_Type *base, void *userData)#

Transfer complete callback 




void (*ibiCallback)(I3C_Type *base, i3c_master_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)#

IBI event callback 




void (*transferComplete)(I3C_Type *base, i3c_master_handle_t *handle, status_t completionStatus, void *userData)#

Transfer complete callback 







struct _i3c_master_transfer#


#include <fsl_i3c.h>
Non-blocking transfer descriptor structure. 
This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. 

Public Members


uint32_t flags#

Bit mask of options for the transfer. See enumeration _i3c_master_transfer_flags for available options. Set to 0 or kI3C_TransferDefaultFlag for normal transfers. 




uint8_t slaveAddress#

The 7-bit slave address. 




i3c_direction_t direction#

Either kI3C_Read or kI3C_Write. 




uint32_t subaddress#

Sub address. Transferred MSB first. 




size_t subaddressSize#

Length of sub address to send in bytes. Maximum size is 4 bytes. 




void *data#

Pointer to data to transfer. 




size_t dataSize#

Number of bytes to transfer. 




i3c_bus_type_t busType#

bus type. 




i3c_ibi_response_t ibiResponse#

ibi response during transfer. 







struct _i3c_master_handle#


#include <fsl_i3c.h>
Driver handle for master non-blocking APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


uint8_t state#

Transfer state machine current state. 




uint32_t remainingBytes#

Remaining byte count in current state. 




i3c_rx_term_ops_t rxTermOps#

Read termination operation. 




i3c_master_transfer_t transfer#

Copy of the current transfer info. 




uint8_t ibiAddress#

Slave address which request IBI. 




uint8_t *ibiBuff#

Pointer to IBI buffer to keep ibi bytes. 




size_t ibiPayloadSize#

IBI payload size. 




i3c_ibi_type_t ibiType#

IBI type. 




i3c_master_transfer_callback_t callback#

Callback functions pointer. 




void *userData#

Application data passed to callback. 







I3C Master DMA Driver#


void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, const i3c_master_edma_callback_t *callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)#

Create a new handle for the I3C master DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function. 







status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer)#

Performs a non-blocking DMA-based transaction on the I3C bus. 
The callback specified when the handle was created is invoked when the transaction has completed.

Note
On parts affected by ERR053412, the I3C controller stalls SCL when the RxFIFO becomes full and does not recover after CPU read FIFO, bus will be stalling indefinitely. This DMA-based API services the RxFIFO with EDMA so it never fills, and is the recommended workaround on affected parts.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
transfer – The pointer to the transfer descriptor. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 







status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count)#

Returns number of bytes transferred so far. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 
count – [out] Number of bytes transferred so far by the non-blocking transaction. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – There is not a DMA transaction currently in progress. 







void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)#

Terminates a non-blocking I3C master transmission early. 

Note
It is not safe to call this function from an IRQ handler that has a higher priority than the DMA peripheral’s IRQ priority.


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C master driver handle. 







void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)#

Reusable routine to handle master interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
i3cHandle – Pointer to the I3C master DMA driver handle. 







typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t#





typedef struct _i3c_master_edma_callback i3c_master_edma_callback_t#

i3c master callback functions. 




struct _i3c_master_edma_callback#


#include <fsl_i3c_edma.h>
i3c master callback functions. 

Public Members


void (*slave2Master)(I3C_Type *base, void *userData)#

Target asks for controller request. 




void (*ibiCallback)(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_ibi_type_t ibiType, i3c_ibi_state_t ibiState)#

IBI event callback. 




void (*transferComplete)(I3C_Type *base, i3c_master_edma_handle_t *handle, status_t status, void *userData)#

Transfer complete callback. 







struct _i3c_master_edma_handle#


#include <fsl_i3c_edma.h>
Driver handle for master EDMA APIs. 

Note
The contents of this structure are private and subject to change. 


Public Members


I3C_Type *base#

I3C base pointer. 




uint8_t state#

Transfer state machine current state. 




uint32_t transferCount#

Indicates progress of the transfer 




uint8_t subaddressBuffer[4]#

Saving subaddress command. 




uint8_t subaddressCount#

Saving command count. 




i3c_master_transfer_t transfer#

Copy of the current transfer info. 




i3c_master_edma_callback_t callback#

Callback function pointer. 




void *userData#

Application data passed to callback. 




edma_handle_t *rxDmaHandle#

Handle for receive DMA channel. 




edma_handle_t *txDmaHandle#

Handle for transmit DMA channel. 




bool ibiFlag#

IBIWON flag. 




uint8_t ibiAddress#

Slave address which request IBI. 




uint8_t *ibiBuff#

Pointer to IBI buffer to keep ibi bytes. 




size_t ibiPayloadSize#

IBI payload size. 




i3c_ibi_type_t ibiType#

IBI type. 




status_t result#

Transfer result. 







I3C Slave Driver#


void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)

Provides a default configuration for the I3C slave peripheral. 
This function provides the following default configuration for the I3C slave peripheral: 
slaveConfig->enableslave             = true;



After calling this function, you can override any settings in order to customize the configuration, prior to initializing the slave driver with I3C_SlaveInit().

Parameters:

slaveConfig – [out] User provided configuration structure for default values. Refer to i3c_slave_config_t. 







void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)

Initializes the I3C slave peripheral. 
This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user provided configuration.

Parameters:

base – The I3C peripheral base address. 
slaveConfig – User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of defaults that you can override. 
slowClock_Hz – Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. 







void I3C_SlaveDeinit(I3C_Type *base)

Deinitializes the I3C slave peripheral. 
This function disables the I3C slave peripheral and gates the clock.

Parameters:

base – The I3C peripheral base address. 







static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)

Enable/Disable Slave. 

Parameters:

base – The I3C peripheral base address. 
isEnable – Enable or disable. 







static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)

Gets the I3C slave status flags. 
A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave status flag state. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Attempts to clear other flags has no effect.

See also
_i3c_slave_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of status flags that are to be cleared. The mask is composed of _i3c_slave_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetStatusFlags(). 







static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)

Gets the I3C slave error status flags. 
A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

See also
_i3c_slave_error_flags



Parameters:

base – The I3C peripheral base address. 


Returns:
State of the error status flags:

1: related status flag is set.
0: related status flag is not set. 








static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)

Clears the I3C slave error status flag state. 

See also
_i3c_slave_error_flags. 



Parameters:

base – The I3C peripheral base address. 
statusMask – A bitmask of error status flags that are to be cleared. The mask is composed of _i3c_slave_error_flags enumerators OR’d together. You may pass the result of a previous call to I3C_SlaveGetErrorStatusFlags(). 







i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)

Gets the I3C slave state. 

Parameters:

base – The I3C peripheral base address. 


Returns:
I3C slave activity state, refer i3c_slave_activity_state_t. 






static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)

Enables the I3C slave interrupt requests. 
Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to enable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)

Disables the I3C slave interrupt requests. 
Only below flags can be disabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Parameters:

base – The I3C peripheral base address. 
interruptMask – Bit mask of interrupts to disable. See _i3c_slave_flags for the set of constants that should be OR’d together to form the bit mask. 







static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)

Returns the set of currently enabled I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of enabled interrupts. 






static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)

Returns the set of pending I3C slave interrupt requests. 

Parameters:

base – The I3C peripheral base address. 


Returns:
A bitmask composed of _i3c_slave_flags enumerators OR’d together to indicate the set of pending interrupts. 






static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)

Enables or disables I3C slave DMA requests. 

Parameters:

base – The I3C peripheral base address. 
enableTx – Enable flag for transmit DMA request. Pass true for enable, false for disable. 
enableRx – Enable flag for receive DMA request. Pass true for enable, false for disable. 
width – DMA read/write unit in bytes. 







static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave transmit data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Transmit Data Register address. 






static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)

Gets I3C slave receive data register address for DMA transfer. 

Parameters:

base – The I3C peripheral base address. 
width – DMA read/write unit in bytes. 


Returns:
The I3C Slave Receive Data Register address. 






static inline void I3C_SlaveSetWatermarks(I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)

Sets the watermarks for I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txLvl – Transmit FIFO watermark level. The kI3C_SlaveTxReadyFlag flag is set whenever the number of words in the transmit FIFO reaches txLvl. 
rxLvl – Receive FIFO watermark level. The kI3C_SlaveRxReadyFlag flag is set whenever the number of words in the receive FIFO reaches rxLvl. 
flushTx – true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. 
flushRx – true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. 







static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)

Gets the current number of bytes in the I3C slave FIFOs. 

Parameters:

base – The I3C peripheral base address. 
txCount – [out] Pointer through which the current number of bytes in the transmit FIFO is returned. Pass NULL if this value is not required. 
rxCount – [out] Pointer through which the current number of bytes in the receive FIFO is returned. Pass NULL if this value is not required. 







status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize)

Performs a polling send transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
txBuff – The pointer to the data to be transferred. 
txSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize)

Performs a polling receive transfer on the I3C bus. 

Parameters:

base – The I3C peripheral base address. 
rxBuff – The pointer to the data to be transferred. 
rxSize – The length in bytes of the data to be transferred. 


Returns:
Error or success status returned by API. 






void I3C_SlaveTransferCreateHandle(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_callback_t callback, void *userData)#

Creates a new handle for the I3C slave non-blocking APIs. 
The creation of a handle is for use with the non-blocking APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.

Note
The function also enables the NVIC IRQ for the input I3C. Need to notice that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to enable the associated INTMUX IRQ in application.


Parameters:

base – The I3C peripheral base address. 
handle – [out] Pointer to the I3C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 







status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask)#

Starts accepting slave transfers. 
Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked from the interrupt context.
The set of events received by the callback is customizable. To do so, set the eventMask parameter to the OR’d combination of i3c_slave_transfer_event_t enumerators for the events you wish to receive. The kI3C_SlaveTransmitEvent and kI3C_SlaveReceiveEvent events are always enabled and do not need to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and receive events that are always enabled. In addition, the kI3C_SlaveAllEvents constant is provided as a convenient way to enable all events.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. Other accepted values are 0 to get a default set of only the transmit and receive events, and kI3C_SlaveAllEvents to enable all events.


Return values:

kStatus_Success – Slave transfers were successfully started. 
kStatus_I3C_Busy – Slave transfers have already been started on this handle. 







status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count)#

Gets the slave transfer status during a non-blocking transfer. 

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to i2c_slave_handle_t structure. 
count – [out] Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not required. 


Return values:

kStatus_Success – 
kStatus_NoTransferInProgress – 







void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle)#

Aborts the slave non-blocking transfers. 

Note
This API could be called at any time to stop slave for handling the bus events. 


Parameters:

base – The I3C peripheral base address. 
handle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 







void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)#

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the non blocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
intHandle – Pointer to struct: _i3c_slave_handle structure which stores the transfer state. 







enum _i3c_slave_flags#

I3C slave peripheral flags. 
The following status register flags can be cleared:

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag


Only below flags can be enabled as interrupts.

kI3C_SlaveBusStartFlag
kI3C_SlaveMatchedFlag
kI3C_SlaveBusStopFlag
kI3C_SlaveRxReadyFlag
kI3C_SlaveTxReadyFlag
kI3C_SlaveDynamicAddrChangedFlag
kI3C_SlaveReceivedCCCFlag
kI3C_SlaveErrorFlag
kI3C_SlaveHDRCommandMatchFlag
kI3C_SlaveCCCHandledFlag
kI3C_SlaveEventSentFlag



Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_SlaveNotStopFlag#

Slave status not stop flag 




enumerator kI3C_SlaveMessageFlag#

Slave status message, indicating slave is listening to the bus traffic or responding 




enumerator kI3C_SlaveRequiredReadFlag#

Slave status required, either is master doing SDR read from slave, or is IBI pushing out. 




enumerator kI3C_SlaveRequiredWriteFlag#

Slave status request write, master is doing SDR write to slave, except slave in ENTDAA mode 




enumerator kI3C_SlaveBusDAAFlag#

I3C bus is in ENTDAA mode 




enumerator kI3C_SlaveBusHDRModeFlag#

I3C bus is in HDR mode 




enumerator kI3C_SlaveBusStartFlag#

Start/Re-start event is seen since the bus was last cleared 




enumerator kI3C_SlaveMatchedFlag#

Slave address(dynamic/static) matched since last cleared 




enumerator kI3C_SlaveBusStopFlag#

Stop event is seen since the bus was last cleared 




enumerator kI3C_SlaveRxReadyFlag#

Rx data ready in rx buffer flag 




enumerator kI3C_SlaveTxReadyFlag#

Tx buffer ready for Tx data flag 




enumerator kI3C_SlaveDynamicAddrChangedFlag#

Slave dynamic address has been assigned, re-assigned, or lost 




enumerator kI3C_SlaveReceivedCCCFlag#

Slave received Common command code 




enumerator kI3C_SlaveErrorFlag#

Error occurred flag 




enumerator kI3C_SlaveHDRCommandMatchFlag#

High data rate command match 




enumerator kI3C_SlaveCCCHandledFlag#

Slave received Common command code is handled by I3C module 




enumerator kI3C_SlaveEventSentFlag#

Slave IBI/P2P/MR/HJ event has been sent 




enumerator kI3C_SlaveIbiDisableFlag#

Slave in band interrupt is disabled. 




enumerator kI3C_SlaveMasterRequestDisabledFlag#

Slave master request is disabled. 




enumerator kI3C_SlaveHotJoinDisabledFlag#

Slave Hot-Join is disabled. 




enumerator kI3C_SlaveClearFlags#

All flags which are cleared by the driver upon starting a transfer. 




enumerator kI3C_SlaveAllIrqFlags#







enum _i3c_slave_error_flags#

I3C slave error flags to indicate the causes. 

Note
These enums are meant to be OR’d together to form a bit mask. 

Values:


enumerator kI3C_SlaveErrorOverrunFlag#

Slave internal from-bus buffer/FIFO overrun. 




enumerator kI3C_SlaveErrorUnderrunFlag#

Slave internal to-bus buffer/FIFO underrun 




enumerator kI3C_SlaveErrorUnderrunNakFlag#

Slave internal from-bus buffer/FIFO underrun and NACK error 




enumerator kI3C_SlaveErrorTermFlag#

Terminate error from master 




enumerator kI3C_SlaveErrorInvalidStartFlag#

Slave invalid start flag 




enumerator kI3C_SlaveErrorSdrParityFlag#

SDR parity error 




enumerator kI3C_SlaveErrorHdrParityFlag#

HDR parity error 




enumerator kI3C_SlaveErrorHdrCRCFlag#

HDR-DDR CRC error 




enumerator kI3C_SlaveErrorS0S1Flag#

S0 or S1 error 




enumerator kI3C_SlaveErrorOverreadFlag#

Over-read error 




enumerator kI3C_SlaveErrorOverwriteFlag#

Over-write error 






enum _i3c_slave_event#

I3C slave.event. 
Values:


enumerator kI3C_SlaveEventNormal#

Normal mode. 




enumerator kI3C_SlaveEventIBI#

In band interrupt event. 




enumerator kI3C_SlaveEventMasterReq#

Master request event. 




enumerator kI3C_SlaveEventHotJoinReq#

Hot-join event. 






enum _i3c_slave_activity_state#

I3C slave.activity state. 
Values:


enumerator kI3C_SlaveNoLatency#

Normal bus operation 




enumerator kI3C_SlaveLatency1Ms#

1ms of latency. 




enumerator kI3C_SlaveLatency100Ms#

100ms of latency. 




enumerator kI3C_SlaveLatency10S#

10s latency. 






enum _i3c_slave_transfer_event#

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 

Values:


enumerator kI3C_SlaveAddressMatchEvent#

Received the slave address after a start or repeated start. 




enumerator kI3C_SlaveTransmitEvent#

Callback is requested to provide data to transmit (slave-transmitter role). 




enumerator kI3C_SlaveReceiveEvent#

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kI3C_SlaveRequiredTransmitEvent#

Callback is requested to provide a buffer in which to place received data (slave-receiver role). 




enumerator kI3C_SlaveStartEvent#

A start/repeated start was detected. 




enumerator kI3C_SlaveHDRCommandMatchEvent#

Slave Match HDR Command. 




enumerator kI3C_SlaveCompletionEvent#

A stop was detected, completing the transfer. 




enumerator kI3C_SlaveRequestSentEvent#

Slave request event sent. 




enumerator kI3C_SlaveReceivedCCCEvent#

Slave received CCC event, need to handle by application. 




enumerator kI3C_SlaveAllEvents#

Bit mask of all available events. 






typedef enum _i3c_slave_event i3c_slave_event_t#

I3C slave.event. 




typedef enum _i3c_slave_activity_state i3c_slave_activity_state_t#

I3C slave.activity state. 




typedef struct _i3c_slave_config i3c_slave_config_t#

Structure with settings to initialize the I3C slave module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 




typedef enum _i3c_slave_transfer_event i3c_slave_transfer_event_t#

Set of events sent to the callback for non blocking slave transfers. 
These event enumerations are used for two related purposes. First, a bit mask created by OR’ing together events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable. Then, when the slave callback is invoked, it is passed the current event through its transfer parameter.

Note
These enumerations are meant to be OR’d together to form a bit mask of events. 





typedef struct _i3c_slave_transfer i3c_slave_transfer_t#

I3C slave transfer structure. 




typedef struct _i3c_slave_handle i3c_slave_handle_t#





typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData)#

Slave event callback function pointer type. 
This callback is used only for the slave non-blocking transfer API. To install a callback, use the I3C_SlaveSetCallback() function after you have created a handle.

Param base:
Base address for the I3C instance on which the event occurred. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle)#

Typedef for slave interrupt handler. 




struct _i3c_slave_config#


#include <fsl_i3c.h>
Structure with settings to initialize the I3C slave module. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


bool enableSlave#

Whether to enable slave. 




uint8_t staticAddr#

Static address. 




uint16_t vendorID#

Device vendor ID(manufacture ID). 




uint32_t partNumber#

Device part number info 




uint8_t dcr#

Device characteristics register information. 




uint8_t bcr#

Bus characteristics register information. 




uint8_t hdrMode#

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest#

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error#

Whether to ignore S0/S1 error in SDR mode. 




bool offline#

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop#

Whether to assert start/stop status only the time slave is addressed. 




uint32_t maxWriteLength#

Maximum write length. 




uint32_t maxReadLength#

Maximum read length. 







struct _i3c_slave_transfer#


#include <fsl_i3c.h>
I3C slave transfer structure. 

Public Members


uint32_t event#

Reason the callback is being invoked. 




uint8_t *txData#

Transfer buffer 




size_t txDataSize#

Transfer size 




uint8_t *rxData#

Transfer buffer 




size_t rxDataSize#

Transfer size 




status_t completionStatus#

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent. 




size_t transferredCount#

Number of bytes actually transferred since start or last repeated start. 







struct _i3c_slave_handle#


#include <fsl_i3c.h>
I3C slave handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


i3c_slave_transfer_t transfer#

I3C slave transfer copy. 




bool isBusy#

Whether transfer is busy. 




bool wasTransmit#

Whether the last transfer was a transmit. 




uint32_t eventMask#

Mask of enabled events. 




uint32_t transferredCount#

Count of bytes transferred. 




i3c_slave_transfer_callback_t callback#

Callback function called at transfer event. 




void *userData#

Callback parameter passed to callback. 




size_t txFifoSize#

Tx Fifo size 







I3C Slave DMA Driver#


void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle, edma_handle_t *txDmaHandle)#

Create a new handle for the I3C slave DMA APIs. 
The creation of a handle is for use with the DMA APIs. Once a handle is created, there is not a corresponding destroy handle. If the user wants to terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.
For devices where the I3C send and receive DMA requests are OR’d together, the txDmaHandle parameter is ignored and may be set to NULL.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C slave driver handle. 
callback – User provided pointer to the asynchronous callback function. 
userData – User provided pointer to the application callback data. 
rxDmaHandle – Handle for the DMA receive channel. Created by the user prior to calling this function. 
txDmaHandle – Handle for the DMA transmit channel. Created by the user prior to calling this function. 







status_t I3C_SlaveTransferEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle, i3c_slave_edma_transfer_t *transfer, uint32_t eventMask)#

Prepares for a non-blocking DMA-based transaction on the I3C bus. 
The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when there’s bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned with master application to ensure the transfer is executed as expected. Callback specified when the handle was created is invoked when the transaction has completed.

Parameters:

base – The I3C peripheral base address. 
handle – Pointer to the I3C slave driver handle. 
transfer – The pointer to the transfer descriptor. 
eventMask – Bit mask formed by OR’ing together i3c_slave_transfer_event_t enumerators to specify which events to send to the callback. The transmit and receive events is not allowed to be enabled. 


Return values:

kStatus_Success – The transaction was started successfully. 
kStatus_I3C_Busy – Either another master is currently utilizing the bus, or another DMA transaction is already in progress. 
kStatus_Fail – The transaction can’t be set. 







void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)#

Abort a slave edma non-blocking transfer in a early time. 

Parameters:

base – I3C peripheral base address 
handle – pointer to i3c_slave_edma_handle_t structure 







void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)#

Reusable routine to handle slave interrupts. 

Note
This function does not need to be called unless you are reimplementing the nonblocking API’s interrupt handler routines to add special functionality. 


Parameters:

base – The I3C peripheral base address. 
i3cHandle – Pointer to the I3C slave DMA driver handle. 







typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t#





typedef struct _i3c_slave_edma_transfer i3c_slave_edma_transfer_t#

I3C slave transfer structure. 




typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData)#

Slave event callback function pointer type. 
This callback is used only for the slave DMA transfer API.

Param base:
Base address for the I3C instance on which the event occurred. 

Param handle:
Pointer to slave DMA transfer handle. 

Param transfer:
Pointer to transfer descriptor containing values passed to and/or from the callback. 

Param userData:
Arbitrary pointer-sized value passed from the application. 






struct _i3c_slave_edma_transfer#


#include <fsl_i3c_edma.h>
I3C slave transfer structure. 

Public Members


uint32_t event#

Reason the callback is being invoked. 




uint8_t *txData#

Transfer buffer 




size_t txDataSize#

Transfer size 




uint8_t *rxData#

Transfer buffer 




size_t rxDataSize#

Transfer size 




status_t completionStatus#

Success or error code describing how the transfer completed. Only applies for kI3C_SlaveCompletionEvent. 







struct _i3c_slave_edma_handle#


#include <fsl_i3c_edma.h>
I3C slave edma handle structure. 

Note
The contents of this structure are private and subject to change. 


Public Members


I3C_Type *base#

I3C base pointer. 




i3c_slave_edma_transfer_t transfer#

I3C slave transfer copy. 




bool isBusy#

Whether transfer is busy. 




bool wasTransmit#

Whether the last transfer was a transmit. 




bool isDdrMode#

Whether this is HDR-DDR transfer. 




uint32_t eventMask#

Mask of enabled events. 




i3c_slave_edma_callback_t callback#

Callback function called at transfer event. 




edma_handle_t *rxDmaHandle#

Handle for receive DMA channel. 




edma_handle_t *txDmaHandle#

Handle for transmit DMA channel. 




void *userData#

Callback parameter passed to callback. 







INPUTMUX: Input Multiplexing Driver#


enum _inputmux_index_t#

Values:


enumerator kINPUTMUX_INDEX_CTIMER0CAPTSEL0#





enumerator kINPUTMUX_INDEX_CTIMER0CAPTSEL1#





enumerator kINPUTMUX_INDEX_CTIMER0CAPTSEL2#





enumerator kINPUTMUX_INDEX_CTIMER0CAPTSEL3#





enumerator kINPUTMUX_INDEX_CTIMER1CAPTSEL0#





enumerator kINPUTMUX_INDEX_CTIMER1CAPTSEL1#





enumerator kINPUTMUX_INDEX_CTIMER1CAPTSEL2#





enumerator kINPUTMUX_INDEX_CTIMER1CAPTSEL3#





enumerator kINPUTMUX_INDEX_CTIMER2CAPTSEL0#





enumerator kINPUTMUX_INDEX_CTIMER2CAPTSEL1#





enumerator kINPUTMUX_INDEX_CTIMER2CAPTSEL2#





enumerator kINPUTMUX_INDEX_CTIMER2CAPTSEL3#





enumerator kINPUTMUX_INDEX_ADC0_TRIGSEL0#





enumerator kINPUTMUX_INDEX_ADC0_TRIGSEL1#





enumerator kINPUTMUX_INDEX_ADC0_TRIGSEL2#





enumerator kINPUTMUX_INDEX_ADC0_TRIGSEL3#





enumerator kINPUTMUX_INDEX_QDC0_ICAPSEL1#





enumerator kINPUTMUX_INDEX_QDC0_ICAPSEL2#





enumerator kINPUTMUX_INDEX_QDC0_ICAPSEL3#





enumerator kINPUTMUX_INDEX_QDC1_ICAPSEL1#





enumerator kINPUTMUX_INDEX_QDC1_ICAPSEL2#





enumerator kINPUTMUX_INDEX_QDC1_ICAPSEL3#





enumerator kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL0#





enumerator kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL1#





enumerator kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL2#





enumerator kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL3#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL0#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL1#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL2#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL3#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL4#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL5#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL6#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL7#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL8#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL9#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL10#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL11#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL12#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL13#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL14#





enumerator kINPUTMUX_INDEX_AOI0_TRIGSEL15#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL0#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL1#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL2#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL3#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL4#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL6#





enumerator kINPUTMUX_INDEX_EXT_TRIGSEL7#







enum _inputmux_connection_t#

INPUTMUX connections type. 
Values:


enumerator kINPUTMUX_CtimerInp0ToTimer0Captsel#

TIMER0 CAPTSEL. 




enumerator kINPUTMUX_CtimerInp1ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp2ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp3ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp4ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp5ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp6ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp7ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp8ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp9ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp10ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp11ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp12ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp13ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp14ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp15ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp16ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp17ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp18ToTimer0Captsel#





enumerator kINPUTMUX_CtimerInp19ToTimer0Captsel#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer0Captsel#





enumerator kINPUTMUX_Aoi0Out0ToTimer0Captsel#





enumerator kINPUTMUX_Aoi0Out1ToTimer0Captsel#





enumerator kINPUTMUX_Aoi0Out2ToTimer0Captsel#





enumerator kINPUTMUX_Aoi0Out3ToTimer0Captsel#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer0Captsel#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer0Captsel#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer0Captsel#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer0Captsel#





enumerator kINPUTMUX_Cmp0OutToTimer0Captsel#





enumerator kINPUTMUX_Cmp1OutToTimer0Captsel#





enumerator kINPUTMUX_Ctimer1M1ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer1M2ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer1M3ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer2M1ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer2M2ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer2M3ToTimer0Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer0Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer0Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer0Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer0Captsel#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer0Captsel#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Captsel#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Captsel#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Captsel#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Captsel#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Captsel#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer0Captsel#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer0Captsel#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Captsel#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Captsel#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Captsel#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Captsel#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Captsel#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Captsel#





enumerator kINPUTMUX_Aoi1Out0ToTimer0Captsel#





enumerator kINPUTMUX_Aoi1Out1ToTimer0Captsel#





enumerator kINPUTMUX_Aoi1Out2ToTimer0Captsel#





enumerator kINPUTMUX_Aoi1Out3ToTimer0Captsel#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer0Captsel#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer0Captsel#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer0Captsel#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer3M1ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer3M2ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer3M3ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer4M1ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer4M2ToTimer0Captsel#





enumerator kINPUTMUX_Ctimer4M3ToTimer0Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer0Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer0Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer0Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer0Captsel#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer0Captsel#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Captsel#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Captsel#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Captsel#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Captsel#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Captsel#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Captsel#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Captsel#

Timer1 CAPTSEL. 




enumerator kINPUTMUX_CtimerInp0ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp1ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp2ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp3ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp4ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp5ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp6ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp7ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp8ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp9ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp10ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp11ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp12ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp13ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp14ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp15ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp16ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp17ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp18ToTimer1Captsel#





enumerator kINPUTMUX_CtimerInp19ToTimer1Captsel#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer1Captsel#





enumerator kINPUTMUX_Aoi0Out0ToTimer1Captsel#





enumerator kINPUTMUX_Aoi0Out1ToTimer1Captsel#





enumerator kINPUTMUX_Aoi0Out2ToTimer1Captsel#





enumerator kINPUTMUX_Aoi0Out3ToTimer1Captsel#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer1Captsel#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer1Captsel#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer1Captsel#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer1Captsel#





enumerator kINPUTMUX_Cmp0OutToTimer1Captsel#





enumerator kINPUTMUX_Cmp1OutToTimer1Captsel#





enumerator kINPUTMUX_Ctimer0M1ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer0M2ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer0M3ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer2M1ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer2M2ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer2M3ToTimer1Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer1Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer1Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer1Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer1Captsel#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer1Captsel#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Captsel#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Captsel#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Captsel#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Captsel#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Captsel#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer1Captsel#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer1Captsel#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Captsel#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Captsel#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Captsel#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Captsel#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Captsel#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Captsel#





enumerator kINPUTMUX_Aoi1Out0ToTimer1Captsel#





enumerator kINPUTMUX_Aoi1Out1ToTimer1Captsel#





enumerator kINPUTMUX_Aoi1Out2ToTimer1Captsel#





enumerator kINPUTMUX_Aoi1Out3ToTimer1Captsel#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer1Captsel#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer1Captsel#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer1Captsel#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer3M1ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer3M2ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer3M3ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer4M1ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer4M2ToTimer1Captsel#





enumerator kINPUTMUX_Ctimer4M3ToTimer1Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer1Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer1Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer1Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer1Captsel#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer1Captsel#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Captsel#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Captsel#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Captsel#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Captsel#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Captsel#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Captsel#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Captsel#

Timer2 CAPTSEL. 




enumerator kINPUTMUX_CtimerInp0ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp1ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp2ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp3ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp4ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp5ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp6ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp7ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp8ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp9ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp10ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp11ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp12ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp13ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp14ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp15ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp16ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp17ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp18ToTimer2Captsel#





enumerator kINPUTMUX_CtimerInp19ToTimer2Captsel#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer2Captsel#





enumerator kINPUTMUX_Aoi0Out0ToTimer2Captsel#





enumerator kINPUTMUX_Aoi0Out1ToTimer2Captsel#





enumerator kINPUTMUX_Aoi0Out2ToTimer2Captsel#





enumerator kINPUTMUX_Aoi0Out3ToTimer2Captsel#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer2Captsel#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer2Captsel#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer2Captsel#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer2Captsel#





enumerator kINPUTMUX_Cmp0OutToTimer2Captsel#





enumerator kINPUTMUX_Cmp1OutToTimer2Captsel#





enumerator kINPUTMUX_Ctimer0M1ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer0M2ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer0M3ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer1M1ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer1M2ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer1M3ToTimer2Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer2Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer2Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer2Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer2Captsel#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer2Captsel#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Captsel#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Captsel#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Captsel#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Captsel#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Captsel#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer2Captsel#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer2Captsel#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Captsel#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Captsel#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Captsel#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Captsel#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Captsel#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Captsel#





enumerator kINPUTMUX_Aoi1Out0ToTimer2Captsel#





enumerator kINPUTMUX_Aoi1Out1ToTimer2Captsel#





enumerator kINPUTMUX_Aoi1Out2ToTimer2Captsel#





enumerator kINPUTMUX_Aoi1Out3ToTimer2Captsel#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer2Captsel#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer2Captsel#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer2Captsel#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer3M1ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer3M2ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer3M3ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer4M1ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer4M2ToTimer2Captsel#





enumerator kINPUTMUX_Ctimer4M3ToTimer2Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer2Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer2Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer2Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer2Captsel#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer2Captsel#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Captsel#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Captsel#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Captsel#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Captsel#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Captsel#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Captsel#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Captsel#

Timer3 CAPTSEL. 




enumerator kINPUTMUX_CtimerInp0ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp1ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp2ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp3ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp4ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp5ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp6ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp7ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp8ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp9ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp10ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp11ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp12ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp13ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp14ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp15ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp16ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp17ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp18ToTimer3Captsel#





enumerator kINPUTMUX_CtimerInp19ToTimer3Captsel#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer3Captsel#





enumerator kINPUTMUX_Aoi0Out0ToTimer3Captsel#





enumerator kINPUTMUX_Aoi0Out1ToTimer3Captsel#





enumerator kINPUTMUX_Aoi0Out2ToTimer3Captsel#





enumerator kINPUTMUX_Aoi0Out3ToTimer3Captsel#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer3Captsel#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer3Captsel#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer3Captsel#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer3Captsel#





enumerator kINPUTMUX_Cmp0OutToTimer3Captsel#





enumerator kINPUTMUX_Cmp1OutToTimer3Captsel#





enumerator kINPUTMUX_Ctimer0M1ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer0M2ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer0M3ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer1M1ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer1M2ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer1M3ToTimer3Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer3Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer3Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer3Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer3Captsel#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer3Captsel#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Captsel#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Captsel#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Captsel#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Captsel#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Captsel#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer3Captsel#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer3Captsel#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Captsel#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Captsel#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Captsel#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Captsel#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Captsel#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Captsel#





enumerator kINPUTMUX_Aoi1Out0ToTimer3Captsel#





enumerator kINPUTMUX_Aoi1Out1ToTimer3Captsel#





enumerator kINPUTMUX_Aoi1Out2ToTimer3Captsel#





enumerator kINPUTMUX_Aoi1Out3ToTimer3Captsel#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer3Captsel#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer3Captsel#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer3Captsel#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer2M1ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer2M2ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer2M3ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer4M1ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer4M2ToTimer3Captsel#





enumerator kINPUTMUX_Ctimer4M3ToTimer3Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer3Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer3Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer3Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer3Captsel#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer3Captsel#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Captsel#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Captsel#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Captsel#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Captsel#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Captsel#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Captsel#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Captsel#

Timer4 CAPTSEL. 




enumerator kINPUTMUX_CtimerInp0ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp1ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp2ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp3ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp4ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp5ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp6ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp7ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp8ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp9ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp10ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp11ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp12ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp13ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp14ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp15ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp16ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp17ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp18ToTimer4Captsel#





enumerator kINPUTMUX_CtimerInp19ToTimer4Captsel#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer4Captsel#





enumerator kINPUTMUX_Aoi0Out0ToTimer4Captsel#





enumerator kINPUTMUX_Aoi0Out1ToTimer4Captsel#





enumerator kINPUTMUX_Aoi0Out2ToTimer4Captsel#





enumerator kINPUTMUX_Aoi0Out3ToTimer4Captsel#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer4Captsel#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer4Captsel#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer4Captsel#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer4Captsel#





enumerator kINPUTMUX_Cmp0OutToTimer4Captsel#





enumerator kINPUTMUX_Cmp1OutToTimer4Captsel#





enumerator kINPUTMUX_Ctimer0M1ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer0M2ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer0M3ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer1M1ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer1M2ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer1M3ToTimer4Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer4Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer4Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer4Captsel#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer4Captsel#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer4Captsel#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Captsel#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Captsel#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Captsel#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Captsel#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Captsel#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer4Captsel#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer4Captsel#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Captsel#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Captsel#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Captsel#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Captsel#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Captsel#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Captsel#





enumerator kINPUTMUX_Aoi1Out0ToTimer4Captsel#





enumerator kINPUTMUX_Aoi1Out1ToTimer4Captsel#





enumerator kINPUTMUX_Aoi1Out2ToTimer4Captsel#





enumerator kINPUTMUX_Aoi1Out3ToTimer4Captsel#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer4Captsel#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer4Captsel#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer4Captsel#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer2M1ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer2M2ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer2M3ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer3M1ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer3M2ToTimer4Captsel#





enumerator kINPUTMUX_Ctimer3M3ToTimer4Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer4Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer4Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer4Captsel#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer4Captsel#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer4Captsel#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Captsel#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Captsel#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Captsel#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Captsel#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Captsel#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Captsel#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Captsel#

TIMER0 Trigger. 




enumerator kINPUTMUX_CtimerInp0ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp1ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp2ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp3ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp4ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp5ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp6ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp7ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp8ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp9ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp10ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp11ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp12ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp13ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp14ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp15ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp16ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp17ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp18ToTimer0Trigger#





enumerator kINPUTMUX_CtimerInp19ToTimer0Trigger#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer0Trigger#





enumerator kINPUTMUX_Aoi0Out0ToTimer0Trigger#





enumerator kINPUTMUX_Aoi0Out1ToTimer0Trigger#





enumerator kINPUTMUX_Aoi0Out2ToTimer0Trigger#





enumerator kINPUTMUX_Aoi0Out3ToTimer0Trigger#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer0Trigger#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer0Trigger#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer0Trigger#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer0Trigger#





enumerator kINPUTMUX_Cmp0OutToTimer0Trigger#





enumerator kINPUTMUX_Cmp1OutToTimer0Trigger#





enumerator kINPUTMUX_Ctimer1M1ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer1M2ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer1M3ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer2M1ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer2M2ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer2M3ToTimer0Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer0Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer0Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer0Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer0Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Trigger#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Trigger#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Trigger#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer0Trigger#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer0Trigger#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Trigger#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Trigger#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Trigger#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Trigger#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Trigger#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Trigger#





enumerator kINPUTMUX_Aoi1Out0ToTimer0Trigger#





enumerator kINPUTMUX_Aoi1Out1ToTimer0Trigger#





enumerator kINPUTMUX_Aoi1Out2ToTimer0Trigger#





enumerator kINPUTMUX_Aoi1Out3ToTimer0Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer0Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer0Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer0Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer3M1ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer3M2ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer3M3ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer4M1ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer4M2ToTimer0Trigger#





enumerator kINPUTMUX_Ctimer4M3ToTimer0Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer0Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer0Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer0Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer0Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Trigger#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Trigger#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Trigger#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Trigger#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Trigger#

Timer1 Trigger. 




enumerator kINPUTMUX_CtimerInp0ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp1ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp2ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp3ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp4ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp5ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp6ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp7ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp8ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp9ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp10ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp11ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp12ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp13ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp14ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp15ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp16ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp17ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp18ToTimer1Trigger#





enumerator kINPUTMUX_CtimerInp19ToTimer1Trigger#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer1Trigger#





enumerator kINPUTMUX_Aoi0Out0ToTimer1Trigger#





enumerator kINPUTMUX_Aoi0Out1ToTimer1Trigger#





enumerator kINPUTMUX_Aoi0Out2ToTimer1Trigger#





enumerator kINPUTMUX_Aoi0Out3ToTimer1Trigger#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer1Trigger#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer1Trigger#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer1Trigger#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer1Trigger#





enumerator kINPUTMUX_Cmp0OutToTimer1Trigger#





enumerator kINPUTMUX_Cmp1OutToTimer1Trigger#





enumerator kINPUTMUX_Ctimer0M1ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer0M2ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer0M3ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer2M1ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer2M2ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer2M3ToTimer1Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer1Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer1Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer1Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer1Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Trigger#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Trigger#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Trigger#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer1Trigger#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer1Trigger#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Trigger#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Trigger#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Trigger#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Trigger#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Trigger#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Trigger#





enumerator kINPUTMUX_Aoi1Out0ToTimer1Trigger#





enumerator kINPUTMUX_Aoi1Out1ToTimer1Trigger#





enumerator kINPUTMUX_Aoi1Out2ToTimer1Trigger#





enumerator kINPUTMUX_Aoi1Out3ToTimer1Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer1Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer1Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer1Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer3M1ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer3M2ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer3M3ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer4M1ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer4M2ToTimer1Trigger#





enumerator kINPUTMUX_Ctimer4M3ToTimer1Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer1Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer1Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer1Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer1Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Trigger#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Trigger#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Trigger#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Trigger#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Trigger#

Timer2 Trigger. 




enumerator kINPUTMUX_CtimerInp0ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp1ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp2ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp3ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp4ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp5ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp6ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp7ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp8ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp9ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp10ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp11ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp12ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp13ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp14ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp15ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp16ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp17ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp18ToTimer2Trigger#





enumerator kINPUTMUX_CtimerInp19ToTimer2Trigger#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer2Trigger#





enumerator kINPUTMUX_Aoi0Out0ToTimer2Trigger#





enumerator kINPUTMUX_Aoi0Out1ToTimer2Trigger#





enumerator kINPUTMUX_Aoi0Out2ToTimer2Trigger#





enumerator kINPUTMUX_Aoi0Out3ToTimer2Trigger#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer2Trigger#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer2Trigger#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer2Trigger#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer2Trigger#





enumerator kINPUTMUX_Cmp0OutToTimer2Trigger#





enumerator kINPUTMUX_Cmp1OutToTimer2Trigger#





enumerator kINPUTMUX_Ctimer0M1ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer0M2ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer0M3ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer1M1ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer1M2ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer1M3ToTimer2Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer2Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer2Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer2Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer2Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer2Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Trigger#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Trigger#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Trigger#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer2Trigger#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer2Trigger#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Trigger#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Trigger#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Trigger#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Trigger#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Trigger#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Trigger#





enumerator kINPUTMUX_Aoi1Out0ToTimer2Trigger#





enumerator kINPUTMUX_Aoi1Out1ToTimer2Trigger#





enumerator kINPUTMUX_Aoi1Out2ToTimer2Trigger#





enumerator kINPUTMUX_Aoi1Out3ToTimer2Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer2Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer2Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer2Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer3M1ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer3M2ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer3M3ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer4M1ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer4M2ToTimer2Trigger#





enumerator kINPUTMUX_Ctimer4M3ToTimer2Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer2Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer2Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer2Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer2Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer2Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Trigger#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Trigger#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Trigger#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Trigger#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Trigger#

Timer3 Trigger. 




enumerator kINPUTMUX_CtimerInp0ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp1ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp2ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp3ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp4ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp5ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp6ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp7ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp8ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp9ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp10ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp11ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp12ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp13ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp14ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp15ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp16ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp17ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp18ToTimer3Trigger#





enumerator kINPUTMUX_CtimerInp19ToTimer3Trigger#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer3Trigger#





enumerator kINPUTMUX_Aoi0Out0ToTimer3Trigger#





enumerator kINPUTMUX_Aoi0Out1ToTimer3Trigger#





enumerator kINPUTMUX_Aoi0Out2ToTimer3Trigger#





enumerator kINPUTMUX_Aoi0Out3ToTimer3Trigger#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer3Trigger#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer3Trigger#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer3Trigger#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer3Trigger#





enumerator kINPUTMUX_Cmp0OutToTimer3Trigger#





enumerator kINPUTMUX_Cmp1OutToTimer3Trigger#





enumerator kINPUTMUX_Ctimer0M1ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer0M2ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer0M3ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer1M1ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer1M2ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer1M3ToTimer3Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer3Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer3Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer3Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer3Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer3Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Trigger#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Trigger#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Trigger#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer3Trigger#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer3Trigger#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Trigger#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Trigger#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Trigger#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Trigger#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Trigger#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Trigger#





enumerator kINPUTMUX_Aoi1Out0ToTimer3Trigger#





enumerator kINPUTMUX_Aoi1Out1ToTimer3Trigger#





enumerator kINPUTMUX_Aoi1Out2ToTimer3Trigger#





enumerator kINPUTMUX_Aoi1Out3ToTimer3Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer3Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer3Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer3Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer2M1ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer2M2ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer2M3ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer4M1ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer4M2ToTimer3Trigger#





enumerator kINPUTMUX_Ctimer4M3ToTimer3Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer3Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer3Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer3Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer3Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer3Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Trigger#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Trigger#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Trigger#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Trigger#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Trigger#

Timer4 Trigger. 




enumerator kINPUTMUX_CtimerInp0ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp1ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp2ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp3ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp4ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp5ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp6ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp7ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp8ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp9ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp10ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp11ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp12ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp13ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp14ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp15ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp16ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp17ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp18ToTimer4Trigger#





enumerator kINPUTMUX_CtimerInp19ToTimer4Trigger#





enumerator kINPUTMUX_Usb0StartOfFrameToTimer4Trigger#





enumerator kINPUTMUX_Aoi0Out0ToTimer4Trigger#





enumerator kINPUTMUX_Aoi0Out1ToTimer4Trigger#





enumerator kINPUTMUX_Aoi0Out2ToTimer4Trigger#





enumerator kINPUTMUX_Aoi0Out3ToTimer4Trigger#





enumerator kINPUTMUX_Adc0Tcomp0ToTimer4Trigger#





enumerator kINPUTMUX_Adc0Tcomp1ToTimer4Trigger#





enumerator kINPUTMUX_Adc0Tcomp2ToTimer4Trigger#





enumerator kINPUTMUX_Adc0Tcomp3ToTimer4Trigger#





enumerator kINPUTMUX_Cmp0OutToTimer4Trigger#





enumerator kINPUTMUX_Cmp1OutToTimer4Trigger#





enumerator kINPUTMUX_Ctimer0M1ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer0M2ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer0M3ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer1M1ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer1M2ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer1M3ToTimer4Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag0ToTimer4Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag1ToTimer4Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag2ToTimer4Trigger#





enumerator kINPUTMUX_Qdc0CmpFlag3ToTimer4Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToTimer4Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Trigger#





enumerator kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Trigger#





enumerator kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Trigger#





enumerator kINPUTMUX_Lpspi0EndOfFrameToTimer4Trigger#





enumerator kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpspi1EndOfFrameToTimer4Trigger#





enumerator kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Trigger#





enumerator kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Trigger#





enumerator kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Trigger#





enumerator kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Trigger#





enumerator kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Trigger#





enumerator kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Trigger#





enumerator kINPUTMUX_Aoi1Out0ToTimer4Trigger#





enumerator kINPUTMUX_Aoi1Out1ToTimer4Trigger#





enumerator kINPUTMUX_Aoi1Out2ToTimer4Trigger#





enumerator kINPUTMUX_Aoi1Out3ToTimer4Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToTimer4Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToTimer4Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToTimer4Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer2M1ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer2M2ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer2M3ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer3M1ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer3M2ToTimer4Trigger#





enumerator kINPUTMUX_Ctimer3M3ToTimer4Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag0ToTimer4Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag1ToTimer4Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag2ToTimer4Trigger#





enumerator kINPUTMUX_Qdc1CmpFlag3ToTimer4Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToTimer4Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Trigger#





enumerator kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Trigger#





enumerator kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Trigger#





enumerator kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Trigger#





enumerator kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Trigger#

Selection for frequency measurement reference clock. 




enumerator kINPUTMUX_ClkInToFreqmeasRef#





enumerator kINPUTMUX_FroOsc12MToFreqmeasRef#





enumerator kINPUTMUX_FroHfDivToFreqmeasRef#





enumerator kINPUTMUX_Clk16K1ToFreqmeasRef#





enumerator kINPUTMUX_SlowClkToFreqmeasRef#





enumerator kINPUTMUX_FreqmeClkIn0ToFreqmeasRef#





enumerator kINPUTMUX_FreqmeClkIn1ToFreqmeasRef#





enumerator kINPUTMUX_Aoi0Out0ToFreqmeasRef#





enumerator kINPUTMUX_Aoi0Out1ToFreqmeasRef#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasRef#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasRef#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasRef#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasRef#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasRef#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasRef#

Selection for frequency measurement target clock. 




enumerator kINPUTMUX_ClkInToFreqmeasTar#





enumerator kINPUTMUX_FroOsc12MToFreqmeasTar#





enumerator kINPUTMUX_FroHfDivToFreqmeasTar#





enumerator kINPUTMUX_Clk16K1ToFreqmeasTar#





enumerator kINPUTMUX_SlowClkToFreqmeasTar#





enumerator kINPUTMUX_FreqmeClkIn0ToFreqmeasTar#





enumerator kINPUTMUX_FreqmeClkIn1ToFreqmeasTar#





enumerator kINPUTMUX_Aoi0Out0ToFreqmeasTar#





enumerator kINPUTMUX_Aoi0Out1ToFreqmeasTar#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasTar#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasTar#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasTar#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasTar#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasTar#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasTar#

Cmp0 Trigger. 




enumerator kINPUTMUX_Aoi0Out0ToCmp0Trigger#





enumerator kINPUTMUX_Aoi0Out1ToCmp0Trigger#





enumerator kINPUTMUX_Aoi0Out2ToCmp0Trigger#





enumerator kINPUTMUX_Aoi0Out3ToCmp0Trigger#





enumerator kINPUTMUX_Cmp1OutToCmp0Trigger#





enumerator kINPUTMUX_Ctimer0M0ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer0M2ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer1M0ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer1M2ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer2M0ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer2M2ToCmp0Trigger#





enumerator kINPUTMUX_Lptmr0ToCmp0Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToCmp0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToCmp0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToCmp0Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToCmp0Trigger#





enumerator kINPUTMUX_WuuToCmp0Trigger#





enumerator kINPUTMUX_Aoi1Out0ToCmp0Trigger#





enumerator kINPUTMUX_Aoi1Out1ToCmp0Trigger#





enumerator kINPUTMUX_Aoi1Out2ToCmp0Trigger#





enumerator kINPUTMUX_Aoi1Out3ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer3M0ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer3M1ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer4M0ToCmp0Trigger#





enumerator kINPUTMUX_Ctimer4M1ToCmp0Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToCmp0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToCmp0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToCmp0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToCmp0Trigger#

Cmp1 Trigger. 




enumerator kINPUTMUX_Aoi0Out0ToCmp1Trigger#





enumerator kINPUTMUX_Aoi0Out1ToCmp1Trigger#





enumerator kINPUTMUX_Aoi0Out2ToCmp1Trigger#





enumerator kINPUTMUX_Aoi0Out3ToCmp1Trigger#





enumerator kINPUTMUX_Cmp0OutToCmp1Trigger#





enumerator kINPUTMUX_Ctimer0M0ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer0M2ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer1M0ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer1M2ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer2M0ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer2M2ToCmp1Trigger#





enumerator kINPUTMUX_Lptmr0ToCmp1Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToCmp1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToCmp1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToCmp1Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToCmp1Trigger#





enumerator kINPUTMUX_WuuToCmp1Trigger#





enumerator kINPUTMUX_Aoi1Out0ToCmp1Trigger#





enumerator kINPUTMUX_Aoi1Out1ToCmp1Trigger#





enumerator kINPUTMUX_Aoi1Out2ToCmp1Trigger#





enumerator kINPUTMUX_Aoi1Out3ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer3M0ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer3M1ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer4M0ToCmp1Trigger#





enumerator kINPUTMUX_Ctimer4M1ToCmp1Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToCmp1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToCmp1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToCmp1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToCmp1Trigger#

Adc0 Trigger. 




enumerator kINPUTMUX_ArmTxevToAdc0Trigger#





enumerator kINPUTMUX_Aoi0Out0ToAdc0Trigger#





enumerator kINPUTMUX_Aoi0Out1ToAdc0Trigger#





enumerator kINPUTMUX_Aoi0Out2ToAdc0Trigger#





enumerator kINPUTMUX_Aoi0Out3ToAdc0Trigger#





enumerator kINPUTMUX_Cmp0OutToAdc0Trigger#





enumerator kINPUTMUX_Cmp1OutToAdc0Trigger#





enumerator kINPUTMUX_Ctimer0M0ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer0M1ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer1M0ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer1M1ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer2M0ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer2M1ToAdc0Trigger#





enumerator kINPUTMUX_Lptmr0ToAdc0Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToAdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToAdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToAdc0Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToAdc0Trigger#





enumerator kINPUTMUX_WuuToAdc0Trigger#





enumerator kINPUTMUX_Aoi1Out0ToAdc0Trigger#





enumerator kINPUTMUX_Aoi1Out1ToAdc0Trigger#





enumerator kINPUTMUX_Aoi1Out2ToAdc0Trigger#





enumerator kINPUTMUX_Aoi1Out3ToAdc0Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToAdc0Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToAdc0Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToAdc0Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer3M0ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer3M1ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer4M0ToAdc0Trigger#





enumerator kINPUTMUX_Ctimer4M1ToAdc0Trigger#





enumerator kINPUTMUX_FlexioCh0ToAdc0Trigger#





enumerator kINPUTMUX_FlexioCh1ToAdc0Trigger#





enumerator kINPUTMUX_FlexioCh2ToAdc0Trigger#





enumerator kINPUTMUX_FlexioCh3ToAdc0Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToAdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToAdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToAdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToAdc0Trigger#

Adc1 Trigger. 




enumerator kINPUTMUX_ArmTxevToAdc1Trigger#





enumerator kINPUTMUX_Aoi0Out0ToAdc1Trigger#





enumerator kINPUTMUX_Aoi0Out1ToAdc1Trigger#





enumerator kINPUTMUX_Aoi0Out2ToAdc1Trigger#





enumerator kINPUTMUX_Aoi0Out3ToAdc1Trigger#





enumerator kINPUTMUX_Cmp0OutToAdc1Trigger#





enumerator kINPUTMUX_Cmp1OutToAdc1Trigger#





enumerator kINPUTMUX_Ctimer0M0ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer0M1ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer1M0ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer1M1ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer2M0ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer2M1ToAdc1Trigger#





enumerator kINPUTMUX_Lptmr0ToAdc1Trigger#





enumerator kINPUTMUX_Qdc0PosMatch0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToAdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToAdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToAdc1Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToAdc1Trigger#





enumerator kINPUTMUX_WuuToAdc1Trigger#





enumerator kINPUTMUX_Aoi1Out0ToAdc1Trigger#





enumerator kINPUTMUX_Aoi1Out1ToAdc1Trigger#





enumerator kINPUTMUX_Aoi1Out2ToAdc1Trigger#





enumerator kINPUTMUX_Aoi1Out3ToAdc1Trigger#





enumerator kINPUTMUX_Adc0Tcomp0ToAdc1Trigger#





enumerator kINPUTMUX_Adc0Tcomp1ToAdc1Trigger#





enumerator kINPUTMUX_Adc0Tcomp2ToAdc1Trigger#





enumerator kINPUTMUX_Adc0Tcomp3ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer3M0ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer3M1ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer4M0ToAdc1Trigger#





enumerator kINPUTMUX_Ctimer4M1ToAdc1Trigger#





enumerator kINPUTMUX_FlexioCh0ToAdc1Trigger#





enumerator kINPUTMUX_FlexioCh1ToAdc1Trigger#





enumerator kINPUTMUX_FlexioCh2ToAdc1Trigger#





enumerator kINPUTMUX_FlexioCh3ToAdc1Trigger#





enumerator kINPUTMUX_Qdc1PosMatch0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToAdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToAdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToAdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToAdc1Trigger#

Dac0 Trigger. 




enumerator kINPUTMUX_ArmTxevToDac0Trigger#





enumerator kINPUTMUX_Aoi0Out0ToDac0Trigger#





enumerator kINPUTMUX_Aoi0Out1ToDac0Trigger#





enumerator kINPUTMUX_Aoi0Out2ToDac0Trigger#





enumerator kINPUTMUX_Aoi0Out3ToDac0Trigger#





enumerator kINPUTMUX_Cmp0OutToDac0Trigger#





enumerator kINPUTMUX_Cmp1OutToDac0Trigger#





enumerator kINPUTMUX_Ctimer0M0ToDac0Trigger#





enumerator kINPUTMUX_Ctimer0M1ToDac0Trigger#





enumerator kINPUTMUX_Ctimer1M0ToDac0Trigger#





enumerator kINPUTMUX_Ctimer1M1ToDac0Trigger#





enumerator kINPUTMUX_Ctimer2M0ToDac0Trigger#





enumerator kINPUTMUX_Ctimer2M1ToDac0Trigger#





enumerator kINPUTMUX_Lptmr0ToDac0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToDac0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToDac0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToDac0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToDac0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToDac0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToDac0Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToDac0Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToDac0Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToDac0Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToDac0Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToDac0Trigger#





enumerator kINPUTMUX_WuuToDac0Trigger#





enumerator kINPUTMUX_Aoi1Out0ToDac0Trigger#





enumerator kINPUTMUX_Aoi1Out1ToDac0Trigger#





enumerator kINPUTMUX_Aoi1Out2ToDac0Trigger#





enumerator kINPUTMUX_Aoi1Out3ToDac0Trigger#





enumerator kINPUTMUX_Adc1Tcomp0ToDac0Trigger#





enumerator kINPUTMUX_Adc1Tcomp1ToDac0Trigger#





enumerator kINPUTMUX_Adc1Tcomp2ToDac0Trigger#





enumerator kINPUTMUX_Adc1Tcomp3ToDac0Trigger#





enumerator kINPUTMUX_Ctimer3M0ToDac0Trigger#





enumerator kINPUTMUX_Ctimer3M1ToDac0Trigger#





enumerator kINPUTMUX_Ctimer4M0ToDac0Trigger#





enumerator kINPUTMUX_Ctimer4M1ToDac0Trigger#

Qdc0 Trigger. 




enumerator kINPUTMUX_ArmTxevToQdc0Trigger#





enumerator kINPUTMUX_Aoi0Out0ToQdc0Trigger#





enumerator kINPUTMUX_Aoi0Out1ToQdc0Trigger#





enumerator kINPUTMUX_Aoi0Out2ToQdc0Trigger#





enumerator kINPUTMUX_Aoi0Out3ToQdc0Trigger#





enumerator kINPUTMUX_Cmp0OutToQdc0Trigger#





enumerator kINPUTMUX_Cmp1OutToQdc0Trigger#





enumerator kINPUTMUX_Ctimer0M2ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer0M3ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer1M2ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer1M3ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer2M2ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer2M3ToQdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn0ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn1ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn2ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn3ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn4ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn5ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn6ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn7ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn8ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn9ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn10ToQdc0Trigger#





enumerator kINPUTMUX_TrigIn11ToQdc0Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Aoi1Out0ToQdc0Trigger#





enumerator kINPUTMUX_Aoi1Out1ToQdc0Trigger#





enumerator kINPUTMUX_Aoi1Out2ToQdc0Trigger#





enumerator kINPUTMUX_Aoi1Out3ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer3M2ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer3M3ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer4M2ToQdc0Trigger#





enumerator kINPUTMUX_Ctimer4M3ToQdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Trigger#

Qdc0 Home. 




enumerator kINPUTMUX_ArmTxevToQdc0Home#





enumerator kINPUTMUX_Aoi0Out0ToQdc0Home#





enumerator kINPUTMUX_Aoi0Out1ToQdc0Home#





enumerator kINPUTMUX_Aoi0Out2ToQdc0Home#





enumerator kINPUTMUX_Aoi0Out3ToQdc0Home#





enumerator kINPUTMUX_Cmp0OutToQdc0Home#





enumerator kINPUTMUX_Cmp1OutToQdc0Home#





enumerator kINPUTMUX_Ctimer0M2ToQdc0Home#





enumerator kINPUTMUX_Ctimer0M3ToQdc0Home#





enumerator kINPUTMUX_Ctimer1M2ToQdc0Home#





enumerator kINPUTMUX_Ctimer1M3ToQdc0Home#





enumerator kINPUTMUX_Ctimer2M2ToQdc0Home#





enumerator kINPUTMUX_Ctimer2M3ToQdc0Home#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Home#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Home#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Home#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Home#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Home#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Home#





enumerator kINPUTMUX_TrigIn0ToQdc0Home#





enumerator kINPUTMUX_TrigIn1ToQdc0Home#





enumerator kINPUTMUX_TrigIn2ToQdc0Home#





enumerator kINPUTMUX_TrigIn3ToQdc0Home#





enumerator kINPUTMUX_TrigIn4ToQdc0Home#





enumerator kINPUTMUX_TrigIn5ToQdc0Home#





enumerator kINPUTMUX_TrigIn6ToQdc0Home#





enumerator kINPUTMUX_TrigIn7ToQdc0Home#





enumerator kINPUTMUX_TrigIn8ToQdc0Home#





enumerator kINPUTMUX_TrigIn9ToQdc0Home#





enumerator kINPUTMUX_TrigIn10ToQdc0Home#





enumerator kINPUTMUX_TrigIn11ToQdc0Home#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc0Home#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc0Home#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc0Home#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc0Home#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc0Home#





enumerator kINPUTMUX_Aoi1Out0ToQdc0Home#





enumerator kINPUTMUX_Aoi1Out1ToQdc0Home#





enumerator kINPUTMUX_Aoi1Out2ToQdc0Home#





enumerator kINPUTMUX_Aoi1Out3ToQdc0Home#





enumerator kINPUTMUX_Ctimer3M2ToQdc0Home#





enumerator kINPUTMUX_Ctimer3M3ToQdc0Home#





enumerator kINPUTMUX_Ctimer4M2ToQdc0Home#





enumerator kINPUTMUX_Ctimer4M3ToQdc0Home#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Home#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Home#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Home#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Home#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Home#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Home#

Qdc0 Index. 




enumerator kINPUTMUX_ArmTxevToQdc0Index#





enumerator kINPUTMUX_Aoi0Out0ToQdc0Index#





enumerator kINPUTMUX_Aoi0Out1ToQdc0Index#





enumerator kINPUTMUX_Aoi0Out2ToQdc0Index#





enumerator kINPUTMUX_Aoi0Out3ToQdc0Index#





enumerator kINPUTMUX_Cmp0OutToQdc0Index#





enumerator kINPUTMUX_Cmp1OutToQdc0Index#





enumerator kINPUTMUX_Ctimer0M2ToQdc0Index#





enumerator kINPUTMUX_Ctimer0M3ToQdc0Index#





enumerator kINPUTMUX_Ctimer1M2ToQdc0Index#





enumerator kINPUTMUX_Ctimer1M3ToQdc0Index#





enumerator kINPUTMUX_Ctimer2M2ToQdc0Index#





enumerator kINPUTMUX_Ctimer2M3ToQdc0Index#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Index#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Index#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Index#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Index#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Index#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Index#





enumerator kINPUTMUX_TrigIn0ToQdc0Index#





enumerator kINPUTMUX_TrigIn1ToQdc0Index#





enumerator kINPUTMUX_TrigIn2ToQdc0Index#





enumerator kINPUTMUX_TrigIn3ToQdc0Index#





enumerator kINPUTMUX_TrigIn4ToQdc0Index#





enumerator kINPUTMUX_TrigIn5ToQdc0Index#





enumerator kINPUTMUX_TrigIn6ToQdc0Index#





enumerator kINPUTMUX_TrigIn7ToQdc0Index#





enumerator kINPUTMUX_TrigIn8ToQdc0Index#





enumerator kINPUTMUX_TrigIn9ToQdc0Index#





enumerator kINPUTMUX_TrigIn10ToQdc0Index#





enumerator kINPUTMUX_TrigIn11ToQdc0Index#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc0Index#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc0Index#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc0Index#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc0Index#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc0Index#





enumerator kINPUTMUX_Aoi1Out0ToQdc0Index#





enumerator kINPUTMUX_Aoi1Out1ToQdc0Index#





enumerator kINPUTMUX_Aoi1Out2ToQdc0Index#





enumerator kINPUTMUX_Aoi1Out3ToQdc0Index#





enumerator kINPUTMUX_Ctimer3M2ToQdc0Index#





enumerator kINPUTMUX_Ctimer3M3ToQdc0Index#





enumerator kINPUTMUX_Ctimer4M2ToQdc0Index#





enumerator kINPUTMUX_Ctimer4M3ToQdc0Index#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Index#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Index#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Index#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Index#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Index#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Index#

Qdc0 Phaseb. 




enumerator kINPUTMUX_ArmTxevToQdc0Phaseb#





enumerator kINPUTMUX_Aoi0Out0ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi0Out1ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi0Out2ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi0Out3ToQdc0Phaseb#





enumerator kINPUTMUX_Cmp0OutToQdc0Phaseb#





enumerator kINPUTMUX_Cmp1OutToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer0M2ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer0M3ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer1M2ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer1M3ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer2M2ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer2M3ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn0ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn1ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn2ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn3ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn4ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn5ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn6ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn7ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn8ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn9ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn10ToQdc0Phaseb#





enumerator kINPUTMUX_TrigIn11ToQdc0Phaseb#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi1Out0ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi1Out1ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi1Out2ToQdc0Phaseb#





enumerator kINPUTMUX_Aoi1Out3ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer3M2ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer3M3ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer4M2ToQdc0Phaseb#





enumerator kINPUTMUX_Ctimer4M3ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phaseb#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phaseb#

Qdc0 Phasea. 




enumerator kINPUTMUX_ArmTxevToQdc0Phasea#





enumerator kINPUTMUX_Aoi0Out0ToQdc0Phasea#





enumerator kINPUTMUX_Aoi0Out1ToQdc0Phasea#





enumerator kINPUTMUX_Aoi0Out2ToQdc0Phasea#





enumerator kINPUTMUX_Aoi0Out3ToQdc0Phasea#





enumerator kINPUTMUX_Cmp0OutToQdc0Phasea#





enumerator kINPUTMUX_Cmp1OutToQdc0Phasea#





enumerator kINPUTMUX_Ctimer0M2ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer0M3ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer1M2ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer1M3ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer2M2ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer2M3ToQdc0Phasea#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phasea#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phasea#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn0ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn1ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn2ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn3ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn4ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn5ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn6ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn7ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn8ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn9ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn10ToQdc0Phasea#





enumerator kINPUTMUX_TrigIn11ToQdc0Phasea#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Aoi1Out0ToQdc0Phasea#





enumerator kINPUTMUX_Aoi1Out1ToQdc0Phasea#





enumerator kINPUTMUX_Aoi1Out2ToQdc0Phasea#





enumerator kINPUTMUX_Aoi1Out3ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer3M2ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer3M3ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer4M2ToQdc0Phasea#





enumerator kINPUTMUX_Ctimer4M3ToQdc0Phasea#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phasea#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phasea#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phasea#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phasea#

Qdc0 Icap1. 




enumerator kINPUTMUX_ArmTxevToQdc0Icap1#





enumerator kINPUTMUX_Aoi0Out0ToQdc0Icap1#





enumerator kINPUTMUX_Aoi0Out1ToQdc0Icap1#





enumerator kINPUTMUX_Aoi0Out2ToQdc0Icap1#





enumerator kINPUTMUX_Aoi0Out3ToQdc0Icap1#





enumerator kINPUTMUX_Cmp0OutToQdc0Icap1#





enumerator kINPUTMUX_Cmp1OutToQdc0Icap1#





enumerator kINPUTMUX_Ctimer0M2ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer0M3ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer1M2ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer1M3ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer2M2ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer2M3ToQdc0Icap1#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Icap1#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Icap1#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn0ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn1ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn2ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn3ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn4ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn5ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn6ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn7ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn8ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn9ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn10ToQdc0Icap1#





enumerator kINPUTMUX_TrigIn11ToQdc0Icap1#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Aoi1Out0ToQdc0Icap1#





enumerator kINPUTMUX_Aoi1Out1ToQdc0Icap1#





enumerator kINPUTMUX_Aoi1Out2ToQdc0Icap1#





enumerator kINPUTMUX_Aoi1Out3ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer3M2ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer3M3ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer4M2ToQdc0Icap1#





enumerator kINPUTMUX_Ctimer4M3ToQdc0Icap1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Icap1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Icap1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Icap1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Icap1#

Qdc1 Trigger. 




enumerator kINPUTMUX_ArmTxevToQdc1Trigger#





enumerator kINPUTMUX_Aoi0Out0ToQdc1Trigger#





enumerator kINPUTMUX_Aoi0Out1ToQdc1Trigger#





enumerator kINPUTMUX_Aoi0Out2ToQdc1Trigger#





enumerator kINPUTMUX_Aoi0Out3ToQdc1Trigger#





enumerator kINPUTMUX_Cmp0OutToQdc1Trigger#





enumerator kINPUTMUX_Cmp1OutToQdc1Trigger#





enumerator kINPUTMUX_Ctimer0M2ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer0M3ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer1M2ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer1M3ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer2M2ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer2M3ToQdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn0ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn1ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn2ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn3ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn4ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn5ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn6ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn7ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn8ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn9ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn10ToQdc1Trigger#





enumerator kINPUTMUX_TrigIn11ToQdc1Trigger#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Aoi1Out0ToQdc1Trigger#





enumerator kINPUTMUX_Aoi1Out1ToQdc1Trigger#





enumerator kINPUTMUX_Aoi1Out2ToQdc1Trigger#





enumerator kINPUTMUX_Aoi1Out3ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer3M2ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer3M3ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer4M2ToQdc1Trigger#





enumerator kINPUTMUX_Ctimer4M3ToQdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Trigger#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Trigger#

Qdc1 Home. 




enumerator kINPUTMUX_ArmTxevToQdc1Home#





enumerator kINPUTMUX_Aoi0Out0ToQdc1Home#





enumerator kINPUTMUX_Aoi0Out1ToQdc1Home#





enumerator kINPUTMUX_Aoi0Out2ToQdc1Home#





enumerator kINPUTMUX_Aoi0Out3ToQdc1Home#





enumerator kINPUTMUX_Cmp0OutToQdc1Home#





enumerator kINPUTMUX_Cmp1OutToQdc1Home#





enumerator kINPUTMUX_Ctimer0M2ToQdc1Home#





enumerator kINPUTMUX_Ctimer0M3ToQdc1Home#





enumerator kINPUTMUX_Ctimer1M2ToQdc1Home#





enumerator kINPUTMUX_Ctimer1M3ToQdc1Home#





enumerator kINPUTMUX_Ctimer2M2ToQdc1Home#





enumerator kINPUTMUX_Ctimer2M3ToQdc1Home#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Home#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Home#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Home#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Home#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Home#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Home#





enumerator kINPUTMUX_TrigIn0ToQdc1Home#





enumerator kINPUTMUX_TrigIn1ToQdc1Home#





enumerator kINPUTMUX_TrigIn2ToQdc1Home#





enumerator kINPUTMUX_TrigIn3ToQdc1Home#





enumerator kINPUTMUX_TrigIn4ToQdc1Home#





enumerator kINPUTMUX_TrigIn5ToQdc1Home#





enumerator kINPUTMUX_TrigIn6ToQdc1Home#





enumerator kINPUTMUX_TrigIn7ToQdc1Home#





enumerator kINPUTMUX_TrigIn8ToQdc1Home#





enumerator kINPUTMUX_TrigIn9ToQdc1Home#





enumerator kINPUTMUX_TrigIn10ToQdc1Home#





enumerator kINPUTMUX_TrigIn11ToQdc1Home#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc1Home#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc1Home#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc1Home#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc1Home#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc1Home#





enumerator kINPUTMUX_Aoi1Out0ToQdc1Home#





enumerator kINPUTMUX_Aoi1Out1ToQdc1Home#





enumerator kINPUTMUX_Aoi1Out2ToQdc1Home#





enumerator kINPUTMUX_Aoi1Out3ToQdc1Home#





enumerator kINPUTMUX_Ctimer3M2ToQdc1Home#





enumerator kINPUTMUX_Ctimer3M3ToQdc1Home#





enumerator kINPUTMUX_Ctimer4M2ToQdc1Home#





enumerator kINPUTMUX_Ctimer4M3ToQdc1Home#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Home#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Home#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Home#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Home#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Home#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Home#

Qdc1 Index. 




enumerator kINPUTMUX_ArmTxevToQdc1Index#





enumerator kINPUTMUX_Aoi0Out0ToQdc1Index#





enumerator kINPUTMUX_Aoi0Out1ToQdc1Index#





enumerator kINPUTMUX_Aoi0Out2ToQdc1Index#





enumerator kINPUTMUX_Aoi0Out3ToQdc1Index#





enumerator kINPUTMUX_Cmp0OutToQdc1Index#





enumerator kINPUTMUX_Cmp1OutToQdc1Index#





enumerator kINPUTMUX_Ctimer0M2ToQdc1Index#





enumerator kINPUTMUX_Ctimer0M3ToQdc1Index#





enumerator kINPUTMUX_Ctimer1M2ToQdc1Index#





enumerator kINPUTMUX_Ctimer1M3ToQdc1Index#





enumerator kINPUTMUX_Ctimer2M2ToQdc1Index#





enumerator kINPUTMUX_Ctimer2M3ToQdc1Index#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Index#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Index#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Index#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Index#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Index#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Index#





enumerator kINPUTMUX_TrigIn0ToQdc1Index#





enumerator kINPUTMUX_TrigIn1ToQdc1Index#





enumerator kINPUTMUX_TrigIn2ToQdc1Index#





enumerator kINPUTMUX_TrigIn3ToQdc1Index#





enumerator kINPUTMUX_TrigIn4ToQdc1Index#





enumerator kINPUTMUX_TrigIn5ToQdc1Index#





enumerator kINPUTMUX_TrigIn6ToQdc1Index#





enumerator kINPUTMUX_TrigIn7ToQdc1Index#





enumerator kINPUTMUX_TrigIn8ToQdc1Index#





enumerator kINPUTMUX_TrigIn9ToQdc1Index#





enumerator kINPUTMUX_TrigIn10ToQdc1Index#





enumerator kINPUTMUX_TrigIn11ToQdc1Index#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc1Index#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc1Index#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc1Index#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc1Index#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc1Index#





enumerator kINPUTMUX_Aoi1Out0ToQdc1Index#





enumerator kINPUTMUX_Aoi1Out1ToQdc1Index#





enumerator kINPUTMUX_Aoi1Out2ToQdc1Index#





enumerator kINPUTMUX_Aoi1Out3ToQdc1Index#





enumerator kINPUTMUX_Ctimer3M2ToQdc1Index#





enumerator kINPUTMUX_Ctimer3M3ToQdc1Index#





enumerator kINPUTMUX_Ctimer4M2ToQdc1Index#





enumerator kINPUTMUX_Ctimer4M3ToQdc1Index#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Index#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Index#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Index#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Index#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Index#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Index#

Qdc1 Phaseb. 




enumerator kINPUTMUX_ArmTxevToQdc1Phaseb#





enumerator kINPUTMUX_Aoi0Out0ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi0Out1ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi0Out2ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi0Out3ToQdc1Phaseb#





enumerator kINPUTMUX_Cmp0OutToQdc1Phaseb#





enumerator kINPUTMUX_Cmp1OutToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer0M2ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer0M3ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer1M2ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer1M3ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer2M2ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer2M3ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn0ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn1ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn2ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn3ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn4ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn5ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn6ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn7ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn8ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn9ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn10ToQdc1Phaseb#





enumerator kINPUTMUX_TrigIn11ToQdc1Phaseb#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi1Out0ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi1Out1ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi1Out2ToQdc1Phaseb#





enumerator kINPUTMUX_Aoi1Out3ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer3M2ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer3M3ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer4M2ToQdc1Phaseb#





enumerator kINPUTMUX_Ctimer4M3ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phaseb#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phaseb#

Qdc1 Phasea. 




enumerator kINPUTMUX_ArmTxevToQdc1Phasea#





enumerator kINPUTMUX_Aoi0Out0ToQdc1Phasea#





enumerator kINPUTMUX_Aoi0Out1ToQdc1Phasea#





enumerator kINPUTMUX_Aoi0Out2ToQdc1Phasea#





enumerator kINPUTMUX_Aoi0Out3ToQdc1Phasea#





enumerator kINPUTMUX_Cmp0OutToQdc1Phasea#





enumerator kINPUTMUX_Cmp1OutToQdc1Phasea#





enumerator kINPUTMUX_Ctimer0M2ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer0M3ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer1M2ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer1M3ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer2M2ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer2M3ToQdc1Phasea#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phasea#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phasea#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn0ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn1ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn2ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn3ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn4ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn5ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn6ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn7ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn8ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn9ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn10ToQdc1Phasea#





enumerator kINPUTMUX_TrigIn11ToQdc1Phasea#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Aoi1Out0ToQdc1Phasea#





enumerator kINPUTMUX_Aoi1Out1ToQdc1Phasea#





enumerator kINPUTMUX_Aoi1Out2ToQdc1Phasea#





enumerator kINPUTMUX_Aoi1Out3ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer3M2ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer3M3ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer4M2ToQdc1Phasea#





enumerator kINPUTMUX_Ctimer4M3ToQdc1Phasea#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phasea#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phasea#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phasea#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phasea#

Qdc1 Icap1. 




enumerator kINPUTMUX_ArmTxevToQdc1Icap1#





enumerator kINPUTMUX_Aoi0Out0ToQdc1Icap1#





enumerator kINPUTMUX_Aoi0Out1ToQdc1Icap1#





enumerator kINPUTMUX_Aoi0Out2ToQdc1Icap1#





enumerator kINPUTMUX_Aoi0Out3ToQdc1Icap1#





enumerator kINPUTMUX_Cmp0OutToQdc1Icap1#





enumerator kINPUTMUX_Cmp1OutToQdc1Icap1#





enumerator kINPUTMUX_Ctimer0M2ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer0M3ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer1M2ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer1M3ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer2M2ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer2M3ToQdc1Icap1#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Icap1#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Icap1#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn0ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn1ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn2ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn3ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn4ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn5ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn6ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn7ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn8ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn9ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn10ToQdc1Icap1#





enumerator kINPUTMUX_TrigIn11ToQdc1Icap1#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Aoi1Out0ToQdc1Icap1#





enumerator kINPUTMUX_Aoi1Out1ToQdc1Icap1#





enumerator kINPUTMUX_Aoi1Out2ToQdc1Icap1#





enumerator kINPUTMUX_Aoi1Out3ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer3M2ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer3M3ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer4M2ToQdc1Icap1#





enumerator kINPUTMUX_Ctimer4M3ToQdc1Icap1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Icap1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Icap1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Icap1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Icap1#

FlexPWM0_SM0_EXTA0 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Exta0#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Exta0#

FlexPWM0_SM1_EXTA1 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Exta1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Exta1#

FlexPWM0_SM2_EXTA2 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Exta2#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Exta2#

FlexPWM0_SM0_EXTSYNC0 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Extsync0#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Extsync0#

FlexPWM0_SM1_EXTSYNC1 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Extsync1#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Extsync1#

FlexPWM0_SM2_EXTSYNC2 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Extsync2#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Extsync2#

FlexPWM0_FAULT input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Fault#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Fault#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Fault#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Fault#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Fault#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Fault#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Fault#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Fault#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Fault#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Fault#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Fault#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Fault#

FlexPWM0_FORCE input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm0Force#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm0Force#





enumerator kINPUTMUX_Cmp0OutToFlexPwm0Force#





enumerator kINPUTMUX_Cmp1OutToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn0ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn1ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn2ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn3ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn4ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn5ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn6ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn7ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn8ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn9ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn10ToFlexPwm0Force#





enumerator kINPUTMUX_TrigIn11ToFlexPwm0Force#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm0Force#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm0Force#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Force#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Force#





enumerator kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Force#





enumerator kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Force#





enumerator kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Force#





enumerator kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Force#

FlexPWM1_SM0_EXTA0 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn10ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_TrigIn11ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Exta0#





enumerator kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Exta0#

FlexPWM1_SM1_EXTA1 input trigger connections. 




enumerator kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta1#





enumerator kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta1#





<

MCXA156

Contents

MCXA156#

AOI: Crossbar AND/OR/INVERT Driver#

CACHE: LPCAC CACHE Memory Controller#

CDOG#

Clock Driver#

CRC: Cyclic Redundancy Check Driver#

CTIMER: Standard counter/timers#

DAC: Digital-to-Analog Converter Driver#

eDMA: Enhanced Direct Memory Access (eDMA) Controller Driver#

eDMA core Driver#

eDMA soc Driver#

EIM: error injection module#

EQDC: Enhanced Quadrature Encoder/Decoder#

ERM: error recording module#

FGPIO Driver#

FlexCAN: Flex Controller Area Network Driver#

FlexCAN Driver#

FlexCAN eDMA Driver#

FlexIO: FlexIO Driver#

Flexio_a-format#

FlexIO Camera Driver#

FlexIO Driver#

FlexIO eDMA I2S Driver#

FlexIO eDMA MCU Interface LCD Driver#

FlexIO eDMA SPI Driver#

FlexIO eDMA UART Driver#

FlexIO I2C Master Driver#

FlexIO I2S Driver#

FlexIO MCU Interface LCD Driver#

FlexIO SPI Driver#

Flexio_t-format#

FlexIO UART Driver#

FlexPWM: Enhanced Flex Pulse Width Modulator#

FREQME: Frequency Measurement#

GLIKEY#

GLIKEY#

GPIO: General-Purpose Input/Output Driver#

GPIO Driver#

I3C: I3C Driver#

I3C Common Driver#

I3C Master Driver#

I3C Master DMA Driver#

I3C Slave Driver#

I3C Slave DMA Driver#

INPUTMUX: Input Multiplexing Driver#